Management of voltage regulator units in field programmable arrays

Abstract

An electronic device has a power rail driven by voltage regulators and supplying a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver a regulator current up to a predefined value to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface via a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and the voltage regulator controller and operates in a standby mode or an operating mode. In standby mode, the bypass unit bypasses the feedback path, and the corresponding voltage regulator does not deliver current to the power rail; while in operating mode, the bypass unit does not bypass the feedback path, and the corresponding voltage regulator delivers a regulator current up to a predefined value to the power rail.

Description

Technical Field

[0001] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 237,485, filed August 26, 2021, entitled “Management of Voltage Regulator Units in Field Programmable Arrays,” the entire contents of which are incorporated herein by reference. Prior Technology

[0002] Electronic devices typically integrate a System-on-a-Chip (SoC) with a Power Management Integrated Circuit (PMIC), communication ports, external memory or storage, and other peripheral functional modules on a main logic board. An SoC includes one or more microprocessor or central processing unit (CPU) cores, memory, input / output ports, and auxiliary storage in a single package. The PMIC is typically positioned adjacent to the SoC on the main logic board and provides multiple DC power rails to the SoC via conductors formed on the main logic board. For each type of SoC, the PMIC and the conductors leading to the SoC require custom design, at least based on the microprocessor or CPU cores included in that type of SoC. Summary of the Invention

[0003] The various embodiments of the systems, methods, and apparatuses within the scope of the appended claims each have several variations, with no single variation solely responsible for the attributes described herein. Without limiting the scope of the appended claims, it will be understood, upon consideration of the content of this document and particularly upon consideration of the section entitled "Implementation," how various variations of the various embodiments can be used to provide a semiconductor device configured to provide a semiconductor device or system with a general-purpose PMIC that can self-adaptively support various types of SoCs with different microprocessors or CPU cores. The general-purpose PMIC provides a plurality of power rails to power one or more processor clusters of the SoC. The semiconductor device includes a plurality of voltage regulators arranged in a field-programmable array and controlled to output power to the plurality of power rails of the SoC based on load information and power state policies associated with the one or more processor clusters coupled to the power rails. In some embodiments, each voltage regulator in the field-programmable array can be electrically decoupled from a plurality of power rails and become a redundant or standby voltage regulator without complete power-off (when the bypass unit of the redundant or standby voltage regulator operates in standby mode to disable the feedback path between the output interface and the input of the redundant or standby voltage regulator).

[0004] Specifically, in one embodiment, an electronic device includes: a power rail configured to provide a rail voltage; and a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes: an output interface, one or more drive paths, a voltage regulator controller, and a bypass unit. The output interface is coupled to the power rail and configured to provide a rail voltage to the power rail and deliver up to a predefined regulator current. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to one or more drive paths and an input coupled to the output interface via a feedback path, and is configured to control one or more drive paths. The bypass unit is coupled to one or more drive paths and the voltage regulator controller. Each of the plurality of voltage regulators is configured to operate in a standby mode or an operating mode according to a control setting. In standby mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the corresponding voltage regulator does not supply current to the power rail. In operating mode, the bypass unit is disabled to prevent the feedback path from being bypassed, and the corresponding voltage regulator supplies up to a predefined regulator current to the power rail.

[0005] In another embodiment, a method for driving a power rail at an electronic device having a plurality of voltage regulators electrically coupled to a power rail is implemented. The method includes generating rail voltage and rail current to drive the power rail. Each corresponding voltage regulator has an output interface coupled to the power rail and is configured to provide a rail voltage to the power rail and deliver up to a predefined regulator current when the corresponding voltage regulator is in an operating mode. The method also includes obtaining control settings for each of the plurality of voltage regulators. The control settings for each corresponding voltage regulator determine whether the corresponding voltage regulator is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operating mode. The method also includes enabling a bypass unit at each standby voltage regulator to bypass the feedback path from the output interface to the input of the voltage regulator controller, such that the standby voltage regulator does not deliver current to the power rail. The method also includes disabling the bypass unit at each operating voltage regulator to prevent the feedback path from being bypassed, such that the corresponding voltage regulator delivers current to the power rail.

[0006] These illustrative embodiments and implementations are mentioned not to limit or restrict the scope of this invention, but to provide examples to illustrate the understanding of the invention. Additional embodiments are discussed in the detailed description, and further descriptions are provided therein. Other implementations and advantages will be apparent to those skilled in the art from the description and drawings in this specification. Simple Explanation of the Diagram

[0007] Figure 1A is a block diagram of an example system module in a typical electronic device according to some embodiments.

[0008] Figure 1B is a cross-sectional view of an integrated semiconductor device according to some embodiments.

[0009] Figure 2 is a block diagram of a power management system according to some embodiments.

[0010] Figure 3 is a simplified block diagram of an integrated semiconductor device according to some embodiments, the integrated semiconductor device including a plurality of voltage regulators for providing one or more power rails to a SoC.

[0011] Figure 4A illustrates a procedure for providing rail current IR at rail voltage VR using a subset of voltage regulators according to some embodiments, and Figure 4B illustrates a procedure for providing rail current IR at rail voltage VR based on one or more redundant voltage regulators according to some embodiments.

[0012] Figure 5A is a block diagram of a voltage regulator according to some embodiments, which is one of the voltage regulators in a field-programmable array.

[0013] Figure 5B is a block diagram of a voltage regulator with a bypass unit according to some embodiments.

[0014] Figure 6 is a circuit diagram of a voltage regulator with an auxiliary circuit for controlling redundancy according to some embodiments.

[0015] Figure 7 is a circuit diagram of an example voltage regulator with a filter-based auxiliary loop according to some embodiments.

[0016] Figure 8 is a circuit diagram of a plurality of voltage regulators configured to drive power rails in a field-programmable array of voltage regulators according to some embodiments.

[0017] Figure 9A is a circuit diagram of a multiphase driver in a voltage regulator having multiple drive paths when operating in an operating mode according to some embodiments, and Figure 9B is a circuit diagram of a voltage regulator having multiple bypass paths when operating in a bypass mode according to some embodiments.

[0018] Figures 9C and 9D are circuit diagrams of equivalent circuits of voltage regulators operating in operating mode and bypass mode according to some embodiments.

[0019] Figure 10 is a flowchart of a method for driving a power rail for an electronic device according to some embodiments.

[0020] To better understand the implementation of the various descriptions, the following figures and specific embodiments should be consulted. In the figures, similar component symbols represent corresponding parts throughout the figures. Implementation

[0021] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art to which this invention pertains that various alternatives may be used without departing from the scope of the claims, and that the subject matter may be practiced without these specific details.

[0022] Figure 1A is a block diagram of an example system module 100 in a typical electronic device according to some embodiments. The system module 100 in this electronic device includes at least a system-on-a-chip (SoC) 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces (such as a network interface 108), and one or more communication buses 130 for interconnecting these components. In some embodiments, the I / O controller 106 allows the SoC 102 to communicate with I / O devices (e.g., a keyboard, mouse, or touchscreen) via a general sequence bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth, each interface allowing the electronic device to exchange data with an external source (e.g., a server or another electronic device). In some embodiments, the communication bus 130 includes circuitry (sometimes referred to as a chipset) that interconnects the various system components included in the system module 100 and controls communication between the various system components.

[0023] In some embodiments, memory module 104 includes high-speed random access memory, such as DRAM, SRAM, DDR-RAM, or other random access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, the non-volatile memory devices within memory module 104, or alternatively, include non-transitory computer-readable storage media. In some embodiments, memory slots are reserved on system module 100 for receiving memory module 104. Once inserted into a memory slot, memory module 104 is integrated into system module 100.

[0024] In some embodiments, system module 100 also includes one or more components selected from the following: The memory controller 110 controls the communication between the SoC 102 and memory components (including the memory module 104) in the electronic device; Solid-state drive (SSD) 112, which uses integrated circuit assemblies to store data in electronic devices, and in many embodiments, is based on NAND or NOR memory configuration; Hard disk 114 is a traditional data storage device used for storing and retrieving digital information based on mechanical disks; Power connector 116 includes one or more DC power interfaces, each DC power interface being configured to receive a different DC supply voltage; The power management integrated circuit (PMIC) 118 regulates different DC supply voltages received via the DC power interface to other desired internal supply voltages (also known as rail voltages) required by various components or circuits within the electronic device (e.g., the processor core in SoC 102), such as 5V, 3.3V, or 1.8V; Graphics module 120, which generates a feed of an output image to one or more display devices based on the desired image / video format of one or more display devices; and The sound module 122, under the control of a computer program, facilitates the input of audio signals to and output of audio signals to electronic devices.

[0025] It should be noted that the communication bus 130 will also interconnect various system components, including components 110-122, and control their communication.

[0026] Furthermore, those skilled in the art to which this invention pertains will know that other non-transitory computer-readable storage media can be used, as new data storage technologies have been developed to store information in non-transitory computer-readable storage media within memory module 104 and SSD 112. These new non-transitory computer-readable storage media include, but are not limited to, storage media made of biological materials, nanowires, carbon nanotubes, and individual molecules, although the corresponding data storage technologies are currently under development and have not yet been commercialized.

[0027] In some embodiments, the SoC 102 is implemented in a semiconductor package including one or more integrated circuits, each integrated circuit integrating a subset of the following on a single substrate: one or more microprocessor or CPU cores, memory, input / output ports, and auxiliary storage. The PMIC 118 is also implemented in a semiconductor package including one or more integrated circuits, each integrated circuit formed on a single substrate. The SoC 102 is configured to receive one or more internal supply voltages (also referred to as rail voltages) provided by the PMIC 118 via one or more power rails. In some embodiments, both the SoC 102 and the PMIC 118 are mounted on a main logic board, for example, on two different areas of the main logic board, and electrically coupled to each other via wires formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that may impair the performance of the SoC, such as causing voltage drops in the internal supply voltages. Alternatively, according to the embodiments described with reference to FIG1B, the semiconductor dies of SoC 102 and PMIC 118 are vertically packaged in an integrated semiconductor device such that they are electrically coupled to each other via electrical connections not formed in the main logic board. This vertical arrangement of the semiconductor dies of SoC 102 and PMIC 118 can reduce the length of the electrical connections between SoC 102 and PMIC 118 and avoid performance degradation caused by wiring on the main logic board.

[0028] In some embodiments, the general-purpose PMIC 118 is configured to drive different types of SoC 102 in different types of electronic devices. Regardless of whether the PMIC 118 and SoC 102 are arranged side-by-side or vertically, the PMIC 118 occupies the same package footprint relative to the main board, while the SoC 102 may have different package footprints based on the electronic modules integrated therein. The PMIC 118 includes a plurality of voltage regulator units (e.g., regulator 320 in FIG. 3) arranged in a field-programmable array. The plurality of voltage regulator units are identical to each other, or alternatively include more than one type of voltage regulator unit. In a particular electronic device, the control settings are determined based on the rail voltage and rail current required to power the SoC 102 and other electronic modules (if any) on the power rails. For each of these power rails, a subset of the voltage regulator units in the field-programmable array of the PMIC 118 is selected using the corresponding control settings, and the selected voltage regulator units collectively provide rail current to the corresponding power rail at the rail voltage. Therefore, PMIC 118 is reconfigured by these control settings to provide rail voltage and current to the power rails of SoC 102, and each of the plurality of configurable voltage regulators in PMIC 118 is redundant or selected to drive one of the power rails via one of the control settings.

[0029] Figure 1B is a cross-sectional view of an integrated semiconductor device 180 according to some embodiments, in which an SoC 102 and a PMIC 118 are arranged vertically. The semiconductor device 180 integrates at least one SoC die 102 and at least one PMIC die 118 in a semiconductor package, and includes at least a package substrate 124 having a first surface 124A and a second surface 124B opposite to the first surface 124A. The SoC die 102 is disposed on the first surface 124A of the package substrate 124, and the PMIC die 118 is mechanically coupled to the second surface 124B of the package substrate 124.

[0030] The packaging substrate 124 also includes a plurality of first via interconnects 126 that pass through the body of the packaging substrate 124 and are exposed on a first surface 124A and a second surface 124B. A PMIC die 118 is electrically coupled to an SoC die 102 via the plurality of first via interconnects 126 of the packaging substrate 124. Specifically, the PMIC die 118 includes a plurality of DC connections 128 configured to output a plurality of rail voltages VR supplied to the SoC die 102 via a plurality of voltage rails. When the PMIC die 118 is mounted on the second surface 124B of the packaging substrate 124, the DC connections 128 are electrically coupled to the plurality of first via interconnects 126 of the packaging substrate 124. In some embodiments, the SoC die 102 includes a plurality of power connections 132 configured to receive a plurality of rail voltages. When the SoC die 102 is mounted on the first surface 124A of the packaging substrate 124, the power connections 132 are electrically coupled to the plurality of first via interconnects 126 of the packaging substrate 124. Therefore, the PMIC die 118 is configured to provide DC power (i.e., the rail voltage and rail current of the power rail 206 in FIG. 2) to the SoC die 102 via the DC connection 128 of the PMIC die 118, the power connection 132 of the SoC die 102, and the first via interconnect 126 of the package substrate 124. Furthermore, by using the extremely low impedance DC connection 128, the quality of the DC power provided by the PMIC die 118 to the SoC die 102 is significantly improved compared to a system in which the PMIC die 118 and the SoC die 102 are respectively packaged and positioned side-by-side on a main board.

[0031] In some embodiments, the power management interface 208 on the PMIC die 118 is controlled by the main power management interface of the SoC die 102 and is configured to receive digital power control signals (e.g., carrying load information 314 in FIG. 3) from the SoC die 102. A subset of the first via interconnect 126 is configured to transmit digital power control signals from the SoC die 102 to the PMIC die 118.

[0032] SoC die 102 has a first package shape on package substrate 124, and PMIC 118 has a second package shape on package substrate 124. In some embodiments, for the purpose of directly coupling the DC connection 128 of PMIC die 118 and the power connection 132 of SoC die 102 using a plurality of first via interconnects 126, the first package shape and the second package shape at least partially overlap. In some cases, the first package shape of SoC die 102 is larger than the second package shape of PMIC die 118 and completely surrounds the second package shape of PMIC die 118. Alternatively, in some cases, the first package shape of SoC die 102 is offset from the second package shape of PMIC die 118, but at least partially overlaps with the second package shape of PMIC die 118. The DC connection 128 of PMIC die 118, the power connection 132 of SoC die 102, and the first via interconnects 126 of package substrate 124 are aligned and surrounded in the overlapping area of ​​the first and second package shapes.

[0033] Furthermore, the PMIC die 118 includes a plurality of thin-film inductors 150 corresponding to a plurality of DC connections 128. The plurality of thin-film inductors 150 are positioned adjacent to or facing the second surface 124B of the package substrate 124, for example, facing the second surface 124B of the package substrate 124 from the top surface of the PMIC die 118. In other words, the plurality of thin-film inductors 150 are disposed between the top surface of the PMIC die 118 and the second surface 124B of the package substrate 124. In some embodiments, the PMIC die 118 is mechanically coupled to the package substrate 124, for example, via an adhesive. The height of the plurality of thin-film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 µm) to maintain robust mechanical coupling between the PMIC die 118 and the package substrate 124. That is, the vertical arrangement of the semiconductor dies of SoC 102 and PMIC 118 is partially facilitated by integrating a thin-film inductor 150 in the limited space between the dies of SoC 102 and PMIC 118. The thin-film inductor is formed and integrated on the substrate of PMIC 118 and has an inductor height controlled to be less than the height of the limited space, so that the thin-film inductor can fit within the limited space between the semiconductor dies of SoC 102 and PMIC 118. Since the thin-film inductor is formed on top of the substrate of PMIC 118, the thin-film inductor can be directly connected to the internal nodes or output nodes of PMIC 118, and the main logic board wires do not need to connect the thin-film inductor to the internal nodes or output nodes of PMIC 118.

[0034] In some embodiments, the integrated semiconductor device 180 also includes a cap 134 coupled to a first surface 124A of the package substrate 124. The cap 134 is configured to conceal at least a portion of the SoC die 102 and the first surface 124A of the package substrate 124, thereby protecting at least a portion of the SoC die 102 and the first surface 124A. Furthermore, in some embodiments, the cap 134 is made of a conductive material and is configured to ground to provide an electrostatic shielding for any other circuitry on the SoC die 102 and the first surface 124A when the cap 134 is completely concealed, or to provide an electrostatic shielding for the portion of the first surface 124 concealed by the cap 134 when the first surface 124A is only partially concealed by the cap 134. In some cases, the cap 134 is made of a thermally conductive material configured to dissipate heat generated by the SoC die 102. In some embodiments, the vaporizer 136 or vaporizer layer is used to couple the SoC die 102 to the inner surface of the cover 134 to uniformly distribute the heat generated by the SoC die 102 from the SoC die 102 to the cover 134.

[0035] In some embodiments, the semiconductor device 180 also includes a socket substrate 138. The socket substrate 138 has a third surface 138A facing a second surface 124B of the package substrate 124. The package substrate 124 is electrically coupled to the socket substrate 138 via a plurality of electrical connectors 140. Specifically, in some embodiments, the second surface 124B of the package substrate 124 includes a first region (e.g., a central region) to which the PMIC die 118 is mechanically coupled and a second region (e.g., a peripheral region) where the plurality of electrical connectors 140 are located. In one example, the second region is adjacent to and surrounds the first region. It should be noted that in some cases, the semiconductor device 180 is provided with the socket substrate 138. However, in some cases, the socket substrate 138 is attached to a circuit board of the electronic device in FIG. 1A and is not part of the integrated semiconductor device 180. Specifically, the semiconductor device 180 is an alternative portion configured to provide the functionality of a combination of the PMIC die 118 and the SoC die 102.

[0036] In some embodiments, the third surface 138A of the socket substrate 138 is substantially flat, and the PMIC die 118 is disposed between the second surface 124B of the package substrate 124 and the third surface 138A of the socket substrate 138. The height of the plurality of thin-film inductors 150 is less than a predetermined threshold height (e.g., 1 mm, 100 µm) determined by the difference between the length of the electrical connector 140 and the thickness of the PMIC die 118. Alternatively, in some embodiments, the socket substrate 138 includes a recessed portion 142 (sometimes referred to as a cavity) configured to receive the PMIC die 118 when it is mechanically and electrically coupled to the second surface 124B of the package substrate 124. The depth of the recessed portion 142 is less than the thickness of the socket substrate 138. In some cases, the PMIC die 118 is suspended in the recessed portion 142, i.e., separated from the bottom surface of the recessed portion 142 via an air gap. Alternatively, in some cases, the PMIC grain 118 begins to contact the bottom surface of the recessed portion 142 directly or via an intermediate layer (e.g., an adhesive layer, a vapor chamber layer, or a layer that is both an adhesive and a vapor chamber).

[0037] In some embodiments not illustrated in FIG1B, the depth of the recess 142 is equal to the thickness of the socket substrate 138, and the recess 142 is an opening or cutoff on the socket substrate 138. When the socket substrate 138 is mounted on a circuit board (e.g., a main logic board), the PMIC die 118 is suspended in the recess 142 (also referred to as an opening or cutoff) and is at least partially surrounded by the package substrate 124, the socket substrate 138, and the circuit board.

[0038] In some embodiments, the power connection 312 of the SoC die 102 is not directly coupled to the first via interconnect 126 of the package substrate 124. Specifically, a first interposer 144 is disposed between the SoC die 102 and a first surface 124A of the package substrate 124. The first interposer 144 also includes a plurality of second via interconnects 146 configured to electrically couple at least the power connection 132 of the SoC die 102 and the first via interconnect 126 of the package substrate 124. Similarly, in some embodiments, the DC connection 128 of the PMIC die 118 is not directly coupled to the first via interconnect 126 of the package substrate 124. Specifically, a second interposer 148 is disposed between the PMIC die 118 and a second surface 124B of the package substrate 124. The second interposer 148 also includes a plurality of third via interconnects 152 configured to electrically couple at least the DC connection 128 of the PMIC die 118 and the first via interconnect 126 of the package substrate 124. Therefore, the power rail 206 of SoC 102 includes at least the power connection 132 of SoC die 102, the first via interconnect 126 of package substrate 124 and the DC connection 128 of PMIC die 118, and in some cases, also includes the second via interconnect 146 of the first interposer 144 and / or the third via interconnect 152 of the second interposer 148.

[0039] In some embodiments, the semiconductor device 180 also includes one or more individual electronic modules 160 (e.g., resistors, capacitors, inductors, transistors, and logic chips). Individual electronic modules 160 may be electrically coupled to the input / output interface circuitry of the SoC die 102 to control input / output coupling to the SoC die 102. Optionally, a subset of individual electronic modules 160 (e.g., components 160A) is disposed on a first surface 124A of the package substrate 124. Each component 160A may be contained within or outside a cover 134. Optionally, a subset of individual electronic modules 160 (e.g., components 160B) is mechanically coupled to a second surface 124B of the package substrate 124. If a corresponding component 160B has a low profile (e.g., thinner than the length of the electrical connector 140), then component 160B may be adapted to fit in the gap between the second surface 124B of the package substrate 124 and the third surface 138A of the socket substrate 138. Otherwise, if component 160B does not have a low profile (e.g., thicker than the length of electrical connector 140), then the corresponding component 160B can be received by the recessed portion 142 of the socket substrate 138 and configured to be adjacent to the PMIC die 118.

[0040] SoC die 102 and PMIC die 118 are vertically arranged in semiconductor device 180. The power connection 132 of SoC die 102 and the DC connection 128 of PMIC die 118 are aligned and placed close to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail 206 providing rail voltage to SoC die 102. It should be noted that in some implementations, a plurality of PMIC dies 118 may be disposed in a recessed portion 142 of socket substrate 138 and electrically coupled to one or more SoC dies 102 disposed on a first surface 124A of package substrate 124. For example, two PMIC dies 118 are disposed in a recessed portion 142 of socket substrate 138 to jointly power four SoC dies 102. One of the SoC dies 102 may optionally correspond to a microprocessor or CPU core, or a cluster of microprocessors or CPU cores.

[0041] Furthermore, in some embodiments of this application, the PMIC die 118 includes a field-programmable array of voltage regulators configurable via control settings to drive different types of SoC dies 102. In some cases, multiple instances of the same PMIC die 118, package substrate 124, and socket substrate 138 are used to support different types of SoC dies 102. A recessed portion 142 formed on the socket substrate 138 has a fixed size to accommodate the same PMIC die 118, and a first via interconnect 126 through the body of the package substrate 124 has a fixed position. Alternatively, in some cases, although the package form factor of the package substrate 124 and the socket substrate 138 differs due to different types of SoC dies 102, the same PMIC die 118 allows the recessed portion 142 and the first via interconnect 126 of the package substrate 124 to remain unchanged, thereby avoiding the need to custom-design the PMIC die 118 and the entire package for each individual type of SoC die 102. Therefore, the application of a field-programmable array of voltage regulators in the PMIC die 118 simplifies the assembly process and improves the cost efficiency of the semiconductor device 180.

[0042] Figure 2 is a block diagram of a power management system 200 configured to provide power to one or more power rails 206 of an SoC (such as SoC 102) according to some embodiments. The power management system 200 receives one or more input DC supply voltages 202 and digital power control signals 204, and converts the input DC supply voltages 202 into one or more rail voltages, which are output by one or more power rails 206A, 206B through 206N and provided to the SoC 102. The power management system 200 includes a power management interface 208, one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B, ... 210N), and one or more output filters 212 (e.g., output filters 212A, 212B, ... 212N). The power management interface 208 receives the input DC supply voltages 202 and digital power control signals 204. In some embodiments, the power management interface 208 is controlled by (e.g., on SoC 102) the main power management interface of the central processing unit and is configured to receive digital power control signals 204 from SoC 102. A DC-DC converter 210 is coupled to the power management interface 208 and the power rail 206 and is controlled by the digital power control signals 204 to generate one or more rail voltages VR supplied on the power rail 206 from the input DC supply voltage 202. An output filter 212 is coupled to the DC-DC converter 210 and is configured to reduce noise in the power rail 206 supplied to SoC 102 and maintain the stability of the power rail 206. In some embodiments, the output filter (e.g., any one of 212A, 212B, ... 212N) includes one or more corresponding output resistors 214 and one or more output capacitors 216 (e.g., 216A, 216B, ... 216N). In some embodiments, the output filter (e.g., 212B) includes an inductor 150 and one or more output capacitors (e.g., capacitor 216B).

[0043] In some embodiments, the power management system 200 is implemented on one or more PMIC dies 118, and each PMIC die 118 has a single substrate. In some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on the substrate of a single PMIC die 118, for example, belonging to the same integrated circuit fabricated on the substrate of the PMIC die 118. Conversely, in some embodiments, the power management interface 208 and the DC-DC converter 210 are formed on a plurality of substrates of a plurality of PMIC dies 118. In some embodiments, in addition to the power management interface 208 and the DC-DC converter 210, each PMIC die 118 also includes a plurality of thin-film inductors, which are fabricated or mounted on the top surface of the substrate of the PMIC die 118. Optionally, the plurality of thin-film inductors include one or more inductors 150 used in the output filter 212. Optionally, a plurality of thin-film inductors include one or more inductors 150' used in the DC-DC converter 210A. In some embodiments, in addition to the power management interface 208, the converter 210, and the inductors 150 / 150', the PMIC die 118 also integrates a subset of the output resistors 214 and capacitors 216 of the output filter 212. Alternatively, in some embodiments, the PMIC 118 and SoC 102 are arranged vertically in the integrated semiconductor device 180, and a subset or all of the capacitor and resistor components of the output filter 212 are formed using individual electronic modules 160 disposed on either surface of the package substrate 124.

[0044] In some embodiments, the power management system 200 includes a field-programmable array of voltage regulator units, an output filter 212, one or more output resistors 214, one or more output capacitors 216, and one or more inductors 150. A digital power control signal 204 is determined, for example, by the SoC 102 based on the target power capacity required for the power rail 206 (e.g., rail voltage and rail current). In other words, the digital power control signal 204 is determined by load information and power state policies for the power rail 206. The power state policies require the power rail to meet at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency). For example, each power rail is configured to supply power to the CPU cluster, cache memory, or function block of the SoC 102 (which has corresponding power requirements used by the SoC 102 to define the target power capacity of the corresponding power rail 260 controlled by the corresponding power state policy). In one example, the power state strategy for a specific power rail 206 requires controlling the corresponding rail current of that power rail 206 to maximize either power conversion efficiency or rail voltage response rate. According to control signal 204, voltage regulator units in the field-programmable array are partitioned and configured to form one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B, ... 210N) to drive the power rail 206 according to the load information and power state strategy associated with it. For each DC-DC converter 210, additional components 212-216 and 150 can also be selected and controlled via a corresponding subset of control signals 204 to achieve the desired noise performance for the corresponding power rail 206.

[0045] Figure 3 is a simplified block diagram of an integrated semiconductor device 300 according to some embodiments, which includes a plurality of voltage regulators 320 for providing one or more power rails 206 to an SoC 102. The plurality of voltage regulators 320 are arranged in a field-programmable array 330. A power array controller 302 includes a plurality of electronic modules (e.g., one or more of an SoC interface, oscillator, microcontroller, LDO, and reference generator) and is coupled to the plurality of voltage regulators 320. The power array controller 302 is configured to control the plurality of voltage regulators 320 to output power to the plurality of power rails 206. Each power rail 206 provides a corresponding rail current IR with a corresponding rail voltage VR. In the example shown in Figure 3, the field-programmable array 330 of voltage regulators 320 supplies power to four power rails 206-1, 206-2, 206-3, and 206-4, and provides rail currents IR1, IR2, IR3, and IR4 at rail voltages VR1, VR2, VR3, and VR4, respectively. For each of the plurality of power rails 206, the power array controller 302 determines the corresponding rail current IR associated with the corresponding power rail 206, selects a subset of voltage regulators 320 based at least on the corresponding rail current IR, and enables the subset of voltage regulators 320 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR. Thus, the power array controller 302 and the voltage regulators 320 implement a power management system for SOC 102 on one or more PMIC dies 118.

[0046] SoC 102 includes a plurality of electronic components, such as one or more microprocessors or CPU cores 304, memory 306, communication modules 308, timing sources, peripheral devices (e.g., clocks, counters, timers), analog interfaces, input / output ports, and / or auxiliary storage. The microprocessors or CPU cores 304 may optionally be arranged in clusters. SoC 102 is implemented by one or more integrated circuits (e.g., SoC dies 302). Each SoC die 102 integrates a subset of the electronic modules of SoC 102 on a corresponding semiconductor substrate. In one example, SoC 102 has a main SoC die including one or more processor cores 304 and accompanying SoC dies including memory 306, analog interfaces, or other components different from the processor cores 304.

[0047] For each power rail 206, the corresponding rail voltage VR is determined by the operation of a corresponding subset of the electronics of the SOC 102, and the corresponding rail current IR is determined by load information and power state policies associated with the corresponding subset of the electronics of the SOC 102. The power array controller 302 is configured to determine a control value 310 based at least on the corresponding rail voltage VR, select a selected subset of voltage regulators 320 based at least on the corresponding rail current IR, and provide the determined control value 310 to the selected subset of voltage regulators 320 corresponding to the corresponding power rail 206, thereby enabling the subset of voltage regulators 320 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR. Furthermore, in some embodiments, the power array controller 302 provides an operation enable signal 312 to the selected subset of voltage regulators corresponding to each power rail 206 to generate the corresponding rail voltage VR and collectively provide the corresponding rail current IR. Therefore, the power array controller 302 is configured to provide each voltage regulator 320 with control settings including control value 310 and operation enable signal 312, thereby selecting different subsets of voltage regulators 320 to provide rail voltage VR and rail current IR to each power rail 206.

[0048] In some embodiments, the power array controller 302 includes one or more processors and memory having instructions stored therein that, when executed by one or more processors, cause the processors to control voltage regulators 320 to output power to a plurality of power rails 206. VRU packet configurations may optionally be stored in the memory of the power array controller 302, in the off-chip non-volatile memory (NVM) of the system module 100, or in the basic input / output system (BIOS) of the system module 100 to associate control values ​​310 and enable signals 312 with a subset of voltage regulators for each of the power rails 206. In some cases, the power array controller 302 loads and implements the VRU packet configuration while the PMIC 118 is being powered on.

[0049] Each of the plurality of power rails 206 is configured to power a subset of the electronic modules of the SOC 102, the subset being the load of the corresponding power rail 206. For each power rail 206, the power array controller 302 is configured to determine load information 314 corresponding to the expected or actual load on the corresponding power rail 206, and to determine the corresponding rail current IR associated with the corresponding power rail based on the load information 314 and a power state policy. The power state policy includes at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency), and the device 300 is configured to operate in accordance with the power state policy for each corresponding power rail. In some embodiments, the power rail 206 is coupled to a main SoC die having one or more processor cores 304 arranged in a cluster, and the load information 314 of the power rail 206 corresponds to processor load information for one or more processor clusters 304 of the main SoC die 102 coupled to the power rail 206. Examples of processor load information include the total computational power of the types of operations to be performed by one or more processor clusters 304. Conversely, in some embodiments, one power rail of power rail 206 is coupled to an accompanying SoC die having memory 306 and is configured to power write and read operations on memory 306. The load information for this power rail 206 corresponds to memory load information for memory access to memory 306 on the accompanying SoC die. Examples of memory load information include the memory type of memory 306, the frequency of memory write operations, and the frequency of memory read operations. Therefore, the rail current IR of each power rail 206 is self-adjusted based on the load information 314 of the corresponding power rail 206 (e.g., processor or memory load information). Furthermore, in some embodiments, given the load information of each power rail 206, the corresponding power state strategy for the power rail 206 requires controlling the corresponding rail current IR of the power rail 206 to maximize either power conversion efficiency or rail voltage response rate. In one instance, according to the power state policy, power rail 206 provides maximum rail current at startup to allow the rail voltage to reach rail voltage VR during transient load response time.

[0050] Furthermore, in some embodiments, each of the plurality of voltage regulators 320 in the field-programmable array 330 corresponds to a corresponding voltage regulator type selected from a plurality of predefined voltage regulator types. For each power rail 206, the selected subset of voltage regulators 320 corresponds to a corresponding voltage regulator type determined based on at least one performance criterion (e.g., one or more of the following: maximum rail current IRLM, maximum regulator current IRGM, output ripple voltage, power supply rejection ratio, load transient response, output noise, and power supply efficiency).

[0051] Referring to Figure 3, after selecting a subset of voltage regulators 320 for each power rail 206, each voltage regulator 320 in that subset is uniquely associated with the corresponding power rail 206 at a specific time. For example, at a first time, power rails 206-1, 206-2, 206-3, and 206-4 are associated with four different sets of voltage regulators 320, as shown in Figure 3. Each voltage regulator 320 in the first row is uniquely associated with power rail 206-1 at the first time, and cannot be associated with any of power rails 206-2, 206-3, and 206-4 at the same first time. However, at a second time, different from the first time, the voltage regulators 320 in the field-programmable array 330 can be reconfigured to power different power rails 206. Each voltage regulator 320 in the first row is uniquely associated with power rail 206-1 at a first time, but can be reconfigured to drive any of power rails 206-2, 206-3, and 206-4 at a second time. More generally, in some embodiments, at least a plurality of voltage regulators 320 in the field-programmable array 330 can be configured to provide power to a selected power rail 206 of the plurality of power rails at any time. Thus, in some embodiments, a subset of voltage regulators 320 is permanently assigned to a particular power rail 206, while other subsets are configurable in which power rail 206 they are connected to. In some other embodiments, all voltage regulators 320 in the field-programmable array 330 are configurable in which power rail 206 they are connected to.

[0052] Each corresponding voltage regulator 320 has at least two modes, including an operating mode and a standby mode. In operating mode, the corresponding voltage regulator 320 outputs a rail voltage VR to one of the power rails 206 associated with it and supplies a predefined regulator current IR to the associated power rail 206. Conversely, standby mode is applied when the corresponding voltage regulator 320 (e.g., 320RA-320RD) is not assigned to drive any power rail 206, and when the corresponding voltage regulator 320 (e.g., 320E) is temporarily disabled to prevent current from being supplied to the power rail 206 to which the corresponding voltage regulator 320 is assigned. Specifically, in the example shown in FIG3, the voltage regulators 320RA-320RD in the field-programmable array 330 are redundant and are not associated with any power rail 206. These voltage regulators 320RA-320RD operate in standby mode and do not exit standby mode until they are reassigned to drive one or more power rails 206. For each voltage regulator 320 assigned to a corresponding power rail 206, the corresponding voltage regulator 320 can be disabled to not supply current to the corresponding power rail 208 during the first duty cycle corresponding to the standby mode. During a second duty cycle, different from the first duty cycle and corresponding to the operating mode, the corresponding voltage regulator 320 can be activated to provide power to the corresponding power rail 206 and supply current. For example, the voltage regulator 320E associated with power rail 206-1 can operate in alternating duty cycles corresponding to standby mode (where the voltage regulator 320 does not supply current to power rail 206-1) and operating mode (where the voltage regulator 320 is enabled to supply current to power rail 206-1).

[0053] More specifically, in some embodiments, each voltage regulator 320 (e.g., voltage regulators 320RA-320RD and 320E) includes a bypass unit configured to provide a dummy load component. In standby mode, the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator 320 (e.g., under the control of the operation enable signal 312), thereby disabling the corresponding voltage regulator 320 from contributing to any rail current IR via the output interface. In operating mode, the bypass unit is disabled to prevent the feedback path from being bypassed, and the voltage regulator operates with the feedback path such that the output interface can output a portion of the rail current of the rail voltage VR and the rail current IR to the corresponding power rail 206. Further details regarding the bypass unit are provided below with reference to Figures 5B and 6-10.

[0054] In some embodiments, the semiconductor device 300 also includes one or more direct current (DC) power interfaces 316. Each DC power interface 316 is configured to receive a different DC supply voltage VIN 202. Each voltage regulator 302 is coupled to a corresponding subset of the one or more DC power interfaces 316 and is configured to be powered by the corresponding DC supply voltage VIN 202 and generate a corresponding rail voltage VR from the corresponding DC supply voltage VIN 202.

[0055] Figure 4A illustrates a procedure 400, according to some embodiments, using a subset of voltage regulators 320 to provide rail current IR at rail voltage VR, and Figure 4B illustrates a procedure 450, according to some embodiments, using one or more redundant voltage regulators 320 to provide rail current IR at rail voltage VR. The rail current IR can vary between 0 and the maximum rail current IRLM. Each of the subsets of voltage regulators 320 is configured to provide a regulator current up to the maximum regulator current IRGM. The subset of voltage regulators 320 has a first number of voltage regulators corresponding to the ratio of the maximum rail current IRLM to the maximum regulator current IRGM. For example, in Figure 3, the first power rail 206-1 is required to output the maximum rail current IRLM, and each voltage regulator 320 can provide a corresponding regulator current up to the maximum regulator current IRGM. Based on the maximum rail current IRLM (e.g., 0.6 A) and the maximum regulator current IRGM (e.g., 80 mA), eight voltage regulators are required to provide rail current IR up to the maximum rail current IRLM for the power rail 206-1.

[0056] In some embodiments, a maximum rail current IRLM is applied during the startup of power rail 206 to achieve rail voltage VR within the transient load response time, and power rail 206 subsequently operates with an operating current less than the maximum rail current IRLM. Power rail 206 is configured to achieve rail voltage VR within the transient load response time at each startup of power rail 206. Sufficient power can be supplied to the power rail to achieve rail voltage VR within the transient load response time by providing a maximum regulator current IRGM and a maximum rail current IRLM during startup, and therefore, the first number of voltage regulators 320 is determined in part based on the transient load response time required for startup of power rail 206. However, in some embodiments, when the voltage on the corresponding power rail 206 is ramped up during power rail startup, the current supplied by the power management system 500 is significantly less than the maximum power rail current for that power rail to reduce system stress, avoid overshoot, etc.

[0057] During operation of power rail 206 (sometimes referred to herein as normal operation, as opposed to startup), the operating current IR supplying power to SoC 102 varies and does not exceed the maximum rail current I RLM. Conversely, in some embodiments, the maximum rail current I RLM is reached at least occasionally during normal operation of power rail 206 when the rail current IR is used to supply power to SoC 102. The operating current varies between 0 and the maximum rail current I RLM. During normal operation of power rail 206, as opposed to startup, a first number of voltage regulators 320 is determined based on the operating current of power rail 206 rather than the transient load response time of power rail 206 at each startup. The transient load response time of power rail 206 can be achieved via a transient rail current less than the maximum rail current I RLM.

[0058] Referring to Figure 4A, power rail 206 has a transient rail current IR at a given time, regardless of whether the given time corresponds to startup or normal operation of power rail 206. In some embodiments, power array controller 302 generates control settings (e.g., control value 310 and operation enable signal 312) to enable all voltage regulators in a subset of voltage regulators 302 to collectively provide the transient rail current IR of power rail 206. In other words, in some embodiments, the subset of voltage regulators 302 does not operate in standby mode because the transient rail current IR varies between 0 and the maximum rail current IRLM. For example, the first power rail 206-1 (Figure 3) outputs a transient rail current IR equal to 0.5 IRLM at a given time and is configured such that all eight voltage regulators providing the maximum rail current IRLM are enabled, while being controlled by power array controller 302 to collectively provide only 0.5 IRLM. Thus, in this example, only a portion of the power capacity of each voltage regulator 302 is utilized. In some cases, the rail voltage VR associated with the transient rail current IR differs from the rail voltage VR associated with the maximum rail current IRLM by a first rail voltage error. The power array controller 302 and / or voltage regulator 320 are configured to keep (e.g., limit or control) the first rail voltage error within the rail drift tolerance VRT.

[0059] Furthermore, in some embodiments, a subset of voltage regulators 320 is controlled to contribute substantially equally to the transient rail current IR. For example, each voltage regulator 320 provides a corresponding portion of the transient rail current IR, and this portion varies by less than 5% (or 10%, 20%, or other predefined margin) among voltage regulators 320 configured to power the same power rail 206. Each voltage regulator 320 may include inter-regulator balancing circuitry to balance the portion of the corresponding rail current IR provided by the corresponding voltage regulator 320 with at least another portion of the corresponding rail current IR provided by different voltage regulators 320 within the subset of voltage regulators 320. In some implementations, the inter-regulator balancing circuitry is located internally within each voltage regulator 320 and uses the portion of the corresponding rail current IR provided by the corresponding voltage regulator 320 as negative feedback to control that portion of the corresponding rail current IR internally and independently of other voltage regulators configured to power the same power rail 206.

[0060] Referring to Figure 4B, in some embodiments, one or more voltage regulators 320 in a subset of voltage regulators 320 are disabled and operate in standby mode (e.g., under the control of operation enable signal 312), while the remainder of the subset of voltage regulators 320 are enabled to collectively provide the transient rail current IR of the corresponding power rail. One or more voltage regulators 320 have a second number of voltage regulators 320, and the second number is determined based on a comparison (e.g., ratio) between the transient rail current IR and the maximum regulator current IRGM, or equivalently based on a comparison (e.g., ratio) between the transient rail current IR and the maximum rail current IRLM. For example, a subset of voltage regulators 320 has 8 voltage regulators, and the second number is equal to a value between 1 and 7. If the transient rail current IR is within a first range (e.g., (0, ...), ... If I RLM]), then the first voltage regulator 320A is activated to provide the transient rail current IR. If the transient rail current IR increases to more than at the corresponding time, I RLM, I RLM, I RLM, I RLM, I RLM, I RLM and If IRLM is activated, then voltage regulators 320B, 320C, 320D, 320E, 320F, 320G, and 320H are activated at those corresponding times (e.g., gradually or continuously) to provide transient rail current IR within the corresponding rail current range. Furthermore, in some embodiments, when a second number of voltage regulators 320 operate in standby mode, the remainder of a subset of voltage regulators 320 are controlled to contribute substantially equally to the transient rail current IR; for example, each activated voltage regulator 320 provides a corresponding portion of the transient rail current IR that varies less than 5% (or 10%, 20%, or other predefined margin) among voltage regulators 320 associated with the same power rail 206.

[0061] In some cases, when one or more voltage regulators 320 operate in standby mode, the rail voltage VR associated with the transient rail current IR and the rail voltage VR associated with the maximum rail current IRLM differ by a second rail voltage error. This second rail voltage error is controlled (e.g., by the power array controller 302 and / or the voltage regulator 320) to keep (e.g., limit or control) the second rail voltage error within the rail drift tolerance VRT. When the same rail current IR is provided using at least one redundant regulator (FIG. 4B) or without using a redundant regulator (FIG. 4A), the second rail voltage error is smaller than the first rail voltage error, and the involvement of the redundant regulator 320 provides higher accuracy for the rail voltage VR with more complex regulator control.

[0062] As explained above, each power rail 206 corresponds to a corresponding first number of voltage regulators 320, wherein a corresponding second number of voltage regulators 320 are enabled each time to operate in standby mode, and the corresponding second number varies dynamically according to the transient rail current IR. The second number is determined based on load information 314 and a power state strategy configured to meet at least one performance criterion (e.g., output ripple voltage, power supply rejection ratio, load transient response, output noise, and / or power efficiency). In one example, the second number of voltage regulators 320 is dynamically adjusted to maximize the power conversion efficiency used to drive the power rail. In other words, in some embodiments, at any point in time when the electronic device is powered on and supplies power to one or more other semiconductor devices (e.g., SoC 102) via power rail 206, a first subset of voltage regulators 320 is in an operating mode, and a second subset of voltage regulators 320 is in a bypass mode, as specified by the control settings of the corresponding voltage regulators (e.g., operation enable signal 312). The control settings are determined by the power array controller 302 based on the load information 314 and the power state policy.

[0063] During regulator adjustment procedure 402, additional voltage regulators 320D and 320E switch from standby mode to operating mode. The internal voltage regulator controllers of the voltage regulators 320A-320E driving power rail 206 dynamically adjust the operating points of these voltage regulators 320A-320E to correct for rail voltage errors in rail voltage VR associated with transient rail current IR. This regulator adjustment procedure 402 is relatively slow due to the time constant of the loop control filters involved in the voltage regulators 320A-320E. Specifically, the control loops of the additional voltage regulators 320D and 320E switching between modes may interfere with the operation of the control loops of the remaining voltage regulators 320A-320C already driving power rail 206 in operating mode, resulting in deviations in the rail voltage VR of power rail 206. Therefore, in some embodiments, any of the redundant voltage regulators 320B-320H operating in standby mode are biased to the same operating point (e.g., the same output voltage including the rail voltage VR) as other operating voltage regulators on the same power rail 206. This helps reduce interference to the output (i.e., rail voltage VR) of the operating voltage regulator 320 when the redundant voltage regulator 320 is added to the operating voltage regulator 320 while driving the power rail 206. Given the same operating point, each corresponding voltage regulator 320 associated with the power rail 206 is configured to transition from standby mode to operating mode and provide a predefined regulator current to the power rail 206 for a predefined period of time (e.g., within 1, 2, 5, or 10 microseconds).

[0064] Figure 5A is a block diagram of a voltage regulator 320, one of the voltage regulators in a field-programmable array 330, according to some embodiments. In the field-programmable array 330, a power rail 206 is electrically coupled to a plurality of voltage regulators 320, which are configured to collectively provide a corresponding rail voltage VR to the power rail. Each voltage regulator 320 includes an output interface 502, one or more drive paths 504, and a voltage regulator controller 506. The output interface 502 is electrically coupled to the power rail 206 to output the rail voltage VR. One or more drive paths 504 are coupled in parallel between the voltage regulator controller 506 and the output interface 502, and each drive path 504 is configured to operate during a corresponding phase and at an operating frequency to provide a corresponding path current IP to the power rail 206. The corresponding path current IP becomes part of the rail current IR injected into the power rail 206. The voltage regulator controller 506 is configured to receive control settings (e.g., control value 310 and operation enable signal 312) from the power array controller 302 and generate path control signals 508 to control one or more drive paths 504.

[0065] Voltage regulator 320 includes a feedback path 522 coupling output interface 502 to voltage regulator controller 506. Specifically, voltage regulator controller 506 has a feedback input 540 configured to receive the output voltage of output interface 502. Voltage regulator controller 506 is configured to dynamically adjust path control signal 508 based on the output voltage of output interface 502 and generate a rail voltage VR as defined by control value 310. Specifically, in some embodiments, path control signal 508 defines a duty cycle dynamically adjusted by voltage regulator controller 506 based on a comparison of the output voltage of output interface 502 with the rail voltage VR as defined by control value 310.

[0066] In some embodiments, the voltage regulator 320 includes a buck converter, i.e., a DC-DC switch-mode converter, which operates based on an integrated switch. Each drive path 504 includes a switching element 510 and a pulse width modulation (PWM) driver 512. The PWM driver 512 is coupled between the voltage regulator controller 506 and the switching element 510. The PWM driver 512 receives a periodic signal 514 (e.g., having a sine, square, triangular, or sawtooth waveform) and a path control signal 508 to control the switching element 510. Specifically, the path control signal 508 defines a duty cycle, and the periodic signal 514 has a frequency equal to the operating frequency of one or more drive paths 504. The PWM driver 512 is configured to modify the periodic signal 514 using the path control signal 508 to generate a switching signal 516. The switching element 510 is controlled by the switching signal 516 to turn on and off at an operating frequency according to the duty cycle. Switching component 510 is also coupled to DC power interface 316 and configured to be powered by a corresponding DC supply voltage Vin, which is thus output to switching output 518 of switching component 510 according to the duty cycle and operating frequency. Switching output 518 of switching component 510 is further regulated (e.g., filtered) by passive load component 520 to generate rail voltage VR. Rail voltage VR is output to power rail 206 via output interface 502. In some implementations, rail voltage VR is substantially constant (e.g., having an output ripple voltage less than the ripple tolerance) and has an average amplitude equal to the product of DC supply voltage Vin, duty cycle, and conversion efficiency of switching component 510.

[0067] Figure 5B is a block diagram of voltage regulator 320, which also includes a bypass unit 528 located inside the voltage regulator 320. In some embodiments, each individual voltage regulator 320 uses the bypass unit 528 to control the current output, independent of any other voltage regulator 320 configured to drive the same power rail 206. The bypass unit 528 is used to enable a standby mode, in which the voltage regulator 320 is disabled to not contribute to the rail current IR of the corresponding power rail 206. The standby mode can be optionally applied when a voltage regulator 320 (e.g., 320E in Figure 3) is applied to drive the power rail 206, or when no voltage regulator 320 (e.g., 320RA-320RD in Figure 3) is applied to drive any power rail 206. The bypass unit 528 is coupled to one or more drive paths 504 and voltage regulator controller 506, and is configured to provide dummy load components (e.g., including passive RC filters or active filters) to replace the load coupled to power rail 206 when voltage regulator 320 is in standby mode.

[0068] In standby mode, bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the input of voltage regulator controller 506, thereby disabling voltage regulator 320 from contributing to the corresponding rail current IR. In the example shown in FIG5B, a first switch 530A is inserted into each drive path 504 and disconnects the interconnection carrying switch signal 516 in each drive path 504, and switch 530B is inserted into the feedback path 522 and disconnects the feedback path 522. In some implementations, each of switches 530A and 530B includes a multiplexer and is controlled by signal 312 via operation received by voltage regulator 320. Bypass unit 528 is coupled between switches 530A and 530B in each drive path 504 and is configured to intercept switch signal 516 and decouple power rail 206 and feedback path 522 from voltage regulator controller 506. Thus, bypass unit 528 enables auxiliary path 532 to bypass feedback path 522 in standby mode. An example of the implementation of bypass unit 528 is illustrated in Figure 6 described below.

[0069] Figure 6 is a circuit diagram of a voltage regulator 320 according to some embodiments, which has an auxiliary loop 602 to facilitate a rapid transition between operation of the voltage regulator in bypass mode and operation of the voltage regulator in operating mode. A voltage regulator controller 506 is coupled to each of the drive paths 504A-504B and provides a path control signal 508 to each drive path. A feedback path 522 connects the output interface 502 of the drive paths 504A-504B to a feedback input 540 of the voltage regulator controller 506. In some embodiments, the voltage regulator controller 506 includes a digital-to-analog converter (DAC) 608, an error amplifier 610, and amplifier feedback circuitry, and is configured to implement pulse width modulation for the drive paths 504A-504B. The DAC 608 applies a control value 310 to generate a reference voltage (e.g., reference voltage 704 in Figure 7) received at the input of the error amplifier 610. The amplifier feedback circuitry and feedback path 522 dynamically control the rail voltage VR output at the output interface 502 to match the reference voltage. Specifically, the path control signal 508 is generated by the voltage regulator controller 506 to control the duty cycle of drive paths 504A-504B to match the rail voltage VR with the reference voltage. In some cases, the power array controller 302 also provides an operation enable signal 312 to each voltage regulator 320 to enable the generation of a corresponding rail voltage VR and a corresponding rail current IR. In some embodiments, the operation enable signal 312 may optionally be applied to control (e.g., enable and disable) the error amplifier 610 and / or DAC 608, thereby disabling the entire voltage regulator 320 when the voltage regulator 320 is a redundant voltage regulator not associated with any power rail 206 (e.g., 320RA-320RD in FIG. 3).

[0070] As explained above, voltage regulator 320 has a standby mode in which voltage regulator 320 (e.g., 320RA-320RD) is not enabled to supply power to any power rail 206, or in which voltage regulator 320 (e.g., 320H in FIG. 4B) is coupled to power rail 206 but is temporarily disabled to not contribute to the corresponding rail current IR of power rail 206. In some embodiments, regardless of whether voltage regulator 320 is coupled to any power rail 206, voltage regulator 320 includes one or more drive paths 504 and a bypass unit 528. Voltage regulator controller 506 of voltage regulator 320 has an output 508 coupled to one or more drive paths 504 and a feedback input 540 coupled to output interface 502 via feedback path 522. Bypass unit 528 is coupled to one or more drive paths 504 and voltage regulator controller 506 and is configured to provide dummy load component 604. In standby mode, when bypass unit 528 is enabled, auxiliary loop 602 is formed, which bypasses the feedback path 522 from the output interface 502 to the input of the voltage regulator controller 506 and drives the dummy load component 604 using one or more switching components 606. Therefore, auxiliary loop 602 includes bypass unit 528 and is enabled in standby mode to replace feedback path 522, disabling the voltage regulator 320 from contributing to the corresponding rail current IR of the power rail 206. When auxiliary loop 602 is enabled, feedback path 522 is disabled because the power regulator 320 is in standby mode.

[0071] Specifically, in standby mode, bypass unit 528 is enabled to bypass the switching element 510 and passive load element 520 of each drive path 504. Each drive path 504 also includes a multiplexer 530A coupled to the PWM driver 512, the switching element 510, and the bypass unit 528. The multiplexer 530A is configured to select the bypass unit 528 and deselect the switching element 510 in standby mode, and electrically couple the PWM driver 512 to the bypass unit 528. The voltage regulator 320 also includes a multiplexer 530B coupled between the feedback input 540 of the voltage regulator controller 506 and the output interface 502. The multiplexer 530B is configured to operate simultaneously with the multiplexer 530A of each drive path 504 to select the bypass unit 538 and deselect the output interface 502 for input to the voltage regulator controller 506. In some embodiments, the operation enable signal 312 is used to simultaneously control multiplexers 530A and 530B to enable standby mode. Through these means, in standby mode, the switching element 510 and passive load element 520 of each drive path 504 are bypassed via the bypass unit 528, while the voltage regulator controller 506 and the PWM driver 512 of each drive path 504 continue to operate together with the dummy load element 604 and the switching element 606 within the bypass unit 528.

[0072] In summary, when the voltage regulator 320 is in standby mode, an auxiliary loop 602 is formed (or enabled) to decouple the output interface 502 without completely shutting down the voltage regulator 320. The voltage regulator controller 506 and the PWM driver 512 of the drive path 504 remain operational, allowing the voltage regulator 320 to wake up quickly and maintain the desired transient response time when it resumes operation from standby mode and in operating mode. For example, in some cases, the voltage regulator controller 506 and the PWM driver 512 of the drive path 504 achieve a rapid switching to operating mode by maintaining the same operating point (e.g., the rail voltage VR at the feedback input 540) in both standby and operating modes. Furthermore, the switching element 510 of the drive path 504 is decoupled and disabled, and the dummy load element 604 and the switching element 1306 are designed to consume less power than the switching element 510 and the load element 520 of the drive path 504. In one example, voltage regulator 320 drives power rail 206 with a rail current of 1.5 A in operating mode and consumes less than 100 mA when driving dummy load component 604 and switching component 606 in standby mode. This efficiently saves power consumption of voltage regulator 320 in standby mode.

[0073] Conversely, in some embodiments or in some cases, the corresponding voltage regulator 320 (e.g., any of voltage regulators 320RA-320RD in FIG. 3) is not assigned to drive any power rail 206 and can be completely turned off or operated in standby mode. In standby mode, the voltage regulator controller 506 and the PWM driver 512 of drive path 504 are operational, and the bypass unit 528 is enabled to bypass the switching component 510 and the load component 520 of drive path 505. When coupled to power rail 206, such redundant voltage regulators 320 can output rail voltage VR when transitioning from standby mode to operating mode and rapidly contribute current to the corresponding rail current IR of power rail 206 (e.g., with transient response time). However, if the voltage regulator 320 is turned off, the voltage regulator controller 506 and the PWM driver 512 of drive path 504 are disabled under the control of the operation enable signal 312. When coupled to power rail 206, this redundant voltage regulator 320 must restart before it can contribute to the corresponding rail current IR of power rail 206 when transitioning from standby mode to operating mode. The restart procedure is typically slow when the voltage regulator 120 recovers from a fully off state, compromising a relatively long transient response time. However, applying the bypass unit 528 together with the operational voltage regulator controller 506 and PWM driver 512 allows for fast mode switching and low power consumption.

[0074] Figure 7 is a circuit diagram of an example voltage regulator 320 with a filter-based auxiliary loop 602 according to some embodiments. A compensator 702 is coupled to a drive path 504 and provides it with a path control signal 508. A feedback path 522 connects the output interface 502 of the voltage regulator 320 to the feedback input 540 of the compensator 702. The compensator 702 is connected to a DAC 608 and is configured to enable pulse width modulation for the drive path 504. The DAC 608 applies a control value 310 to generate a reference voltage 704, which is received at the reference input of the compensator 702. The compensator 702 dynamically controls the rail voltage VR output at the output interface 502 to match the reference voltage 704 output by the DAC 608. Specifically, the path control signal 508 is generated by the compensator 702 to control the duty cycle of the drive path 504 to match the rail voltage VR and the reference voltage 704. In some cases, the power array controller 302 also provides an operation enable signal 312 to each voltage regulator 320 to enable the generation of the corresponding rail voltage VR and the corresponding rail current IR, and the operation enable signal 312 controls the switch 530 to enable one of the standby mode and operating mode for the corresponding voltage regulator 320. In some embodiments, the compensator 702 is one of a type II compensator and a type III compensator. In some embodiments, for example for implementations where a phase margin exceeding a threshold phase margin is required to maintain stability of both the feedback loop and the auxiliary loop 602 corresponding to the feedback path 522, a type III compensator is used.

[0075] The switching component 510 of the drive path 504 includes an upper switching transistor 706A and a lower switching transistor 706B. The upper switching transistor 706A is coupled between the DC supply voltage VIN 202 and the passive load component 520, and is controlled by an upper quasi-shifter 708A that receives and converts the switching signal 516 generated by the PWM driver 512. The lower switching transistor 706B is coupled between a low DC supply voltage (e.g., ground, sometimes referred to as circuit ground) and the passive load component 520, and is controlled by a low quasi-shifter 708B that receives and converts the switching signal 516 generated by the PWM driver 512.

[0076] Voltage regulator 320 also includes a bypass unit 528, which is coupled to switches 530A and 530B at its input and output. Switch 530A' is inserted into drive path 504 and disconnects the interconnect carrying switch signal 516 in drive path 504, while switch 530A' is inserted into feedback path 522 and disconnects feedback path 522. Bypass unit 528 is coupled in parallel to switching component 510 and passive load component 520 of drive path 504 via switches 530A, 530A', 530B, and 530B'. Switches 530A and 530A' may optionally be two separate switches coupled to each other or integrated in a single-input dual-output multiplexer. Switches 530B and 530B' may optionally be two separate switches coupled to each other or integrated in a dual-input single-output multiplexer. In standby mode, switches 530A and 530B are enabled, and switches 530A' and 530B' are disabled, enabling auxiliary path 532 to bypass feedback path 522 from the output interface 502 to the feedback input of compensator 702. Therefore, voltage regulator 320 is disabled to not contribute to the corresponding rail current IR of the power rail 206 to which voltage regulator 320 is allocated for driving. In operating mode, switches 530A' and 530B' are enabled, and switches 530A and 530B' are disabled, disabling auxiliary path 532, and enabling switching component 510 and passive load component 520 to output rail voltage VR to power rail 206. Each of switches 530A, 530A', 530B, and 530B' is controlled via operation enable signal 312 or its complementary signal.

[0077] The bypass unit 528 includes a bypass switch component 606 having an upper switching transistor 714A and a lower switching transistor 714B. The upper switching transistor 714A is coupled between the DC supply voltage VIN 202 and the dummy load component 604 and is controlled by an upper alignment shifter 716A, which receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. The lower switching transistor 714B is coupled between a low DC supply voltage (e.g., ground) and the dummy load component 604 and is controlled by the lower alignment shifter 716B, which receives and converts the switching signal 516 generated by the PWM driver 512 in standby mode. In some embodiments not shown, the dummy load component 604 includes an inductor-capacitor (LC) resonant cavity. In some embodiments, the dummy load component 604 includes an active filter 720 to simulate an LC resonant cavity. The active filter 720 is coupled to the bypass output 722 of the bypass unit 528 and includes an operating amplifier and passive feedback components. In one example, the active filter 720 is a second-order Sallen-Key filter. Through these means, the auxiliary loop 602 is established based on the replicated power stage and the active filter 720, and closed-loop control of the voltage regulator 320 is achieved without engaging the output interface 502 of the voltage regulator 320.

[0078] In operating mode, switches 530A and 530B are disabled, and switches 530A' and 530B' are enabled. Control loop control is formed by a feedback path 522 from the output interface 502 to the feedback input of the compensator 702. The compensator 702 generates a path control signal 508 to control the drive path 504 to generate the rail voltage VR supplying power to the power rail 206. Conversely, in standby mode, the path control signal 508 is configured to replicate the power stage while reducing its size to lower power consumption. Driven via the switch signal 516, the active filter 720 achieves this reduction in power stage size and power saving. Specifically, given a reference voltage 704, the output voltage at the output interface 502 and the bypass output 722 is low-pass filtered by the compensator 702.

[0079] In some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in standby mode is substantially equal to (e.g., within a predefined error margin) the rail voltage VR output at the output interface 502 of the voltage regulator 320 in operating mode. Alternatively, in some embodiments, the bypass voltage output at the bypass output 722 of the voltage regulator 320 in standby mode is not equal to the rail voltage VR and has a deviation from the rail voltage VR by a less than threshold voltage difference. In some embodiments, the output interface 502 and the bypass output 722 of the voltage regulator 320 are configured to be physically close to each other on the PMIC die 118. Through these means, when the standby mode is changed to the operating mode, the voltage regulator 320 can provide a predefined regulator current IR and rail voltage VR to the power rail 206 for a predefined time period (e.g., within 10 microseconds).

[0080] Referring to FIG7, in some embodiments, the voltage regulator 320 includes only one drive path 504, and the bypass unit 528 includes only one bypass path 724 configured to bypass a portion of one drive path 504 of the voltage regulator 320 in standby mode. Alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504, and the bypass unit 528 includes multiple bypass paths 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320. The bypass paths 724 have the same number of paths as the drive paths 504, or a different number of paths. Furthermore, and alternatively, in some embodiments, the voltage regulator 320 includes multiple drive paths 504, and the bypass unit 528 includes only one bypass path 724 configured to bypass the multiple drive paths 504 of the voltage regulator 320 in standby mode.

[0081] Figure 8 is a circuit diagram of a plurality of voltage regulators 800 in a field-programmable array configured to drive a voltage regulator 206 according to some embodiments. The plurality of voltage regulators 800 includes a first voltage regulator 800A, a second voltage regulator 800B, and a third voltage regulator 800C. Voltage regulators 800A-800C are identical to each other. In this example, each voltage regulator 800 has the same circuit configuration as the voltage regulator 320 discussed above with reference to Figure 7. Specifically, each voltage regulator 800 includes a compensator 702 coupled to a drive path 504 and a bypass path 724. The compensator 702 provides a path control signal 508 to the drive path 504. A feedback path 522 connects the output interface 502 coupled to the drive path 504 to the feedback input 540 of the compensator 702. The reference input of compensator 702 is coupled to DAC 608 and configured to receive a reference voltage 704 generated by DAC 608 according to control value 310. Compensator 702 dynamically controls the rail voltage VR output at output interface 502 to match the reference voltage 704 by enabling pulse width modulation for drive path 504. Specifically, compensator 702 generates a path control signal 508 to control the duty cycle of drive path 504 to match rail voltage VR and reference voltage 704. Bypass unit 528 is coupled to bypass path 724, and switch 530 is applied to couple bypass unit 528 in parallel with PWM driver 512 and compensator 702, thereby allowing a portion of drive path 504, including output interface 502 coupled to power rail 206, to be bypassed in standby mode.

[0082] The output interface 502 of voltage regulators 800A-800C is electrically coupled to the same power rail 206. However, each of the voltage regulators 800A-800C is independently controlled to drive the power rail 206 via a different corresponding operation enable signal 312. In each voltage regulator 800, the operation enable signal 312 controls a switch 530 to selectively enable only one of the feedback path 522 and the auxiliary path 532. Furthermore, the voltage regulators 800A-800C share the same DC supply voltage VIN 202 and a low DC supply voltage (e.g., ground) coupled to the switching component 510 and the bypass switching component 606. In some embodiments, the control values ​​310 of the voltage regulators 800A-800C are identical to each other, such that the PWM driver 512 of the voltage regulators 800A-800C generates switching signals 516 with the same duty cycle in the different voltage regulators 800A-800C. Alternatively, in some embodiments, the control value 310 of the voltage regulators 800A-800C is independently controlled using the operation enable signal 312 of the voltage regulators 800A-800C.

[0083] In some cases, each of the first voltage regulator 800A and the second voltage regulator 800B operates in operating mode to drive the power rail 206. In operating mode, feedback paths 522 of the respective voltage regulators 800A and 800B are enabled between the output interface 502 and the feedback input 540. Conversely, in standby mode, the third voltage regulator 800C is electrically decoupled from the power rail 206, and in standby mode, the bypass unit 528 of the third voltage regulator 800C is enabled to bypass the feedback path 522 of the third voltage regulator 800C.

[0084] Alternatively, in some cases, each of the first voltage regulator 800A and the second voltage regulator 800B operates in standby mode, and the bypass unit 528 of the respective voltage regulators 800A and 800B is enabled to bypass the feedback path 522 between the output interface 502 of the respective voltage regulators 800A and 800B and the feedback input 540. Conversely, the third voltage regulator 800C operates in operating mode, wherein in operating mode, the feedback path 522 of the voltage regulator 800C is enabled between the output interface 502 of the voltage regulator 800C and the feedback input 540. Alternatively and additionally, in some cases, all three voltage regulators 800A-800C operate in operating mode, in which the feedback path 522 of each and every voltage regulator 800A-800C is enabled between the output interface 502 of the respective voltage regulator 800A-800C and the feedback input 540.

[0085] Referring to Figure 8, a plurality of voltage regulators 800 are configured to drive power rail 206 in a configurable manner. In some embodiments, each voltage regulator 800 is fine-tuned to minimize relative mismatches (e.g., offset errors, gain errors, and / or bandwidth errors) with other voltage regulators 800. In-situ and parallel fine-tuning mechanisms are optionally applied to SoC 102 and PMIC 118, which are fully integrated or assembled, as shown in Figure 1B. During in-situ and parallel fine-tuning, each voltage regulator 800 enables its corresponding auxiliary loop 602 and disables its corresponding feedback path 522. Through these means, the gain and offset errors of each voltage regulator 800 are adjusted without causing power supply sequence problems.

[0086] In some cases, multiple voltage regulators 800 are powered on. When a DC supply voltage (e.g., voltage 202) is initially applied, the voltage difference between the rail voltages VR output by the feedback-based voltage regulators 800 is large, causing the voltage regulators 800 to react against each other and slowing down the power-on process of the voltage regulators 800. This is undesirable for rapid power state transitions. To avoid this situation, in some embodiments, voltage regulators 800 coupled to the same power rail are pre-regulated using an analog signal level before being coupled to power rail 206. Specifically, in some cases, the output interface 502 of the voltage regulator 800 is electrically decoupled from power rail 206 when the DC supply voltage is initially applied. During the power-on process of each voltage regulator 800, standby mode and operating mode are applied sequentially. During power-on operation, the auxiliary circuit 602 of each voltage regulator 800 is first activated until the corresponding voltage regulator 800 stabilizes to output rail voltage VR at bypass output 722, and the feedback path 522 is then activated to couple the corresponding voltage regulator 800 to power rail 206.

[0087] Alternatively, during power-on operation, each voltage regulator 800 is activated in operating mode. The output voltage at the output interface 502 of each voltage regulator 800 is monitored and compared to a threshold start-up voltage. For each voltage regulator 800, based on a decision that the output voltage exceeds the threshold start-up voltage, the output interface 502 of the voltage regulator 800 is electrically coupled to the power rail 206. More specifically, in one example, the threshold start-up voltage is 1V, and the rail voltage VR is 1.8V. Voltage regulators 800A-800C are each powered on separately to avoid counter-current between regulators. Depending on the voltage regulator 800A-800C, the output voltage at the output interface 502 of the voltage regulator (e.g., 800A) is determined to reach 1 V. The output interface 502 of the voltage regulator (e.g., 800A) is electrically coupled to the power rail 206, for example, by using a switch coupled between the output interface 502 of the voltage regulator (e.g., 800A) and the power rail 206.

[0088] During power-on testing, the normal loop of each voltage regulator 800 on PMIC 118 operates to ramp up the rail voltage VR to drive SoC 102. In some cases, one of SoC 102 and PMIC 118 may fail, resulting in a hardware failure condition. For field fault diagnosis, the location of the fault needs to be identified from the different voltage regulators 800 of SoC 102 and PMIC 118. Therefore, each of SoC 102 and voltage regulator 800 can be isolated and monitored separately, i.e., each SoC 102 or voltage regulator 800 can operate independently with any other SoC 102 or voltage regulator 800. In one example, each voltage regulator 800 is decoupled from SoC 102 or other voltage regulator 800 by entering a standby mode, in which bypass unit 528 is enabled to bypass the feedback path 522 from output interface 502 to feedback input 540 of compensator 702.

[0089] Figure 9A is a circuit diagram of a portion 900 (hereinafter referred to herein as multiphase drive portion 900) of a voltage regulator 320 having a plurality of drive paths 504 according to some embodiments, and Figure 9B is a circuit diagram of another portion 920 (hereinafter referred to herein as multiphase bypass portion 920) of a voltage regulator 320 having a plurality of bypass paths 724 according to some embodiments. The drive portion 900 corresponds to portions of two parallel drive paths 504A and 504B, and the bypass portion 920 corresponds to two parallel bypass paths 724A and 724B. Each portion of drive path 504A or 504B of the drive portion 900 and the corresponding bypass path 724 of the bypass portion 920 are coupled in parallel to each other via a switch 530. Referring to Figure 5B, the switch 530 selects either the drive portion 900 or the bypass portion 920 (e.g., one of them) to be electrically coupled to the feedback input 540 of the PWM driver 512 and the voltage regulator controller 506. In addition to drive path 504, drive section 900 also includes an output interface 502 coupled to each drive path 504. As shown in a complete voltage regulator schematic (e.g., in FIG. 6), output interface 502 is coupled to feedback input 540 of voltage regulator controller 506. Output interface 502 is also coupled to power rail 206 and is configured to supply rail voltage VR generated by voltage regulator 320 to power rail 206 and deliver up to a predefined regulator current.

[0090] Each drive path 504 (e.g., 504A or 504B) includes a switching element 510 (as shown in FIG. 6), a passive load element 520, and a PWM driver 512, and is arranged parallel to other drive paths 504 in the same voltage regulator 320. Each drive path 504 is configured to operate during a corresponding phase and at an operating frequency to provide a corresponding path current IP to the power rail 206. The corresponding path circuit IP becomes part of the rail current IR injected into the power rail 206. The drive section 900 (FIG. 9A) includes a first number of drive paths 504, and the bypass section 920 (FIG. 9B) has a second number of bypass paths 724. Optionally, the second number is equal to the first number, such that each bypass path 722 is configured to bypass the switching element 510 and the passive load element 520 of the corresponding single drive path 504. The same PWM driver 512 that drives the corresponding single drive path 504 in operating mode is configured to drive the corresponding bypass path 724 in standby mode. Therefore, in standby mode, each bypass path 724 is configured to operate during the corresponding phase and at the operating frequency, and different bypass paths 722 may optionally have different phases under the control of different PWM drivers 512.

[0091] In some embodiments, bypass portion 920 serves as bypass unit 528 of voltage regulator 320 (e.g., in FIG. 5B). In some embodiments, bypass portion 920 includes a plurality of bypass switching components (e.g., component 606 in FIG. 6, or components 714A and 714B in FIG. 9B and 9D) and a single dummy load component 604 coupled between the plurality of bypass switching components 606 and the bypass output 722 of bypass unit 528. In this example, dummy load component 604 includes an active filter 720 (e.g., a second-order Sallen-Key filter), and the plurality of bypass paths 724 of bypass unit 528 share the same active filter 720. From this perspective, the active filter 720 acts as a summing filter with multiple inputs from the parallel bypass switching components 606. Conversely, in some embodiments not illustrated in Figures 9B and 9D, the bypass unit 528 has a plurality of bypass paths 724, and each bypass path 724 has a different bypass switch component 606 coupled to a different active filter 720. The bypass outputs 722 of the different active filters 620 may optionally be coupled to or decoupled from each other.

[0092] Each bypass switch component 606 corresponds to a corresponding drive path 504 and is configured to bypass a portion of the corresponding drive path 504 in standby mode. Specifically, the switch component 510 of the drive path 504 includes an upper switching transistor 706A configured to establish a current path to the DC supply voltage VIN 202 and a lower switching transistor 706 configured to establish a current path to a low DC supply voltage (e.g., ground). The bypass switch component 606 of the bypass path 724 also has an upper switching transistor 714A configured to establish a current path to the DC supply voltage VIN 202 and a lower switching transistor 714B configured to establish a low DC supply voltage (e.g., ground). In some embodiments, the upper switching transistor 714A of the bypass path 724 has a smaller transistor size compared to the upper switching transistor 706A of the drive path 504, while the lower switching transistor 714B of the bypass path 724b has a smaller transistor size compared to the lower switching transistor 706B of the drive path 544.

[0093] Figures 9C and 9D are circuit diagrams of equivalent circuits 940 and 960 of a voltage regulator 320 operating in an operating mode and a bypass mode, respectively, according to some embodiments. The voltage regulator 320 is a two-phase buck converter. In standby mode (Figure 9D), bypass unit 528 is enabled to bypass the feedback path 522 from the output interface 502 to the feedback input 540 of the voltage regulator controller 506 (specifically, the compensator 702 therein), and the voltage regulator 320 does not supply current to the power rail 206. The voltage regulator 520 has a first alternating current (AC) loop response in standby mode. The first AC loop response has a first low-frequency gain, a first cutoff frequency, and a first phase margin. In operating mode (Figure 9C), bypass unit 528 is disabled to prevent bypassing the feedback path 522, and the voltage regulator 320 supplies up to a predefined regulator current to the power rail 206. The voltage regulator 120 has a second AC loop response in operating mode. The second AC circuit response has a second low-frequency gain, a second cutoff frequency, and a second phase margin. The first and second low-frequency gains are substantially equal to each other, for example, having a first gain difference less than a first threshold. The first and second cutoff frequencies are substantially equal to each other, for example, having a second frequency difference less than a second threshold (such as 5 kHz). The first and second phase margins are substantially equal to each other, for example, having a third phase margin difference less than a third threshold (such as 5°).

[0094] Voltage regulator 320 incorporates active filter 720 in bypass unit 528. Active filter 720 provides an LC filter frequency response with a sufficient quality factor (e.g., greater than a quality factor threshold). In standby mode, auxiliary loop 602 is stabilized based on phase margin and gain margin. The phase margin is greater than a phase margin threshold, and the gain margin is greater than a gain margin threshold. Active filter 720 includes operational amplifier 902, which has sufficient drive capability for large loads (e.g., loads greater than a threshold load). Furthermore, in operating mode, bypass output 722 is decoupled from power rail 206 and therefore does not interfere with the operation of SoC 102 coupled to power rail 206.

[0095] In some embodiments (e.g., in FIG9C), a bypass unit 528 having one or more bypass paths 724 is applied in a buck converter to bypass the feedback path 522. It should be noted that in some embodiments, a bypass unit 528 having one or more bypass paths 724 is similarly applied in a boost converter or buck-boost converter to bypass the feedback path 522.

[0096] Figure 10 is a flowchart of a method 1000 for driving a power rail 206 of an electronic device according to some embodiments. In some embodiments, the electronic device includes an integrated semiconductor device 180 that vertically integrates a SoC 102 and a PMIC 118. In some embodiments, the electronic device includes a SoC 102 and a PMIC 118 mounted on a circuit board. The power rail 206 is provided by the PMIC 118 to drive the operation of the SoC 102. The electronic device has a plurality of voltage regulators 320 electrically coupled to the power rail 206 and configured to provide a rail voltage VR and a rail current IR to one of the power rails 206.

[0097] The electronic device generates a rail voltage VR and a rail current IR and provides them to the power rail 206 (1002). Each corresponding voltage regulator 320 has an output interface (1004) coupled to the power rail 206 and configured to provide the rail voltage VR to the power rail 206 and deliver up to a predefined regulator current when the corresponding voltage regulator 320 is in operation mode. The electronic device obtains (1006) control settings for each of the plurality of voltage regulators. The control settings for each corresponding voltage regulator 320 determine (1008) whether the corresponding voltage regulator 320 is a standby voltage regulator operating in standby mode or an operating voltage regulator operating in operation mode. Each standby voltage regulator 320 (e.g., regulator 800C in FIG. 8) enables (1010) the standby voltage regulator bypass unit 528 to bypass the feedback path 522 from the output interface 502 to the input 540 of the voltage regulator controller 506, so that the standby voltage regulator 320 does not supply current to the power rail 206. Each operating voltage regulator 320 (e.g., regulator 800A or 800B in FIG. 8) disables (1012) the bypass unit 528 to prevent the feedback path 522 from being bypassed, so that the corresponding voltage regulator 320 supplies current to the power rail 206.

[0098] In some embodiments, each of the plurality of voltage regulators, with its corresponding voltage regulator 320, is configured to transition from a standby mode to an operating mode according to a change in control settings, and to supply a predefined regulator current to the power rail 206 for a predefined time period (e.g., within 1, 2, 5, or 10 microseconds). That is, in some cases, the predefined time period is in the range of 0.1 to 10 microseconds. Given that each voltage regulator 320 is not completely turned off in standby mode, the corresponding voltage regulator 320 can quickly switch from standby mode to operating mode to supply the predefined regulator current to the power rail 206.

[0099] In some embodiments, for each respective voltage regulator 320, the control settings include a control value 310 and an operation enable signal 312. The control value 310 defines the magnitude of the rail voltage VR, and the operation enable signal 311 is configured to control the respective voltage regulator 320 to operate in standby mode or operating mode. In standby mode, the bypass unit 528 is enabled to bypass the feedback path 522; in operating mode, the bypass unit 528 is disabled to prevent the feedback path 522 from being bypassed, thereby controlling the total current injected into the power rail 206 in association with the rail voltage VR. Specifically, the operation enable signal 312 is applied to control the switch 530 to select either the bypass unit 528 or the feedback path 522 to be electrically coupled to the voltage regulator controller 506 and the PWM driver 512.

[0100] In some embodiments, each respective voltage regulator 320 includes one or more drive paths 504 coupled to the output interface 502 and is configured to operate at an operating frequency. A voltage regulator controller 506 of the respective voltage regulator 320 has an output 508 coupled to the one or more drive paths 504 and an input 540 coupled to the output interface 502 via a feedback path 522. The voltage regulator controller 506 is configured to control the one or more drive paths 504 and a bypass unit 528.

[0101] In some embodiments, the electronic device dynamically and instantaneously determines (1014) the control settings for each corresponding voltage regulator 320 coupled to the power rail 206 based on the load conditions and power state strategy associated with the power rail 206.

[0102] In some embodiments, referring to FIG5B, each voltage regulator includes one or more drive paths 504 coupled to an output interface 502 and a voltage regulator controller 506. Each drive path 505 also includes: a passive load component 520 coupled to the output interface 502; a driver 512 configured to receive a periodic signal 514 having an operating frequency and modulate the periodic signal 514 to provide a switching signal 516 having a different phase; and a power switch component 510 coupled to the driver 512 and the passive load component 520. The power switch component 510 is configured to couple the passive load component 520 to one or more DC supply voltages VIN under the control of the switching signal 516. Furthermore, in some embodiments, in standby mode, bypass unit 528 is enabled to bypass the power supply component 510 and passive load component 520 of each drive path 504, and each drive path 504 also includes a first multiplexer 530A coupled to driver 512, power switch component 510, and bypass unit 528. The first multiplexer 530A is configured to be controlled via a control setting (specifically, operation enable signal 312) to enable standby mode, i.e., to select access to bypass unit 528 and deselect access to power switch component 510, electrically coupled to driver 512 of drive path 504. Additionally, each voltage regulator 320 also includes a second multiplexer 530B coupled to input 540 of voltage regulator controller 506, output interface 502 of power rail 206, and bypass output 722 of bypass unit 528. The second multiplexer 530B is configured to be controlled simultaneously with the first multiplexer 530A via a control setting (specifically, operation enable signal 312) to enable standby mode, that is, to select the bypass output 722 of the bypass unit 528 and deselect the output interface 502 of the power rail 206 to couple to the input 540 of the voltage regulator controller 506.

[0103] In some embodiments, referring to Figures 6 and 7, the bypass unit 538 includes one or more bypass paths 724, and each bypass path 723 includes a corresponding bypass switch component 606 having a bypass switch transistor 714 of a first size. The switch component 510 of each drive path 504 has a path switch transistor 706 having a second size. The second size of the path switch transistor 706 is larger than the first size of the bypass switch transistor 714.

[0104] In some embodiments, a plurality of voltage regulators 320 are electrically coupled to a power array controller 506. The power array controller 506 is configured to determine control settings for each voltage regulator 320 coupled to the power rail 206. Furthermore, in some embodiments, for each voltage regulator 320, the control settings are dynamically and instantaneously adjusted by the power array controller 506 based on load conditions and power state policies associated with the power rail 206. For example, the power state policy requires that the control settings maximize the power conversion efficiency of the plurality of voltage regulators, or that the quality factor of the voltage regulator 320 is greater than a quality factor threshold.

[0105] In various embodiments of this invention, the PMIC has a field-programmable array of voltage regulators configured to provide rail voltages to a plurality of power rails. Each power rail is associated with a plurality of identical voltage regulators in the field-programmable array, and in some embodiments, the field-programmable array also includes one or more redundant voltage regulators not used to drive any power rail. In some cases, for each power rail, all identical voltage regulators are coupled to drive the corresponding power rail to provide maximum drive capability, while in other cases, a subset of standby voltage regulators may be decoupled from the corresponding power rail during the standby duration. During the standby duration, a standby mode is enabled to convert voltage regulators driving the power rail in operating mode to redundant or standby voltage regulators. In this standby mode, bypass units of the voltage regulators are enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the voltage regulators do not supply current to the corresponding power rail. The voltage regulator is not completely shut down in standby mode and can be switched to operating mode to rapidly supply a predefined regulator current to the power rail (e.g., within microseconds).

[0106] An implementation example is described in at least the following numbered clauses:

[0107] Clause 1: An electronic device comprising: a power rail configured to provide a rail voltage; a plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage, each of the plurality of voltage regulators comprising: an output interface coupled to the power rail and configured to provide the rail voltage to the power rail and deliver up to a predefined regulator current; one or more drive paths coupled to the output interface and configured to operate at an operating frequency; and a voltage regulator controller having an output coupled to the one or more drive paths and an input coupled to the output interface via a feedback path, and configured to... The controller controls one or more drive paths; and a bypass unit coupled to the one or more drive paths and the voltage regulator controller; wherein each of the plurality of voltage regulators is configured to operate in a standby mode or an operating mode according to a control setting, in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the corresponding voltage regulator does not supply current to the power rail; in which the bypass unit is disabled to not bypass the feedback path, and the corresponding voltage regulator supplies up to the power rail a predefined regulator current.

[0108] Clause 2: An electronic device pursuant to Clause 1, wherein each of the plurality of voltage regulators is configured to switch from the standby mode to the operating mode according to a change in the control setting, and to supply the predefined regulator current to the power rail for a predefined time period.

[0109] Clause 3: Electronic equipment pursuant to Clause 1, wherein for each respective voltage regulator, the control setting includes a control value and an operation enable signal, the control value defining the magnitude of the rail voltage, and the operation enable signal being configured to control the respective voltage regulator to operate in either a standby mode or an operating mode, wherein in the standby mode the bypass unit is enabled to bypass the feedback path, and in the operating mode the bypass unit is disabled to prevent the feedback path from being bypassed.

[0110] Clause 4: An electronic device pursuant to Clause 1, wherein each of the one or more drive paths also includes: a passive load component coupled to the output interface; a driver configured to receive a periodic signal having an operating frequency and modulate the periodic signal to provide a switching signal having a different phase; and a power switch component coupled to the driver and the passive load component, the power switch component being configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal.

[0111] Clause 5: An electronic device pursuant to Clause 4, wherein in the standby mode, the bypass unit is enabled to bypass the power switching component and the passive load component of each drive path, and each of the one or more drive paths also includes: a first multiplexer coupled to the driver, the power switching component and the bypass unit, wherein the first multiplexer is configured to be controlled via the control settings to enable the standby mode, in which the first multiplexer selects access to the bypass unit and deselects access to the power switching component to electrically couple to the driver of the drive path.

[0112] Clause 6: In the electronic device pursuant to Clause 5, each corresponding voltage regulator also includes: a second multiplexer coupled to the input of the voltage regulator controller, the output interface of the power rail, and the output of the bypass unit, wherein the second multiplexer is configured to be controlled simultaneously with the first multiplexer via the control setting to enable the standby mode, in which the second multiplexer selects the output of the bypass unit and deselects the output interface of the power rail to couple to the input of the voltage regulator controller.

[0113] Clause 7: An electronic device pursuant to Clause 5, wherein: the bypass unit includes one or more bypass paths, each bypass path including a corresponding bypass switching component of a bypass switching transistor having a first size; the power switching component of each drive path has a path switching transistor having a second size; and the second size of the path switching transistor is larger than the first size of the bypass switching transistor.

[0114] Clause 8: An electronic device pursuant to any one of Clauses 1-7, wherein the plurality of voltage regulators are electrically coupled to a power array controller, and the power array controller is configured to determine control settings for each voltage regulator coupled to the power rail.

[0115] Clause 9: Electronic devices pursuant to Clause 8, wherein for each voltage regulator, the control settings are dynamically and instantaneously adjusted by the power array controller based on the load conditions and power state policies associated with the power rail.

[0116] Clause 10: An electronic device according to any one of Clauses 1-6, wherein the bypass unit includes one or more bypass paths, each bypass path having a corresponding bypass switch component and a corresponding dummy load component, the dummy load component being coupled between the bypass switch component and the output of the bypass unit, each bypass path being configured to bypass the corresponding drive path of the feedback path in the standby mode.

[0117] Clause 11: Electronic devices pursuant to Clause 10, wherein for each bypass path, the corresponding dummy load component includes an active filter.

[0118] Clause 12: Electronic devices pursuant to Clause 11, wherein the active filter is a second-order Sallen-Key filter.

[0119] Clause 13: An electronic device according to any one of Clauses 1-12, wherein for each respective voltage regulator, the bypass unit is electrically decoupled from the power rail in the standby mode and is configured to output the rail voltage and provide the rail voltage to the input of the voltage regulator controller in the standby mode, such that when the standby mode is changed to the operating mode, the respective voltage regulator is able to provide the predefined regulator current to the power rail for a predefined time period.

[0120] Clause 14: An electronic device pursuant to Clause 1, wherein: the bypass unit includes one or more bypass switching components and a dummy load component, the dummy load component being coupled between the one or more bypass switching components and the output of the bypass unit; and in the standby mode, each bypass switching component is coupled to a corresponding drive path.

[0121] Clause 15: An electronic device pursuant to Clause 14, wherein the dummy load component includes one of an active filter, and the active filter is a Sallen-Key filter.

[0122] Clause 16: An electronic device according to any one of Clauses 1-15, wherein: the plurality of voltage regulators includes a first voltage regulator, a second voltage regulator, and a third voltage regulator; each of the first voltage regulator and the second voltage regulator operates in the operating mode to drive the power rail, and in the operating mode, the feedback path of the respective voltage regulator is enabled between the output interface of the respective voltage regulator and the input; the third voltage regulator is electrically decoupled from the power rail in the standby mode, and in the standby mode, the bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator.

[0123] Clause 17: An electronic device according to any one of Clauses 1-16, wherein the plurality of voltage regulators coupled to the power rail are identical to each other.

[0124] Clause 18: An electronic device according to any one of Clauses 1-17, wherein: each voltage regulator has a first AC loop response in the standby mode, the first AC loop response having a first low-frequency gain, a first cutoff frequency, and a first phase margin; each voltage regulator has a second AC loop response in the operating mode, the second AC loop response having a second low-frequency gain, a second cutoff frequency, and a second phase margin; a first difference between the first low-frequency gain and the second low-frequency gain is less than a first threshold; a second difference between the first cutoff frequency and the second cutoff frequency is less than a second threshold; and a third difference between the first phase margin and the second phase margin is less than a third threshold.

[0125] Clause 19: A method for driving a power rail, further comprising: at an electronic device having a plurality of voltage regulators electrically coupled to the power rail: generating a rail voltage and a rail current to drive the power rail, each respective voltage regulator having an output interface coupled to the power rail and configured to provide the rail voltage to the power rail and deliver up to a predefined regulator current when the respective voltage regulator is in an operating mode; obtaining control settings for each of the plurality of voltage regulators for determining whether the respective voltage regulator is a standby voltage regulator operating in a standby mode or an operating voltage regulator operating in the operating mode; at each standby voltage regulator, enabling a bypass unit of the standby voltage regulator to bypass a feedback path from the output interface to an input of the voltage regulator controller, such that the standby voltage regulator does not deliver current to the power rail; and at each operating voltage regulator, disabling the bypass unit to prevent the feedback path from being bypassed, such that the respective voltage regulator delivers current to the power rail.

[0126] Clause 20: The method according to Clause 19, wherein each respective voltage regulator includes one or more drive paths coupled to the output interface and configured to operate at an operating frequency, the voltage regulator controller of the respective voltage regulator has an output coupled to the one or more drive paths and an input coupled to the output interface via the feedback path, and is configured to control the one or more drive paths, the bypass unit coupled to the one or more drive paths, and the voltage regulator controller.

[0127] Clause 21: The method according to Clause 19 also includes: dynamically and in real time determining the control settings for each corresponding voltage regulator coupled to the power rail based on the load conditions and power state policies associated with the power rail.

[0128] Clause 22: A non-transitory computer-readable storage medium storing one or more programs executable by a plurality of voltage regulator electronic devices electrically coupled to a power rail, the one or more programs including instructions, when executed by the electronic device, to cause the electronic device to perform the method according to any one of Clauses 19-22.

[0129] Clause 23: An apparatus for driving a power rail at an electronic device having a plurality of voltage regulators electrically coupled to the power rail, comprising at least one unit for the method according to any one of Clauses 19-22.

[0130] The above description has been provided with reference to specific implementations. However, the above illustrative discussion is not intended to be exhaustive or limited to the precise form revealed. In view of the above teachings, many modifications and variations are possible. These implementations were chosen and described in order to best explain the revealed principles and their practical applications, thereby enabling others to best utilize the content of this case and various implementations with modifications suitable for the specific intended use.

[0131] The terminology used in the various implementations described herein is for the purpose of describing a particular implementation only and is not intended to be limiting. As used in the implementations of the various descriptions and the descriptions of the appended claims, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It will also be understood that the term "and / or" as used herein is intended to include any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," when used in this specification, specify the presence of that feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0132] As used herein, the term "if" may be interpreted as meaning "when," "at," "in response to a decision," "in response to detection," or "according to a decision," depending on the context. Similarly, the phrases "if a decision" or "if [the condition or event] is detected" may be interpreted as meaning "when a decision is made," "in response to a decision," "when [the condition or event] is detected," "in response to the detection of [the condition or event]," or "according to the decision that [the condition or event] is detected," depending on the context.

[0133] Although the diagrams illustrate multiple logical stages in a specific order, stages that are not dependent on the order can be reordered, and other stages can be combined or decomposed. While some reorderings or other encapsulations are specifically mentioned, other reorderings or encapsulations will be apparent to those skilled in the art to which this invention pertains, and therefore the orderings and encapsulations provided herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that these stages can be implemented in hardware, firmware, software, or any combination thereof.

[0134] 100: System Module 102: System-on-a-Chip (SoC) 104: Memory Module 106: Input / Output (I / O) Controller 108: Network Interface 110: Memory controller 112: Solid State Drive (SSD) 114: Hard Drive 116: Power connector 118: Power Management Integrated Circuit (PMIC) 120: Graphics Module 122: Sound Module 124: Packaging substrate 124A: First surface 124B: Second Surface 126: First through-hole interconnect 128: DC Connection 130: Communication Bus 132: Power Connection 134: Capping 136: Heat exchanger 138: Socket substrate 138A: Third Surface 140: Electrical connector 142: Depressed portion 144: First Intermediary Layer 146: Second through-hole interconnect 148: Second Intermediary Layer 150: Inductor 150': Inductor 152: Third through-hole interconnect 160: Electronic Module 160A: Component 160B: Component 180: Semiconductor devices 200: Power Management System 202: Input DC power supply voltage 204: Digital power control signal 206-1: Power Rail 206-2: Power Rail 206-3: Power Rail 206-4: Power Rail 206A: Power Rail 206B: Power Rail 206N: Power rail 208: Power Management Interface 210N: DC-DC converter 212A: Output Filter 212B: Output Filter 212N: Output Filter 214: Output resistor 216: Output capacitor 216A: Output capacitor 216B: Output capacitor 216N: Output capacitor 300: Semiconductor Devices 302: Power Array Controller 304: Microprocessor or CPU core 306: Memory 308: Communication Module 310: Control value 312: Operation Enable Signal 314: Load Information 316: DC Power Interface 320: Voltage Regulator 320A: First voltage regulator 320B: Redundant Voltage Regulator 320C: Redundant Voltage Regulator 320D: Redundant Voltage Regulator 320E: Redundant Voltage Regulator 320F: Redundant Voltage Regulator 320G: Redundant Voltage Regulator 320H: Redundant voltage regulator 320I: Voltage Regulator 320RA: Voltage Regulator 320RB: Voltage Regulator 320RC: Voltage Regulator 320RD: Voltage Regulator 330: Field Programmable Array 400: Program 402: Regulator Adjustment Procedure 450: Program 502: Output Interface 504: Driver Path 504A: Driver Path 504B: Driver Path 506: Voltage Regulator Controller 508: Path control signal 510: Switching components 512: Pulse Width Modulation (PWM) Driver 514: Periodic signal 516: Switch signal 518: Switch Output 520: Passive load components 522: Feedback Path 528: Bypass Unit 530A: Multiplexer 530A': Switch 530B: Switch 530B': Switch 532: Auxiliary Path 540: Feedback Input 602: Auxiliary Circuit 604: Dummy load component 606: Bypass switch component 608: Digital-to-Analog Converter (DAC) 610: Error Amplifier 702: Compensator 704: Reference Voltage 706A: Upper switching transistor 706B: Lower switching transistor 708A: Upper part alignment shifter 708B: Low-level shifter 714A: Upper switching transistor 714B: Lower switching transistor 716A: Upper part alignment shifter 716B: Lower part quasi-shifter 720: Active Filter 722: Bypass Output 724: Bypass Path 724A: Parallel Bypass Path 724B: Parallel Bypass Path 800: Voltage Regulator 800A: First voltage regulator 800B: Second Voltage Regulator 800C: Third Voltage Regulator 900: Driver section 920: Bypass section 940: Equivalent Circuit 960: Equivalent Circuit 1000: Method 1002: Square 1004: Square 1006: Square 1008: Square 1010: Square 1012: Square 1014: Square IR: Rail current VR: Rail Voltage Vin: DC power supply voltage

[0135] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An electronic device, comprising: It is configured to provide a single power rail with a single voltage rail. A plurality of voltage regulators electrically coupled to the power rail and configured to collectively provide the rail voltage, each of the plurality of voltage regulators including: an output interface coupled to the power rail and configured to provide the rail voltage to the power rail and deliver up to a predefined regulator current; One or more drive paths coupled to the output interface and configured to operate at an operating frequency; a voltage regulator controller having an output coupled to the one or more drive paths and an input coupled to the output interface via a feedback path, and configured to control the one or more drive paths; and a bypass unit coupled to the one or more drive paths and the voltage regulator controller; wherein each of the plurality of voltage regulators is configured to operate in a standby mode or an operating mode according to a control setting, in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, and the corresponding voltage regulator does not supply current to the power rail, and in which the bypass unit is disabled to not bypass the feedback path, and the corresponding voltage regulator supplies up to the power rail a predefined regulator current.

2. The electronic device according to claim 1, wherein each of the plurality of voltage regulators is configured to: switch from the standby mode to the operating mode according to a change in the control setting, and provide the predefined regulator current to the power rail for a predefined time period.

3. The electronic device according to claim 1, wherein for each corresponding voltage regulator, the control setting includes a control value and an operation enable signal, the control value defining an amplitude of the rail voltage, and the operation enable signal being configured to control the corresponding voltage regulator to operate in either a standby mode or the operating mode, wherein in the standby mode the bypass unit is enabled to bypass the feedback path, and in the operating mode the bypass unit is disabled to prevent the feedback path from being bypassed.

4. The electronic device according to claim 1, wherein each of the one or more drive paths also includes: A passive load component coupled to the output interface; A driver configured to: receive a periodic signal having an operating frequency and modulate the periodic signal to provide a switching signal having a different phase; and a power switching component coupled to the driver and the passive load component, the power switching component being configured to couple the passive load component to one or more DC supply voltages under the control of the switching signal.

5. The electronic device according to claim 4, wherein in the standby mode, the bypass unit is enabled to bypass the power switching component and the passive load component of each drive path, and each of the one or more drive paths also includes: A first multiplexer coupled to the driver, the power switch component, and the bypass unit, wherein the first multiplexer is configured to be controlled via the control settings to enable the standby mode, in which the first multiplexer selects an access to the bypass unit and deselects an access to the power switch component to electrically couple to the driver of the drive path.

6. The electronic device according to claim 5, each corresponding voltage regulator also includes: A second multiplexer coupled to the input of the voltage regulator controller, the output interface of the power rail, and an output of the bypass unit, wherein the second multiplexer is configured to be controlled simultaneously with the first multiplexer via the control settings to enable the standby mode, in which the second multiplexer selects the output of the bypass unit and deselects the output interface of the power rail to couple to the input of the voltage regulator controller.

7. The electronic device according to claim 4, wherein: The bypass unit includes one or more bypass paths, each bypass path including a corresponding bypass switch component having a bypass switch transistor of a first size; the power switch component of each drive path has a path switch transistor having a second size; and the second size of the path switch transistor is larger than the first size of the bypass switch transistor.

8. The electronic device according to claim 1, wherein the plurality of voltage regulators are electrically coupled to a power array controller, and the power array controller is configured to determine the control settings for each voltage regulator coupled to the power rail.

9. The electronic device according to claim 8, wherein for each voltage regulator, the control settings are dynamically and in real time adjusted by the power array controller based on a load condition and a power state strategy associated with the power rail.

10. The electronic device according to claim 1, wherein the bypass unit includes one or more bypass paths, each bypass path having a corresponding bypass switch component and a corresponding dummy load component, the dummy load component being coupled between the bypass switch component and an output of the bypass unit, each bypass path being configured to bypass a corresponding drive path of the feedback path in the standby mode.

11. The electronic device according to claim 10, wherein for each bypass path, the corresponding dummy load component includes an active filter.

12. The electronic device according to claim 11, wherein the active filter is a first or second order Sallen-Key filter.

13. The electronic device according to claim 1, wherein for each corresponding voltage regulator, the bypass unit is electrically decoupled from the power rail in the standby mode and is configured to output the rail voltage and provide the rail voltage to the input of the voltage regulator controller in the standby mode, such that when the standby mode is changed to the operating mode, the corresponding voltage regulator is able to provide the predefined regulator current to the power rail for a predefined time period.

14. The electronic device according to claim 1, wherein: The bypass unit includes one or more bypass switch components and a dummy load component, the dummy load component being coupled between the one or more bypass switch components and an output of the bypass unit; and in the standby mode, each bypass switch component is coupled to a corresponding drive path.

15. The electronic device according to claim 14, wherein the dummy load component includes one of an active filter, and the active filter is a Sallen-Key filter.

16. The electronic device according to claim 1, wherein: The plurality of voltage regulators includes a first voltage regulator, a second voltage regulator, and a third voltage regulator; each of the first and second voltage regulators operates in the operating mode to drive the power rail, and in the operating mode, the feedback path of the corresponding voltage regulator is enabled between the output interface and the input of the corresponding voltage regulator; the third voltage regulator is electrically decoupled from the power rail in the standby mode, and in the standby mode, the bypass unit of the third voltage regulator is enabled to bypass the feedback path of the third voltage regulator.

17. The electronic device according to claim 1, wherein the plurality of voltage regulators coupled to the power rail are identical to each other.

18. The electronic device according to claim 1, wherein: Each voltage regulator has a first AC loop response in the standby mode, the first AC loop response having a first low-frequency gain, a first cutoff frequency, and a first phase margin; each voltage regulator has a second AC loop response in the operating mode, the second AC loop response having a second low-frequency gain, a second cutoff frequency, and a second phase margin; a first difference between the first low-frequency gain and the second low-frequency gain is less than a first threshold; a second difference between the first cutoff frequency and the second cutoff frequency is less than a second threshold; and a third difference between the first phase margin and the second phase margin is less than a third threshold.

19. A method for driving a power rail, further comprising the steps of: at an electronic device having a plurality of voltage regulators electrically coupled to the power rail: generating a rail voltage and a rail current to drive the power rail, each corresponding voltage regulator having an output interface coupled to the power rail and configured to provide the rail voltage to the power rail and deliver up to a predefined regulator current when the corresponding voltage regulator is in an operating mode; obtaining a control setting for each of the plurality of voltage regulators, the control setting for each corresponding voltage regulator being used to determine whether the corresponding voltage regulator is a standby voltage regulator operating in a standby mode or an operating voltage regulator operating in the operating mode; At each standby voltage regulator, a bypass unit of the standby voltage regulator is enabled to bypass a feedback path from the output interface to an input of a voltage regulator controller, so that the standby voltage regulator does not supply current to the power rail; and at each operating voltage regulator, the bypass unit is disabled to prevent the feedback path from being bypassed, so that the corresponding voltage regulator supplies current to the power rail.

20. The method of claim 19, wherein each corresponding voltage regulator includes one or more drive paths coupled to the output interface and configured to operate at an operating frequency, the voltage regulator controller of the corresponding voltage regulator having an output coupled to the one or more drive paths and an input coupled to the output interface via the feedback path, and configured to control the one or more drive paths, the bypass unit coupled to the one or more drive paths, and the voltage regulator controller.

21. The method according to claim 19 also includes the following steps: dynamically and in real time determining the control settings for each corresponding voltage regulator coupled to the power rail based on a load condition and a power state strategy associated with the power rail.

22. A non-transitory computer-readable storage medium storing one or more programs for execution by an electronic device having a plurality of voltage regulators electrically coupled to a power rail, the one or more programs including instructions, when executed by the electronic device, to cause the electronic device to perform the following operations: generating a rail voltage and a rail current to drive the power rail, each corresponding voltage regulator having an output interface coupled to the power rail and configured to provide the rail voltage to the power rail and deliver up to a predefined regulator current when the corresponding voltage regulator is in an operating mode; obtaining a control setting for each of the plurality of voltage regulators, the control setting for each corresponding voltage regulator being used to determine whether the corresponding voltage regulator is a standby voltage regulator operating in a standby mode or an operating voltage regulator operating in the operating mode; At each standby voltage regulator, a bypass unit of the standby voltage regulator is enabled to bypass a feedback path from the output interface to an input of a voltage regulator controller, so that the standby voltage regulator does not supply current to the power rail; and at each operating voltage regulator, the bypass unit is disabled to prevent the feedback path from being bypassed, so that the corresponding voltage regulator supplies current to the power rail.

23. The non-transitory computer-readable storage medium according to claim 22, wherein each of the plurality of voltage regulators is configured to: switch from the standby mode to the operating mode according to a change in the control setting, and provide the predefined regulator current to the power rail for a predefined time period.

24. The non-transitory computer-readable storage medium according to claim 22, wherein for each corresponding voltage regulator, the control setting includes a control value and an operation enable signal, the control value defining an amplitude of the rail voltage, and the operation enable signal being configured to control the corresponding voltage regulator to operate in either a standby mode or an operating mode, wherein in the standby mode the bypass unit is enabled to bypass the feedback path, and in the operating mode the bypass unit is disabled to prevent the feedback path from being bypassed.

25. A means for driving a power rail at an electronic device having a plurality of voltage regulators electrically coupled to a power rail, comprising: The unit is used to generate a rail voltage and a rail current to drive the power rail, each corresponding voltage regulator having an output interface coupled to the power rail and configured to provide the rail voltage and deliver up to a predefined regulator current to the power rail when the corresponding voltage regulator is in an operating mode; the unit is used to obtain a control setting for each of the plurality of voltage regulators, the control setting for each corresponding voltage regulator being used to determine whether the corresponding voltage regulator is a standby voltage regulator operating in a standby mode or an operating voltage regulator operating in the operating mode; the unit is used to enable a bypass unit for each standby voltage regulator to bypass a feedback path from the output interface to an input of a voltage regulator controller, such that the standby voltage regulator does not deliver current to the power rail; and the unit is used to disable the bypass unit for each operating voltage regulator to prevent the feedback path from being bypassed, such that the corresponding voltage regulator delivers current to the power rail.

26. The apparatus of claim 25, wherein each respective voltage regulator includes one or more drive paths coupled to the output interface and configured to operate at an operating frequency, the voltage regulator controller of the respective voltage regulator having an output coupled to the one or more drive paths and an input coupled to the output interface via the feedback path, and configured to control the one or more drive paths, the bypass unit coupled to the one or more drive paths, and the voltage regulator controller.

27. The apparatus according to claim 25 also includes: A unit for dynamically and instantaneously determining the control settings for each corresponding voltage regulator coupled to the power rail based on a load condition and a power state strategy associated with the power rail.

Images