Foveated binned rendering associated with sample spaces

Abstract

The various approaches proposed in this paper relate to methods and apparatuses for graphics processing, including, for example, devices for GPUs. The apparatus can receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with a magnified and / or reduced sampling space. The apparatus can also perform block passes on the plurality of primitives, the block passes being associated with an unscaled sampling space, wherein the block passes classify each of the plurality of primitives into one or more blocks associated with each of the one or more frames. Furthermore, the apparatus can perform one of one or more rendering passes for each of the one or more blocks. The apparatus can also rasterize each of the plurality of primitives based on at least one of a magnified or reduced sampling space.

Description

Technical Field

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit of U.S. non-provisional patent application serial number 17 / 478,694, filed on September 17, 2021, entitled "FOVEATED BINNED RENDERING ASSOCIATED WITH SAMPLE SPACES", the entire contents of which are expressly incorporated herein by reference.

[0003] This case concerns processing systems in general, and more specifically, one or more technologies used for graphics processing. Prior Technology

[0004] Computing devices frequently perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablets, and video game consoles. A GPU is configured to execute a graphics processing pipeline comprising one or more processing stages that work together to execute graphics processing commands and output frames. A CPU can control the operation of a GPU by issuing one or more graphics processing commands to it. Modern CPUs are typically capable of running multiple applications concurrently, each of which may require the use of a GPU during execution. A display processor is configured to convert digital information received from the CPU into analog values ​​and can issue commands to a display panel to display visual content. Devices that provide content for visual presentation on a display can use a GPU and / or a display processor.

[0005] The device's GPU can be configured to perform processing in the graphics processing pipeline. Furthermore, a display processor or display processing unit (DPU) can be configured to execute display processing programs. However, with the advent of wireless communication and smaller handheld devices, the demand for improved graphics or display processing continues to increase. Summary of the Invention

[0006] The following is a simplified overview of one or more states to provide a basic understanding of some states of the invention. This overview is not a comprehensive overview of all anticipated states, and is neither intended to identify key or essential elements of all states, nor to define the scope of any or all states. Its sole purpose is to present some concepts of one or more states in a simplified form as a prelude to the more detailed description that follows.

[0007] In one embodiment, this application provides a method, a computer-readable medium, and an apparatus. The apparatus may be a graphics processing unit (CPU) or any device capable of graphics processing. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives. The apparatus may also receive from a graphics processing unit (GPU) driver a scaling factor for at least one of the enlarged or reduced sampling spaces. Additionally, the apparatus may perform block passing on the plurality of primitives, the block passing being associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames. The apparatus can also perform one of one or more rendering passes for each of one or more blocks, each of the one or more rendering passes being associated with at least one of an enlarged sampling space or a reduced sampling space, and each of the one or more rendering passes including a viewport transformation for each of the plurality of primitives. The apparatus can also perform a culling procedure on each of the plurality of primitives after performing one or more rendering passes for each of the plurality of primitives. Furthermore, the apparatus can rasterize each of the plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. The apparatus can also render each of the plurality of primitives based on the rasterization of each of the plurality of primitives. The apparatus can also send the rendered plurality of primitives after rendering each of the plurality of primitives.

[0008] One or more examples of this case will be set forth in detail in the accompanying drawings and the following description. Other features, objects, and advantages of this case will be apparent from the specification, drawings, and claims. Simple Explanation of the Diagram

[0009] Figure 1 is a block diagram illustrating an example of a system for generating content based on one or more technologies in this case.

[0010] Figure 2 illustrates an example GPU based on one or more technologies in this case.

[0011] Figure 3 illustrates an example image or surface based on one or more techniques in this case.

[0012] Figure 4 is a diagram illustrating an example rasterization procedure.

[0013] Figure 5 is a diagram illustrating the example block gaze point procedure.

[0014] Figure 6A is a diagram illustrating the example block gaze point procedure.

[0015] Figure 6B is a diagram illustrating the example block fixation procedure.

[0016] Figure 7 is an illustration of the rendering process.

[0017] Figure 8 is an illustration of the rendering process.

[0018] Figure 9 is a communication flowchart illustrating an example of communication between the GPU pipeline, GPU components, and the display / buffer.

[0019] Figure 10 is a flowchart of an example method for graphics processing.

[0020] Figure 11 is a flowchart of an example method for graphics processing. Implementation

[0021] Some graphics processing styles may utilize foveated rendering, another optimization technique used in rendering virtual reality (VR), augmented reality (AR), or extended reality (XR) scenes. Additionally, some graphics processing styles may utilize foveated tiled rendering, primarily used in VR / AR / XR applications. In foveated tiled rendering, the tile at the center of the field of view (FoV) can be rendered at full resolution (e.g., a tile in a tiled pass), while tiles outside the main FoV (e.g., a tile in a render pass) can be rendered at a lower or scaled-down resolution, such as 1x:2y, 1x:4y, 2x:4y, etc. Some graphics processing styles may also utilize viewport transform procedures (e.g., Xform). The viewport transform procedure used may depend on parameters of the target render resolution (i.e., scale and offset). Foveated tiled rendering uses different tile sizes in scaled-down render passes. For example, in foveated tiled rendering, tiled passes can use the original viewport scale and viewport offset, while render passes can use adjusted viewport scale and offset for each tile to achieve the same or lower resolution. Because the viewport scale may differ between tiled and render passes, the same primitives / triangles may have different screen coordinates between the two. Based on this, primitives / triangles may not cover any samples in the tiled pass, but (e.g., due to finite precision, face flipping, etc.) it may cover valid samples in the render pass. This process can lead to visual artifacts in the scene. As indicated in this paper, some graphics processing issues may result from different viewport parameters between tiled and render passes, such as including different scaling factors. These different scaling factors can cause visual artifacts in the scene. To avoid these artifacts, the software on the GPU may disable several culling algorithms and may force primitives to be visible in the tiled pass. However, this can have a significant impact on GPU performance. The variants in this paper can provide graphics processing techniques that include similar viewport parameters between tiled and render passes. For example, the samples in this invention may include viewport transformations without scaling between chunked and render passes. Additionally, the samples in this invention may include similar scaling factors or offset parameters between chunked and render passes. For example, the samples in this invention may keep the scaling or offset parameters within a reduced space.

[0022] Various forms of systems, apparatuses, computer program products, and methods are described more fully below with reference to the accompanying drawings. However, this application may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this application. Rather, these forms are provided so that this application will be exhaustive and complete, and will fully convey its scope to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this application is intended to cover any form of the systems, apparatuses, computer program products, and methods of this application, whether implemented independently of or in combination with any other form of this application. For example, an apparatus or method may be implemented using any number of the forms set forth herein. Furthermore, the scope of this application is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than or different from the various forms of this application set forth herein. Any form of this application may be embodied by one or more elements of the claim.

[0023] Although various forms are described herein, many variations and arrangements of these forms fall within the scope of this application. While some potential benefits and advantages of the various forms of this application are mentioned, the scope of this application is not intended to be limited to any particular benefit, use, or objective. Rather, the various forms of this application are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transport protocols, some of which are illustrated by way of example in the accompanying drawings and the embodiments described below. The detailed description and accompanying drawings are illustrative only and not limiting, and the scope of this application is defined by the appended claims and their equivalents.

[0024] Several examples will now be presented with reference to various devices and methods. These devices and methods are described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether such an element is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system.

[0025] For example, an element, or any part of an element, or any combination of elements, can be implemented as a "processing system" (which may also be referred to as a processing unit) comprising one or more processors. Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware configured to perform the various functions described throughout this document. One or more processors in a processing system can run software. Whether referred to as software, firmware, intermediary software, microcode, hardware description language, or other forms, software can be broadly interpreted to mean instructions, instruction sets, code, code fragments, program code, program, subprogram, software component, application, software application, software suite, convention, subconvention, object, executable file, execution thread, program, function, etc. The term application can refer to software. As described herein, one or more technologies can refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application can be stored on memory, such as on-chip memory of the processor, system memory, or any other memory. The hardware described herein, such as a processor, can be configured to execute the application. For example, an application can be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware can access code from memory and execute the code accessed from memory to perform one or more technologies described herein. In some examples, components are identified in this case. In such examples, a component can be hardware, software, or a combination thereof. A component can be a single component or a sub-component of a single component.

[0026] Therefore, in one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or codes on or encoded on a computer-readable medium. Computer-readable media includes computer storage media. Storage media can be any available media accessible by a computer. By way of example and not limitation, such computer-readable storage media can include random access memory (RAM), read-only memory (ROM), electronically erasable programmable read-only memory (EEPROM), optical disk memory, magnetic disk memory, other magnetic storage devices, combinations of computer-readable media of the foregoing types, or any other media that can be used to store computer-executable code in the form of computer-accessible instructions or data structures.

[0027] Generally, this document describes techniques for achieving the following effects: having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on processing units (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this document describes techniques for graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this document.

[0028] As used herein, instances of the term "content" can refer to "graphic content," "image," or vice versa. This applies regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" can refer to content produced by one or more processes in the graphics processing pipeline. In some examples, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0029] In some examples, as used herein, the term "display content" can refer to content produced by a processing unit configured to perform display processing. Graphical content can be processed to become display content. For example, a graphics processing unit can output graphical content, such as frames, to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content, such as one or more frames, from the buffer and perform one or more display processing techniques on it to produce display content. For example, a display processing unit can be configured to perform compositing on one or more rendering layers to produce frames. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers into a single frame. A display processing unit can be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form a frame, i.e., the frame comprises two or more layers and can be subsequently blended together to form frames comprising two or more layers.

[0030] Figure 1 is a block diagram illustrating an example content generation system 100 configured to implement one or more of the technologies described herein. The content generation system 100 includes a device 104. The device 104 may include one or more elements or circuits for performing the various functions described herein. In some examples, one or more elements of the device 104 may be elements of a System-on-a-Chip (SOC). The device 104 may include one or more elements configured to perform one or more of the technologies described herein. In the illustrated example, the device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some cases, the device 104 may include multiple optional elements, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. The representation of a display 131 may refer to one or more displays 131. For example, a display 131 may include a single display or multiple displays. A display 131 may include a first display and a second display. The first display may be a left-eye display and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for rendering on them. In other examples, the first and second displays may receive the same frames for rendering on them. In further examples, the results of graphics processing may not be displayed on the device; for example, the first and second displays may not receive any frames for rendering on them. Instead, the frames or graphics processing results can be transmitted to another device. In some cases, this may be referred to as split-screen rendering.

[0031] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor, such as display processor 127, to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0032] External memory, such as system memory 124, can be accessed by processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 can be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 and content encoder / decoder 122 can be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 can be communicatively coupled to each other via a bus or different connections.

[0033] Content encoder / decoder 122 can be configured to receive graphical content from any source, such as system memory 124 and / or communication interface 126. System memory 124 can be configured to store received encoded or decoded graphical content. Content encoder / decoder 122 can be configured to receive encoded or decoded graphical content from system memory 124 and / or communication interface 126, for example, in the form of encoded pixel data. Content encoder / decoder 122 can be configured to encode or decode any graphical content.

[0034] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), flash memory, magnetic data media or optical storage media, or any other type of memory.

[0035] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may mean that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is immovable or that its contents are static. As one example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may not be removed from device 104.

[0036] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may otherwise be incorporated into a peripheral device configured to interact with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these technologies are partially implemented in software, the processing unit 120 can store instructions for the software in a suitable, non-transitory computer-readable storage medium, such as internal memory 121, and can use one or more processors to execute hardware instructions to perform the technologies of this invention. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., can be considered as one or more processors.

[0037] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are implemented in part in software, the content encoder / decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, such as internal memory 123, and may use one or more processors to execute hardware instructions to perform the techniques of this invention. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., can be considered as one or more processors.

[0038] In some embodiments, the content generation system 100 may include an optional communication interface 126. Communication interface 126 may include a receiver 128 and a transmitter 130. Receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Additionally, receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or location information. Transmitter 130 may be configured to perform any of the sending functions described herein with respect to device 104. For example, transmitter 130 may be configured to send information to another device, which may include a request for content. Receiver 128 and transmitter 130 may be combined to form transceiver 132. In such examples, transceiver 132 may be configured to perform any of the receiving and / or sending functions described herein with respect to device 104.

[0039] Referring again to Figure 1, in some configurations, processing unit 120 may include a decision element 198 configured to receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives. Decision element 198 may also be configured to receive from a graphics processing unit (GPU) driver a scaling factor for at least one of the enlarged or reduced sampling spaces. Decision element 198 may also be configured to perform block passing on the plurality of primitives, the block passing being associated with an unscaled sampling space for the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames. The decision element 198 can also be configured to perform one of one or more rendering passes for each of one or more blocks, each of the one or more rendering passes being associated with at least one of an enlarged or reduced sampling space, each of the one or more rendering passes including a viewport transformation for each of the plurality of primitives. The decision element 198 can also be configured to perform a culling procedure on each of the plurality of primitives after performing one of the one or more rendering passes for each of the plurality of primitives. The decision element 198 can also be configured to rasterize each of the plurality of primitives based on at least one of an enlarged or reduced sampling space. The decision element 198 can also be configured to rasterize and render each of the plurality of primitives based on each of the plurality of primitives. The decision element 198 can also be configured to send the rendered plurality of primitives after rendering each of the plurality of primitives. Although the following description may focus on graphics processing, the concepts described herein are applicable to other similar processing techniques.

[0040] As described herein, a device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation or mainframe computer), terminal product, device, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA), wearable computing device (e.g., smartwatch), augmented reality device or virtual reality device, non-wearable device, display or display device, television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein. The program herein can be described as being executed by a specific element (e.g., GPU); however, in further embodiments, other elements (e.g., CPU) consistent with the disclosed embodiments may be used for execution.

[0041] A GPU can process various types of data or data packets within the GPU pipeline. For example, in some cases, the GPU can process two types of data or data packets, such as context register packets and draw call data. A context register packet can be a set of global state information, such as information about global registers, shaders, or constant data, which can specify how to handle the graphics context. For example, a context register packet may include information about color formats. In some cases of context register packets, there may be bits indicating which workload belongs to the context register. Furthermore, multiple functions or programs can run simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0042] Context states can be used to determine how individual processing units operate, such as vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors, and / or what mode a processing unit operates in. For this purpose, the GPU can use context registers and programming data. In some cases, the GPU can generate workloads in the pipeline based on the context register definition of a mode or state, such as vertex or pixel workloads. Some processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Additionally, workloads corresponding to modes or states may follow constantly changing modes or states.

[0043] Figure 2 illustrates an example GPU 200 according to one or more technologies of this invention. As shown in Figure 2, GPU 200 includes a command processor (CP) 210, a drawing call packet 212, a VFD 220, a VS 222, a vertex cache memory (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-processing engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, a level 2 (L2) cache memory (UCHE) 238, and system memory 240. Although Figure 2 shows GPU 200 including processing units 220-238, GPU 200 may include multiple additional processing units. Additionally, processing units 220-238 are merely examples, and the GPU according to this invention may use any combination and / or order of processing units. GPU 200 also includes command buffer 250, context register packet 260, and context state 261.

[0044] As shown in Figure 2, the GPU can utilize a CP, such as CP 210, or a hardware accelerator to parse the command buffer into context register packets, such as context register packet 260, and / or draw call data packets, such as draw call packet 212. CP 210 can then send the context register packet 260 or the draw call data packet 212 to a processing unit or block in the GPU via a separate pass. Furthermore, the command buffer 250 can alternate between different states of the context register and the draw call. For example, the command buffer can be constructed as follows: context register of context N, draw call of context N, context register of context N+1, and draw call of context N+1.

[0045] GPUs can render images in a variety of different ways. In some cases, GPUs can render images using both tiling and / or direct rendering. In a tiling GPU, an image can be divided or separated into different segments or pieces. After the image is divided, each segment or piece can be rendered individually. A tiling GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a piece) is rendered individually. In some cases, the image can be divided into different blocks or pieces during chunking. In some cases, a visibility stream can be constructed during chunking, where visible primitives and / or draw calls can be identified. Compared to tiling, direct rendering does not divide the frame into smaller blocks or pieces. Instead, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs can support both tiling and direct rendering simultaneously.

[0046] In some scenarios, the GPU can apply drawing or rendering processes to different blocks or slices. For example, the GPU can render to a block and perform all drawing of the primitives or pixels within that block. In a block-based rendering process, the render target can reside in GMEM. In some cases, after rendering to a block, the contents of the render target can be moved to system memory, and GMEM can be freed to render the next block. Additionally, the GPU can render to another block and perform drawing of the primitives or pixels within that block. Therefore, in some scenarios, there may be a small number of blocks, for example, four blocks, covering all drawing on a surface. Furthermore, the GPU can loop through all drawing within a block but perform drawing only for visible drawing calls, i.e., including drawing calls for visible geometry. In some scenarios, such as in a chunked pass, a visibility stream can be generated to determine the visibility information of each primitive in the image or scene. For example, this visibility stream can identify whether a primitive is visible. In some scenarios, this information can be used to remove invisible primitives, for example, in a render pass. In addition, at least some primitives that are identified as visible can be rendered in the rendering pass.

[0047] In some tiling rendering styles, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, such as a visibility or block visibility pass and a rendering or block rendering pass. During a visibility pass, the GPU can input the rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which block or region. In some styles of visibility passes, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During a rendering pass, the GPU can input the visibility stream and process one block or region at a time. In some styles, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. Therefore, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0048] In some scenarios, certain types of primitive geometry, such as position-only geometry, can be processed during visibility pass-through. Additionally, primitives or triangles can be categorized into different blocks or regions based on their position or orientation. In some cases, primitives or triangles can be categorized into different blocks by determining their visibility information. For example, the GPU can determine or write visibility information for each primitive in each block or region, for example, in system memory. This visibility information can be used to determine or generate a visibility stream. During rendering pass-through, primitives in each block can be rendered individually. In these cases, the visibility stream can be retrieved from memory to remove primitives that are not visible to that block.

[0049] GPUs or GPU architectures offer various rendering options, such as software rendering and hardware rendering. In software rendering, the driver or CPU can replicate the entire frame geometry by processing each view once. Additionally, different states may change depending on the view. Therefore, in software rendering, the software can replicate the entire workload by changing certain states that can be used for rendering for each viewpoint of the image. In some cases, this can increase the administrative burden because the GPU may submit the same workload multiple times for each viewpoint of the image. In hardware rendering, the hardware or GPU may be responsible for replicating or processing the geometry for each viewpoint of the image. Therefore, the hardware can manage the replication or processing of primitives or triangles for each viewpoint of the image.

[0050] Figure 3 illustrates an image or surface 300 comprising a plurality of primitives divided into multiple blocks. As shown in Figure 3, the image or surface 300 includes a region 302 comprising primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided or placed into different blocks, such as blocks 310, 311, 312, 313, 314, and 315. Figure 3 illustrates an example of tiling rendering using multiple viewpoints for primitives 321-324. For example, primitives 321-324 are in a first viewpoint 350 and a second viewpoint 351. Therefore, GPU processing or rendering of the image or surface 300 including region 302 can utilize multi-view or multi-view rendering.

[0051] As indicated in this article, GPUs or graphics processing units can use a tiling rendering architecture to reduce power consumption or save memory bandwidth. As previously mentioned, this rendering method divides the scene into multiple blocks and includes a visibility passthrough to identify the triangles visible within each block. Therefore, in tiling rendering, a full screen can be divided into multiple blocks or slices. The scene can then be rendered multiple times, for example, once or multiple times per block.

[0052] In graphics rendering, some graphics applications may render to a single target, i.e., the render target, once or multiple times. For example, in graphics rendering, the frame buffer on system memory may be updated multiple times. The frame buffer can be memory or part of random access memory (RAM), for example, containing bitmaps or storage to help store GPU display data. The frame buffer can also be a storage buffer containing complete data frames. Additionally, the frame buffer can be a logical buffer. In some formats, updating the frame buffer can be performed in block or tile rendering, where, as mentioned above, the surface is divided into multiple blocks or slices, and each block or slice can then be rendered individually. Moreover, in tile rendering, the frame buffer can be divided into multiple blocks or slices.

[0053] As indicated in this article, some aspects of graphics processing can utilize different types of rendering, such as tiled rendering or tiled rendering. Tiled rendering or tiled rendering is a procedure that subdivides a computer graphics scene into a rectangular grid in display space and renders each segment (i.e., piece or block) of the grid separately. Graphics processing units (GPUs) with limited memory access bandwidth can use tiled or tiled rendering. In some cases, tiled rendering can be performed in a number of passes, for example, two passes, to maximize GPU utilization, such as tiled passes and render passes.

[0054] In tiled or tiled rendering, a tile pass analyzes the frame and determines the primitives belonging to each block or slice. This may result in a primitive-to-block graph, which can be stored in an intermediate data structure. A render pass can render each block or slice separately. For each block or slice, the intermediate graph can be queried, and the primitives belonging to the corresponding block / slice can be rendered to the on-chip buffer. At the end of the render pass for each block, the on-chip buffer can be resolved to system memory or the display buffer.

[0055] Figure 4 illustrates an example of a rasterization procedure, Figure 400. More specifically, Figure 400 in Figure 4 shows the rasterization procedure for primitive 410. As shown in Figure 4, rasterization is a procedure in the GPU that generates a sampled coverage area for a primitive, such as primitive 410. Typically, the rasterizer examines each sample against the edge of the primitive / triangle, and if the sample is inside the primitive / triangle, it is marked as covered. In other words, the rasterizer can test each sample against the edge equation of the primitive / triangle. As shown in Figure 4, if a sample is inside a primitive / triangle, such as primitive 410, it can be marked as covered.

[0056] Additionally, some graphics processing techniques may utilize foveated rendering, another optimization technique used in rendering virtual reality (VR), augmented reality (AR), or extended reality (XR) scenarios. In foveated rendering, eye trackers, such as those integrated into VR headsets, can be used to identify the primary field of view (FoV) within the rendering target. The resulting FoV information can be used to render individual areas of the scene at different resolutions. This can significantly reduce rendering workload without significantly impacting the visual quality of the rendered image. Furthermore, some graphics processing techniques may utilize foveated tiled rendering, also used in VR / AR / XR applications. In foveated tiled rendering, the tile at the center of the FoV can be rendered at full resolution (e.g., a tile in a tiled pass), while tiles outside the primary FoV (e.g., tiles in a render pass) can be rendered at lower or reduced resolutions, such as 1x:2y, 1x:4y, 2x:4y, etc.

[0057] Some graphics processing techniques can also utilize viewport transform procedures (e.g., Xform). Viewport transform is a mathematical step in GPU processing that transforms primitives from normalized device coordinate (NDC) space to the final screen space. Viewport transform procedures use parameters (i.e., scale and offset) that may depend on the resolution of the rendering target. These viewport transform scales and offsets can also directly affect primitive geometry.

[0058] Foveative tiled rendering uses different tile sizes in scaled-down render passes. For example, in foveative tiled rendering, a tile pass can use the original viewport scale and viewport offset, while a render pass can use an adjusted viewport scale and offset for each tile to achieve the same or lower resolution. For example, a render pass can use various scales (e.g., 1:1, 1:2, or 1:4 viewport scales) for each tile in the X and / or Y directions. Because the viewport scales may differ between tile and render passes, the same primitives / triangles may have different screen coordinates between the two passes. For example, different viewport parameters may cause vertices to fall in different positions in the sampling space between the tile and render passes. Based on this, primitives / triangles may not cover any samples in the tile pass, but (e.g., due to limited precision, face flipping, etc.) they may cover valid samples in the render pass. This process can lead to visual artifacts in the scene. Furthermore, this can occur at both the frame level and the tile level, and is more likely a common problem in the VR / AR / XR segment.

[0059] Figure 5 illustrates an example of a block foveated procedural, Figure 500. As shown in Figure 5, Figure 500 is an example block foveated procedural including blocks 511, 512, 513, 514, and primitive 520. More specifically, Figure 5 shows the visibility problem of primitive 520 in the block foveated procedural. That is, primitive 520 includes the sampling coverage problem in blocks 511-514. As shown in Figure 5, the points in each of blocks 511-514 correspond to a 1x scale sampling, while the "x" at the center of blocks 511-514 corresponds to a 2x scale sampling. For example, primitive 520 does not cover any 1x scale sampling, so it can be removed in the block procedural. This can cause artifacts in the scene.

[0060] Figures 6A and 6B illustrate Figures 600 and 650, respectively, of another example of a block foveated procedure. As shown in Figures 6A and 6B, Figures 600 and 650 are example block foveated procedures including primitives 611, 612, 613, and 614. More specifically, Figures 6A and 6B show a visibility problem with primitive 614 in the block pass of Figure 6A and the render pass of Figure 6B. That is, the face of primitive 614 is flipped between the block pass of Figure 6A and the render pass of Figure 6B. For example, due to the limited precision of fixed-point operations within the GPU, due to different viewport scales and floating-to-fixed-point snapping, primitives / triangles may flip their faces. This primitive / triangle face flipping problem can cause artifacts in the scene.

[0061] As shown in Figure 6A, primitive 614 is a back face triangle in the chunked pass, and all samples are covered by primitives 611 / 612 / 613. For example, primitive 614 is culled in the chunk due to backface culling. However, as shown in Figure 6B, in the render pass, primitive 614 becomes visible due to fixed-point snapping. Furthermore, some samples may be covered by primitive 614. Since primitive 614 has already been culled in the chunk, it may create a hole in the mesh at its location during scaled-down rendering. This can also lead to visual artifacts. Additionally, primitives detected in "zero regions" in the chunked pass may end up in "non-zero regions" in the render pass. This is another potential cause of visual artifacts.

[0062] Figure 7 illustrates an example rendering pass, Figure 700. As shown in Figure 7, Figure 700 is an example rendering pass including steps 710, 720, 730, and 740. More specifically, Figure 7 shows a rendering pass that includes a viewport transformation with scaling compared to a chunked pass. That is, the rendering pass in Figure 7 includes viewport scaling and offset parameters different from those of a chunked pass. As shown in Figure 7, at step 710, input primitives / triangles are received. At step 720, a viewport transformation is performed using scaling (i.e., compared to a chunked pass). At step 730, a culling procedure is performed. At step 740, a rasterization procedure is performed. Because there are different scaling factors between chunked and rendered passes, this can cause visual artifacts in the scene.

[0063] As mentioned earlier, some graphics processing problems may result from differences in viewport parameters between chunked and render passes, such as including different scaling factors. These different scaling factors can cause visual artifacts in the scene. To avoid these artifacts, the software on the GPU might disable multiple culling algorithms and might force primitives to be visible in the chunked pass. However, this can have a significant impact on GPU performance. Therefore, including similar viewport parameters between the chunked and render passes may be beneficial. For example, including viewport transformations without scaling between the chunked and render passes may be advantageous. Furthermore, including similar scaling factors or offset parameters between the chunked and render passes may be beneficial. For example, keeping scaling or offset parameters within a reduced space may be advantageous.

[0064] The various forms of this invention can provide graphics processing techniques that include similar viewport parameters between chunked and render passes. For example, the various forms of this invention can include viewport transformations without scaling between chunked and render passes. Additionally, the various forms of this invention can include similar scaling factors or offset parameters between chunked and render passes. For example, the various forms of this invention can keep scaling or offset parameters within a reduced space.

[0065] In some cases, the variants of this invention can perform artifact-free downscaling rendering while maintaining most culling algorithms enabled. For example, the main cause of the aforementioned visual artifacts is the different culling results for the same primitives in tiled and downscaled rendering. As mentioned earlier, this may be due to different viewport parameters in tiled and rendered passes. Therefore, the variants of this invention can propose keeping the viewport scaling and offset parameters the same as those in tiled passes during downscaling rendering.

[0066] By maintaining similar viewport scaling and / or offset parameters in both tiled and render passes, this ensures that primitives have the same culling results in both the tiled and render processes. Therefore, this can potentially facilitate seamless enabling of culling algorithms in both tiled and render passes. For example, in a scaled-down render pass, the rasterizer can generate sampled coverage within the scaled-down domain. To achieve this, the anisotropy in this case can perform a magnified visibility test of the sampled space for primitives with the same resolution as in the tiled pass. In some cases, this may have the same effect as determining / identifying coverage within the scaled-down domain.

[0067] Figure 8 illustrates an example of a rendering pass according to the various forms described in this case, Figure 800. As shown in Figure 8, Figure 800 is an example rendering pass including steps 810, 820, 830, and 840. More specifically, Figure 8 shows a rendering pass that includes a viewport transformation with scaling compared to a chunked pass. That is, the rendering pass in Figure 8 includes viewport scaling and offset parameters similar to those of a chunked pass. In doing so, the rendering pass in Figure 8 ensures the same primitive culling results across chunked and rendering passes.

[0068] As shown in Figure 8, at step 810, the sample in this embodiment can receive input primitives / triangles. At step 820, the sample in this embodiment can perform viewport transformation without scaling (i.e., compared to chunked transfer). For example, the sample in this embodiment can calculate the coverage in the enlarged sampling space. Furthermore, the sample in this embodiment can maintain other parameters in the reduced space. At step 830, the sample in this embodiment can perform a culling procedure. At step 840, the sample in this embodiment can perform a rasterization procedure using the enlarged sampling space. As described herein, steps 810-840 in the render transfer in Figure 8 can help seamlessly enable the culling algorithm in both chunked transfer and render transfer.

[0069] In some patterns, to maintain similarity in viewport scaling and / or offset parameters across chunked and rendered passes, the patterns in this invention can utilize multiple different edge equations. More specifically, the patterns in this invention can multiply the edge equations of primitives / triangles by different scaling factors, such as XY scaling factors. For example, the rasterizer can utilize the first equation: R = E aX step + E bY step + C ref, where E a is the edge equation of primitive A, E b is the edge equation of primitive B, X step is the X step component, Y step is the Y step component, and C ref is a constant. For scaled-down rasterization, the X step and Y step can be multiplied by the X scaling factor (S x) and the Y scaling factor (S y). Therefore, the first equation can be transformed into the second equation = E a(X step * S x) + E b(Y step * S y) + C ref. The second equation can be rearranged into the third equation = (Ea*Sx)Xstep + (Eb*Sy)Ystep + Cref. Furthermore, the third equation can be transformed into the fourth equation = Ea''Xstep + Eb''Ystep + Cref. The fourth equation is likely similar to the first equation, except that it uses modified forms of Ea (i.e., Ea'') and Eb (i.e., Eb''). As shown above, according to the third equation, if Ea and Eb are multiplied by the scaling factor X(Sx) and the scaling factor Y(Sy), respectively, this could result in the sampling being moved into the magnified space.

[0070] Additionally, the various forms in this case can use different steps for the edge equations to maintain similar viewport scaling and / or offset parameters in chunked and rendered transfers. For example, the raster equation (R) of the chunked procedure can be: R = Ea*X + Eb*Y + Cinit, where Ea is the edge equation for primitive A, Eb is the edge equation for primitive B, X is the X component, Y is the Y component, and Cinit is the initial constant. For frontal primitives, the test point (X, Y) can be: if R > 0, the test point is inside a line; if R < 0, the test point is outside the line; and if R = 0, the test point is on the line. Additionally, the second rasterizer equation in a scaled-down render (R') with scaling factors X and Y in the X and Y directions, respectively, could be: R' = E a' * X' + E b' * Y' + C init', where E a' = E a / scaling Y, E b' = E b / scaling X, and C init' = C init / (scaling X * scaling Y). Based on the above equation, R' * scaling X * scaling Y = (E a ​​* scaling X) * X' + (E b * scaling Y) * Y' + C init. In some cases, if scaling X and scaling Y are positive, the signs of the above equations may be sufficient to perform edge testing. Therefore, the third rasterizer equation corresponding to primitive edges in the scaled-down render (R'') could be: R'' = E a'' * X' + E b'' * Y' + C init, where E a'' = E a * scaling X and E b'' = E b * scaling Y.

[0071] The variants of this invention can utilize the aforementioned edge equations, such as the third rasterizer equation (R''), in edge testing for sampling primitive edges in scaled-down rendering. The aforementioned edge equations for the variants of this invention can include numerous benefits or advantages. For example, by keeping the culling algorithm intact, the aforementioned edge equations can provide a fast and robust strategy for foveated block rendering. More specifically, these edge equations can allow robust foveated strategies that may not impede GPU performance by keeping the culling algorithm enabled. These edge equations can also achieve artifact-free, robust, and fast block foveated strategies. Furthermore, these edge equations allow the variants of this invention to not compromise GPU performance, as the proposed strategy helps keep the culling algorithm enabled.

[0072] Figure 9 is a communication flowchart 900 of graphics processing according to one or more technologies of this invention. As shown in Figure 9, according to one or more technologies of this invention, Figure 900 includes example communication between GPU pipeline 902 (e.g., an element in the GPU pipeline), GPU element 904 (e.g., another element in the GPU pipeline), and display or buffer 906.

[0073] At 910, GPU pipeline 902 can receive a plurality of primitives associated with one or more frames in a scene, such as primitive 912, a portion of the scene associated with at least one of a magnified sampling space for the plurality of primitives or a reduced sampling space for the plurality of primitives. The plurality of primitives can be received from at least one application outside the graphics processing unit (GPU) pipeline or at least one game outside the GPU pipeline.

[0074] At 920, GPU pipeline 902 can receive a scaling factor from the graphics processing unit (GPU) driver for at least one of an enlarged sampling space or a reduced sampling space. In some cases, at least one of the enlarged or reduced sampling space may correspond to a scaling factor.

[0075] At 930, GPU pipeline 902 can perform block passing on a plurality of primitives, which is associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of one or more frames. In some cases, block passing can use the unscaled sampling space to assign each of the plurality of primitives to one or more blocks in which each primitive appears.

[0076] At 940, GPU pipeline 902 can execute one of one or more rendering passes for each of one or more blocks, each of the one or more rendering passes being associated with at least one of an enlarged or reduced sampling space, and each of the one or more rendering passes including a viewport transformation for each of a plurality of primitives. The one or more rendering passes can be associated with a foveated rendering procedure.

[0077] In some configurations, the viewport transformation for each of a plurality of primitives can be associated with an unscaled sampling space for the plurality of primitives. Similarly, the viewport transformation can be associated with at least one of the viewport scales or at least one offset parameter of the unscaled viewport transformation. The viewport transformation can also be associated with each of a plurality of geometric parameters that maintain all of the plurality of primitives in the unscaled sampling space.

[0078] At 950, GPU pipeline 902 can perform a culling procedure for each of the plurality of primitives after performing one of one or more rendering passes for each of the plurality of primitives.

[0079] At 960, GPU pipeline 902 can rasterize each of a plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. In some cases, the GPU of this invention can compute the coverage of each of the plurality of primitives in at least one of an enlarged sampling space or a reduced sampling space. For example, rasterizing each of the plurality of primitives may also include computing the coverage of each of the plurality of primitives in at least one of an enlarged sampling space or a reduced sampling space. Similarly, the GPU of this invention can modify one or more edge coefficients for each of the plurality of primitives. For example, computing the coverage of each of the plurality of primitives may also include modifying one or more edge coefficients for each of the plurality of primitives.

[0080] At 970, GPU pipeline 902 can render each of the plurality of primitives based on the rasterization of each of the plurality of primitives.

[0081] At 980, GPU pipeline 902 can send the rendered plurality of primitives, such as primitive 982, after rendering each of the plurality of primitives. The rendered plurality of primitives can be sent to at least one of the display or storage buffer.

[0082] Figure 10 is a flowchart 1000 of an example method for graphics processing according to one or more technologies of this invention. As used in conjunction with the examples of Figures 1-9, the method can be executed by a GPU, such as a device for graphics processing, another graphics processor, a GPU pipeline, a wireless communication device, and / or any device capable of performing graphics processing.

[0083] As illustrated in the examples in Figures 1-9, at 1002, the GPU can receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of a magnified sampling space or a reduced sampling space for the plurality of primitives. For example, as shown at 910 in Figure 9, GPU pipeline 902 can receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of a magnified sampling space or a reduced sampling space for the plurality of primitives. Furthermore, step 1002 can be performed by processing unit 120 in Figure 1. The plurality of primitives can be received from at least one application outside the graphics processing unit (GPU) pipeline or at least one game outside the GPU pipeline.

[0084] As illustrated in the examples in Figures 1-9, at 1006, the GPU can perform block passing on a plurality of primitives, which is associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of one or more frames. For example, as shown at 930 in Figure 9, GPU pipeline 902 can perform block passing on a plurality of primitives, which is associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of one or more frames. Furthermore, step 1006 can be performed by processing unit 120 in Figure 1. In some cases, block passing can use an unscaled sampling space to assign each of the plurality of primitives to one or more blocks in which each primitive appears.

[0085] As illustrated in the examples in Figures 1-9, at 1008, the GPU can perform one of one or more rendering passes for each of one or more blocks, each of which is associated with at least one of an enlarged or reduced sampling space, and each of the rendering passes includes a viewport transformation for each of a plurality of primitives. For example, as shown at 940 in Figure 9, GPU pipeline 902 can perform one of one or more rendering passes for each of one or more blocks, each of which is associated with at least one of an enlarged or reduced sampling space, and each of the rendering passes includes a viewport transformation for each of a plurality of primitives. Furthermore, step 1008 can be performed by processing unit 120 in Figure 1. The one or more rendering passes can be associated with a foveated rendering procedure.

[0086] In some configurations, the viewport transformation for each of a plurality of primitives can be associated with an unscaled sampling space for the plurality of primitives. Similarly, the viewport transformation can be associated with at least one of the viewport scales or at least one offset parameter of the unscaled viewport transformation. The viewport transformation can also be associated with each of a plurality of geometric parameters that maintain all of the plurality of primitives in the unscaled sampling space.

[0087] As illustrated in the examples in Figures 1-9, at 1012, the GPU can rasterize each of a plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. For example, as described at 960 in Figure 9, GPU pipeline 902 can rasterize each of a plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. Furthermore, step 1012 can be performed by processing unit 120 in Figure 1. In some cases, the GPU of this invention can calculate the coverage of each of the plurality of primitives in at least one of an enlarged sampling space or a reduced sampling space. For example, rasterizing each of the plurality of primitives may further include calculating the coverage of each of the plurality of primitives in at least one of an enlarged sampling space or a reduced sampling space. Similarly, the GPU of this invention can modify one or more edge coefficients for each of the plurality of primitives. For example, calculating the coverage of each of the plurality of primitives may further include modifying one or more edge coefficients for each of the plurality of primitives.

[0088] Figure 11 is a flowchart 1100 of an example method of graphics processing according to one or more techniques of this invention. As used in conjunction with the examples of Figures 1-9, the method can be executed by a GPU, such as a device for graphics processing, another graphics processor, a GPU pipeline, a wireless communication device, and / or any device capable of performing graphics processing.

[0089] As illustrated in the examples in Figures 1-9, at 1102, the GPU can receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of a magnified sampling space or a reduced sampling space for the plurality of primitives. For example, as shown at 910 in Figure 9, GPU pipeline 902 can receive a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of a magnified sampling space or a reduced sampling space for the plurality of primitives. Furthermore, step 1102 can be performed by processing unit 120 in Figure 1. The plurality of primitives can be received from at least one application outside the graphics processing unit (GPU) pipeline or at least one game outside the GPU pipeline.

[0090] As illustrated in the examples in Figures 1-9, at 1104, the GPU can receive a scaling factor from the GPU driver for at least one of an enlarged or reduced sampling space. For example, as shown at 920 in Figure 9, GPU pipeline 902 can receive a scaling factor from the GPU driver for at least one of an enlarged or reduced sampling space. Furthermore, step 1104 can be performed by the processing unit 120 in Figure 1. In some cases, at least one of an enlarged or reduced sampling space may correspond to a scaling factor.

[0091] As illustrated in the examples in Figures 1-9, at 1106, the GPU can perform block passing on a plurality of primitives, which is associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of one or more frames. For example, as shown at 930 in Figure 9, GPU pipeline 902 can perform block passing on a plurality of primitives, which is associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of one or more frames. Furthermore, step 1106 can be performed by processing unit 120 in Figure 1. In some cases, block passing can use an unscaled sampling space to assign each of the plurality of primitives to one or more blocks in which each primitive appears.

[0092] As illustrated in the examples in Figures 1-9, at 1108, the GPU can perform one of one or more rendering passes for each of one or more blocks, each of which is associated with at least one of an enlarged or reduced sampling space, and each of the rendering passes includes a viewport transformation for each of a plurality of primitives. For example, as shown at 940 in Figure 9, GPU pipeline 902 can perform one of one or more rendering passes for each of one or more blocks, each of which is associated with at least one of an enlarged or reduced sampling space, and each of the rendering passes includes a viewport transformation for each of a plurality of primitives. Furthermore, step 1108 can be performed by processing unit 120 in Figure 1. The one or more rendering passes can be associated with a foveated rendering procedure.

[0093] In some configurations, the viewport transformation for each of a plurality of primitives can be associated with an unscaled sampling space for the plurality of primitives. Similarly, the viewport transformation can be associated with at least one of the viewport scales or at least one offset parameter of the unscaled viewport transformation. The viewport transformation can also be associated with each of a plurality of geometric parameters that maintain all of the plurality of primitives in the unscaled sampling space.

[0094] As illustrated in the examples in Figures 1-9, at step 1110, the GPU can perform a culling procedure for each of the plurality of primitives after performing one of one or more rendering passes for each of the primitives. For example, as shown at step 950 in Figure 9, GPU pipeline 902 can perform a culling procedure for each of the plurality of primitives after performing one of one or more rendering passes for each of the primitives. Furthermore, step 1110 can be performed by the processing unit 120 in Figure 1.

[0095] As illustrated in the examples in Figures 1-9, at 1112, the GPU can rasterize each of the plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. For example, as described in 960 of Figure 9, GPU pipeline 902 can rasterize each of the plurality of primitives based on at least one of an enlarged sampling space or a reduced sampling space. Furthermore, step 1112 can be performed by processing unit 120 in Figure 1. In some cases, at 1112a, the GPU can calculate the coverage of each of the plurality of primitives in at least one of the enlarged or reduced sampling spaces. For example, rasterizing each of the plurality of primitives may further include calculating the coverage of each of the plurality of primitives in at least one of the enlarged or reduced sampling spaces. Similarly, at 1112b, the GPU can modify one or more edge coefficients for each of the plurality of primitives. For example, calculating the coverage of each of the plurality of primitives may further include modifying one or more edge coefficients for each of the plurality of primitives.

[0096] As illustrated in the examples in Figures 1-9, at step 1114, the GPU can render each of the plurality of primitives based on the rasterization of each of the plurality of primitives. For example, as shown at 970 in Figure 9, GPU pipeline 902 can render each of the plurality of primitives based on the rasterization of each of the plurality of primitives. Furthermore, step 1114 can be performed by the processing unit 120 in Figure 1.

[0097] As illustrated in the examples in Figures 1-9, at step 1116, the GPU can send the rendered plurality of primitives after rendering each of the plurality of primitives. For example, as shown at 980 in Figure 9, GPU pipeline 902 can send the rendered plurality of primitives after rendering each of the plurality of primitives. Furthermore, step 1116 can be performed by the processing unit 120 in Figure 1. The rendered plurality of primitives can be sent to at least one of a display or a storage buffer.

[0098] In this configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a graphics processing unit, or some other processor capable of performing graphics processing. In various embodiments, the apparatus may be a processing unit 120 within device 104, or it may be some other hardware within device 104 or another device. The apparatus, for example, processing unit 120, may include components for receiving a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; components for performing block passing on the plurality of primitives, the block passing being associated with an unscaled sampling space for the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; and components for performing one of one or more rendering passes for each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transformation for each of the plurality of primitives; A component for rasterizing each of a plurality of primitives based on at least one of an enlarged or reduced sampling space; a component for performing a culling procedure on each of the plurality of primitives after performing one of one or more rendering passes for each of the plurality of primitives; a component for receiving a scaling factor from a graphics processing unit (GPU) driver for at least one of the enlarged or reduced sampling space; a component for calculating the coverage of each of the plurality of primitives in at least one of the enlarged or reduced sampling space; a component for modifying one or more edge coefficients for each of the plurality of primitives; a component for rendering each of the plurality of primitives based on the rasterization of each of the plurality of primitives; and a component for sending the rendered plurality of primitives after rendering each of the plurality of primitives.

[0099] The subjects described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a graphics processing unit, or some other processor capable of performing graphics processing to implement the tiled and rendering techniques described herein. This can also be achieved at a lower cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques of this invention can improve or accelerate data processing or execution. In addition, the graphics processing techniques of this invention can improve resource or data utilization and / or resource efficiency. Additionally, various embodiments of this invention can utilize unscaled tiled and rendering techniques to improve memory bandwidth efficiency and / or increase processing speed at the GPU.

[0100] It should be understood that the specific order or hierarchy of blocks in the illustrated program / flowchart is an illustration of the example method. Based on design preferences, it should be understood that the specific order or hierarchy of blocks in the program / flowchart can be rearranged. Furthermore, some blocks can be combined or omitted. The accompanying method's request items present the elements of each block in the example order and are not intended to limit one to the specific order or hierarchy presented.

[0101] The preceding description is provided to enable any person skilled in the art to practice the various forms described herein. Various variations of these forms will be apparent to those skilled in the art, and the general principles defined herein can be applied to other forms. Therefore, the claims are not intended to be limited to the forms shown herein, but should be given the full scope consistent with the language of the claims, wherein, unless expressly stated, elements referred to in the singular are not intended to mean "one and only one," but rather "one or more." The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any form described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other forms.

[0102] Unless otherwise expressly stated, the term "some" means one or more, and the term "or" may be interpreted as "and / or," where the context does not specify otherwise. Combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. In particular, "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may contain one or more members of A, B, or C. All structural and functional equivalents of the elements of various forms described herein, which are known or will be known by one of ordinary skill in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, regardless of whether the contents disclosed herein are expressly stated in the claims, they are not intended to be disclosed to the public. The words “module,” “mechanism,” “element,” “device,” etc., may not replace the word “component.” Thus, unless an element is explicitly described using the phrase “component for…,” no element in any claim should be interpreted as a component plus a function.

[0103] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this document, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technology, or other module described herein is implemented in software, then the function, processing unit, technology, or other module described herein may be stored on a computer-readable medium or transmitted as one or more instructions or codes.

[0104] In this case, unless otherwise specified in the context, the term "or" can be understood as "and / or". Additionally, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not others, features not using such language may be interpreted as implying such a meaning unless otherwise specified in the context.

[0105] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this document, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technology, or other module described herein is implemented in software, then the function, processing unit, technology, or other module described herein may be stored on or transmitted as one or more instructions or codes on a computer-readable medium. A computer-readable medium may include computer data storage media or communication media, which includes any media that facilitates the transfer of computer programs from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to obtain instructions, code, and / or data structures to implement the technology described herein. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices. As used herein, magnetic disks and optical discs include CDs, laser discs, optical discs, DVDs, floppy disks and Blu-ray discs, wherein magnetic disks typically reproduce data magnetically, and optical discs reproduce data optically by laser. Combinations of the above should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0106] This code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Similarly, these techniques can be fully implemented in one or more circuit or logic elements.

[0107] The technology described herein can be implemented in a variety of devices or apparatuses, including wireless handheld devices, integrated circuits (ICs), or IC sets, such as chip sets. Various elements, modules, or units are described in this invention to emphasize the functional characteristics of a device configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. Rather, as mentioned above, various units can be combined with suitable software and / or firmware in any hardware unit or provided by a collection of interactive operating hardware units, including one or more processors as described above. Therefore, the term "processor" as used herein can refer to any of the aforementioned structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuit or logic elements.

[0108] The following examples are illustrative only and may be combined with other examples or teachings described herein without limitation.

[0109] State Sample 1 is an apparatus for graphics processing, comprising at least one processor coupled to memory and configured to: receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; perform block passing on the plurality of primitives, the block passing being associated with an unscaled sampling space of the plurality of primitives, wherein the block passing classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; perform one of one or more rendering passes for each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transformation for each of the plurality of primitives; and rasterize each of the plurality of primitives based on at least one of the enlarged sampling space or the reduced sampling space.

[0110] State 2 is an apparatus based on State 1, wherein a viewport transformation for each of a plurality of primitives is associated with an unscaled sampling space for the plurality of primitives.

[0111] State 3 is an apparatus according to any one of states 1 and 2, wherein the viewport transformation is associated with at least one or at least one offset parameter of the viewport scale of the unscaled viewport transformation.

[0112] State 4 is an apparatus according to any one of states 1 to 3, wherein the viewport transformation is associated with each of a plurality of geometric parameters of all complex primitives in the unscaled sampling space.

[0113] State 5 is an apparatus according to any one of states 1 to 4, wherein block transfer uses an unscaled sampling space to assign each of the plurality of primitives to one or more blocks in which each primitive appears.

[0114] State 6 is an apparatus according to any one of states 1 to 5, wherein the at least one processor is further configured to: perform a culling procedure for each of the plurality of primitives after performing one of one or more rendering passes for each of the plurality of primitives.

[0115] State 7 is an apparatus according to any one of states 1 to 6, wherein at least one of the enlarged sampling space or the reduced sampling space corresponds to a scaling factor.

[0116] State 8 is an apparatus according to any one of states 1 to 7, wherein the at least one processor is further configured to receive from a graphics processing unit (GPU) driver a scaling factor for at least one of an enlarged sampling space or a reduced sampling space.

[0117] State 9 is an apparatus according to any one of states 1 to 8, wherein, in order to rasterize each of the plurality of primitives, the at least one processor is further configured to: calculate the coverage of each of the plurality of primitives in at least one of an enlarged sampling space or a reduced sampling space.

[0118] State 10 is an apparatus according to any one of states 1 to 9, wherein, in order to calculate the coverage of each of the plurality of primitives, the at least one processor is further configured to modify one or more edge coefficients for each of the plurality of primitives.

[0119] State 11 is an apparatus according to any one of states 1 to 10, wherein the at least one processor is further configured to render each of the plurality of primitives based on the rasterization of each of the plurality of primitives.

[0120] State 12 is an apparatus according to any one of states 1 to 11, wherein the at least one processor is further configured to: send the rendered plurality of primitives after rendering each of the plurality of primitives.

[0121] State 13 is an apparatus according to any one of states 1 to 12, wherein a plurality of rendered primitives are sent to at least one of a display or a storage buffer.

[0122] State 14 is an apparatus according to any one of states 1 to 13, wherein one or more rendering passes are associated with a foveated rendering procedure.

[0123] State 15 is an apparatus according to any one of states 1 to 14, wherein the plurality of primitives are received from at least one application outside the graphics processing unit (GPU) pipeline or at least one game outside the GPU pipeline.

[0124] State 16 is an apparatus according to any one of states 1 to 15, further comprising at least one of an antenna or transceiver coupled to at least one processor.

[0125] State 17 is a graphics processing method used to implement any one of states 1 to 16.

[0126] State 18 is a device for graphics processing, including components for implementing any one of states 1 to 16.

[0127] Sample 19 is a computer-readable medium that stores computer-executable code, which, when executed by a processor, causes the at least one processor to implement any one of samples 1 to 16.

[0128] 100: Content Generation System 104: Equipment 107: Graphics Processing Pipeline 120: Processing Unit 121: Internal Memory 122: Content Encoder / Decoder 123: Internal Memory 124: System Memory 126: Communication Interface 127: Display Processor 128: Receiver 130: Transmitter 131: Monitor 132: Transceiver 198: Determining Components 200: GPU 210: Command Processor (CP) 212: Drawing call packet 220:VFD 222:VS 224: Vertex Cache (VPC) 226: Triangle Setting Engine (TSE) 228: Raster Imager (RAS) 230: Z Processing Engine (ZPE) 232: Pixel Interpolator (PI) 234: Fragment Shader (FS) 236: Render Backend (RB) 238: Level 2 (L2) Cache (UCHE) 240: System Memory 250: Command Buffer 260: Context register packet 261: Context State 300: Image or surface 302: Area 310: block 311: block 312: block 313: block 314: block 315: block 321: Primitive 322: Primitive 323: Primitive 324: Primitive 350: First-person perspective 351: Second Viewpoint 400: Figure 410: Primitive 500: Image 511: block 512: blocks 513: block 514: block 520: Primitive 600: Figure 611: Primitive 612: Primitive 613: Primitive 614: Primitive 650: Figure 700: Figure 710: Steps 720: Steps 730: Steps 740: Steps 800: Figure 810: Steps 820: Steps 830: Steps 840: Steps 900: Communication Flowchart 902: GPU Pipeline 904: GPU component 906: Buffer 910: Steps 912: Primitive 920: Steps 930: Steps 940: Steps 950: Steps 960: Steps 970: Steps 980: Steps 982: Primitive 1000: Flowchart 1002: Steps 1006: Steps 1008: Steps 1012: Steps 1100: Flowchart 1102: Steps 1104: Steps 1106: Steps 1108: Steps 1110: Steps 1112: Steps 1112a: Steps 1112b: Steps 1114: Steps 1116: Steps

[0129] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An apparatus for graphics processing, comprising: One memory; and at least one processor coupled to the memory and configured to: receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; perform a block pass on the plurality of primitives, the block pass being associated with an unscaled sampling space of the plurality of primitives, wherein the block pass classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; perform one of one or more rendering passes for each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transformation for each of the plurality of primitives; After performing one of the one or more rendering passes for each of the one or more blocks, a culling procedure is performed on each of the plurality of primitives; and each of the plurality of primitives is rasterized based on at least one of the magnified or reduced sampling space, wherein, in order to rasterize each of the plurality of primitives, the at least one processor is configured to: calculate a coverage of each of the plurality of primitives in at least one of the magnified or reduced sampling space, and wherein, in order to calculate the coverage of each of the plurality of primitives, the at least one processor is configured to: modify one or more edge coefficients for each of the plurality of primitives using XY scaling factors, wherein rasterizing each of the plurality of primitives is based on an equation: R = EaX step + EbY step + Cref, where Ea is an edge equation of a first primitive A, Eb is an edge equation of a second primitive B, X step is an X step component, Y step is a Y step component, and Cref is a constant.

2. The apparatus according to claim 1, wherein the viewport transformation for each of the plurality of primitives is associated with the unscaled sampling space for the plurality of primitives.

3. The apparatus according to claim 2, wherein the viewport transformation is associated with at least one offset parameter of the unscaled viewport transformation.

4. The apparatus according to claim 2, wherein the viewport transformation is associated with each of a plurality of geometric parameters of all the plurality of primitives in the unscaled sampling space.

5. The apparatus according to claim 1, wherein the block transfer uses an unscaled sampling space to assign each of the plurality of primitives to the one or more blocks in which each primitive appears.

6. The apparatus according to claim 1, wherein at least one of the enlarged sampling space or the reduced sampling space corresponds to a scaling factor.

7. The apparatus according to claim 6, wherein the at least one processor is further configured to: receive from a graphics processing unit (GPU) driver the scaling factor for at least one of the enlarged sampling space or the reduced sampling space.

8. The apparatus according to claim 1, wherein the at least one processor is further configured to: render each of the plurality of primitives based on the rasterization of each of the plurality of primitives.

9. The apparatus according to claim 8, wherein the at least one processor is further configured to: send the rendered plurality of primitives after rendering each of the plurality of primitives.

10. The apparatus according to claim 9, wherein, in order to transmit the rendered plurality of primitives, the at least one processor is configured to transmit the rendered plurality of primitives to at least one of a display or a storage buffer.

11. The apparatus according to request item 1, wherein the one or more rendering passes are associated with a foveated rendering procedure.

12. The apparatus according to claim 1 further includes a transceiver coupled to the at least one processor, wherein, in order to receive the plurality of primitives, the at least one processor is configured to receive the plurality of primitives from at least one application outside a graphics processing unit (GPU) pipeline via the transceiver.

13. A method for graphics processing, comprising: The method comprises: receiving a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; performing a block pass on the plurality of primitives, the block pass being associated with an unscaled sampling space for the plurality of primitives, wherein the block pass classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; performing one or more rendering passes on each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transform for each of the plurality of primitives; performing a culling procedure on each of the plurality of primitives after performing one or more rendering passes on each of the one or more blocks; and rasterizing each of the plurality of primitives based on at least one of the enlarged sampling space or the reduced sampling space. In order to rasterize each of the plurality of primitives, the at least one processor is configured to: calculate a coverage area of ​​each of the plurality of primitives in at least one of the magnified or reduced sampling spaces, and wherein, in order to calculate the coverage area of ​​each of the plurality of primitives, the at least one processor is configured to: modify one or more edge coefficients for each of the plurality of primitives using an XY scaling factor, wherein rasterizing each of the plurality of primitives is based on an equation: R = EaX step + EbY step + Cref, where Ea is an edge equation of a first primitive A, Eb is an edge equation of a second primitive B, X step is an X step component, Y step is a Y step component, and Cref is a constant.

14. The method of claim 13, wherein the viewport transformation for each of the plurality of primitives is associated with the unscaled sampling space for the plurality of primitives.

15. The method of claim 14, wherein the viewport transformation is associated with at least one offset parameter of the unscaled viewport transformation.

16. The method of claim 14, wherein the viewport transformation is associated with each of a plurality of geometric parameters of all the plurality of primitives in the unscaled sampling space.

17. The method of request item 13, wherein the block transfer uses an unscaled sampling space to assign each of the plurality of primitives to the one or more blocks in which each primitive appears.

18. The method of claim 13, wherein at least one of the enlarged sampling space or the reduced sampling space corresponds to a scaling factor.

19. The method according to claim 18 further includes: The scaling factor is received from a graphics processing unit (GPU) driver for at least one of the magnified or reduced sampling space.

20. The method according to claim 13 further includes: Each of the plurality of primitives is rendered based on the rasterization of each of the primitives.

21. The method according to request item 20 further includes: Send the rendered primitives after rendering each of the plurality of primitives.

22. The method of claim 21, wherein the rendered plurality of primitives are sent to at least one of a display or a storage buffer.

23. The method of request item 13, wherein the one or more rendering passes are associated with a foveated rendering procedure.

24. The method of claim 13, wherein the plurality of primitives are received from at least one application outside a graphics processing unit (GPU) pipeline.

25. An apparatus for graphics processing, comprising: A component for receiving a plurality of primitives associated with one or more frames in a scene, a portion of which is associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; a component for performing a block pass on the plurality of primitives, the block pass being associated with an unscaled sampling space for the plurality of primitives, wherein the block pass classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; a component for performing one of one or more rendering passes for each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transform for each of the plurality of primitives; A component for performing a culling procedure on each of the plurality of primitives after performing one of the one or more rendering passes for each of the one or more blocks; and a component for rasterizing each of the plurality of primitives based on at least one of the enlarged sampling space or the reduced sampling space, wherein the component for rasterizing each of the plurality of primitives includes: a component for calculating a coverage area of ​​each of the plurality of primitives in at least one of the enlarged sampling space or the reduced sampling space, and wherein the component for calculating the coverage area of ​​each of the plurality of primitives includes: a component for modifying one or more edge coefficients for each of the plurality of primitives using an XY scaling factor, wherein the component for rasterizing each of the plurality of primitives is based on an equation: R = EaX step + EbY step + Cref, where Ea is an edge equation of a first primitive A, Eb is an edge equation of a second primitive B, X step is an X step component, Y step is a Y step component, and Cref is a constant.

26. A non-transitory computer-readable medium storing computer-executable code for graphics processing, the code, when executed by a processor, causing the processor to: receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with at least one of an enlarged sampling space or a reduced sampling space for the plurality of primitives; perform a block pass on the plurality of primitives, the block pass being associated with an unscaled sampling space of the plurality of primitives, wherein the block pass classifies each of the plurality of primitives into one or more blocks associated with each of the one or more frames; perform one of one or more rendering passes for each of the one or more blocks, each of the one or more rendering passes being associated with at least one of the enlarged sampling space or the reduced sampling space, each of the one or more rendering passes including a viewport transform for each of the plurality of primitives; After performing one of the one or more rendering passes for each of the one or more blocks, a culling procedure is performed on each of the plurality of primitives; and each of the plurality of primitives is rasterized based on at least one of the magnified or reduced sampling space, wherein rasterizing each of the plurality of primitives includes the following steps: calculating a coverage area of ​​each of the plurality of primitives in at least one of the magnified or reduced sampling space, and wherein calculating the coverage area of ​​each of the plurality of primitives includes the following steps: modifying one or more edge coefficients for each of the plurality of primitives using XY scaling factors, wherein rasterizing each of the plurality of primitives is based on an equation: R = EaX step + EbY step + Cref, where Ea is an edge equation of a first primitive A, Eb is an edge equation of a second primitive B, X step is an X step component, Y step is a Y step component, and Cref is a constant.

Images