Electrically erasable programmable read only memory (eeprom) cell and forming method thereof

Abstract

An electrically erasable programmable read-only memory (EEPROM) cell includes a first gate, a second gate, and an erase gate. The first and second gates are disposed on a substrate. The first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erase gate is sandwiched between the first and second gates. Both the side portion of the first floating gate directly below the erase gate and the side portion of the second floating gate directly below the erase gate have multiple tips. The present invention further provides a method for forming an electrically erasable programmable read-only memory (EEPROM) cell.

Description

Technical Field

[0001] This invention relates to a memory cell and a method for forming the same, and more particularly to an electronically erasable rewritable read-only memory cell and a method for forming the same. Prior Technology

[0002] Semiconductor memory devices are basically divided into two types: volatile memory devices and non-volatile memory devices. Volatile memory devices include Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Non-volatile memory devices include Electrically Erasable Programmable Read Only Memory (EEPROM), Ferroelectric Random Access Memory (FeRAM), Phase-change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), and Flash Memory. When the external power supply is cut off, volatile memory loses all stored data, while non-volatile memory continues to retain its previously stored data. Summary of the Invention

[0003] This invention proposes an electronically erasable rewritable read-only memory cell and a method for forming the same. The cell forms a floating gate with multiple tips, and these tips are adjacent to the erase gate. Therefore, the electronic erasure capability of the memory cell can be improved by enhancing the local electric field to promote tip discharge (FN-tunneling).

[0004] This invention provides an electrically erasable programmable read-only memory (EEPROM) cell, comprising a first gate, a second gate, and an erase gate. The first gate and the second gate are disposed on a substrate, wherein the first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. The erase gate is sandwiched between the first gate and the second gate, wherein one side of the first floating gate directly below the erase gate and one side of the second floating gate directly below the erase gate each have multiple tips.

[0005] This invention provides a method for forming an electrically erasable programmable read-only memory (EEPROM) cell, comprising the following steps: First, a floating gate layer and a control gate are sequentially formed stacked on a substrate. Next, a first spacer wall is formed on the floating gate layer and a first sidewall of the control gate. Then, the exposed top of the floating gate layer is removed, thereby forming a front floating gate layer, wherein the front floating gate layer has a stepped sidewall portion. Subsequently, a second spacer wall is formed on the front floating gate layer and the first sidewall of the control gate. Then, the exposed portion of the front floating gate layer is removed, thereby forming a floating gate, wherein the floating gate has one or two stepped sidewall portions.

[0006] Based on the above, this invention proposes an electronically erasable rewritable read-only memory cell and its formation method. A first gate and a second gate are disposed on a substrate. The first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. An erase gate is disposed between the first gate and the second gate. Both the first floating gate directly below the erase gate and the second floating gate directly below the erase gate have multiple tips. Thus, this invention can improve the electronic erasure capability of the memory cell by facilitating tip tunneling (FN-tunneling) by aligning multiple tips adjacent to the erase gate. Simple Explanation of the Diagram

[0007] Figure 1 illustrates a cross-sectional schematic diagram of an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 2 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 3 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 4 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 5 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 6 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 7 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Figure 8 illustrates a cross-sectional schematic diagram of a method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. Implementation

[0008] Figure 1 illustrates a cross-sectional schematic diagram of an electronically erasable rewritable read-only memory cell according to a preferred embodiment of the present invention. As shown in Figure 1, a substrate 110 is provided, wherein the substrate 110 is, for example, a silicon substrate, a silicon-containing substrate (e.g., SiC), a group III-V substrate (e.g., GaN), a group III-V silicon-coated substrate (e.g., GaN-on-silicon), a graphene-on-silicon substrate, a silicon-on-insulator (SOI) substrate, or a substrate containing an epitaxial layer, etc., semiconductor substrates. In the illustration of this embodiment, only the substrate 110 of the electronically erasable rewritable read-only memory region is shown.

[0009] A first gate G1 and a second gate G2 are disposed on the substrate 110. In this embodiment, the first gate G1 includes a dielectric layer 122a, a first floating gate 124a, an oxy-nitrogen-oxygen layer 126a, a first control gate 128a, and a first hard shield 129a stacked from bottom to top, and the second gate G2 includes a dielectric layer 122b, a second floating gate 124b, an oxy-nitrogen-oxygen layer 126b, a second control gate 128b, and a second hard shield 129b stacked from bottom to top. The dielectric layers 122a / 122b may be, for example, oxide layers; the first floating gate 124a and the second floating gate 124b may be, for example, polycrystalline silicon layers; the oxygen-nitrogen-oxygen layers 126a / 126b are composed of oxide layers / nitride layers / oxide layers stacked from bottom to top; the first control gate 128a and the second control gate 128b may be, for example, polycrystalline silicon layers; and the first hard mask 129a and the second hard mask 129b may be, for example, nitride layers, but the present invention is not limited thereto.

[0010] Spacer wall 132a is located on the first floating gate 124a on the side of the first control gate 128a and the first hard shield 129a, and spacer wall 132b is located on the second floating gate 124b on the side of the second control gate 128b and the second hard shield 129b. In this embodiment, spacer walls 132a / 132b may be, for example, a double-layer spacer wall composed of an inner oxide layer and an outer nitride layer, but the present invention is not limited thereto. The first dielectric layer 134a further covers the sides of the first control gate 128a and the first hard shield 129a and the first floating gate 124a, and the second dielectric layer 134b further covers the sides of the second control gate 128b and the second hard shield 129b and the second floating gate 124b, in order to isolate the first floating gate 124a / the second floating gate 124b and the erase gate above. In a preferred embodiment, the first dielectric layer 134a and the second dielectric layer 134b are connected as a blanket-covered dielectric layer. In this embodiment, the first dielectric layer 134a and the second dielectric layer 134b are oxide layers, but the present invention is not limited thereto.

[0011] An erase gate 142 is sandwiched between a first gate G1 and a second gate G2. A first dielectric layer 134a isolates the erase gate 142 and the first floating gate 124a, while a second dielectric layer 134b isolates the erase gate 142 and the second floating gate 124b. One side portion P1 of the first floating gate 124a directly below the erase gate 142 and one side portion P2 of the second floating gate 124b directly below the erase gate 142 both have multiple tips. In this way, the present invention can improve the electronic erasure capability of memory cells by enhancing the local electric field to promote tip discharge. In this embodiment, the side portion P1 of the first floating gate 124a has two tips, and the side portion P2 of the second floating gate 124b has two tips. In other words, the side portion P1 of the first floating gate 124a directly below the erase gate 142 and the side portion P2 of the second floating gate 124b directly below the erase gate 142 are both two-stage stepped side portions, each of which contains two steps, but the present invention is not limited thereto.

[0012] A first word line 144a is disposed on the side of the first gate G1 opposite to the erase gate 142, and a second word line 144b is disposed on the side of the second gate G2 opposite to the erase gate 142. In a preferred embodiment, the erase gate 142, the first word line 144a, and the second word line 144b are all composed of the same material, such as polycrystalline silicon, and are formed simultaneously by the same process, but the present invention is not limited thereto.

[0013] Spacer walls 150a / 150b are disposed on the substrate 110 on the side of the first word line 144a relative to the erase gate 142 and the side of the second word line 144b relative to the erase gate 142. Bit line BL is located in the substrate 110 on the sides of spacer walls 150a / 150b. Bit line contact plug BLC is disposed directly above bit line BL. A source line SL is located in the substrate 110 directly below the erase gate 142.

[0014] The other side portion P3 of the first floating gate 124a relative to the erasure gate 142 and the other side portion P4 of the second floating gate 124b relative to the erasure gate 142 both have vertical sidewalls, but the present invention is not limited thereto.

[0015] In a preferred embodiment, a top surface T1 of the first hard mask 129a and a top surface T2 of the second hard mask 129b are higher than a top surface T3 of the erase gate 142 to prevent the first word line 144a, the second word line 144b from being connected to the erase gate 142 and causing a short circuit. In a more preferred embodiment, gap walls 160a / 160b are disposed on the erase gate 142 on the sides of the first hard mask 129a and the second hard mask 129b.

[0016] The following describes a method for forming an electronically erasable rewritable read-only memory cell with multiple pointed floating gates. Figures 2-8 illustrate a cross-sectional schematic diagram of the method for forming an electronically erasable rewritable read-only memory cell in a preferred embodiment of the present invention. As shown in Figure 2, a dielectric layer 222, a floating gate layer 224, an oxy-nitrogen-oxygen layer 226, a control gate 228, and a hard mask layer 229 are stacked on a substrate 210. In detail, a dielectric layer 222, a floating gate layer 224, an oxy-nitrogen-oxygen layer (not shown), a control gate layer (not shown), and a hard mask layer (not shown) are sequentially formed to cover the substrate 210. The hard mask layer (not shown), the control gate layer (not shown), and the oxy-nitrogen-oxygen layer (not shown) are then patterned to form a dielectric layer 222, a floating gate layer 224, an oxy-nitrogen-oxygen layer 226, a control gate 228, and a hard mask layer 229 stacked from bottom to top.

[0017] Referring to Figures 2-3, a first spacer wall 312 is formed on the floating gate layer 224 and on the side of a first sidewall S1 of the control gate 228. As shown in Figure 2, spacer walls 314 and 312 are formed on the floating gate layer 224 and on the sides of the first sidewall S1 and a second sidewall S2 of the control gate 228, respectively. Next, a photoresist K1 can be formed, and a selective doping process Q1 can be performed to form a first doped region 10 in the substrate 210 on the side of the first spacer wall 312 on the side of the second sidewall S2 of the control gate 228. Then, the first spacer wall 312 on the side of the second sidewall S2 of the control gate 228 is removed, but the first spacer wall 312 on the side of the first sidewall S1 of the control gate 228 is retained, as shown in Figure 3. Subsequently, the photoresist K1 is removed. The method of forming the first gap wall 312 on the floating gate layer 224 and the first side wall S1 side of the control gate 228 is not limited thereto.

[0018] As shown in Figures 3-4, after removing the photoresist K1, the exposed top 224a of the floating gate layer 224 is removed, thus forming a front floating gate layer 224b, wherein the front floating gate layer 224b has a stepped side portion C1. It is worth noting that the stepped side portion C1 is only located directly below the first spacer wall 312.

[0019] Please refer to Figures 5-7. A second spacer wall 322 is formed on the front floating gate layer 224b and on the side of the first sidewall S1 of the control gate 228. As shown in Figure 5, the second spacer wall 322 is formed on the front floating gate layer 224b and on the sides of the first sidewall S1 and the second sidewall S2 of the control gate 228, respectively. Since the first spacer wall 312 has not yet been removed, the second spacer wall 322 is located next to the first spacer wall 312 of the first sidewall S1 and next to the spacer wall 314 of the second sidewall S2, respectively. Then, as shown in Figure 6, a photoresist K3 can be formed first, and a doping process Q3 can be selectively performed to form a second doped region 30 in the substrate 210 on the side of the second spacer wall 322 on the side of the second sidewall S2 of the control gate 228. Then, remove the second gap wall 322 on the second sidewall S2 side of the control gate 228, but retain the second gap wall 322 on the first sidewall S1 side of the control gate 228, as shown in Figure 7. Subsequently, remove the photoresist K3.

[0020] As shown in Figure 7, after removing the photoresist K3, the exposed portion 224c of the front floating gate layer 224b is removed, thus forming a floating gate 224d. The floating gate 224d has a stepped side portion C1 (similar to the two stepped side portions P1 and P2 in Figure 1, where the tips of the steps promote discharge). Furthermore, in this embodiment, the width of the first gap wall 312 is defined as W1, and the width of the second gap wall 322 is defined as W2. Widths W1 and W2 affect the stepped width of the floating gate 224d. The stepped width can be adjusted according to actual needs, and this invention is not limited thereto.

[0021] Subsequently, as shown in Figure 8, after removing the first gap wall 312 and the second gap wall 322 on the first sidewall S1 side of the control gate 228, a blanket-type dielectric layer (not shown) and a polysilicon layer 240 are sequentially formed on the substrate 210 on the side of the floating gate 224d. A portion 242 of the polysilicon layer 240 on the stepped side portion C1 serves as an erase gate, and a portion 244 of the polysilicon layer 240 opposite to the stepped side portion C1 serves as a line. That is, the erase gate 242 covers the floating gate 224d and contacts the tip of the stepped side portion C1 of the floating gate 224d. This invention can form a floating gate 224d with multiple tips, thus improving the electronic erasure capability of memory cells by promoting tip discharge.

[0022] In summary, this invention proposes an electronically erasable rewritable read-only memory cell and its formation method. A first gate and a second gate are disposed on a substrate. The first gate includes a first floating gate and a first control gate stacked from bottom to top, and the second gate includes a second floating gate and a second control gate stacked from bottom to top. An erase gate is disposed between the first gate and the second gate. Both the first floating gate directly below the erase gate and the second floating gate directly below the erase gate have multiple tips. Thus, this invention can improve the electronic erasure capability of the memory cell by facilitating tip discharge (FN-tunneling) by adjacenting the multiple tips of the floating gate to the erase gate.

[0023] Preferably, the side portion of the first floating gate directly below the erase gate and the side portion of the second floating gate directly below the erase gate are both two-stage stepped side portions, each of which contains two steps, in order to improve the electronic erasure capability of the memory cell and simplify the manufacturing process. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0024] 10: First doped region 20: Doped region 30: Second doped region 110, 210: Base 122a, 122b, 222: Dielectric layers 124a: First floating gate 124b: Second floating gate 126a, 126b, 226: Oxygen-nitrogen-oxygen layer 128a: First control gate 128b: Second control gate 129a: First Hard Mask 129b: Second Hard Mask 132a, 132b, 314: Spacer wall 134a: First dielectric layer 134b: Second dielectric layer 142: Erasure gate 144a: First letter line 144b: Second letter line 150a, 150b, 160a, 160b: Spacer walls 224: Floating gate layer 224b: Pre-floating gate layer 224c: Partial 224d: Floating gate 228: Control gate 229: Hard mask layer 230: Oxide layer 312: First gap wall 322: Second spacer wall BL: Bitline BLC: Bitline Contact Plug C1: Side of the staircase G1: First gate G2: Second gate K1, K2, K3: Photoresist P1, P2: Side sections P3, P4: The other side section Q1, Q2, Q3: Doping process SL: Source Line S1: First sidewall S2: Second sidewall T1, T2, T3: Top surface W1, W2: Width

Claims

1. A method for forming an electrically erasable programmable read-only memory (EEPROM) cell, comprising: sequentially forming a floating gate layer, a control gate, and a hard mask on a substrate; forming a first gap wall on the floating gate layer and a first sidewall side of the control gate; removing the exposed top of the floating gate layer to form a front floating gate layer, wherein the front floating gate layer has a stepped sidewall portion; forming a second gap wall on the front floating gate layer and the first sidewall side of the control gate, wherein a width of the first gap wall is smaller than a width of the second gap wall; The exposed portion of the front floating gate layer is removed, thus forming a floating gate, wherein the floating gate has one or two stepped side sections; The method includes forming a single-layer blanket-type dielectric layer, wherein the blanket-type dielectric layer directly contacts one of the top surfaces of the substrate and the two stepped side portions of the floating gate; and forming a polycrystalline silicon layer on the blanket-type dielectric layer and on the substrate on the side of the floating gate, wherein a portion of the polycrystalline silicon layer on the side of the two stepped side portions serves as an erase gate, and a portion of the polycrystalline silicon layer opposite to the two stepped side portions serves as a line, and one of the top surfaces of the hard mask is higher than one of the top surfaces of the erase gate.

2. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, further comprising: forming a control gate layer and a hard mask layer on the floating gate layer; and patterning the hard mask layer and the control gate layer to form the control gate and the hard mask.

3. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, wherein the step of forming the first gap wall on the floating gate layer and on the first sidewall side of the control gate comprises: forming the first gap wall on the floating gate layer and on the first sidewall and a second sidewall side of the control gate respectively; and removing the first gap wall on the second sidewall side of the control gate, but retaining the first gap wall on the first sidewall side of the control gate.

4. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 3, further comprising, before removing the first gap wall on the second sidewall side of the control gate: forming a first doped region in the substrate on the first gap wall side of the second sidewall side of the control gate.

5. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, further comprising, after forming the front floating gate layer having the stepped side portion, removing the first gap wall of the first sidewall side of the control gate.

6. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, wherein the step of forming the second gap wall on the front floating gate layer and on the first sidewall side of the control gate comprises: forming the second gap wall on the front floating gate layer and on the first sidewall and a second sidewall side of the control gate respectively; and removing the second gap wall on the second sidewall side of the control gate, but retaining the second gap wall on the first sidewall side of the control gate.

7. The method for forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 6, further comprising, before removing the second gap wall on the second sidewall side of the control gate: forming a second doped region in the substrate on the second gap wall side of the second sidewall side of the control gate.

8. The method of forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, wherein the width of the first gap wall is half the width of the second gap wall.

9. The method of forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, further comprising forming another gap wall on the erase gate on one side of the hard shield.

10. The method of forming an electrically erasable programmable read-only memory (EEPROM) cell as described in claim 1, wherein the floating gate has a vertical sidewall on the other side of the two stepped side portion.

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