Semiconductor device and operating method thereof

Abstract

In one embodiment of this disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes: a first conductive structure extending in a first direction and coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced apart from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed above the first conductive structure in a third direction perpendicular to both the first and second directions; and a via structure disposed above the second conductive structure and in contact with the dielectric material, wherein the dielectric material is used to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Programmable read-only memory (PROM) is a form of digital memory in which each bit is locked by a fuse, anti-fuse, electric fuse, or any other type of fuse. Similar to other read-only memory (ROM), data in a PROM is permanent and immutable. PROMs are used in digital electronic devices to store permanent data typically used for low-level programming such as firmware or microcode. The difference from standard ROM is that data is written to ROM during manufacturing, and then programmed into the PROM after manufacturing. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] In addition, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," and the like, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] This disclosure provides various embodiments of fuse structures and methods for forming fuse structures. Metal fuse structures without the improved features disclosed herein may require maintaining large programming currents to break down fuse elements such as resistors, thereby changing the resistance from low to high. In such structures, the metal-oxide-semiconductor (MOS) programming device coupled to the fuse element may need to be excessively large to maintain such large currents.

[0008] In some embodiments, the fuse structure disclosed herein includes a fuse element comprising a conductive structure parallel to and not in contact with a second conductive structure, the second conductive structure having a via structure disposed on top of the second conductive structure. In some embodiments, the fuse structure is programmed by short-circuiting the fuse element. That is, in some embodiments, the fuse structure is programmed by applying a programmed voltage to the second conductive structure and causing a channel to be formed between the first conductive structure and the second conductive structure via breakdown (e.g., thereby changing the fuse resistance from high resistance to low resistance). In some embodiments, the width of the via structure is greater than the width of the second conductive structure, such that the spacing between the first conductive structure and the via structure is less than a second spacing between the first conductive structure and the second conductive structure.

[0009] Advantageously, embodiments of the disclosed structures and methods can achieve several benefits. In one embodiment, by using voltage instead of current to break down the fuse element and thereby programming the fuse structure, embodiments of the disclosed structures and methods can use smaller MOS programming devices. In another embodiment, embodiments of the disclosed structures and methods can achieve a reduction in the area of ​​the fuse structure (e.g., a reduction of more than 90%) compared to embodiments lacking the improvements disclosed herein. In yet another embodiment, the programming voltage required for dielectric breakdown can be reduced by properly sizing and arranging several via structures. For example, the via structures can be enlarged, the via structures can be offset along the direction of the conductive structure separation, and / or more via structures can be arranged in, for example, triangular, parallelogram, or trapezoidal configurations.

[0010] Figure 1A illustrates a schematic circuit diagram of a non-standardized single-transistor fuse unit 100 according to some embodiments. The fuse unit 100 includes a transistor M1. The transistor M1 may be a metal-oxide-semiconductor (MOS) transistor, an N-type MOS (NMOS) transistor, a P-type MOS (PMOS) transistor, or any other type of transistor. The transistor M1 may have a MOS device type with a standard threshold voltage (SVT), a low threshold voltage (LVT), a high threshold voltage (HVT), a high voltage (HV), or an input / output (IO), or any other type of MOS device. The transistor M1 may include a gate electrode, a drain electrode, and a source electrode. A first conductor (e.g., a word line WL) may be coupled to the gate electrode of M1. The second conductor (e.g., bit line bar BLB) may be coupled to the drain electrode of M1. The third conductor (e.g., ground VSS) may be coupled to the source electrode of M1. The fuse unit 100 may include a fourth conductor (e.g., bit line BL). In some embodiments, the second conductor BLB and the fourth conductor BL are not coupled (e.g., disconnected), or are weakly coupled (e.g., the resistance between BLB and BL is greater than 100 kilohms, or any of various other resistances).

[0011] In some embodiments, during a read operation of fuse unit 100, the first conductor WL receives an enable signal to enable M1, and the fourth conductor BL receives (e.g., carries) a first signal (e.g., a read signal) having a first voltage. In some embodiments, a sensor or memory controller senses the first signal on the fourth conductor BL. In some embodiments, the first voltage is greater than a predetermined threshold value, thereby indicating that fuse unit 100 has not been programmed.

[0012] In some embodiments, during programmed operation of fuse unit 100, the first conductor WL receives an enable signal to enable M1, and the fourth conductor BL receives a second signal (e.g., a programmed signal) having a second voltage. In some embodiments, a sensor or memory controller applies the second signal to the fourth conductor BL. In some embodiments, the second voltage is greater than a predetermined breakdown voltage and breaks down the dielectric to form a channel between BL and BLB, as further explained in Figure 1B.

[0013] Figure 1B illustrates a schematic circuit diagram of a programmed single-transistor fuse unit 120 according to some embodiments. The fuse unit 120 is similar to fuse unit 100, except that the fuse unit 120 includes a resistor R1 between the second conductor BLB and the fourth conductor BL. In some embodiments, the resistor R1 represents / embodies / is the resistance of a channel between the second conductor BLB and the fourth conductor BL, which is formed when the dielectric between BL and BLB responds to the application of a programmed voltage to the fourth conductor BL. In some embodiments, the resistor R1 is less than 10 ohms or any of various other resistors.

[0014] In some embodiments, during a read operation of fuse unit 120, the first conductor WL receives an enable signal to enable M1, and the fourth conductor BL receives a first signal having a third voltage. In some embodiments, the third voltage is less than a predetermined threshold value, thereby indicating that fuse unit 120 has been programmed.

[0015] Figure 1C illustrates a schematic circuit diagram of a non-standardized dual-transistor fuse unit 140 according to some embodiments. The fuse unit 140 includes transistors M1 and M2, each of which may be similar to transistor M1 in Figure 1A. A first conductor (e.g., a word line WL) may be coupled to the gate electrode of M1. A second conductor (e.g., an n-type common-source gate or NCGATE) may be coupled to the gate electrode of M2. In some embodiments, the second conductor NCGATE receives a bias signal having a voltage equal to or a small fraction (e.g., half) of a reference plane (e.g., a voltage source VDD).

[0016] A third conductor (e.g., bit line BLB) may be coupled to the drain electrode of M2. A fourth conductor (e.g., ground VSS) may be coupled to the source electrode of M1. The drain electrode of M1 may be coupled to the source electrode of M2 (e.g., transistors M1 and M2 are connected in series / stacked). Fuse unit 140 may include a fifth conductor (e.g., bit line BL). In some embodiments, the third conductor BLB and the fifth conductor BL are not coupled, or are weakly coupled (e.g., the resistance between BLB and BL is greater than 100 kilohms, or any of other various resistances). In some embodiments, the read and programmable operation of dual-transistor fuse unit 140 is similar to that of single-transistor fuse unit 100.

[0017] Figure 1D illustrates a schematic circuit diagram of a programmed dual-transistor fuse unit 160 according to some embodiments. Fuse unit 160 is similar to fuse unit 140, except that fuse unit 160 includes a resistor R1 between the third conductor BLB and the fifth conductor BL. The resistor R1 of fuse unit 160 is similar to the resistor R1 of fuse unit 120. In some embodiments, the read operation of dual-transistor fuse unit 160 is similar to the read operation of single-transistor fuse unit 120. Each of fuse units 100 to 160 may be described as a semiconductor device while remaining within the scope of one embodiment of this disclosure.

[0018] Figure 2 illustrates a circuit layout of a semiconductor fuse unit 200 according to various embodiments. Although the fuse unit 200 illustrated in Figure 2 includes two examples of fuse unit 140, it should be understood that fuse unit 200 may include any number of examples of fuse unit 140, or any number of examples of various other fuse units (e.g., fuse unit 100), while remaining within the scope of one embodiment of this disclosure. Fuse unit 200 may be described as a semiconductor device, while remaining within the scope of one embodiment of this disclosure.

[0019] The fuse unit 200 includes an active structure (OD). In some embodiments, the active structure OD is a doped semiconductor material (e.g., with p-type or n-type dopants). In some embodiments, the active structure OD is disposed above a semiconductor substrate. In some embodiments, a well (e.g., an n-type well or a p-type well) structure is disposed above the active structure OD.

[0020] The fuse unit 200 includes a plurality of metal-defined contacts / structures (MDs) extending in a first lateral direction (e.g., the Y direction) and spaced apart from each other in a second lateral direction (e.g., the X direction) perpendicular to the first lateral direction. Although the first lateral direction is described herein as the Y direction, the first and second lateral directions may be interchanged while remaining within the scope of one embodiment disclosed herein. As illustrated in Figure 2, the MDs include MD1, MD2, MD3, MD4, and MD5. In some embodiments, MD1 is attached to a first end of the MD along the second lateral direction, MD2 is attached between MD1 and MD3, MD3 is attached between MD2 and MD4, MD4 is attached between MD3 and MD5, and MD5 is attached to the other end of the MD. In some embodiments, at least a portion of each MD is positioned above (e.g., overlapping) the OD along a vertical direction (e.g., the Z direction) perpendicular to both the first and second lateral directions. In some embodiments, each MD corresponds to either the drain electrode or the source electrode of a transistor such as M1 or M2 in Figure 1C. In some embodiments, at least one of the MDs corresponds to the drain electrode of a first transistor (e.g., M1) and the source electrode of a second transistor (e.g., M2). Although the fuse unit 200 illustrated in Figure 2 includes five MDs, it should be understood that the fuse unit 200 may include any number of MDs while remaining within the scope of one embodiment disclosed herein. Each of the metal-defined structures may include any of Cu, Al, Co, Ru, W, or other various conductive materials.

[0021] The fuse unit 200 includes a plurality of gate-defined structures (GDs) extending in a first lateral direction and spaced apart from each other in a second lateral direction. As illustrated in Figure 2, the GDs include GD1, GD2, GD3, and GD4. In some embodiments, GD1 is attached to a first end of the GD along the second lateral direction, GD2 is attached between GD1 and GD3, GD3 is attached between GD2 and GD4, and GD4 is attached to the other end of the GD. In some embodiments, each GD is disposed between and spaced apart from a pair of MDs along the second lateral direction. In some embodiments, at least a portion of each GD is disposed above the OD in a vertical direction. In some embodiments, the portion of each GD covering the OD defines a conductive channel of a transistor. In some embodiments, each GD corresponds to a gate electrode of a transistor such as M1 or M2 in Figure 1C. Although the fuse unit 200 illustrated in Figure 2 includes four GDs, it should be understood that the fuse unit 200 may include any number of GDs while remaining within the scope of one embodiment disclosed herein. Each of the gate-defining structures includes any of Cu, Al, Co, Ru, W, polycrystalline Si, or other various conductive materials. In some embodiments, a portion of MD1, GD1, MD2, and OD (MD1, GD1, and MD2 disposed above this portion) corresponds to M2 in Figure 1C. In some embodiments, a portion of MD2, GD2, MD3, and OD (MD2, GD2, and MD3 disposed above this portion) corresponds to M1 in Figure 1C.

[0022] The fuse unit 200 includes a plurality of conductive structures of an Mx layer, which extend in a second lateral direction and are spaced apart from each other in a first lateral direction. In some embodiments, the Mx layer is one of a metal O (MO) layer or other various metal layers. As illustrated in Figure 2, the conductive structures of the Mx layer include a conductive structure bit line (BL) Mx, a conductive structure bit line bar (BLB) Mx, a conductive structure VSS, a conductive structure WL, and a conductive structure NCGATE. In some embodiments, BL Mx and BLB Mx are adjacent to each other along the first lateral direction (e.g., immediately adjacent to each other in the absence of other similar structures). In some embodiments, BL Mx is attached to a first end of the MD along the first lateral direction, BLB Mx is attached between BL Mx and VSS, VSS is attached between BLB Mx and WL, WL is attached between VSS and NCGATE, and NCGATE is attached to the other end of the MD. In some embodiments, the width MxW of each conductive structure in the Mx layer is in the range of 10 nm to 30 nm, or any of other various values. In some embodiments, the spacing MxSp between each pair of adjacent conductive structures in the Mx layer is in the range of 10 nm to 30 nm, or any of other various values. Each conductive structure in the Mx layer may include Cu, Al, Co, Ru, W, or any of other various conductive materials.

[0023] In some embodiments, BL Mx and BLB Mx are at least partially disposed above OD. In some embodiments, the conductive structure BL Mx is a solid structure corresponding to BL in Figure 1C, and the conductive structure BLB Mx is a solid structure corresponding to BLB in Figure 1C. In some embodiments, the fuse unit 200 includes a dielectric DIEL between BL Mx and BLB Mx along a second lateral direction and is in contact with (e.g., coupled to) BL Mx and BLB Mx. In some embodiments, a channel is formed in response to a voltage applied to BL Mx or another conductor electrically coupled to BL Mx (e.g., the dielectric DIEL creates a channel). In some embodiments, the applied voltage has a voltage level greater than a threshold value for forming the channel (e.g., a dielectric breakdown voltage threshold value). In some embodiments, the first resistance of the channel is lower than the second resistance of the dielectric DIEL.

[0024] In some embodiments, one or more of VSS, WL, and NCGATE are at least partially disposed above OD, while in other embodiments, VSS, WL, and NCGATE are not disposed above OD. In some embodiments, the conductive structure VSS is a solid structure corresponding to VSS in Figure 1C, the conductive structure WL is a solid structure corresponding to WL in Figure 1C, and the conductive structure NCGATE is a solid structure corresponding to NCGATE in Figure 1C. Although the fuse unit 200 illustrated in Figure 2 includes two conductive structures of the Mx layer, it should be understood that the fuse unit 104 may include any number of conductive structures of the Mx layer while remaining within the scope of one embodiment disclosed herein.

[0025] The fuse unit 200 includes a plurality of vias (VDs), each of which is disposed vertically between a corresponding conductive structure and a corresponding MD structure of the Mx layer. As illustrated in Figure 2, the first VD is between BLB Mx and MD1, the second VD is between VSS and MD3, and the third VD is between BLB Mx and MD5. In some embodiments, each VD is electrically coupled to and in contact with the corresponding MD structure and the corresponding conductive structure of the Mx layer, with the VD disposed between the corresponding MD structure and the corresponding conductive structure. Although the fuse unit 200 illustrated in Figure 2 includes three VDs, it should be understood that the layout circuit 200 may include any number of VDs while remaining within the scope of one embodiment disclosed herein. Each VD may include any of Cu, Al, Co, Ru, W, or other various conductive materials.

[0026] The fuse unit 200 includes a plurality of vias (VGs), each of which is disposed vertically between a corresponding conductive structure and a corresponding GD structure of the Mx layer. As illustrated in Figure 2, the first VG is between NCGATE and GD1, the second VG is between WL and GD2, the third VG is between WL and GD3, and the fourth VG is between NCGATE and GD4. In some embodiments, each GD is electrically coupled to and in contact with the corresponding GD structure and the corresponding conductive structure of the Mx layer, with the GD disposed between the corresponding GD structure and the corresponding conductive structure. Although the fuse unit 200 illustrated in Figure 2 includes two VGs, it should be understood that the layout circuit 200 may include any number of VGs while remaining within the scope of one embodiment disclosed herein. Each VG may include any of Cu, Al, Co, Ru, W, or other various conductive materials.

[0027] The fuse unit 200 includes a plurality of conductive structures of a My layer, which extend in a first lateral direction and are spaced apart from each other in a second lateral direction. In some embodiments, the My layer is one of a metal 1 (M1) layer or other various metal layers. In some embodiments, My is a metal layer disposed above and adjacent to Mx. That is, in some embodiments, there are no other metal layers between Mx and My, but via layers may be present. In some embodiments, each of the conductive structures of the My layer is partially disposed above one or more of the conductive structures of the Mx layer. In some embodiments, each of the conductive structures of the My layer is disposed or partially disposed above a corresponding MD. Although not illustrated, in some embodiments, one or more of the conductive structures of the My layer are not disposed above a corresponding MD, or are partially disposed above two or more MDs.

[0028] As shown in Figure 2, the conductive structure of the My layer includes conductive structures BL My, BLB My, BL My2, BLB My2, and BL My3. In some embodiments, BL My is attached to one end of the conductive structure in the My layer along a second lateral direction, BLB My is attached between BL My and BL My2, BL My2 is attached between BLB My and BLB My2, BLB My2 is attached between BL My2 and BL My3, and BL My3 is attached to the other end of the conductive structure in the My layer.

[0029] In some embodiments, the width MyW of each conductive structure in the My layer is in the range of 10 nm to 30 nm, or any of other various values. In some embodiments, the spacing MySp between any two adjacent conductive structures in the My layer is in the range of 10 nm to 30 nm, or any of other various values. Each conductive structure in the My layer may include any of Cu, Al, Co, Ru, W, or other various conductive materials.

[0030] In some embodiments, each of the conductive structures BL (e.g., BL My, BL My2, and BL My3) is a solid structure corresponding to BL in Figure 1C, and each of the conductive structures BLB (e.g., BLB My and BLB My2) is a solid structure corresponding to BLB in Figure 1C. Although the fuse unit 200 illustrated in Figure 2 includes five conductive structures of the My layer, it should be understood that the layout circuit 200 may include any number of conductive structures of the My layer while remaining within the scope of one embodiment of this disclosure.

[0031] The fuse unit 200 includes a plurality of vias (Vx) disposed vertically between corresponding conductive structures of the Mx layer and corresponding conductive structures of the My layer. As illustrated in Figure 2, the first Vx is between BL Mx and BL My, the second Vx is between BLB Mx and BLB My, the third Vx is between BL Mx and BL My2, the fourth Vx is between BLB Mx and BLB My2, and the fifth Vx is between BL Mx and BL My3. In some embodiments, each Vx is electrically coupled to and in contact with the corresponding conductive structures of the Mx layer and the corresponding conductive structures of the My layer, with the Vx disposed between the corresponding conductive structures. In some embodiments, each via Vx is only partially disposed above each conductive structure of the Mx layer (e.g., the width of the via along the first lateral direction is greater than the width of the corresponding conductive structure of the Mx layer along the first lateral direction). In some embodiments, one or more of the Vx vias may be aligned (e.g., centered) with respect to the corresponding conductive structure of the Mx layer along a first direction. In some embodiments, one or more of the Vx vias may be offset (e.g., not centered) with respect to the corresponding conductive structure of the Mx layer along the first direction.

[0032] In some embodiments, the dielectric DIEL of the Mx layer is also located in the Vx layer. In some embodiments, the DIEL is disposed above the BLB Mx and between each Vx and the BLB Mx. In some embodiments, the width VxW of each of the vias Vx is in the range of 10 nm to 30 nm, or any of other various values. In some embodiments, the length VxL of each of the vias Vx is in the range of 10 nm to 30 nm, or any of other various values. In some embodiments, VxW is equal to VxL, such that Vx is square in the plane along the first lateral direction and the second lateral direction. In some embodiments, VxW is different from VxL, such that Vx is rectangular in the plane along the first lateral direction and the second lateral direction. Although the fuse unit 200 illustrated in Figure 2 includes five Vx, it should be understood that the layout circuit 200 may include any number of Vx while remaining within the scope of one embodiment disclosed herein. Each via Vx may include any of CuAl, Co, Ru, W, or other various conductive materials.

[0033] Figure 3A illustrates a fuse structure 300 according to various embodiments. The fuse structure 300 is a cross-sectional view of various layers of the fuse unit 200 taken along A-A' according to various embodiments. As shown in Figure 3A, the fuse structure 300 includes an active structure (OD). In some embodiments, a metal-defined structure MD1 is disposed above the active structure OD. In some embodiments, a first via layer is disposed above the metal-defined structure MD1. In some embodiments, a via structure VD is disposed above the first via layer. In some embodiments, a first metal layer (e.g., a metal O layer) is disposed above the first via layer. In some embodiments, conductive structures BL Mx and BLB Mx are disposed above the first metal layer. In some embodiments, conductive structure BLB Mx is disposed above the via structure VD. In some embodiments, BL Mx and BLB Mx are spaced apart from each other in a first lateral direction (e.g., the Y direction). In some embodiments, the top surface (e.g., the top critical dimension) MxT of the conductive structure BL Mx has a width MxTW in the range of 10 nm to 30 nm or any of other various values.

[0034] In some embodiments, a second via layer (e.g., via layer 0) is disposed above the first metal layer. In some embodiments, a via structure Vx is disposed in the second via layer and above the conductive structure BL Mx. In some embodiments, Vx is wider than BL Mx. In some embodiments, the bottom surface (e.g., bottom critical dimension) VxB of the conductive structure Vx has a width VxBW in the range of 10 nm to 30 nm or any of other various values. In some embodiments, VxBW intersects MxTW in the range of 1 nm to 4 nm (e.g., on one or both sides) or any of other various values. VxBW can be made larger than MxTW by process adjustments. In some embodiments, a first spacing (e.g., space, distance) (VxSp) between Vx and BLB Mx is in the range of 6 nm to 30 nm or any of other various values. In some embodiments, a second spacing (MxSp) between BL Mx and BLB Mx is in the range of 10 nm to 30 nm or any of other various values. In some embodiments, the ratio of VxSp to MxSp is in the range of 0.4 to 1 (e.g., 0.4 to 0.9, 0.4 to 0.7, or 0.4 to 0.5), or any of the various other values.

[0035] In some embodiments, the via structure Vx may be aligned with respect to the conductive structure BL Mx along a first lateral direction. In some embodiments, the via structure Vx may be offset with respect to the conductive structure BL Mx along the first lateral direction such that the spacing between the via structure Vx and the conductive structure BLB Mx is smaller than a second spacing when the via structure Vx is not offset with respect to the conductive structure BL Mx. In some embodiments, the conductive structure BLB Mx, the conductive structure BL Mx, and the via structure Vx may be collectively referred to as a fuse element. Advantageously, a smaller spacing between the via structure Vx and the conductive structure BLB Mx allows for a lower voltage to be required for programming the fuse element.

[0036] A dielectric DIEL is disposed between the first metal layer and the second via layer. The dielectric DIEL is disposed between conductive structures BLB Mx and BL Mx, between conductive structure BLB Mx and via structure Vx, and above conductive structure BLB Mx. In some embodiments, a second metal layer (e.g., metal layer 1) is disposed above the second via layer. In some embodiments, conductive structure BL My is disposed in the second metal layer and above via structure Vx. Although not illustrated, other metal and via layers are within the scope of one embodiment disclosed herein.

[0037] Figure 3B illustrates a fuse structure 310 according to various embodiments. The fuse structure 310 is a cross-sectional view of various layers of the fuse unit 200 taken along A-A' according to various embodiments. In some embodiments, the fuse structure 310 corresponds to the fuse unit 160 of Figure 1D (e.g., a stylized fuse unit). In some embodiments, the fuse structure 310 is similar to the fuse structure 300, except for the differences described herein. In some embodiments, the fuse structure 310 includes a channel CH disposed between a via structure Vx and a conductive structure BLB Mx. The channel CH electrically couples the via structure Vx to the conductive structure BLB Mx. In some embodiments, the channel CH corresponds to R1 in Figure 1D. Each of the fuse structures 300 to 310 may be described as a semiconductor device while remaining within the scope of one embodiment of this disclosure.

[0038] Figure 4 illustrates a circuit layout of an array 400 of several fuse units, such as fuse units 200, according to some embodiments. In some embodiments, the array 400 is a 2×2 array of fuse units 200. In some embodiments, the fuse units are configured in a column-row configuration, wherein bit lines and bit bar lines extend in a first lateral direction (e.g., the Y direction) to couple to fuse units in the row, and word lines extend in a second lateral direction (e.g., the X direction) to couple to fuse units in the column. For example, BL0 extends along the first lateral direction to couple to each of the fuse units 200 in the first row, BL1 extends along the first lateral direction to couple to each of the fuse units 200 in the second row, WL0 extends along the second lateral direction to couple to each of the fuse units 200 in the first column, and WL1 extends along the second lateral direction to couple to each of the fuse units 200 in the second column. Although array 400 in Figure 4 is depicted as a 2×2 array, it should be understood that array 400 may include any number of fuse units while remaining within the scope of one embodiment disclosed herein.

[0039] Figures 5A through 5F respectively illustrate various circuit layouts of fuse units 500 to 550 according to some embodiments. In some embodiments, fuse units 500 to 550 are similar to fuse unit 200 of Figure 2, except for the differences described herein. At higher levels, the differences include the number of vias disposed, the arrangement of the vias relative to each other, and the shape of the vias. In some embodiments, the circuit layout of fuse unit 500 of Figure 5A includes: a plurality of Mx conductive structures (e.g., conductive structures of Mx layers) extending in a second lateral direction (e.g., X direction), a plurality of My conductive structures (e.g., conductive structures of My layers) extending in a first lateral direction (e.g., Y direction) at least partially disposed above the plurality of Mx conductive structures, and a plurality of vias disposed along a vertical direction between the two. Other layout details are omitted for simplicity.

[0040] In some embodiments, the plurality of Mx conductive structures include BL Mx and BLB Mx spaced apart from BL Mx in a first lateral direction. In some embodiments, the plurality of My conductive structures include BL My, BLB My spaced apart from BL My in a first lateral direction, and BL My2 spaced apart from BLB My in a first lateral direction. In some embodiments, the via is square (e.g., the length of the via is equal to the width of the via). In some embodiments, the vias are configured in a triangular configuration in a plane along the first and second lateral directions. For example, a first Vx is disposed between BL Mx and BL My, a second Vx is disposed between BLB Mx and BLB My, and a third Vx is disposed between BL Mx and BL My2. Advantageously, having more vias (e.g., having a triangular configuration) reduces the via-to-metal breakdown voltage compared to having only one via. Furthermore, having more vias reduces the likelihood that the fuse unit cannot be programmable due to metal or via process defects (e.g., because it is unlikely that all vias will be affected by the same process defects). Although the number of Mx conductive structures is two, the number of My conductive structures is three, and the number of vias is three, as illustrated in Figure 5A, it should be understood that the fuse unit 500 may include any number of Mx conductive structures, My conductive structures, and Vx vias, while remaining within the scope of one embodiment disclosed herein.

[0041] In some embodiments, two fuse walls (FWs) extend in a second lateral direction and are each spaced apart from the corresponding ends of a plurality of Mx conductive structures along a first lateral direction. In some embodiments, the FWs are floating (e.g., not coupled to any voltage / current / power source / signal source / power supply). In some embodiments, the FWs protect other circuitry during the breakdown of the fuse element of fuse unit 500 by isolating fuse unit 500 and preventing fuse material of fuse unit 500 (e.g., fuse element or conductive structure) from sputtering onto other circuitry. The fuse material may include Cu, Co, or any of a variety of other materials. Although the number of FWs is two as illustrated in Figure 5A, it should be understood that fuse unit 500 may include any number of FWs while remaining within the scope of one embodiment of this disclosure.

[0042] In some embodiments, the fuse unit 510 of Figure 5B is similar to the fuse unit 500 of Figure 5A, except for the differences described herein. At higher levels, the differences include the vias being configured in a parallelogram configuration in planes along the first and second lateral directions. In some embodiments, the fuse unit 510 includes an additional My conductive structure BLB My2 extending in the first lateral direction and spaced apart from BL My2 in the second lateral direction. In some embodiments, the fuse unit 510 includes an additional via structure (third Vx) disposed vertically between BLB Mx and BLB My2. Advantageously, having more vias (e.g., a parallelogram configuration) reduces the via-to-metal breakdown voltage compared to a triangular configuration with 3 vias. Furthermore, having more vias reduces the likelihood that the fuse unit is attributable to metal or via process defects that cannot be programmed. Although the number of My conductive structures and the number of vias are four as illustrated in Figure 5B, it should be understood that the fuse unit 520 may include any number of My conductive structures and Vx vias while remaining within the scope of one embodiment disclosed herein.

[0043] In some embodiments, the fuse unit 520 of Figure 5C is similar to the fuse unit 510 of Figure 5B, except for the differences described herein. At higher levels, the differences include vias configured in a trapezoidal configuration in planes along the first and second lateral directions. In some embodiments, the fuse unit 520 includes an additional My conductive structure BL My3 extending in the first lateral direction and spaced apart from BLB My2 in the second lateral direction. In some embodiments, the fuse unit 520 includes an additional via structure (fourth Vx) disposed vertically between BL Mx and BL My3. Advantageously, having more vias (e.g., a trapezoidal configuration) reduces the via-to-metal breakdown voltage compared to a parallelogram configuration with 4 vias. Furthermore, having more vias reduces the likelihood that the fuse unit is attributable to metal or via process defects that cannot be programmed. Although the number of My conductive structures and the number of vias are five as illustrated in Figure 5C, it should be understood that the fuse unit 520 may include any number of My conductive structures and Vx vias, while remaining within the scope of one embodiment disclosed herein.

[0044] In some embodiments, the Vx vias of fuse units 500 to 520 are configured in two or more columns (or rows), wherein the two or more columns (or rows) are offset from each other. That is, in some embodiments, a first plurality of Vx via structures are configured along a second lateral direction, wherein each of the first plurality of via structures is disposed above a different Mx conductive structure, and a second plurality of Vx via structures are configured along the second lateral direction, spaced apart from the first plurality of via structures in a first lateral direction and offset from the first plurality of via structures in a second lateral direction, wherein each of the second plurality of via structures is disposed above a different Mx conductive structure (e.g., different from each other and different from the Mx conductive structure above which the first plurality of via structures are disposed).

[0045] In some embodiments, the fuse unit 530 in Figure 5D, the fuse unit 540 in Figure 5E, and the fuse unit 550 in Figure 5F are similar to the fuse unit 500 in Figure 5A, the fuse unit 510 in Figure 5B, and the fuse unit 520 in Figure 5C, respectively, except that the Vx via is rectangular rather than square and the corresponding Mx conductive structure is wider. Advantageously, compared to a square via, having a larger rectangular via can reduce the via-to-metal breakdown voltage by increasing the surface area of ​​the via.

[0046] Figure 6 illustrates a circuit layout of a fuse unit 600 according to various embodiments. In some embodiments, fuse unit 600 is similar to fuse unit 200, except for the differences described herein. At higher levels, the differences include additional BL conductive structures disposed opposite to the first BL and BLB, wherein additional vias are disposed along the additional BL conductive structures. In some embodiments, in addition to the conductive structures of the Mx layer of fuse unit 200 (e.g., BL Mx, BLB Mx), fuse unit 600 includes a conductive structure BL Mx2 extending in a second lateral direction. In some embodiments, conductive structure BL Mx2 is spaced apart from BLB Mx in a first lateral direction (e.g., the Y direction) and disposed opposite to BL Mx and BLB Mx (e.g., such that the conductive structures are arranged in the order of BL Mx, BLB Mx, and BL Mx2 along the first lateral direction).

[0047] In some embodiments, in addition to the Vx vias of fuse unit 200, fuse unit 600 includes additional Vx vias. As illustrated in Figure 6, a sixth Vx is located between BL Mx2 and BL My, a seventh Vx is located between BL Mx2 and BL My2, and an eighth Vx is located between BL Mx2 and BL My3. Advantageously, having more vias (e.g., along additional BL conductive structures) reduces the via-to-metal breakdown voltage compared to having only one BL conductive structure where the vias are arranged along the BL conductive structure. Furthermore, having more vias reduces the likelihood that the fuse unit is attributable to metal or via process defects that cannot be programmed.

[0048] Figure 7A illustrates a fuse structure 700 according to various embodiments. The fuse structure 700 is a cross-sectional view of various layers of the fuse unit 600 taken along B-B' according to various embodiments. In some embodiments, the fuse structure 700 is similar to the fuse structure 300, except for the differences described herein. As illustrated in Figure 7A, in addition to the conductive structures Mx and BLB Mx of the fuse structure 300, a conductive structure BL Mx2 is disposed in a first metal layer. In some embodiments, the conductive structure BL Mx2 is disposed opposite to BL Mx and BLB Mx. In some embodiments, in addition to the via structure Vx of the fuse structure 300, a second via structure Vx is disposed in a second via layer. In some embodiments, the second via structure Vx is disposed above the conductive structure BL Mx2. In some embodiments, a dielectric DIEL is disposed between the conductive structures BLB Mx and BL Mx2, between the conductive structure BLB Mx and the second via structure Vx, and above the conductive structure BLB Mx2.

[0049] Figure 7B illustrates a fuse structure 710 according to various embodiments. Fuse structure 700 is a cross-sectional view of various layers of fuse unit 600 taken along B-B' according to various embodiments. In some embodiments, fuse structure 710 is similar to fuse structure 310, except for the differences described herein. In some embodiments, fuse structure 710 includes the same differences included in fuse structure 700. Additionally, in some embodiments, fuse structure 710 includes a second channel CH disposed between via structure Vx and conductive structure BLB Mx2.

[0050] Figures 8A through 8F respectively illustrate various circuit layouts of fuse units 800 through 850 according to some embodiments. In some embodiments, fuse units 800 through 850 are respectively similar to fuse units 500 through 550 of Figures 5A through 5F, except for the differences described herein. At higher levels, the differences include additional BL conductive structures disposed opposite to the first BL and BLB, wherein additional vias are disposed along the additional BL conductive structures. In some embodiments, in addition to the Mx conductive structures (e.g., BL Mx, BLB Mx) of each fuse unit of fuse units 500 through 550, each of fuse units 800 through 850 includes an Mx conductive structure BL Mx2 extending in a second lateral direction (e.g., the X direction). In some embodiments, the Mx conductive structure BL Mx2 is opposite to BL Mx and BLB Mx. In some embodiments, each fuse unit 800 through 850 includes two additional Vx vias. In some embodiments, a first additional Vx via is disposed between BL Mx2 and BL My, and a second additional Vx via is disposed between BL Mx2 and BL My2. In some embodiments, fuse units 820 and 850 include a third additional Vx via disposed between BL Mx2 and BL My3. Advantageously, having more vias (e.g., disposed along additional BL conductive structures) reduces the via-to-metal breakdown voltage compared to having only one BL conductive structure where the vias are disposed along the BL conductive structure. Furthermore, having more vias reduces the likelihood that the fuse unit is attributable to metal or via process defects that cannot be programmed.

[0051] Figure 9 illustrates a circuit layout of a fuse unit 900 according to various embodiments. In some embodiments, the fuse unit 900 is similar to the fuse unit 200, except for the differences described herein. In some embodiments, the conductive structures of the My layers BLB My and BLB My2 are omitted. In some embodiments, a plurality of Vx vias are arranged along a second lateral direction (e.g., the X direction) (e.g., arranged in a single column). For example, a first Vx is located between BL Mx and BL My, a second Vx is located between BL Mx and BL My2, and a third Vx is located between BL Mx and BL My3. In some embodiments, the Vx between BLB Mx and BLB My and the Vx between BLB Mx and BLB My2 are omitted. In some embodiments, the plurality of Vx vias are not disposed between BLBs (e.g., BLB Mx, BLB My). In some embodiments, each of the plurality of Vx vias is disposed only between the corresponding BLs (e.g., BL Mx, BL My).

[0052] Figures 10A to 10F respectively illustrate various circuit layouts of fuse units 1000 to 1050 according to various embodiments. In some embodiments, fuse units 1000 to 1050 are similar to fuse units 500 to 550 of Figures 5A to 5F, except for the differences described herein. In some embodiments, the My conductive structures BLB My and BLB My2 are omitted from fuse units 1000 to 1050. In some embodiments, the Vx disposed between BLB Mx and BLB My in fuse units 800 to 850, and the Vx between BLB Mx and BLB My2 in fuse units 810, 820, 840, and 850 are omitted.

[0053] Figure 11 illustrates a flowchart of a method 1100 for operating a semiconductor device according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of method 1100 may be used to form a fuse unit 200 or a fuse structure 300. Please note that method 1100 is merely an example and is not intended to limit an embodiment of the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 1100 depicted in Figure 11, and some other operations are only briefly described herein.

[0054] Method 1100 begins with the following operation 1110: receiving a word line voltage via a first conductive structure (e.g., WL in Figure 2) electrically coupled to the gate of a metal-oxide-semiconductor (MOS) device (e.g., M2 in Figure 2). Method 1100 continues with the operation 1120 of receiving a bit line voltage greater than a predetermined voltage via a second conductive structure (e.g., BL Mx or BL My in Figure 2).

[0055] In some embodiments, method 1100 continues with operation 1130 of creating a channel (e.g., CH in Figure 3B) between the second conductive structure and a third conductive structure (e.g., BLB Mx in Figure 2) electrically coupled to one of the drain or source of the MOS device. In some embodiments, the second conductive structure is electrically coupled to a via structure (e.g., Vx in Figure 2), and the method includes creating a channel between the via structure and the third conductive structure. In some embodiments, method 1100 further includes sensing a second bit line voltage via the second conductive structure. In some embodiments, the second bit line voltage is less than a predetermined threshold value, thereby indicating that the fuse unit has been programmed.

[0056] Figure 12 is a block diagram illustrating the configuration of a memory system according to various embodiments of the present disclosure. As shown in the figure, the memory system 1200 according to various embodiments of the present disclosure includes a non-volatile memory device 1220 and a memory controller 1210.

[0057] The non-volatile memory device 1220 may include an array 400 of fuse units, such as fuse units 200, as disclosed herein. Furthermore, the non-volatile memory device 1220 may be a multi-chip package comprising several ferromagnetic memory chips.

[0058] The memory controller 1210 is used to control the non-volatile memory device 1220. The memory controller 1210 may include an SRAM 1211, a central processing unit (CPU) 1212, a host interface (I / F) 1213, an error-correcting code (ECC) 1214, and a memory interface 1215. The SRAM 1211 acts as the operating memory of the CPU 1212. The CPU 1212 performs general-purpose control operations for data exchange with the memory controller 1210. The host interface 1213 includes a data exchange protocol coupled to a host computer of the memory system 1200. In addition, the ECC 1214 can detect and correct errors included in the data read from the non-volatile memory device 1220. The memory interface 1215 interfaces with the control of the non-volatile memory device 1220. The memory controller 1210 can further store code data for interfacing with the host.

[0059] In one embodiment of this disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes: a first conductive structure extending in a first direction, the first conductive structure being coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced apart from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed above the first conductive structure in a third direction perpendicular to both the first and second directions; and a via structure disposed above the second conductive structure and in contact with the dielectric material, wherein the dielectric material is used to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

[0060] In some embodiments, the semiconductor device further includes a third conductive structure extending in a second direction and disposed above the via structure. In some embodiments, the semiconductor device further includes a fourth conductive structure extending in a first direction and spaced apart from the second conductive structure and the first conductive structure; and a second via structure disposed above the fourth conductive structure, wherein the third conductive structure is disposed above the second via structure.

[0061] In some embodiments, the semiconductor device further includes: a second via structure disposed above the first conductive structure and spaced apart from the via in a first direction and a second direction; and a fourth conductive structure extending in a second direction, spaced apart from the third conductive structure in the first direction and disposed above the second via structure.

[0062] In some embodiments, the semiconductor device further includes: a first plurality of via structures disposed along a second direction, wherein each of the first via structures is disposed over a different conductive structure, wherein a third conductive structure is disposed over the via structure, wherein the first via structure includes a via structure; and a second plurality of via structures disposed along the second direction, spaced apart from the first via structure in a first direction and offset from the first via structure in the second direction, wherein each of the second via structures is disposed over a different conductive structure, wherein a fourth conductive structure is disposed over the second via structure, wherein the second via structure includes a second via structure.

[0063] In some embodiments, the second conductive structure includes a first width in the second direction, and the third conductive structure includes a second width in the first direction, the first width being equal to the second width, and the through-hole structure being square in a plane along the first and second directions. In some embodiments, the second conductive structure includes a first width in the second direction, the third conductive structure includes a second width in the first direction, and the first width is greater than the second width, and the through-hole structure is rectangular in a plane along the first and second directions.

[0064] In some embodiments, the via structure is aligned with the second conductive structure along the second direction. In some embodiments, the via structure is offset from the second conductive structure along the second direction. In some embodiments, the second conductive structure includes a first width in the second direction, the via structure includes a second width in the second direction, and the second width is greater than the first width.

[0065] In one embodiment of this disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes: a first conductive structure extending in a first direction, the first conductive structure being coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced apart from the first conductive structure by a first distance in a second direction perpendicular to the first direction; and a via structure disposed above the second conductive structure, wherein the via structure is spaced apart from the first conductive structure by a second distance in the second direction, and wherein a ratio of the second distance to the first distance is in the range of 0.4 to 0.9.

[0066] In some embodiments, the semiconductor device further includes a third conductive structure extending in a second direction and disposed above the via structure. In some embodiments, the semiconductor device further includes a fourth conductive structure extending in a first direction and spaced apart from the second conductive structure and the first conductive structure; and a second via structure disposed above the fourth conductive structure, wherein the third conductive structure is disposed above the second via structure.

[0067] In some embodiments, the semiconductor device further includes: a second via structure disposed above the first conductive structure and spaced apart from the via in a first direction and a second direction; and a fourth conductive structure extending in a second direction, spaced apart from the third conductive structure in the first direction and disposed above the second via structure.

[0068] In some embodiments, the second conductive structure includes a first width in the second direction, the third conductive structure includes a second width in the first direction, the first width of the second conductive structure is equal to the second width, and the through-hole structure is square in a plane along the first and second directions.

[0069] In some embodiments, the second conductive structure includes a first width in the second direction, the third conductive structure includes a second width in the first direction, the first width of the second conductive structure is greater than the second width, and the through-hole structure is rectangular in a plane along the first and second directions. In some embodiments, the through-hole structure is aligned with the second conductive structure along the second direction. In some embodiments, the through-hole structure is offset from the second conductive structure along the second direction.

[0070] In one embodiment of this disclosure, a method of operating a semiconductor device is disclosed. In some embodiments, the method includes: receiving a word line voltage via a first conductive structure electrically coupled to a metal-oxide-semiconductor (MOS) device; receiving a bit line voltage greater than a predetermined voltage via a second conductive structure; and creating a channel between the second conductive structure and a third conductive structure, the third conductive structure being electrically coupled to either a drain or a source of the MOS device. When a voltage is applied to the second conductive structure, a channel is created between the first conductive structure and a via structure. In some embodiments, the method further includes the step of: sensing a second bit line voltage via the second conductive structure.

[0071] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the appearance of an embodiment disclosed herein. Those skilled in the art should understand that an embodiment disclosed herein can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that such equivalent constructions can be modified, replaced, and substituted in various ways herein without departing from the spirit and scope of an embodiment disclosed herein. [Simplified Explanation of the Diagram]

[0004] The present disclosure is best understood by reading in conjunction with the accompanying drawings from the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1A and 1B each illustrate schematic circuit diagrams of fuse units in various operational stages according to some embodiments. Figures 1C and 1D each illustrate schematic circuit diagrams of another fuse unit in various operational stages according to some embodiments. Figure 2 illustrates the circuit layout of a fuse unit according to some embodiments. Figures 3A and 3B each illustrate cross-sectional views of a fuse structure in various operational stages according to some embodiments. Figure 4 illustrates the circuit layout of an array of several fuse units 200 according to some embodiments. Figures 5A to 5F illustrate various circuit layouts of fuse units according to some embodiments. Figure 6 illustrates the circuit layout of a fuse unit according to some embodiments. Figures 7A and 7B each illustrate cross-sectional views of fuse structures at various operational stages according to some embodiments. Figures 8A to 8F illustrate various circuit layouts of fuse units according to some embodiments. Figure 9 illustrates a circuit layout of a fuse unit according to some embodiments. Figures 10A to 10F illustrate various circuit layouts of fuse units according to some embodiments. Figure 11 illustrates a flowchart of an example method of operating a semiconductor device according to some embodiments. Figure 12 is a block diagram illustrating the configuration of a memory system according to some embodiments. [Biomaterial Storage]

[0073] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device comprising: a first conductive structure extending in a first direction and connected to a drain electrode of a metal-oxide-semiconductor device; a second conductive structure extending in the first direction, parallel to the first conductive structure, and spaced apart from the first conductive structure in a second direction perpendicular to the first direction, wherein a gate electrode of the metal-oxide-semiconductor device is connected to a conductive structure other than the first conductive structure or the second conductive structure; a dielectric material disposed at least above the first conductive structure; and a via structure disposed directly above the second conductive structure and electrically coupled to the second conductive structure in a third direction perpendicular to the first and second directions, wherein when a voltage is applied to the second conductive structure, a channel is formed in the dielectric material to electrically short-circuit the second conductive structure and the first conductive structure.

2. The semiconductor device as claimed in claim 1, further comprising: a third conductive structure extending in the second direction and disposed above the via structure.

3. A semiconductor device comprising: a first conductive structure extending in a first direction and connected to a drain electrode of a metal-oxide-semiconductor device; a second conductive structure extending in the first direction and spaced apart from the first conductive structure, and spaced apart from the first conductive structure by a first distance in a second direction perpendicular to the first direction, wherein a gate electrode of the metal-oxide-semiconductor device is connected to a conductive structure other than the first conductive structure or the second conductive structure; and a via structure disposed above the second conductive structure, wherein the via structure is spaced apart from the first conductive structure by a second distance in the second direction, and wherein a ratio of the second distance to the first distance is in the range of 0.4 to 0.9; wherein when a voltage is applied to the second conductive structure, a channel is formed in a dielectric material to electrically short-circuit the second conductive structure and the first conductive structure.

4. The semiconductor device as claimed in claim 3, further comprising: a third conductive structure extending in the second direction and disposed above the via structure.

5. A method of operating a semiconductor device, comprising the steps of: receiving a word line voltage via a first conductive structure electrically coupled to a gate of a metal-oxide-semiconductor device; receiving a bit line voltage greater than a predetermined voltage via a second conductive structure; and generating a first channel between the second conductive structure and a third conductive structure, the third conductive structure being electrically coupled to either a drain or a source of the metal-oxide-semiconductor device, wherein the second and third conductive structures extend in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction.

6. A method of operating a semiconductor device, comprising the steps of: receiving a word line voltage via a first conductive structure electrically coupled to a gate of a metal-oxide-semiconductor device; receiving a bit line voltage via a second conductive structure; and generating a first channel between the second conductive structure and a third conductive structure, the third conductive structure being electrically coupled to either a drain or a source of the metal-oxide-semiconductor device; wherein the second and third conductive structures extend in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction, and the first conductive structure extends in the second direction.

7. A method of operating a semiconductor device, comprising the steps of: receiving a word line voltage via a first conductive structure electrically coupled to a gate of a metal-oxide-semiconductor device; receiving a word line voltage via a second conductive structure extending in a first direction; and generating a channel between a third conductive structure and a fourth conductive structure, each of the third conductive structure and the fourth conductive structure extending in a second direction, wherein the fourth conductive structure is electrically coupled to either a drain or a source of the metal-oxide-semiconductor device; wherein the second conductive structure is located above the third conductive structure and the fourth conductive structure.

8. A semiconductor device comprising: a first conductive structure extending in a first direction; a second conductive structure extending in a second direction perpendicular to the first direction, wherein the second conductive structure and the first conductive structure are perpendicularly spaced apart from each other; and a via structure connecting the second conductive structure to the first conductive structure; wherein a programmed voltage is applied through the via structure to the second conductive structure and to the first conductive structure to short-circuit the first conductive structure and the third conductive structure, and wherein the third conductive structure and the first conductive structure are parallel to each other and spaced apart from each other in the second direction.

9. A semiconductor device comprising: a first conductive structure extending in a first direction; a second conductive structure extending in the first direction, parallel to and spaced apart from the first conductive structure; a third conductive structure extending in a second direction perpendicular to the first direction and located above the first conductive structure and the second conductive structure; and a via structure connecting the third conductive structure to the first conductive structure; wherein a programmed voltage is applied through the via structure to the third conductive structure and to the first conductive structure to short-circuit the first conductive structure and the second conductive structure.

10. A semiconductor device comprising: a plurality of first conductive structures extending in a first direction and parallel to each other; a plurality of second conductive structures extending in a second direction perpendicular to the first direction and parallel to each other, wherein the second conductive structures and the first conductive structures are perpendicularly spaced apart from each other; and a plurality of via structures connecting one of the corresponding second conductive structures to one of the corresponding first conductive structures; wherein a programmed voltage is applied through the corresponding via structures to each of the second conductive structures to short-circuit one of the corresponding first conductive structures and the other of the first conductive structures.

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