Package comprising a substrate with post interconnects and a solder resist layer having a cavity

Abstract

A package includes: a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first and second substrates. The first substrate includes: at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

Description

Technical Field

[0001] This patent application claims priority and benefit to non-provisional application No. 17 / 579,434 filed with the U.S. Patent and Trademark Office on January 19, 2022, the entire contents of which are incorporated herein by reference, as if fully set forth herein and for all applicable purposes.

[0002] Various features relate to packages with substrates and integrated devices. Prior Technology

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing a variety of electrical functions. There is a continuous need to provide packages with better performance. There is also a continuous need to reduce the overall size of the package. Summary of the Invention

[0004] Various features are involved in packaging with a substrate and integrated devices.

[0005] One example provides a package including: a first substrate including at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate; and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of post interconnects; and a solder mask coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The solder mask includes a cavity. The cavity is located between the first integrated device and the solder mask. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0006] Another example provides a package including: a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first and second substrates. The first substrate includes: at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity. The cavity is located between the first integrated device and the second solder resist layer. The plurality of solder interconnects are located between the first and second substrates. The plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0007] Another example provides a package including: a first substrate including at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate; and cells coupled to the first and second substrates for inter-substrate interconnection. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder resist layer coupled to a second surface of the second substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The cells for inter-substrate interconnection are located between the first and second substrates. The cells for inter-substrate interconnection are configured to couple the first substrate to the second substrate.

[0008] Another example provides a method comprising: providing a first substrate, the first substrate including at least one first dielectric layer and a first plurality of interconnects. The method couples a first integrated device to the first substrate. The method couples a second substrate to the first substrate via a plurality of inter-substrate interconnects such that the plurality of inter-substrate interconnects are located between the first substrate and the second substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder resist layer coupled to a second surface of the second substrate. The solder resist layer includes a cavity. The cavity is located between the solder resist layer and the first integrated device. Simple Explanation of the Diagram

[0009] Various features, properties and advantages will become apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which the same element symbols are indicated accordingly throughout.

[0010] Figure 1 illustrates an exemplary cross-sectional profile of a package that includes a substrate comprising pillar interconnects and a solder mask layer having cavities.

[0011] Figure 2 illustrates a close-up cross-sectional profile of the package, which includes a substrate comprising pillar interconnects and a solder mask layer with cavities.

[0012] Figure 3 illustrates an exemplary cross-sectional profile of a package that includes a substrate comprising pillar interconnects and a solder mask layer having cavities.

[0013] Figure 4 shows a close-up cross-sectional profile of the package, which includes a substrate comprising pillar interconnects and a solder mask layer with cavities.

[0014] Figures 5A-5C illustrate exemplary sequences for manufacturing a package, the package including a substrate including pillar interconnects and a solder mask layer having cavities.

[0015] Figures 6A-6C illustrate exemplary sequences for manufacturing a package, the package including a substrate including pillar interconnects and a solder mask layer having cavities.

[0016] Figure 7 illustrates an exemplary flowchart of a method for manufacturing a package, the package including a substrate including pillar interconnects and a solder mask layer having cavities.

[0017] Figure 8 illustrates an exemplary flowchart of a method for manufacturing a package, the package including a substrate coupled via ball interconnects.

[0018] Figure 9 illustrates an exemplary flowchart of a method for manufacturing a package, the package including a substrate coupled via solder interconnects.

[0019] Figures 10A-10C illustrate exemplary sequences for fabricating substrates including pillar interconnects and solder mask layers with cavities.

[0020] Figure 11 shows an exemplary flowchart of a method for manufacturing a substrate including pillar interconnects and a solder resist layer with cavities.

[0021] Figure 12 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Implementation

[0022] In the following description, specific details are provided to provide a thorough understanding of the various aspects of this invention. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid confusing the various aspects of this invention.

[0023] This application describes a package comprising: a first substrate including at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate; and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate. The second substrate includes a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder mask layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The solder mask layer includes a cavity. The cavity is located between the first integrated device and the solder mask layer. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate. This application also describes a package comprising: a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate includes: at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity. The cavity is located between the first integration device and the second solder resist layer. A plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of solder interconnects are configured to couple the first substrate to the second substrate. As further described below, this package provides high-density interconnect routing (e.g., high-density inter-substrate interconnects) between the substrates, which helps to provide improved packaging performance while maintaining a small and thin package. An exemplary package including a substrate having pillar interconnects and a solder mask layer with cavities.

[0024] Figure 1 illustrates a cross-sectional profile view of package 100, which includes a substrate having pillar interconnects and a solder mask layer with cavities. Package 100 may be a package-on-package (PoP). Package 100 is coupled to board 106 via a plurality of solder interconnects 110. Board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. Board 106 may include a printed circuit board (PCB).

[0025] Package 100 includes a first substrate 102, a first integrated device 105, and an underfill 152. The first substrate 102, the first integrated device 105, and the underfill 152 can be considered part of a first package. The first integrated device 105 is coupled to a first surface (e.g., the top surface) of the substrate 102 via a plurality of pillar interconnects 150. The first substrate 102 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 102 via the plurality of pillar interconnects 150. Solder interconnects (not shown) may be present between the plurality of pillar interconnects 150 and the first plurality of interconnects 122. That is, in some embodiments, solder interconnects may be used to couple the plurality of pillar interconnects 150 to the first plurality of interconnects 122. The underfill 152 is located between the first integrated device 105 and the first substrate 102. The first substrate 102 includes a solder mask layer 124 and a solder mask layer 126. Solder resist layer 124 is coupled to a first surface of the first substrate 102 (e.g., the top surface of the first substrate 102). Solder resist layer 126 is coupled to a second surface of the first substrate 102 (e.g., the bottom surface). A plurality of passive devices 130 are coupled to the second surface of the first substrate 102. Passive devices 130 may include capacitors and / or inductors.

[0026] Package 100 includes a second substrate 104 and a second integrated device 107. The second substrate 104 and the second integrated device 107 can be considered part of a second package. The second integrated device 107 is coupled to a first surface (e.g., top surface) of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of interconnects 142. As will be further described below, the second plurality of interconnects 142 may include a plurality of pillar interconnects. The second integrated device 107 is coupled to a second plurality of interconnects 142 of the second substrate 104 via the plurality of solder interconnects 170. The second substrate 104 includes a solder mask layer 144 and a solder mask layer 146. The solder mask layer 144 is coupled to the first surface (e.g., top surface) of the second substrate 104. The solder mask layer 146 is coupled to a second surface (e.g., bottom surface) of the second substrate 104. The solder mask layer 146 includes cavities. The solder mask layer 146 may include a variable thickness. The second substrate 104 may be an interposer. The second substrate 104 may include two or more metal layers. In some embodiments, the second substrate 104 may be fabricated using an improved semi-additive process (mSAP). In some embodiments, the first substrate 102 may be fabricated using an embedded trace substrate (ETS) process.

[0027] The second substrate 104 is coupled to the first substrate 102 via a plurality of ball interconnects 109 and a plurality of solder interconnects 190. The plurality of ball interconnects 109 and the plurality of solder interconnects 190 are coupled to (i) a first plurality of interconnects 122 of the first substrate 102, and (ii) a second plurality of interconnects 142 of the second substrate 104. The plurality of ball interconnects 109 may include copper balls. The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 may be cells for inter-substrate interconnection. The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 may be examples of inter-substrate interconnection. The plurality of solder interconnects 190 facilitates the coupling of the plurality of ball interconnects 109 to interconnections from the first substrate 102 and interconnections from the second substrate 104. The plurality of solder interconnects 190 may at least partially encapsulate the plurality of ball interconnects 109.

[0028] The first integrated device 105 is located between the first substrate 102 and the second substrate 104. A cavity in the solder mask layer 146 is located above (e.g., above) the first integrated device 105. For example, the cavity may be located between the solder mask layer 146 and the first integrated device 105. The back side of the first integrated device 105 faces the cavity in the solder mask layer 144. The cavity may be located between the solder mask layer 146 and the back side of the first integrated device 105. The cavity may be located in the region of a package including the first integrated device 105.

[0029] Package 100 includes an enclosure layer 108. Enclosure layer 108 is located between a first substrate 102 and a second substrate 104. Enclosure layer 108 may enclose a first integrated device 105, a plurality of ball interconnects 109, and / or a plurality of solder interconnects 190. Enclosure layer 108 may be located within a cavity of solder mask layer 144. Enclosure layer 108 may include a mold, resin, and / or epoxy resin. Enclosure layer 108 may be a unit for enclosure. Enclosure layer 108 may be provided via compression and transfer molding, sheet molding, or liquid molding processes.

[0030] As will be further described below, the use of cavities (e.g., 250), pillar interconnects (from a plurality of interconnects 142), a plurality of ball interconnects 109, and / or a plurality of solder interconnects 190 in the solder mask 146 allows for more interconnects between substrates, which helps improve package performance. For example, the use of cavities (e.g., 250), pillar interconnects (from a plurality of interconnects 142), a plurality of ball interconnects 109, and / or a plurality of solder interconnects 190 in the solder mask 146 allows for interconnects between substrates with smaller pitch (e.g., smaller center-to-center distance between adjacent interconnects), which allows for more interconnects between substrates (thus increasing interconnect density). The use of cavities, pillar interconnects (from a plurality of interconnects 142), a plurality of ball interconnects 109, and / or a plurality of solder interconnects 190 in the solder mask 146 allows for thinner packages with smaller gaps between substrates, enabling the package to have inter-substrate interconnects between substrates with low pitch. This, in turn, helps to provide high wiring density interconnects between substrates. For example, the interconnect between the first substrate 102 and the second substrate 104 can have a pitch of less than 270 micrometers. For example, the interconnect between the first substrate 102 and the second substrate 104 can have a pitch between 150 and 270 micrometers. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 102 and the second substrate 104 can be equal to or greater than 300. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 102 and the second substrate 104 can be up to 400. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 102 and the second substrate 104 can be between 300 and 400. Reducing the spacing between adjacent interconnects (e.g., adjacent ball interconnects, adjacent solder interconnects) and increasing the number of inter-substrate interconnects helps to provide high-density interconnect wiring in the package. High-density interconnect wiring between substrates helps to improve package performance. In some embodiments, reducing the spacing between adjacent interconnects can reduce the space occupied by the interconnects by up to 30%. In addition to increasing wiring density, the overall package thickness can also be reduced by providing a solder mask layer with cavities, where the cavities in the solder mask layer are located above the integrated device. That is, the cavities can be located between the solder mask layer and the back of the integrated device.

[0031] Figure 2 illustrates a close-up view of package 100. Package 100 includes a solder mask 146, which includes a cavity 250. The cavity 250 is filled with an occlusive layer 108. The solder mask 146 includes two portions with different thicknesses. The solder mask 146 includes solder mask 146a (e.g., a first portion of solder mask 146) and solder mask 146b (e.g., a second portion of solder mask 146). Solder mask 146a has a thickness 240 and solder mask 146b has a thickness 242. Solder mask 146a is thicker than solder mask 146b. Thickness 240 is greater than thickness 242. A gap 282 exists between solder mask 146b and the back portion of the first integrated device 105. Gap 282 includes the cavity 250 of solder mask 146. Gap 282 is filled with an occlusive layer 108. Gap 280 exists between solder mask 146a and solder mask 124. Gap 280 is filled with sealing layer 108. In some embodiments, the thickness of gap 282 may be less than the thickness of gap 280. Thus, for example, the vertical gap between solder mask 146b and the back surface of integrated device 105 may be less than the vertical gap between solder mask 146a of second substrate 104 and solder mask 124 of first substrate 102. In some embodiments, a portion of the back surface of integrated device 105 may be located in cavity 250. Thus, cavity 250 facilitates accommodating integrated device 105 between first substrate 102 and second substrate 104 while reducing the space or gap between first substrate 102 and second substrate 104.

[0032] The first plurality of interconnects 142 includes a plurality of pillar interconnects 142a. The plurality of pillar interconnects 142a are coupled to a plurality of ball interconnects 109 and a plurality of solder interconnects 190. The thickness of the plurality of pillar interconnects 142a is less than the thickness of the solder mask layer 146a. The plurality of pillar interconnects 142a may be laterally surrounded by the solder mask layer 146a. The first plurality of interconnects 122 includes a plurality of interconnects 122a (e.g., pad interconnects). The plurality of interconnects 122a are coupled to a plurality of ball interconnects 109 and a plurality of solder interconnects 190.

[0033] In some embodiments, the plurality of ball interconnects 109 may have a pitch of approximately 200-270 micrometers. In some embodiments, the plurality of ball interconnects 109 may include up to 400 ball interconnects laterally surrounding the first integrated device 105. Each ball interconnect 109 may represent a separate electrical path between the first substrate 102 and the second substrate 104. This configuration allows for a smaller and thinner package with higher density wiring between the first substrate 102 and the second substrate 104, while avoiding any short circuits between adjacent interconnects (e.g., adjacent ball interconnects 109, adjacent solder interconnects 190). The cavity 250 in the solder mask 146 helps ensure that the solder mask does not directly contact the first integrated device 105, as the first substrate 102 and the second substrate 104 are coupled together as close as possible.

[0034] In some embodiments, to maximize and / or optimize the number of inter-substrate interconnects between the first substrate 102 and the second substrate 104, it may be necessary to reduce the spacing between the inter-substrate interconnects to equal or less than 270 micrometers (e.g., 200–270 micrometers). To achieve this, the vertical gap and / or vertical space between the interconnects from the first substrate 102 (e.g., 122a) and the interconnects from the second substrate 104 (e.g., 142a) can be reduced, allowing the use of a plurality of ball interconnects 109 and / or a plurality of solder interconnects 190 with smaller dimensions and / or smaller spacing. This can be achieved by providing pillar interconnects (from the plurality of interconnects 142), which helps to reduce the vertical gap between the interconnects from the first substrate 102 and the interconnects from the second substrate 104, thereby allowing for smaller-sized and / or smaller-pitch ball interconnects 109 and / or solder interconnects 190. As the vertical gap between the first substrate 102 and the second substrate 104 is reduced, the first integration device 105 can collide with the second substrate 104. To accommodate the first integrated device 105 between the first substrate 102 and the second substrate 104, while still reducing the vertical gap between the first substrate 102 and the second substrate 104, a cavity 250 is formed in the solder mask layer 146 such that the back side of the first integrated device 105 does not directly contact the second substrate 104. In some embodiments, the use of pillar interconnects in the second substrate 104 helps to provide a smaller pitch for the solder interconnects between the substrates because the pillar interconnects of the second substrate 104 and the interconnects of the first substrate 102 are closer to each other. A smaller pitch between solder interconnects means that more solder interconnects can be provided in the same area, which means more high-density wiring between the substrates. As will be further described below at least in Figures 3 and 4, in some embodiments, the use of pillar interconnects in both the first substrate 102 and the second substrate 104 helps to provide a smaller pitch for the solder interconnects between the substrates because the pillar interconnects of each substrate are closer to each other. This means that more high-density wiring can be provided between the substrates.

[0035] The various components of package 100 can have various thicknesses and / or dimensions. In some embodiments, the plurality of pillar interconnects 142a can have a thickness of approximately 40-50 micrometers. In some embodiments, the solder mask layer 146a can have a thickness of approximately 65-80 micrometers (e.g., 240). In some embodiments, the gap (e.g., 280) between the solder mask layer 124 and the solder mask layer 146a can be approximately 75-95 micrometers. In some embodiments, the plurality of ball interconnects 109 can have a diameter of approximately 100-120 micrometers. In some embodiments, the plurality of ball interconnects 109 can be optional. Therefore, some packages can bypass the use of the plurality of ball interconnects 109.

[0036] Figure 3 illustrates a cross-sectional profile of package 300, which includes a substrate with pillar interconnects and a solder mask layer with cavities. Package 300 may be a stacked package (PoP). Package 300 may be similar to package 100 described in Figures 1 and 2. Package 300 bypasses the use of ball interconnects while still providing a thin package with high-density wiring (e.g., high-density inter-substrate interconnects) between substrates. Package 300 is coupled to board 106 via a plurality of solder interconnects 110.

[0037] Package 300 includes a first substrate 302, a first integrated device 105, and a bottom filler 152. The first substrate 302, the first integrated device 105, and the bottom filler 152 can be considered part of a first package. The first integrated device 105 is coupled to a first surface (e.g., the top surface) of the substrate 302 via a plurality of pillar interconnects 150. The first substrate 302 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. The first plurality of interconnects 122 includes a plurality of pillar interconnects 322. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 302 via the plurality of pillar interconnects 150. Solder interconnects (not shown) may be present between the plurality of pillar interconnects 150 and the first plurality of interconnects 122. The plurality of pillar interconnects 150 can be coupled to the first plurality of interconnects 122 using solder interconnects. The bottom filler 152 is located between the first integrated device 105 and the first substrate 302. The first substrate 302 includes a solder resist layer 324 and a solder resist layer 126. The solder resist layer 324 is coupled to a first surface (e.g., the top surface) of the first substrate 302. The thickness of the solder resist layer 324 is greater than (e.g., thicker than) the thickness of a plurality of pillar interconnects 322. The plurality of pillar interconnects 322 may be laterally surrounded by the solder resist layer 324. The solder resist layer 126 is coupled to a second surface (e.g., the bottom surface) of the first substrate 302. A plurality of passive devices 130 are coupled to the second surface of the first substrate 302. The passive devices 130 may include capacitors and / or inductors.

[0038] Package 300 includes a second substrate 104 and a second integrated device 107. The second substrate 104 and the second integrated device 107 can be considered part of a second package. The second integrated device 107 is coupled to a first surface (e.g., a top surface) of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of interconnects 142. As will be further described below, the second plurality of interconnects 142 may include a plurality of pillar interconnects. The second integrated device 107 is coupled to a second plurality of interconnects 142 of the second substrate 104 via the plurality of solder interconnects 170. The second substrate 104 includes a solder resist layer 144 and a solder resist layer 146. The solder resist layer 144 is coupled to the first surface (e.g., a top surface) of the second substrate 104. The solder resist layer 146 is coupled to a second surface (e.g., a bottom surface) of the second substrate 104. The solder resist layer 146 includes cavities. The solder resist layer 146 may include a variable thickness. The second substrate 104 may be an interposer. The first substrate 302 may include a solder mask layer 324 with a thickness (e.g., 460 mm) greater than (e.g., thicker than) the thickness of a plurality of pillar interconnects 322. The second substrate 104 may include two or more metal layers. In some embodiments, the second substrate 104 may be fabricated using an improved semi-additive process (mSAP). In some embodiments, the first substrate 302 may be fabricated using an embedded trace substrate (ETS) process.

[0039] The second substrate 104 is coupled to the first substrate 302 via a plurality of solder interconnects 190. The plurality of solder interconnects 190 are coupled to (i) a plurality of pillar interconnects 322 of the first substrate 302, and (ii) a second plurality of pillar interconnects 142a of the second substrate 104. The plurality of solder interconnects 190 may be cells for inter-substrate interconnection. The plurality of solder interconnects 190 may be an example of a plurality of inter-substrate interconnections.

[0040] The first integration device 105 is located between the first substrate 302 and the second substrate 104. A cavity (e.g., 250) in the solder mask layer 146 is located above (e.g., on top of) the first integration device 105. The back side of the first integration device 105 faces the cavity in the solder mask layer 146. In some embodiments, at least a portion of the back side of the first integration device 105 may be located in the cavity 250 of the solder mask layer 146.

[0041] Package 300 includes a sealing layer 108. The sealing layer 108 is located between a first substrate 302 and a second substrate 104. The sealing layer 108 may seal the first integrated device 105 and / or a plurality of solder interconnects 190. The sealing layer 108 may be located in a cavity of the solder mask layer 146.

[0042] As will be further described below, the use of cavities, pillar interconnects (from a plurality of interconnects 142), a plurality of solder interconnects 190, and a plurality of pillar interconnects 322 in the solder mask layer 146 allows for thinner packages having interconnects between substrates having low pitch. This, in turn, facilitates providing high wiring density interconnects (e.g., high-density inter-substrate interconnects) between substrates. For example, the interconnects between the first substrate 302 and the second substrate 104 can have a pitch of less than 270 micrometers. For example, the interconnects between the first substrate 302 and the second substrate 104 can have a pitch between 150 and 270 micrometers. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 302 and the second substrate 104 can be equal to or greater than 300. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 302 and the second substrate 104 can be up to 400. In some embodiments, the number of inter-substrate interconnects (e.g., the number of pins) between the first substrate 302 and the second substrate 104 can be between 300 and 400. Reducing the spacing between adjacent interconnects (e.g., adjacent solder interconnects) and increasing the number of inter-substrate interconnects helps to provide high-density interconnect wiring in a package. High-density inter-substrate interconnect wiring (e.g., high-density inter-substrate interconnects) helps to improve package performance. In some embodiments, reducing the spacing between adjacent interconnects can reduce the space occupied by the interconnects by up to 30%. In addition to increasing wiring density, the overall thickness of the package can also be reduced by providing a solder mask with cavities, wherein the cavities in the solder mask are located above the integrated device.

[0043] Figure 4 illustrates a close-up view of package 300. Package 300 includes a solder mask 146, which includes a cavity 250. The cavity 250 is filled with a sealing layer 108. The solder mask 146 includes two portions with different thicknesses. The solder mask 146 includes solder mask 146a and solder mask 146b. Solder mask 146a has a thickness 240 and solder mask 146b has a thickness 242. Solder mask 146a is thicker than solder mask 146b. Thickness 240 is greater than thickness 242. A gap 282 exists between solder mask 146b and the back portion of the first integrated device 105. Gap 282 includes the cavity 250 of solder mask 146. Gap 282 is filled with the sealing layer 108. A gap 480 exists between solder mask 146a and solder mask 124. Gap 480 is filled with the sealing layer 108.

[0044] The first plurality of interconnects 142 includes a plurality of pillar interconnects 142a. The plurality of pillar interconnects 142a are coupled to a plurality of solder interconnects 190. The thickness of the plurality of pillar interconnects 142a is less than the thickness of the solder mask layer 146a. The thickness of the plurality of pillar interconnects 322 is less than the thickness of the solder mask layer 324. The plurality of pillar interconnects 322 are coupled to the plurality of solder interconnects 190.

[0045] In some embodiments, to maximize and / or optimize the number of inter-substrate interconnects between the first substrate 102 and the second substrate 104, it may be necessary to reduce the spacing between the inter-substrate interconnects to equal or less than 270 micrometers (e.g., 150–270 micrometers). To achieve this, the vertical gap and / or vertical space between the interconnects from the first substrate 102 (e.g., 122a) and the interconnects from the second substrate 104 (e.g., 142a) can be reduced, allowing the use of a plurality of solder interconnects 190 with smaller dimensions and / or smaller spacing. This can be achieved by providing pillar interconnects (from the plurality of interconnects 142) and pillar interconnects 322 (from the plurality of interconnects 122), which helps to reduce the vertical gap between the interconnects from the first substrate 102 and the interconnects from the second substrate 104, thereby allowing for smaller dimensions and / or smaller spacing of the solder interconnects 190. As the vertical gap between the first substrate 102 and the second substrate 104 is reduced, the first integration device 105 may collide with the second substrate 104. To accommodate the first integrated device 105 between the first substrate 102 and the second substrate 104 while still reducing the vertical gap between the first substrate 102 and the second substrate 104, a cavity 250 is formed in the solder mask layer 146 such that the back side of the first integrated device 105 does not directly contact the second substrate 104. The following are exemplary dimensions and / or values ​​for various components that facilitate inter-substrate interconnects with a pitch equal to or less than 270 micrometers (e.g., 150–270 micrometers). In some embodiments, the use of pillar interconnects in both the first substrate 102 and the second substrate 104 helps to provide a smaller pitch for solder interconnects between the substrates (due to the pillar interconnects on each substrate being closer to each other). A smaller pitch between solder interconnects means that more solder interconnects can be provided in the same area, which translates to more high-density wiring between the substrates.

[0046] The various components of package 300 can have various thicknesses and / or dimensions. In some embodiments, the plurality of pillar interconnects 142a can have a thickness of approximately 40-50 micrometers. In some embodiments, the solder mask 146a can have a thickness of approximately 65-80 micrometers (e.g., 240). In some embodiments, the gap between solder mask 124 and solder mask 146a (e.g., 480) can be approximately 50-70 micrometers. In some embodiments, solder mask 324 can have a thickness of approximately 30-50 micrometers (e.g., 460). In some embodiments, the plurality of solder interconnects 190 can have a diameter of approximately 50-70 micrometers. In some embodiments, the thickness of gap 282 can be less than the thickness of gap 480. Therefore, for example, the vertical gap between solder mask 146b and the back surface of integrated device 105 can be less than the vertical gap between solder mask 146a of second substrate 104 and solder mask 324 of first substrate 102. In some embodiments, a portion of the back side of the integrated device 105 may be located within the cavity 250. Thus, the cavity 250 facilitates the housing of the integrated device 105 between the first substrate 102 and the second substrate 104, while reducing the space or gap between the first substrate 102 and the second substrate 104.

[0047] In some embodiments, the aforementioned dimensions facilitate providing a package comprising a plurality of solder interconnects 190, which may have a pitch of approximately 150-270 micrometers. In some embodiments, the plurality of solder interconnects 190 may comprise up to 400 solder interconnects (e.g., solder balls) laterally surrounding the first integrated device 105. Each of the solder interconnects 190 may represent a separate electrical path between the first substrate 302 and the second substrate 104. This configuration allows for smaller and thinner packages with higher wiring density between the first substrate 302 and the second substrate 104, while avoiding any short circuits between adjacent interconnects (e.g., adjacent solder interconnects 190). The cavity 250 in the solder mask 146 helps ensure that the solder mask does not directly contact the first integrated device 105, as the first substrate 302 and the second substrate 104 are coupled together as close as possible.

[0048] As used in this application, pillar interconnects may be interconnects whose height (e.g., thickness) is equal to and / or greater than their width and / or diameter. Pillar interconnects may be coupled to pad interconnects. Pillar interconnects may extend vertically from pad interconnects (e.g., vertically from the surface of the pad interconnect). Pillar interconnects may be laterally surrounded by a solder mask (e.g., partially or completely). Pillar interconnects may extend vertically and / or perpendicularly from the surface of the substrate (e.g., a first surface, a second surface). Pillar interconnects of the substrate may extend vertically and / or perpendicularly from the surface of the substrate and away from the dielectric layer of the substrate where the pillar interconnect is part. Pillar interconnects may not be in direct contact with the dielectric layer of the substrate. Pillar interconnects (e.g., 142a, 322) may be in direct contact with the solder mask layer of the substrate (e.g., 146a, 324).

[0049] The integrated device (e.g., 105, 107) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. The integrated device (e.g., 105, 107) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include transistors. The integrated device may be an example of an electronic component and / or electronic device. In some embodiments, the integrated device may be a wafer. The manufacture of wafers can provide better and / or improved yield (relative to other types of integrated devices), which can reduce the overall cost of manufacturing wafers. Different wafers can have different sizes and / or shapes. Different wafers can be configured to provide different functions. Different wafers may have different interconnect densities (e.g., interconnects with different widths and / or spacing). In some implementations, multiple wafers can be used to perform the functions of one or more wafers (e.g., one or more integrated devices). Using multiple wafers that perform multiple functions can reduce the overall cost of the package compared to using a single wafer to perform all the functions of the package.

[0050] The package (e.g., 100, 300) can be implemented in a radio frequency (RF) package. The RF package can be a radio frequency front-end (RFFE) package. The package (e.g., 100, 300) can be configured to provide Wireless Fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 300) can be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 100, 300) can be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0051] Various packages have been described; the sequence of packages used for manufacturing will be described below. An exemplary sequence for fabricating a package including a substrate having pillar interconnects and a solder mask layer having cavities.

[0052] In some embodiments, manufacturing a package includes several procedures. Figures 5A-5C illustrate exemplary sequences for providing or manufacturing a package. In some embodiments, the sequences of Figures 5A-5C may be used to provide or manufacture package 100. However, the procedures of Figures 5A-5C may be used to manufacture any package described in this document (e.g., 300).

[0053] It should be noted that the sequences in Figures 5A–5C may combine one or more stages to simplify and / or clarify the sequence used to provide or manufacture the package. In some embodiments, the order of the procedures may be changed or modified. In some embodiments, one or more procedures may be replaced or substituted without departing from the scope of this invention.

[0054] Phase 1 (as shown in Figure 5A) illustrates the state after substrate 102 is provided. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Substrate 102 can be manufactured using the methods described in Figures 10A–10C. In some embodiments, a cored substrate (e.g., a substrate including a core layer) is provided.

[0055] Phase 2 illustrates the state after the first integrated device 105 is coupled to a first surface (e.g., the top surface) of the substrate 102. The first integrated device 105 may be coupled to the substrate 102 via a plurality of pillar interconnects 150 and solder interconnects (not shown). A solder reflow process may be used to couple the first integrated device 105 to the substrate 102. Phase 2 also illustrates the provisioning and / or formation of a bottom filler 152 between the first integrated device 105 and the substrate 102.

[0056] Phase 3 describes the state after substrate 104 is provided. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. Substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The plurality of interconnects 142 may include pillar interconnects 142a. Substrate 104 includes solder resist layers 144 and 146. Solder resist layer 146 includes cavities (e.g., 250). Substrate 104 can be manufactured using the methods described in Figures 10A–10C. In some embodiments, a cored substrate (e.g., a substrate including a core layer) is provided.

[0057] Phase 4 describes the state after substrate 104 is coupled to substrate 102 via a plurality of ball interconnects 109 and a plurality of solder interconnects 190. A solder reflow process can be used to couple substrate 104 to substrate 102. The plurality of ball interconnects 109 can be coupled to substrate 104 before substrate 104 is coupled to substrate 102. Substrate 104 is coupled to substrate 102 such that a first integration device 105 is located between substrate 102 and substrate 104. The first integration device 105 can be located below a cavity (e.g., 250) of solder mask layer 146. The plurality of ball interconnects 109 and the plurality of solder interconnects 190 are coupled to (i) a plurality of pillar interconnects 142a of the second substrate 104 and (ii) a plurality of interconnects 122 of the first substrate 102.

[0058] Phase 5 (as shown in Figure 5B) illustrates the state after a sealing layer 108 is provided between substrates 102 and 104. The sealing layer 108 may seal the first integrated device 105, a plurality of ball interconnects 109, and / or a plurality of solder interconnects 190. The sealing layer 108 may be located within a cavity (e.g., 250) of the solder mask layer 146. The sealing layer 108 may include a mold, resin, and / or epoxy resin. The sealing layer 108 may be a unit for sealing. The sealing layer 108 may be provided via a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0059] Phase 6 describes the state after the second integrated device 107 is coupled to the first surface (e.g., the top surface) of the substrate 104. The second integrated device 107 can be coupled to the substrate 104 via a plurality of solder interconnects 170. The second integrated device 107 can be coupled to the substrate 104 using a solder reflow process.

[0060] Phase 7 (as shown in Figure 5C) illustrates the coupling of a plurality of passive devices 130 to a second surface (e.g., the bottom surface) of the substrate 102. The plurality of passive devices 130 may be coupled to the substrate 102 via a plurality of solder interconnects (not shown). A solder reflow process may be used to couple the plurality of passive devices 130 to the substrate 102.

[0061] Phase 8 describes the state after a plurality of solder interconnects 110 are coupled to the second surface of substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to substrate 102. Phase 8 can describe package 100. Package 100 can be manufactured one at a time, or it can be manufactured together as part of one or more wafers and then singulated into individual packages. An exemplary sequence for fabricating a package including a substrate having pillar interconnects and a solder mask layer having cavities.

[0062] In some embodiments, manufacturing a package includes several procedures. Figures 6A-6C illustrate exemplary sequences for providing or manufacturing a package. In some embodiments, the sequences of Figures 6A-6C can be used to provide or manufacture package 300. However, the procedures of Figures 6A-6C can be used to manufacture any package (e.g., 100) described in this document.

[0063] It should be noted that the sequences in Figures 6A–6C can be combined with one or more stages to simplify and / or clarify the sequence of providing or manufacturing the package. In some embodiments, the order of the procedures can be changed or modified. In some embodiments, one or more procedures can be replaced or substituted without departing from the scope of this invention.

[0064] Phase 1 (as shown in Figure 6A) illustrates the state after substrate 302 is provided. Substrate 302 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 includes a plurality of pillar interconnects 322. Substrate 302 includes a solder resist layer 324 and a plurality of solder resist layers 126. Substrate 302 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Substrate 302 can be manufactured using the methods described in Figures 10A–10C. In some embodiments, a cored substrate (e.g., a substrate including a core layer) is provided.

[0065] Phase 2 describes the state after the first integrated device 105 is coupled to a first surface (e.g., the top surface) of the substrate 302. The first integrated device 105 may be coupled to the substrate 302 via a plurality of pillar interconnects 150 and solder interconnects (not shown). A solder reflow process may be used to couple the first integrated device 105 to the substrate 302. Phase 2 also describes the provisioning and / or formation of a bottom filler 152 between the first integrated device 105 and the substrate 102.

[0066] Phase 3 describes the state after substrate 104 is provided. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. Substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The plurality of interconnects 142 may include pillar interconnects 142a. Substrate 104 includes solder resist layers 144 and 146. Solder resist layer 146 includes cavities (e.g., 250). Substrate 104 can be manufactured using the methods described in Figures 10A–10C. In some embodiments, a cored substrate (e.g., a substrate including a core layer) is provided.

[0067] Phase 4 describes the state after substrate 104 is coupled to substrate 302 via a plurality of solder interconnects 190. A solder reflow process can be used to couple substrate 104 to substrate 302. Substrate 104 is coupled to substrate 302 such that a first integrated device 105 is located between substrate 302 and substrate 104. The first integrated device 105 may be located below a cavity (e.g., 250) of solder mask layer 146. The plurality of solder interconnects 190 are coupled to (i) a plurality of pillar interconnects 142a of the second substrate 104 and (ii) a plurality of pillar interconnects 322 of the first substrate 302. The plurality of solder interconnects 190 may first be coupled to substrate 104 via a solder reflow process, and then substrate 104 may be coupled to substrate 302 via a solder reflow process via the plurality of solder interconnects 190.

[0068] Phase 5 (as shown in Figure 6B) illustrates the state after a sealing layer 108 is provided between substrate 302 and substrate 104. Sealing layer 108 may encapsulate the first integrated device 105 and / or a plurality of solder interconnects 190. Sealing layer 108 may be located within a cavity (e.g., 250) of solder mask layer 146. Sealing layer 108 may include a mold, resin, and / or epoxy resin. Sealing layer 108 may be a unit for sealing. Sealing layer 108 may be provided via compression and transfer molding, sheet molding, or liquid molding processes.

[0069] Phase 6 describes the state after the second integrated device 107 is coupled to the first surface (e.g., the top surface) of the substrate 104. The second integrated device 107 can be coupled to the substrate 104 via a plurality of solder interconnects 170. The second integrated device 107 can be coupled to the substrate 104 using a solder reflow process.

[0070] Stage 7 (as shown in Figure 6C) illustrates the coupling of a plurality of passive devices 130 to a second surface (e.g., the bottom surface) of the substrate 302. The plurality of passive devices 130 may be coupled to the substrate 302 via a plurality of solder interconnects (not shown). A solder reflow process may be used to couple the plurality of passive devices 130 to the substrate 302.

[0071] Phase 8 describes the state after the plurality of solder interconnects 110 are coupled to the second surface of the substrate 302. A solder reflow process can be used to couple the plurality of solder interconnects 110 to the substrate 302. Phase 8 can also describe package 300. Package 300 can be manufactured one at a time, or it can be manufactured together as part of one or more wafers and subsequently diced into individual packages. An exemplary flowchart of a method for manufacturing a package including a substrate having pillar interconnects and a solder mask layer having cavities.

[0072] In some embodiments, manufacturing a package includes several procedures. Figure 7 illustrates an exemplary flowchart of a method 700 for providing or manufacturing a package. In some embodiments, the method 700 of Figure 7 can be used to provide or manufacture the package 100 described herein. However, method 700 can be used to provide or manufacture any package described herein (e.g., 300).

[0073] It should be noted that the method 700 of Figure 7 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a package. In some embodiments, the order of the procedures can be changed or modified.

[0074] The method provides (at 705) a first substrate (e.g., 102) and a first integrated device (e.g., 105) coupled to a first surface of the first substrate (e.g., 102). The first substrate 102 and the first integrated device 105 may be part of a first package. The first substrate 102 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. In some embodiments, the first substrate may include a plurality of pillar interconnects (e.g., 322). The first substrate 102 may include a solder mask layer 124 and / or a solder mask layer 126. The substrate 102 may be manufactured using the methods described in Figures 10A–10C. Phase 1 of Figure 5A illustrates and describes an example of the provided first substrate. Phase 2 of Figure 5A illustrates and describes an example of a first substrate with the first integrated device. Phase 1 of Figure 6A illustrates and describes an example of the provided first substrate. Phase 2 of Figure 6A illustrates and describes an example of a first substrate with the first integrated device.

[0075] The method provides a second substrate (e.g., 104) at 710. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of interconnects 142. The plurality of interconnects 142 may include pillar interconnects (e.g., 142a). The second substrate may include a solder mask layer with a variable thickness. For example, the second substrate may include a solder mask layer with a first thickness and a second thickness. The second substrate may include a solder mask layer with cavities (e.g., 250). The substrate 104 can be fabricated using the methods described in Figures 10A–10C. In some embodiments, the substrate 104 can be fabricated using mSAP. Phase 3 of Figure 5A illustrates and describes an example of the provided second substrate. Phase 3 of Figure 6A illustrates and describes an example of the provided second substrate.

[0076] This method couples a second substrate (e.g., 104) to a first substrate (e.g., 102) via a plurality of ball interconnects (e.g., 109) and / or a plurality of solder interconnects (e.g., 190). The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 are examples of inter-substrate interconnects. A solder reflow process can be used to couple the second substrate to the first substrate. Stage 4 of Figure 5A illustrates and describes an example of a second substrate coupled to the first substrate. Stage 4 of Figure 6A illustrates and describes an example of a second substrate coupled to the first substrate.

[0077] This method provides a sealing layer (e.g., 108) between a first substrate (e.g., 102, 302) and a second substrate (e.g., 104) at 720. The sealing layer 108 may include a mold, resin, and / or epoxy resin. The sealing layer 108 may be a unit for sealing. The sealing layer 108 may be provided via a compression and transfer molding process, a sheet molding process, or a liquid molding process. At least a portion of the sealing layer 108 may be located between the second substrate 104 and the first integrated device 105. Stage 5 of Figure 5B illustrates and describes an example of providing a sealing layer. Stage 5 of Figure 6B illustrates and describes an example of providing a sealing layer.

[0078] This method couples a second integrated device (e.g., 107) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 170). A solder reflow process can be used to couple the second integrated device to the first surface of the second substrate 104. Stage 6 of Figure 5B illustrates and describes an example of a second integrated device coupled to a second substrate. Stage 6 of Figure 6B illustrates and describes an example of a second integrated device coupled to a second substrate.

[0079] This method couples a passive device (e.g., 130) and a plurality of solder interconnects (e.g., 110) (at 730) to a second surface of a first substrate (e.g., 102, 302). A solder reflow process can be used to couple the passive device and / or solder interconnects to the second surface of the first substrate (e.g., 102, 302). Stage 7 of Figure 5C illustrates and describes an example of coupling a passive device to a substrate. Stage 7 of Figure 6C illustrates and describes an example of coupling a passive device to a substrate. Stage 8 of Figure 5C illustrates and describes an example of coupling solder interconnects to a substrate. Stage 8 of Figure 6C illustrates and describes an example of coupling solder interconnects to a substrate.

[0080] In some implementations, several packages are manufactured simultaneously. In this case, the method can divide the packages (e.g., 100, 300). An exemplary flowchart of a method for manufacturing a package, the package including a substrate coupled via ball interconnects.

[0081] Figure 8 illustrates an exemplary flowchart of a method 800 for providing or manufacturing a package. In some embodiments, method 800 of Figure 8 can be used to provide or manufacture some or all of the package of Figure 1 described in this document. However, method 800 can be used to provide or manufacture any package described in this document.

[0082] It should be noted that the method 800 of Figure 8 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing the package. In some embodiments, the order of the procedures can be changed or modified.

[0083] This method provides a wafer (at 805). The wafer can be used as a substrate on which integrated devices can be formed and / or coupled. In some embodiments, other substrates can be coupled to the wafer. The wafer may include silicon. The wafer can be used as a base on which components are built.

[0084] This method forms solder interconnects on the wafer (at 810). Solder reflow processes can be used to form (e.g., couple) solder interconnects on the wafer.

[0085] This method prepares (at 815) one or more integrated devices (e.g., dies) for coupling. Preparing the integrated devices may include manufacturing the integrated devices.

[0086] This method provides and prepares (at 820) a first substrate (e.g., substrate 102, bottom substrate) by pre-baking the first substrate. The first substrate may be pre-baked to remove moisture to prevent degassing during subsequent thermocompression flip-chip coupling processes. This method pre-cleans (at 825) the first substrate. This method removes (at 827) the organic solderability protectant (OSP) from the first substrate.

[0087] Once the first substrate is provided and prepared, it can be coupled to the wafer via solder interconnects formed on the wafer.

[0088] One or more integrated devices are coupled (at 830) to a first substrate. For example, integrated device 105 may be coupled to substrate 102 via a thermocompression flip-chip process. Underfill may be provided between the integrated device and the substrate. Phase 2 of Figure 5A illustrates and describes an example of an integrated device coupled to a substrate and an example of underfill disposed between the integrated device and the substrate.

[0089] This method performs plasma cleaning of the first substrate (at 835). Plasma cleaning removes contaminants from the substrate surface.

[0090] This method pre-cleans (at 840) the second substrate (e.g., substrate 104, the top substrate). Phase 3 of Figure 5A illustrates and describes an example of the provided second substrate. The method couples (at 845) ball interconnects (e.g., copper core balls) to the second substrate. The ball interconnects can be coupled to the second substrate 104 via solder interconnects (e.g., 190). A solder reflow process can be used to couple the ball interconnects to the second substrate. The method performs (at 847) stripping of the second substrate. This can be done when multiple substrates are manufactured simultaneously and subsequently stripped.

[0091] This method performs flux cleaning (at 850°) on one or more substrates. Flux cleaning removes oxides from the substrate metal. Flux cleaning can be performed on a first substrate and / or a second substrate.

[0092] This method couples a second substrate (e.g., 104) to a first substrate (e.g., 102) via ball interconnects. A solder reflow process can be used to couple the second substrate to the first substrate. Stage 4 of Figure 5A illustrates and describes an example of coupling a substrate to another substrate.

[0093] This method provides a sealing layer (e.g., 108) between the first and second substrates (at 860). Phase 5 of Figure 5B illustrates and describes an example of providing a sealing layer between the substrates.

[0094] This method forms solder interconnects or pad-side arrays (LSAs) on a first substrate (at 865). A solder reflow process can be used to form the solder interconnects. The solder interconnects can be ball grid arrays (BGAs).

[0095] This method divides the package (at 870) into individual packages. This can happen when multiple packages are manufactured simultaneously. Dividing the package may include dividing a wafer comprising a first substrate, one or more integrated devices, and a second substrate. The package can be divided using mechanical processes (e.g., sawing) or lasers.

[0096] This method performs final testing and a final visual inspection of the package (at 875). This may include testing the package for proper functioning by attaching probes to it to determine if it works as expected. The visual inspection may include visual examination to check for any defects in the package.

[0097] This method performs (at 880) the packaging of tape and reel. This may include sealing the segmented packages together with tape so that the packages can be transported correctly.

[0098] It should be noted that additional processes can be performed on the package, including coupling other components such as passive components and / or integrated devices to the package. Figure 8 illustrates an example of how a package can be manufactured. Figure 8 is not intended to illustrate the only way a package can be manufactured. An exemplary flowchart of a method for manufacturing a package, the package including a substrate coupled via solder interconnects.

[0099] Figure 9 illustrates an exemplary flowchart of a method 900 for providing or manufacturing a package. In some embodiments, method 900 of Figure 9 can be used to provide or manufacture some or all of the package of Figure 3 described in this document. However, method 900 can be used to provide or manufacture any package described in this document.

[0100] It should be noted that the method 900 of Figure 9 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a package. In some embodiments, the order of the procedures can be changed or modified.

[0101] This method provides a wafer (at 905). The wafer can be used as a substrate on which integrated devices can be formed and / or coupled. In some embodiments, other substrates can be coupled to the wafer. The wafer may include silicon. The wafer can be used as a base on which components are built.

[0102] This method forms solder interconnects on the wafer (at 910). Solder reflow processes can be used to form (e.g., couple) solder interconnects on the wafer.

[0103] This method prepares (at 915) one or more integrated devices (e.g., dies) for coupling. Preparing the integrated devices may include manufacturing the integrated devices.

[0104] This method provides and prepares (at 920) a first substrate (e.g., substrate 302, bottom substrate) by pre-baking the first substrate. The first substrate may be pre-baked to remove moisture to prevent degassing during subsequent thermocompression flip-chip coupling processes. This method pre-cleans (at 925) the first substrate. This method removes (at 927) the organic solderability protectant (OSP) from the first substrate.

[0105] Once the first substrate is provided and prepared, it can be coupled to the wafer via solder interconnects formed on the wafer.

[0106] One or more integrated devices are coupled (at 930) to a first substrate. For example, integrated device 105 may be coupled to substrate 102 via a thermocompression flip-chip process. Underfill may be provided between the integrated device and the substrate. Phase 2 of Figure 6A illustrates and describes an example of an integrated device coupled to a substrate and an example of underfill disposed between the integrated device and the substrate.

[0107] This method performs plasma cleaning of the first substrate (at 935). Plasma cleaning removes contaminants from the surface of the substrate.

[0108] The method pre-cleans (at 940) the second substrate (e.g., substrate 104, the top substrate). Stage 3 of Figure 6A illustrates and describes an example of the provided second substrate. The method forms (at 945) solder interconnects on the second substrate. The solder interconnects (e.g., 190) can be coupled to the second substrate 104 via a paste printing process or via a solder ball attachment process. A solder reflow process can be used to couple the ball interconnects to the second substrate. The method performs (at 947) stripping of the second substrate. This can be done when multiple substrates are manufactured simultaneously and then subsequently stripped.

[0109] This method performs flux cleaning (at 950°) on one or more substrates. Flux cleaning removes oxides from the substrate metal. Flux cleaning can be performed on a first substrate and / or a second substrate.

[0110] This method couples a second substrate (e.g., 104) to a first substrate (e.g., 102) via ball interconnects. A solder reflow process can be used to couple the second substrate to the first substrate. Stage 4 of Figure 6A illustrates and describes an example of coupling one substrate to another.

[0111] This method provides a sealing layer (e.g., 108) between the first and second substrates (at 960). Phase 5 of Figure 6B illustrates and describes an example of providing a sealing layer between the substrates.

[0112] This method forms solder interconnects or pad-side arrays (LSAs) on a first substrate (at 965). A solder reflow process can be used to form the solder interconnects. The solder interconnects can be ball grid arrays (BGAs).

[0113] This method divides the package (at 970) into individual packages. This can happen when multiple packages are manufactured simultaneously. Dividing a package may include dividing a wafer comprising a first substrate, one or more integrated devices, and a second substrate. Mechanical processes (e.g., sawing) or lasers can be used to divide the package.

[0114] This method performs final testing and a final visual inspection of the package (at 975). This may include testing the package for proper functioning by attaching probes to it to determine if it works as expected. The visual inspection may include visual examination to check for any defects in the package.

[0115] This method performs (at 980) the packaging of tape and reel. This may include sealing the segmented packages together with tape so that the packages can be transported correctly.

[0116] Note that additional processes can be performed on the package, including coupling other components such as passive parts and / or integrated devices to the package. Figure 9 illustrates an example of how a package can be manufactured. Figure 9 is not intended to illustrate the only way a package can be manufactured. Exemplary sequence for manufacturing substrates

[0117] In some embodiments, manufacturing the substrate includes several procedures. Figures 10A-10C illustrate exemplary sequences for providing or manufacturing a substrate. In some embodiments, the sequences of Figures 10A-10C may be used to provide or manufacture substrate 104. However, the procedures of Figures 10A-10C may be used to manufacture any substrate described in this document, such as substrate 102 and / or substrate 302.

[0118] It should be noted that the sequences of Figures 10A-10C can be combined with one or more stages to simplify and / or clarify the sequence used to provide or manufacture the substrate. In some embodiments, the order of the procedures can be changed or modified. In some embodiments, one or more procedures can be replaced or substituted without departing from the scope of this invention.

[0119] Phase 1 (as shown in Figure 10A) illustrates the state after the carrier 1000 is provided. A seed layer 1001 and interconnects 1002 may be located on the carrier 1000. Interconnects 1002 may be located on the seed layer 1001. Interconnects 1002 can be formed using electroplating and etching processes. In some embodiments, the carrier 1000 may be provided with a seed layer 1001 and a metal layer patterned to form interconnects 1002. Interconnects 1002 may represent at least some interconnects from a plurality of interconnects 142.

[0120] Phase 2 describes the state after the dielectric layer 1020 is formed on the carrier 1000, seed layer 1001, and interconnect 1002. The dielectric layer 1020 can be formed using deposition and / or lamination processes. The dielectric layer 1020 may include prepreg and / or polyimide. The dielectric layer 1020 may include a photoimageable dielectric. However, different embodiments may use different materials for the dielectric layer.

[0121] Stage 3 describes the state after the plurality of cavities 1010 are formed in the dielectric layer 1020. The plurality of cavities 1010 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0122] Phase 4 describes the state after interconnects 1012 are formed in and on dielectric layer 1020 (including in and on the plurality of cavities 1010). For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0123] Phase 5 describes the state after dielectric layer 1022 is formed over dielectric layer 1020 and interconnect 1012. Dielectric layer 1022 can be formed using deposition and / or lamination processes. Dielectric layer 1022 may include prepreg and / or polyimide. Dielectric layer 1022 may include a photoimageable dielectric. However, different embodiments may use different materials for the dielectric layer.

[0124] Stage 6 (as shown in Figure 10B) illustrates the state after the plurality of cavities 1030 are formed in the dielectric layer 1022. The plurality of cavities 1030 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0125] Stage 7 describes the state after interconnects 1014 are formed in and on dielectric layer 1022 (including in and on the plurality of cavities 1030). For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0126] Phase 8 describes the state after interconnects 1016 are formed on some interconnects 1014. Interconnects 1016 may be pillar interconnects. Electroplating processes may be used to form interconnects 1016. A plurality of interconnects 1002, a plurality of interconnects 1012, and / or a plurality of interconnects 1014 may be represented by a plurality of interconnects 142. Dielectric layers 1020 and / or dielectric layers 1022 may be represented by at least one dielectric layer 140. At least one dielectric layer 140 may include a photoimageable dielectric. At least one dielectric layer 140 may include a prepreg and / or polyimide.

[0127] Stage 9 illustrates the state after the carrier 1000 is decoupled from at least one dielectric layer 140 and seed layer 1001 (e.g., removed, taken away, ground off), with a portion of the seed layer 1001 removed (e.g., etched away), leaving a substrate 104 comprising at least one dielectric layer 140 and a plurality of interconnects 142.

[0128] Stage 10 (as shown in Figure 10C) illustrates the state after the solder resist layer 144 is formed on the first surface of the substrate 104 and after the solder resist layer 146 is formed on the second surface of the substrate 104. Deposition processes and / or lamination processes can be used to form the solder resist layer 144 and / or the solder resist layer 146.

[0129] Phase 11 describes the state after an additional solder mask layer is formed on a portion of the solder mask layer 146, resulting in different thicknesses in different portions of the solder mask layer 146. The additional solder mask layer is considered part of the solder mask layer 146. The additional solder mask layer creates cavities 1460 in the solder mask layer 146. The additional solder mask can be formed using deposition processes and / or lamination processes.

[0130] Different implementations may use different processes to form one or more metal layers and / or interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form one or more metal layers. Exemplary flowchart of a method for manufacturing a substrate

[0131] In some embodiments, manufacturing a substrate includes several procedures. Figure 11 illustrates an exemplary flowchart of a method 1100 for providing or manufacturing a substrate. In some embodiments, the method 1100 of Figure 11 can be used to provide or manufacture one or more substrates in this case. For example, the method 1100 of Figure 11 can be used to manufacture substrate 104.

[0132] It should be noted that method 1100 of Figure 11 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a substrate. In some embodiments, the order of procedures can be changed or modified.

[0133] This method provides a carrier (e.g., 1000) at 1105. Different embodiments may use different materials for the carrier 1000. The carrier 1000 may include a seed layer (e.g., 1001). The seed layer 1001 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Phase 1 of Figure 10A illustrates and describes an example of a carrier having the provided seed layer.

[0134] This method forms and patterns (at 1110) interconnects on a carrier 1000 and a seed layer 1001. A metal layer can be patterned to form the interconnects. An electroplating process can be used to form the metal layer and the interconnects. In some embodiments, the carrier and seed layer may include a metal layer. The metal layer is located on top of the seed layer and can be patterned to form interconnects (e.g., 142). Phase 1 of Figure 10A illustrates and describes an example of forming and patterning interconnects on the seed layer and the carrier.

[0135] This method forms a dielectric layer 1020 (at 1115) over a seed layer 1001, a carrier 1000, and an interconnect 1002. The dielectric layer 1020 can be formed using deposition and / or lamination processes. The dielectric layer 1020 may include a prepreg and / or polyimide. The dielectric layer 1020 may include a photoimageable dielectric. Forming the dielectric layer 1020 may also include forming a plurality of cavities (e.g., 1010) within the dielectric layer 1020. The plurality of cavities can be formed using an etching process (e.g., photolithography) or a laser process. Stages 2-3 of Figure 10A illustrate and describe examples of forming the dielectric layer and cavities within the dielectric layer.

[0136] This method forms interconnects (at 1120) in and on the dielectric layer. For example, interconnect 1012 can be formed in and on the dielectric layer 1020. An electroplating process can be used to form the interconnects. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities within the dielectric layer. Stage 4 of Figure 10A illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0137] This method forms a dielectric layer 1022 (at 1125) over a dielectric layer 1020 and an interconnect 1012. The dielectric layer 1022 can be formed using deposition and / or lamination processes. The dielectric layer 1022 may include a prepreg and / or polyimide. The dielectric layer 1022 may include a photoimageable dielectric. Forming the dielectric layer 1022 may also include forming a plurality of cavities (e.g., 1030) within the dielectric layer 1022. The plurality of cavities can be formed using an etching process (e.g., photolithography) or a laser process. Stages 5-6 of Figures 10A-10B illustrate and describe examples of forming the dielectric layer and cavities within it.

[0138] This method forms interconnects (at 1130) in and on a dielectric layer. For example, interconnect 1014 can be formed in and on dielectric layer 1022. An electroplating process can be used to form the interconnects. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Forming interconnects may include forming pillar interconnects. Stages 7-8 of Figure 10B illustrate and describe examples of forming interconnects (including pillar interconnects) in and on a dielectric layer.

[0139] This method decouples the carrier (e.g., 1000) from the seed layer (e.g., 1001) (at 1135). The carrier 1000 can be removed and / or ground away. This method can also remove a portion of the seed layer (e.g., 1001) (at 1135). A portion of the seed layer 1001 can be removed using an etching process. Stage 9 of Figure 10B illustrates and describes an example of decoupling carrier and seed layer removal.

[0140] This method can form one or more solder resist layers (at 1140) on a first surface and / or a second surface of a substrate. For example, a first solder resist layer can be formed on the first surface of the substrate, and / or a second solder resist layer can be formed on the second surface of the substrate. The first solder resist layer and / or the second solder resist layer may each have a variable thickness, such that the first solder resist layer and / or the second solder resist layer may have cavities, as described in Figures 1-4. That is, a first portion of the solder resist layer may have a first thickness and a second portion of the same solder resist layer may have a second thickness different from the first thickness. Stages 10 and 11 of Figure 10C illustrate and describe examples of providing and / or forming solder resist layers with cavities.

[0141] Different implementations may use different processes to form one or more metal layers. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form one or more metal layers. Exemplary electronic devices

[0142] Figure 12 illustrates various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1202, laptop device 1204, fixed-location terminal device 1206, wearable device 1208, or motor vehicle 1210 may include device 1200 as described herein. Device 1200 can be any device and / or integrated circuit (IC) package described herein, for example. Devices 1202, 1204, 1206, and 1208, and vehicle 1210 shown in Figure 12 are merely exemplary. Other electronic devices may also be characterized as device 1200, including but not limited to a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (e.g., meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0143] Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 show one or more components, programs, features, and / or functions that can be rearranged and / or combined into a single component, program, feature, or function, or embodied in multiple components, programs, or functions. Additional components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some embodiments, Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 and their corresponding descriptions can be used to manufacture, establish, provide, and / or produce equipment and / or integrate devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an interposer.

[0144] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, these drawings may not be drawn to scale. In some cases, not all parts and / or components may be shown for clarity. In some cases, the position, orientation, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some embodiments, the various parts and / or components in the drawings may be optional.

[0145] The term "exemplary" as used herein means "serving as an example, illustration, or description." Any embodiment or manner described herein as "exemplary" is not necessarily to be construed as preferred or superior to other manners of this application. Similarly, the term "manner" does not require that all manners of this application include the features, advantages, or modes of operation discussed. The term "coupling" as used herein refers to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they do not physically contact each other. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power supply, ground) may flow between the two objects. Electrically coupled objects may or may not have current flowing between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms "closed," "closed," and / or any derivatives indicate that the object can partially or completely close another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this case, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another instance, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. It should also be noted that in the context of one component being above another component, the term "above" as used in this case can be used to refer to a component on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, a first component on top of a second component may mean (1) the first component is on top of the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component may be partially or completely located in the second component. A value of X-XX may mean a value between X and XX, including X and XX. One or more values ​​between X and XX may be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this case refers to a value within 10% of 'value X'. For example, a value of about 1 or approximately 1 represents a value in the range of 0.9–1.1.

[0146] In some embodiments, an interconnect is a device or packaged element or component that allows or facilitates an electrical connection between two points, elements, and / or parts. In some embodiments, an interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or sequences to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0147] Furthermore, it should be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although a flowchart may describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Moreover, the order of operations can be rearranged. The program terminates when its operations are completed.

[0148] Further examples are described below to facilitate understanding of the invention.

[0149] Version 1: A package comprising: a first substrate including at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate; and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first and second substrates. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The plurality of ball interconnects and the plurality of solder interconnects are located between the first and second substrates. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0150] Sample 2: Package according to claim 1, wherein the plurality of ball interconnects and the plurality of solder interconnects are coupled to the plurality of pillar interconnects of the second substrate, and wherein the plurality of pillar interconnects are laterally surrounded by the solder resist layer.

[0151] State 3: Package of State 1 to 2, wherein the plurality of ball interconnects includes adjacent ball interconnects with a pitch equal to or less than 270 micrometers.

[0152] State 4: Package of State 3, wherein the plurality of ball interconnects includes adjacent ball interconnects with a pitch in the range of approximately 200-270 micrometers.

[0153] Type 5: Package of types 1 to 4, wherein the plurality of ball interconnects includes at least 300 ball interconnects that laterally surround the first integrated device.

[0154] Phase 6: The package of phases 1 to 5 also includes a sealing layer located between the first substrate and the second substrate, wherein a portion of the sealing layer is located between the solder resist layer and the first integrated device.

[0155] State 7: Package of State 6, wherein the enclosure layer at least partially encloses the first integrated device, the plurality of ball interconnects and the plurality of solder interconnects.

[0156] State 8: Package of states 1 to 7, wherein the solder mask layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the first portion of the solder mask layer has a first thickness greater than the thickness of the plurality of pillar interconnects, wherein the second portion of the solder mask layer has a second thickness less than the thickness of the plurality of pillar interconnects, and wherein the second portion of the solder mask layer is located above the first integrated device.

[0157] Type 9: Packages of types 1 to 8 also include a second integrated device coupled to a first surface of the second substrate, wherein the vertical gap between the solder resist layer of the second substrate and the back surface of the first integrated device is smaller than another vertical gap between the solder resist layer of the second substrate and the solder resist layer of the first substrate.

[0158] State 10: Packages of states 1 to 9, wherein the plurality of ball interconnects include copper core balls (CCB).

[0159] Version 11: A package includes: a first substrate, a first integrated device coupled to the first substrate, and a second substrate, and a plurality of solder interconnects coupled to the first and second substrates. The first substrate includes at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer coupled to a first surface of the first substrate. The second substrate includes a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity. The cavity is located between the first integrated device and the second solder resist layer. The plurality of solder interconnects are located between the first and second substrates. The plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0160] State 12: Package of State 11, wherein the plurality of solder interconnects are coupled to (i) the first plurality of pillar interconnects of the first substrate and (ii) the second plurality of pillar interconnects of the second substrate, wherein the first plurality of pillar interconnects are laterally surrounded by the first solder mask layer and wherein the second plurality of pillar interconnects are laterally surrounded by the second solder mask layer.

[0161] State 13: Package of states 11 to 12, wherein the plurality of solder interconnects includes adjacent solder interconnects with a pitch equal to or less than 270 micrometers.

[0162] State 14: Package of State 13, wherein the plurality of solder interconnects include adjacent solder interconnects with a pitch in the range of approximately 150-270 micrometers.

[0163] Type 15: Package of types 11 to 14, wherein the plurality of solder interconnects includes at least 300 solder interconnects laterally surrounding the first integrated device.

[0164] Package 16: Packages of packages 11 to 15 also include a sealing layer located between the first substrate and the second substrate, wherein a portion of the sealing layer is located between the second solder mask layer and the first integrated device.

[0165] State 17: Package of State 16, wherein the enclosure layer at least partially encloses the first integrated device and the plurality of solder interconnects.

[0166] State 18: Package of states 11 to 17, wherein the second solder mask layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the first portion of the second solder mask layer has a first thickness greater than the thickness of the second plurality of pillar interconnects, wherein the second portion of the second solder mask layer has a second thickness less than the thickness of the second plurality of pillar interconnects, and wherein the second portion of the second solder mask layer is located above the first integrated device.

[0167] Package 19: Packages of packages 11 to 18 also include a second integrated device coupled to a first surface of the second substrate, wherein the vertical gap between the solder resist layer of the second substrate and the back surface of the first integrated device is smaller than another vertical gap between the solder resist layer of the second substrate and the solder resist layer of the first substrate.

[0168] State 20: Packages of states 11 to 19, also including passive devices coupled to the first substrate.

[0169] Version 21: A package comprising: a first substrate including at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate; and cells coupled to the first and second substrates for inter-substrate interconnection. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder resist layer coupled to a second surface of the second substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The cells for inter-substrate interconnection are located between the first and second substrates. The cells for inter-substrate interconnection are configured to couple the first substrate to the second substrate.

[0170] State 22: Package of State 21, wherein the unit for inter-substrate interconnection includes a plurality of ball interconnects and / or a plurality of solder interconnects.

[0171] State 23: Package of states 21 to 22, wherein the cell for inter-substrate interconnection is coupled to the plurality of pillar interconnects of the second substrate.

[0172] Package of Form 24: Form 23, wherein the first substrate includes a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and wherein the cell for inter-substrate interconnection is coupled to the first plurality of pillar interconnects of the first substrate.

[0173] Type 25: Packages of types 21 to 24, wherein the unit for inter-substrate interconnection includes interconnects with a pitch in the range of about 150-270 micrometers.

[0174] Sample 26: A method comprising: providing a first substrate including at least one first dielectric layer and a first plurality of interconnects. The method couples a first integrated device to the first substrate. The method couples a second substrate to the first substrate via a plurality of inter-substrate interconnects such that the plurality of inter-substrate interconnects are located between the first substrate and the second substrate. The second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a solder resist layer coupled to a second surface of the second substrate. The solder resist layer includes a cavity. The cavity is located between the solder resist layer and the first integrated device.

[0175] Method of Form 27: Form 26, wherein the interconnects between the plurality of substrates include a plurality of ball interconnects and / or a plurality of solder interconnects.

[0176] Method of state 28: state 26 to 27, wherein the plurality of inter-substrate interconnects are coupled to the plurality of pillar interconnects of the second substrate.

[0177] Method of State 29: State 28, wherein the first substrate includes a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and wherein the inter-substrate interconnects are coupled to the first plurality of pillar interconnects of the first substrate.

[0178] Methods of states 30: 26 to 29, wherein the interconnects between the plurality of substrates include interconnects with a pitch in the range of about 150-270 micrometers.

[0179] Various features of the present invention described herein can be implemented in different systems without departing from this scope. It should be noted that the above-described embodiments of the invention are merely examples and do not constitute a limitation thereof. The description of the embodiments herein is intended to be illustrative and not to limit the scope of the claims. Therefore, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art to which this invention pertains.

[0180] 100: Package 102: First substrate 104: Second substrate 105: First Integration Device 106: Board 107: Second Integration Device 108: Closed layer 109: Interconnection 110: Solder interconnect 120: At least one first dielectric layer 122: The first complex interconnection 122a: Interconnection 124: Solder mask layer 126: Solder mask layer 130: Passive Device 140: At least one second dielectric layer 142: The second complex interconnection 142a: Column Interconnection 144: Solder mask layer 146: Solder mask layer 146a: Solder mask layer 146b: Solder mask layer 150: Column Interconnection 152: Bottom Fill 160: At least one plate dielectric layer 162: Interconnection 170: Solder interconnect 190: Solder interconnect 240: Thickness 242: Thickness 250: Cavity 280: Gap 282: Gap 300: Package 302: First substrate 322: Column Interconnection 324: Solder mask layer 460: Thickness 480: Gap 700: Method 705: Square 710: Square 715: Square 720: Square 725: Square 730: Square 800: Method 805: Square 810: Square 815: Square 820: Square 825: Square 827: Square 830: Square 835: Square 840: Square 845: Square 847: Square 850: Square 855: Square 860: Square 865: Square 870: Square 875: Square 880: Square 900: Method 905: Square 910: Square 915: Square 920: Square 925: Square 927: Square 930: Square 935: Square 940: Square 945: Square 947: Square 950: Square 955: Square 960: Square 965: Square 970: Square 975: Square 980: Square 1000: Carrier 1001: Seed layer 1002: Interconnection 1010: Cavity 1012: Interconnection 1014: Interconnection 1016: Interconnection 1020: Dielectric layer 1022: Dielectric layer 1030: Cavity 1100: Method 1105: Square 1110: Square 1115: Square 1120: Square 1125: Square 1130: Square 1135: Square 1200: Equipment 1202: Equipment 1204: Equipment 1206: Equipment 1208: Equipment 1210: Vehicles 1460: Cavity

[0181] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated device package, comprising: A first substrate includes: at least one first dielectric layer; a first plurality of interconnects; and a first solder resist layer; a first integrated device coupled to the first substrate; a second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a second solder resist layer coupled to the second surface of the second substrate, wherein the second solder resist layer includes: a first solder resist layer portion including a first thickness, wherein the first solder resist layer portion overlaps with the first integrated device in a vertical direction; and a second solder resist layer portion including a second thickness greater than the first thickness, wherein the second solder resist layer portion is coupled to and contacts a side surface portion from each of the pillar interconnects of the plurality of pillar interconnects, wherein the second surface of the second substrate faces the first substrate, wherein the second solder resist layer includes a cavity, wherein the cavity is located laterally between the second solder resist layer portion and one of the pillar interconnects of the plurality of pillar interconnects. The cavity is located vertically between the first integrated device and the second solder mask layer, and the second solder mask layer directly contacts the at least one second dielectric layer of the second substrate. A plurality of ball interconnects and a plurality of solder interconnects are coupled to the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate. A first solder interconnect from one of the plurality of solder interconnects directly contacts (i) one of the ball interconnects, (ii) one of the first plurality of interconnects from the first substrate, (iii) the pillar interconnect from the plurality of pillar interconnects from the second substrate, (iv) the first solder mask layer of the first substrate, and (v) the second solder mask layer of the second substrate; and a sealing layer is located between the first substrate and the second substrate. The sealing layer directly contacts the first solder resist layer of the first substrate and the second solder resist layer of the second substrate, and the sealing layer is made of a different material than the first solder resist layer and the second solder resist layer.

2. The integrated device package according to claim 1, wherein the second solder mask laterally surrounds each pillar interconnect from the plurality of pillar interconnects, wherein the second solder mask contacts the entire side portion of each pillar interconnect from the plurality of pillar interconnects, wherein the pillar interconnect includes a thickness and a width, wherein the pillar interconnect directly contacts another interconnect from the second plurality of interconnects of the second substrate, and wherein the thickness of the pillar interconnect is greater than the width of the pillar interconnect.

3. The integrated device package according to claim 1, wherein the plurality of ball interconnects includes adjacent ball interconnects having a pitch equal to or less than 270 micrometers.

4. The integrated device package according to claim 3, wherein the plurality of ball interconnects includes adjacent ball interconnects having a spacing in the range of about 200 to 270 micrometers.

5. The integrated device package according to claim 1, wherein the plurality of ball interconnects includes at least 300 ball interconnects laterally surrounding the first integrated device.

6. The integrated device package according to claim 1, wherein a portion of the closure layer is located in a vertical direction between the second solder mask layer and the first integrated device, wherein the closure layer is at least partially located in the cavity, and wherein the portion of the closure layer located in the vertical direction between the second solder mask layer and the first integrated device is located transversely to the second solder mask layer portion and the post interconnection.

7. The integrated device package according to claim 6, wherein the enclosure layer at least partially encloses the first integrated device, the plurality of ball interconnects and the plurality of solder interconnects.

8. The integrated device package according to claim 1 also includes a second integrated device coupled to the first surface of the second substrate, wherein a vertical gap between the second solder mask layer of the second substrate and the back surface of the first integrated device is smaller than another vertical gap between the second solder mask layer of the second substrate and the first solder mask layer of the first substrate.

9. The integrated device package according to claim 1, wherein the plurality of ball interconnects include copper core balls (CCBs).

10. An integrated device package, comprising: A first substrate includes: at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer coupled to a first surface of the first substrate; a first integrated device coupled to the first substrate; and a second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to the second surface of the second substrate, wherein the second surface of the second substrate faces the first substrate, wherein the second solder resist layer includes a cavity and wherein the cavity is located between the first integrated device and the second solder resist layer; and a plurality of solder interconnects coupled to the first substrate and the second substrate, wherein the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of solder interconnects are configured to couple the first substrate to the second substrate, and wherein a first solder interconnect from one of the plurality of solder interconnects directly contacts (i) a first solder resist layer of the first substrate and (ii) the second solder resist layer of the second substrate.

11. The integrated device package according to claim 10, wherein the plurality of solder interconnects are coupled to (i) the first plurality of pillar interconnects of the first substrate and (ii) the second plurality of pillar interconnects of the second substrate, wherein the first solder resist layer laterally surrounds the first plurality of pillar interconnects and wherein the second solder resist layer laterally surrounds the second plurality of pillar interconnects.

12. The integrated device package according to claim 10, wherein the plurality of solder interconnects includes adjacent solder interconnects having a pitch of equal to or less than 270 micrometers.

13. The integrated device package according to claim 12, wherein the plurality of solder interconnects includes adjacent solder interconnects having a spacing in the range of about 150 to 270 micrometers.

14. The integrated device package according to claim 10, wherein the plurality of solder interconnects includes at least 300 solder interconnects laterally surrounding the first integrated device.

15. The integrated device package according to claim 10 also includes a sealing layer located between the first substrate and the second substrate, wherein a portion of the sealing layer is located between the second solder mask layer and the first integrated device.

16. The integrated device package according to claim 15, wherein the enclosure layer at least partially encloses the first integrated device and the plurality of solder interconnects.

17. The integrated device package according to claim 10, wherein the second solder mask layer includes a first portion having a first thickness and a second portion having a second thickness, wherein the first portion of the second solder mask layer has a first thickness greater than the thickness of the second plurality of post interconnects, wherein the second portion of the second solder mask layer has a second thickness less than the thickness of the second plurality of post interconnects, and wherein the second portion of the second solder mask layer is located above the first integrated device.

18. The integrated device package according to claim 10 also includes a second integrated device coupled to the first surface of the second substrate, wherein a vertical gap between the solder resist layer of the second substrate and the back surface of the first integrated device is smaller than another vertical gap between the solder resist layer of the second substrate and a solder resist layer of the first substrate.

19. The integrated device package according to claim 10 also includes a passive device coupled to the first substrate.

20. An integrated device package, comprising: A first substrate includes: at least one first dielectric layer; a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects; and a first solder resist layer; a first integrated device coupled to the first substrate; a second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a second plurality of pillar interconnects; and a second solder resist layer coupled to the second surface of the second substrate, wherein the second solder resist layer includes: a first solder resist layer portion including a first thickness, wherein the first solder resist layer portion overlaps with the first integrated device in a vertical direction; and a second solder resist layer portion including a second thickness greater than the first thickness, wherein the second solder resist layer portion is coupled to and contacts a side portion of each pillar interconnect of the plurality of pillar interconnects, wherein the second solder resist layer includes a cavity, wherein the cavity is located laterally between the second solder resist layer portion and one pillar interconnect of the plurality of pillar interconnects. The cavity is located vertically between the first integrated device and the second solder mask layer, and the second solder mask layer directly contacts the at least one second dielectric layer of the second substrate, coupled to the inter-substrate interconnection unit of the first substrate and the second substrate, wherein the inter-substrate interconnection unit is located between the first substrate and the second substrate, wherein the inter-substrate interconnection unit is configured to couple and directly contact the first plurality of pillar interconnects of the first substrate and the second plurality of pillar interconnects of the second substrate, wherein the inter-substrate interconnection unit includes a plurality of ball interconnects and a plurality of solder interconnects, and wherein a first solder interconnect from one of the plurality of solder interconnects directly contacts (i) a first ball interconnect from one of the plurality of ball interconnects, (ii) a pillar interconnect from one of the first plurality of pillar interconnects of the first substrate, (iii) a pillar interconnect from the second plurality of pillar interconnects of the second substrate, (iv) a first solder mask layer of the first substrate and (v) the second solder mask layer of the second substrate.

21. The integrated device package according to claim 20, wherein the first ball interconnect is a unique ball interconnect located in the vertical direction between (i) the pillar interconnect of the first plurality of pillar interconnects from the first substrate and (ii) the pillar interconnect of the second plurality of pillar interconnects from the second substrate.

22. The integrated device package according to claim 20, wherein the second solder mask contacts the entire side portion of each pillar interconnect from the plurality of pillar interconnects, wherein the pillar interconnect from the second plurality of pillar interconnects of the second substrate includes a thickness and a width, wherein the pillar interconnect directly contacts another interconnect from the second plurality of interconnects of the second substrate, and wherein the thickness of the pillar interconnect from the second plurality of pillar interconnects of the second substrate is greater than the width of the pillar interconnect.

23. The integrated device package according to claim 20, wherein the unit for inter-substrate interconnection includes interconnects having a pitch in the range of about 150 to 270 micrometers.

24. A method for manufacturing a package, comprising the steps of: providing a first substrate including at least one first dielectric layer, a first plurality of interconnects, and a first solder resist layer; A first integrated device is coupled to the first substrate; and a second substrate is coupled to the first substrate via a plurality of inter-substrate interconnects, such that the plurality of inter-substrate interconnects are located between the first substrate and the second substrate, wherein the second substrate includes: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, wherein the second plurality of interconnects includes a plurality of pillar interconnects; and a second solder mask layer coupled to the second surface of the second substrate, wherein the second solder mask layer includes: a first solder mask layer portion including a first thickness, wherein the first solder mask layer portion overlaps the first integrated device in a vertical direction; and a second solder mask layer portion including a second thickness greater than the first thickness, wherein the second solder mask layer portion is coupled to and contacts a side portion of each pillar interconnect of the plurality of pillar interconnects, wherein the second solder mask layer includes a cavity, wherein the cavity is located laterally between the second solder mask layer portion and one pillar interconnect of the plurality of pillar interconnects. The cavity is located vertically between the second solder resist layer and the first integrated device, and the second solder resist layer is in direct contact with the at least one second dielectric layer of the second substrate.

25. The method of claim 24, wherein the plurality of substrate interconnects comprises a plurality of ball interconnects and / or a plurality of solder interconnects.

26. The method of claim 24, wherein the plurality of inter-substrate interconnects are coupled to the plurality of pillar interconnects of the second substrate.

27. The method of claim 26, wherein the first substrate includes a first plurality of interconnects, wherein the first plurality of interconnects includes a first plurality of pillar interconnects, and wherein the inter-substrate interconnects are coupled to the first plurality of pillar interconnects of the first substrate.

28. The method of claim 24, wherein the plurality of substrate interconnects include interconnects having a spacing in the range of about 150 to 270 micrometers.

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