Semiconductor layout pattern and manufacturing method thereof

Abstract

The present invention provides a semiconductor layout pattern, comprising a first metal layer, the first metal layer including a plurality of first patterns and a plurality of herringbone patterns arranged on the same layer, wherein each herringbone pattern includes a main axis extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the main axis, a second metal layer located on the first metal layer, and a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer, wherein each MTJ element is arranged in a diamond shape.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly to a semiconductor layout pattern having diamond-shaped arranged magnetic tunnel junction (MTJ) elements. Prior Art

[0002] Magnetic random access memory (MRAM) is a non-volatile memory technology that uses magnetization states to represent stored data. Generally speaking, MRAM comprises multiple magnetic storage cells arranged in an array. Each storage cell essentially represents a single bit of data. These storage cells contain at least one magnetic element, which may include two magnetic plates (or material layers on a semiconductor substrate), each with an associated magnetic force direction (or bit direction of magnetic moment), and a thin non-magnetic layer between the two plates.

[0003] More specifically, an MRAM device is typically based on a magnetic tunnel junction (MTJ) element. An MTJ element comprises at least three basic layers: a free layer, an insulating layer, and a pinned layer. The free layer and the pinned layer are magnetic layers, and the insulating layer is an insulating layer located between the free and pinned layers. The magnetization of the free layer can rotate freely, but is constrained by the physical dimensions of the layers to point in one of two directions (parallel or antiparallel to the magnetic direction of the pinned layer). The magnetization of the pinned layer is fixed to a specific direction. A bit is written by positioning the magnetization of the free layer in one of these two directions. The resistance of the MTJ element changes depending on whether the magnetic moments of the free and pinned layers are aligned or opposite. Therefore, the bit value can be read by determining the resistance of the MTJ element. Specifically, when the magnetization directions of the free and pinned layers are parallel and their magnetic moments have the same polarity, the resistance of the MTJ element is in a low-resistance state. Essentially, the value stored in this state is "0." When the magnetization directions of the free layer and the pinned layer are antiparallel and the magnetic moments have opposite polarities, the resistance of the MTJ element is in a high-resistance state. Basically, the value stored in this state represents "1". Summary of the Invention

[0004] The present invention provides a semiconductor layout pattern, comprising a first metal layer, the first metal layer including a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern includes a main axis extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the main axis; a second metal layer located on the first metal layer; and a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer, wherein each MTJ element is arranged in a diamond shape.

[0005] The present invention further provides a method for forming a semiconductor layout pattern, comprising forming a first metal layer, the first metal layer comprising a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a main axis extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the main axis; forming a second metal layer located on the first metal layer; and forming a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer, wherein each MTJ element is arranged in a diamond shape.

[0006] The present invention is characterized by providing a semiconductor layout pattern including magnetic tunneling junction (MTJ) elements and a method for fabricating the same. Multiple MTJ elements are arranged in a diamond pattern, thereby achieving advantages such as increased spacing between elements, reduced alignment offset, and reduced overall element size. Furthermore, to accommodate the diamond-shaped MTJ elements, the present invention designs a first metal layer having a special shape, which includes multiple first patterns and multiple fishbone patterns. The specially shaped first metal layer designed by the present invention facilitates connection to subsequently formed MTJ elements, allowing multiple MTJ elements to be arranged in a diamond pattern, thereby achieving the aforementioned advantages. Simple diagram description

[0007] FIG. 1 is a schematic diagram illustrating the connection relationship between various components of the semiconductor structure of the present invention. FIG. 2 is a top view of the first metal layer in the semiconductor layout of the present invention. FIG. 3 illustrates a top view of a first metal layer, a first contact, and a second metal layer in a semiconductor layout of the present invention. FIG. 4 is a top view illustrating the second metal layer and the MTJ element in the semiconductor layout of the present invention. FIG. 5 is a top view of the MTJ element and the third metal layer in the semiconductor layout of the present invention. Implementation Method

[0008] In order to enable those skilled in the art to further understand the present invention, the following lists preferred embodiments of the present invention and describes in detail the components and intended effects of the present invention in conjunction with the accompanying drawings.

[0009] For ease of explanation, the various figures of the present invention are merely illustrative to facilitate understanding of the present invention. The detailed proportions may be adjusted based on design requirements. Those skilled in the art will readily understand that the upper and lower relationships between components depicted in the figures refer to the relative positions of the objects. Therefore, the figures can be reversed to present the same components, and this is fully within the scope of this specification. This is further clarified.

[0010] Please refer to Figure 1, which schematically illustrates the connections between the various components of the semiconductor structure of the present invention. First, a substrate 10 includes at least one transistor T, wherein the transistor T includes a gate G, a source S, and a drain D. The gate G is located on the surface of the substrate 10, while the source S and drain D are formed within the substrate 10, for example, by ion doping, and are located on either side of the gate G.

[0011] In this embodiment, the source S of transistor T is connected to a select line SL via a contact structure CT, while the drain D of transistor T is connected to a first metal layer M1, a first contact V1, a second metal layer M2, and a magnetic tunneling junction MTJ (hereinafter referred to as an MTJ element) via the contact structure CT. Furthermore, the MTJ element can be further connected to a bit line (BL), and the gate G of transistor T can be connected to a word line (WL). However, for simplicity, the word line and bit line are not shown in FIG. 1.

[0012] In this embodiment, the MTJ element includes a pinned layer, an insulating layer, and a free layer. The magnetization direction of the free layer can rotate freely in one or two directions and can be switched using spin-torque transfer (STT). For the pinned layer, an antiferromagnetic layer can be used to fix the magnetization direction in a specific direction. An isolation layer is disposed between the free layer and the pinned layer. As for the first metal layer M1, the second metal layer M2, the third metal layer M3, or the contact structure CT, the first contact V1 and other elements, their materials are preferably metals, such as copper, tungsten, etc., but the present invention is not limited thereto. The materials and manufacturing methods of the transistor T, the MTJ element, or the various metal layers or contact structures are conventional technologies in the art and will not be elaborated here.

[0013] The present invention arranges multiple MTJ elements in a diamond shape, rather than a standard matrix array. This increases the spacing between MTJ elements, reduces element misalignment, and reduces overall device size. The diamond-shaped layout pattern will be described in more detail later. In order to arrange the MTJ elements in a diamond shape, the present invention requires a specially designed first metal layer M1 to correspond to the position of each MTJ element.

[0014] FIG2 illustrates a top view of the first metal layer in the semiconductor layout of the present invention. FIG2 shows a first metal layer M1 formed, wherein the first metal layer M1 of the present invention has a unique shape. Specifically, the first metal layer M1 includes a plurality of fishbone line patterns 12 and a plurality of first patterns 14. Each fishbone line pattern 12 includes a main axis 12A and a plurality of branches 12B. The main axis 12A is arranged along a first direction (e.g., the X-axis), while the branches 12B are arranged along a second direction (e.g., the Y-axis). The branches 12B are located on either side of the main axis 12A (e.g., above and below) and are spaced evenly apart. Furthermore, the branches 12B located above and below the main axis 12A are aligned in the second direction. Therefore, a portion of the main axis 12A and two adjacent branches 12B together form a U-shaped opening. The first pattern 14 is preferably a rectangular pattern and is located within the U-shaped opening formed by the portion of the main axis 12A and two adjacent branches 12B. In other words, each first pattern 14 is located between two adjacent branches 12B and a portion of the main axis 12A. In addition, in other embodiments of the present invention, the first pattern 14 may also be an elliptical pattern.

[0015] In this embodiment, the fishbone pattern 12 and the first pattern 14 are located in the same layer and both belong to the first metal layer M1. In this embodiment, the first metal layer M1 is designed with a special shape to facilitate the formation of the subsequent diamond-shaped MTJ elements.

[0016] In this embodiment, referring to both Figures 1 and 2 , the main axis 12A of the fishbone pattern 12 is electrically connected to the select line SL, while the branches 12B of the fishbone pattern 12 are electrically connected to the source S of the transistor T. In other words, the source S of the transistor T can be connected to the select line SL via the fishbone pattern. Furthermore, the first pattern 14 is electrically connected to the drain D of the transistor T.

[0017] Please refer to Figure 3, which illustrates a top view of the first metal layer, first contact, and second metal layer in the semiconductor layout of the present invention. After forming the first metal layer M1, the first contact V1 and second metal layer M2 are subsequently formed. The first contact V1 is connected to the first pattern 14 in the first metal layer M1. The second metal layer M2 includes a plurality of rectangular patterns arranged in an array, each of which is electrically connected to the first contact V1 and the underlying first pattern 14.

[0018] Furthermore, in this embodiment, the second metal layers M2 are not arranged in a matrix. Specifically, for any fishbone pattern 12, there is an offset in the second direction (Y direction) between the second metal layers M2 located above and below the fishbone pattern 12. For example, FIG. 3 illustrates three second metal layers, defined as a second metal layer M2-1, a second metal layer M2-2, and a second metal layer M2-3. The second metal layers M2-1 and M2-2 are located above and below a fishbone pattern 12, respectively, and are offset in the Y direction. However, the second metal layers M2-1 and M2-3 are aligned in the Y direction.

[0019] Please refer to FIG. 4 , which illustrates a top view of the second metal layer and MTJ elements in the semiconductor layout of the present invention. Multiple MTJ elements are then formed on the second metal layer M2, wherein the multiple MTJ elements are arranged in a diamond shape. The diamond shape defined in this embodiment means that any four adjacent MTJ elements can be arranged in a diamond shape (e.g., the diamond shape depicted in FIG. 4 ), and two of the four MTJ elements are aligned in the first direction and the other two are aligned in the second direction. The extension line between the two MTJ elements aligned in the first direction (extension line L1 in FIG. 4 ) and the extension line between the two MTJ elements aligned in the second direction (extension line L2 in FIG. 4 ) intersect and are perpendicular to each other. The remaining definitions of diamonds not described in detail in the present invention are the same as those in the conventional art.

[0020] Please refer to Figures 2 through 4. Because the first metal layer M1 is designed with a special shape, after the second metal layers M2 are formed, each second metal layer M2 has a relatively larger area. This allows, for example, adjusting the subsequent MTJ element formation position so that each MTJ element can be formed on a different second metal layer M2 and arranged in a diamond shape. Furthermore, in the present invention, arranging the MTJ elements in a diamond shape increases the spacing between MTJ elements compared to a standard rectangular array, while also improving the tolerance for element alignment (i.e., reducing the probability of misalignment) and reducing the overall element area.

[0021] Please refer to Figure 5, which illustrates a top view of the MTJ element and the third metal layer in the semiconductor layout of the present invention. Subsequently, the third metal layer M3 is formed, which connects to the MTJ element and subsequently to the bit line. The layout pattern of the third metal layer M3 shown in this embodiment is merely an example and is not intended to limit the present invention.

[0022] In summary, the present invention provides a semiconductor layout pattern comprising a first metal layer M1, wherein the first metal layer M1 includes a plurality of first patterns 14 and a plurality of fishbone line patterns 12 arranged on the same layer, wherein each fishbone line pattern 12 includes a main axis 12A extending along a first direction (X-axis) and a plurality of branches 12B arranged along a second direction (Y-axis), and each first pattern 14 is located between two adjacent branches 12B and the main axis 12A; a second metal layer M2 located on the first metal layer M1; and a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer M2, wherein each MTJ element is arranged in a diamond shape.

[0023] The present invention further provides a method for forming a semiconductor layout pattern, comprising forming a first metal layer M1, wherein the first metal layer M1 includes a plurality of first patterns 14 and a plurality of fishbone line patterns 12 arranged on the same layer, wherein each fishbone line pattern 12 includes a main axis 12A extending along a first direction (X-axis) and a plurality of branches 12B arranged along a second direction (Y-axis), and each first pattern 14 is located between two adjacent branches 12B and the main axis 12A; forming a second metal layer M2 located on the first metal layer M1; and forming a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer M2, wherein each MTJ element is arranged in a diamond shape.

[0024] In some embodiments of the present invention, the plurality of branches 12B are arranged at equal intervals on both sides of the main axis 12A.

[0025] In some embodiments of the present invention, any two adjacent branches 12B and a portion of the main axis 12A define a U-shaped opening, and the first pattern 14 is located within the U-shaped opening.

[0026] In some embodiments of the present invention, the first pattern 14 includes a rectangle or an ellipse.

[0027] In some embodiments of the present invention, the first pattern 14 is electrically connected to the second metal layer M2, and each second metal layer M2 is electrically connected to one of the magnetic tunneling junction elements.

[0028] In some embodiments of the present invention, the fishbone line pattern 12 is electrically connected to a selection line SL.

[0029] In some embodiments of the present invention, the magnetic tunneling interface elements are arranged in a diamond shape, wherein any four adjacent magnetic tunneling interface elements can be arranged into a diamond shape, wherein no other magnetic tunneling interface elements are contained between the four adjacent magnetic tunneling interface elements, and two of the four adjacent magnetic tunneling interface elements are aligned in a first direction, and the other two magnetic tunneling interface elements are aligned in a second direction.

[0030] In some embodiments of the present invention, the first direction (X-axis) and the second direction (Y-axis) are perpendicular to each other.

[0031] In some embodiments of the present invention, the second metal layer M2 includes a plurality of second patterns (rectangular patterns in FIG. 4 ), and each magnetic tunneling junction element is located on one of the second patterns.

[0032] In some embodiments of the present invention, a transistor T is further included below the first metal layer M1, the transistor including a gate G, a source S, and a drain D, wherein the fishbone pattern 12 is electrically connected to a source S of the transistor T, and the first pattern 14 is electrically connected to a drain D of the transistor T.

[0033] The present invention is characterized by providing a semiconductor layout pattern including magnetic tunneling junction (MTJ) elements and a method for fabricating the same. Multiple MTJ elements are arranged in a diamond pattern, thereby achieving advantages such as increased spacing between elements, reduced alignment offset, and reduced overall element size. Furthermore, to accommodate the diamond-shaped MTJ elements, the present invention designs a first metal layer having a special shape, which includes multiple first patterns and multiple fishbone patterns. The specially shaped first metal layer designed by the present invention facilitates connection to subsequently formed MTJ elements, allowing multiple MTJ elements to be arranged in a diamond pattern, thereby achieving the aforementioned advantages. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0034] 10: Base 12: Fishbone pattern 12A: Spindle 12B: Branch 14: First pattern CT: Contact structure D: Drain G: Gate L1: Extension line L2: Extension line M1: First metal layer M2: Second metal layer M2-1: Second metal layer M2-2: Second metal layer M2-3: Second metal layer M3: The third metal layer MTJ: Magnetic Tunneling Junction S: Source SL: Select Line T: Transistor V1: First Contact

Claims

1. A semiconductor layout pattern, comprising: a first metal layer including a plurality of first patterns and a herringbone pattern, wherein the plurality of first patterns and the herringbone pattern are both made of conductive material and aligned on an XY plane, wherein the herringbone pattern includes a main axis extending along a first direction and a plurality of branches connecting the main axis and extending in a second direction, wherein the main axis and the plurality of branches do not overlap in a normal direction of the XY plane, and each of the first patterns is located between any two adjacent branches of the plurality of branches and the main axis of the herringbone pattern; a second metal layer located on the first metal layer; and a plurality of magnetic tunnel junctions (MTJ) elements located on the second metal layer, wherein each of the magnetic tunnel junction elements is arranged in a diamond shape.

2. The semiconductor layout pattern as described in claim 1, wherein along the first direction, the spacing between any two adjacent branches of the plurality of branches of the herringbone pattern is equal.

3. The semiconductor layout pattern as described in claim 2, wherein any two adjacent branches of the plurality of branches and a portion of the main axis define a U-shaped opening, and the first pattern is located within the U-shaped opening.

4. The semiconductor layout pattern as described in claim 1, wherein each of the plurality of first patterns comprises a rectangle or an ellipse.

5. The semiconductor layout pattern as described in claim 1, wherein each of the plurality of first patterns is electrically connected to the second metal layer, and the second metal layer is electrically connected to one of the magnetic tunneling interface elements.

6. The semiconductor layout pattern as described in claim 1, wherein the herringbone pattern is electrically connected to a select line.

7. The semiconductor layout pattern as described in claim 1, wherein the plurality of magnetic tunneling interface elements are arranged in a rhomboid pattern, wherein: any four adjacent magnetic tunneling interface elements are arranged in the rhomboid pattern, wherein no other magnetic tunneling interface elements are included between the four adjacent magnetic tunneling interface elements; a first magnetic tunneling interface element and a second magnetic tunneling interface element are aligned in the first direction among the four adjacent magnetic tunneling interface elements, and a third magnetic tunneling interface element and a fourth magnetic tunneling interface element are aligned in the second direction.

8. The semiconductor layout pattern as described in claim 1, wherein the first direction and the second direction are both located on the XY plane, and the first direction and the second direction are perpendicular to each other.

9. The semiconductor layout pattern as described in claim 1, wherein the second metal layer comprises a plurality of second patterns, and one of the plurality of magnetic tunneling interface elements is located on one of the plurality of second patterns.

10. The semiconductor layout pattern as described in claim 1, further comprising a transistor located below the first metal layer, the transistor comprising a gate, a source and a drain, wherein the herringbone pattern is electrically connected to a source of the transistor, and one of the plurality of first patterns is electrically connected to a drain of the transistor.

11. A method for forming a semiconductor layout pattern, comprising: forming a first metal layer, the first metal layer including a plurality of first patterns and a herringbone pattern, wherein the plurality of first patterns and the herringbone pattern are both made of conductive material and aligned on an XY plane, wherein the herringbone pattern includes a main axis extending along a first direction and a plurality of branches connecting the main axis and extending in a second direction, wherein the main axis and the plurality of branches do not overlap in a normal direction of the XY plane, and each of the first patterns is located between any two adjacent branches of the plurality of branches and the main axis of the herringbone pattern; forming a second metal layer on the first metal layer; and forming a plurality of magnetic tunnel junctions (MTJ) elements on the second metal layer, wherein each of the magnetic tunnel junction elements is arranged in a diamond shape.

12. The method of forming a semiconductor layout pattern as described in claim 11, wherein along the first direction, the spacing between any two adjacent branches of the plurality of branches of the herringbone pattern is equal.

13. The method for forming a semiconductor layout pattern as described in claim 12, wherein any two adjacent branches of the plurality of branches and a portion of the main axis define a U-shaped opening, and the first pattern is located within the U-shaped opening.

14. The method for forming a semiconductor layout pattern as described in claim 11, wherein each of the plurality of first patterns comprises a rectangle or an ellipse.

15. The method of forming a semiconductor layout pattern as described in claim 11, wherein each of a plurality of first patterns is electrically connected to the second metal layer, and the second metal layer is electrically connected to one of the magnetic tunneling interface elements.

16. The method for forming a semiconductor layout pattern as described in claim 11, wherein the herringbone pattern is electrically connected to a selection line.

17. The method for forming a semiconductor layout pattern as described in claim 11, wherein the plurality of magnetic tunneling interface elements are arranged in a rhomboid pattern, wherein: any four adjacent magnetic tunneling interface elements are arranged in the rhomboid pattern, wherein no other magnetic tunneling interface elements are included between the four adjacent magnetic tunneling interface elements; a first magnetic tunneling interface element and a second magnetic tunneling interface element are aligned in a first direction among the four adjacent magnetic tunneling interface elements, and a third magnetic tunneling interface element and a fourth magnetic tunneling interface element are aligned in a second direction.

18. The method for forming a semiconductor layout pattern as described in claim 11, wherein the first direction and the second direction are both located on the XY plane, and the first direction and the second direction are perpendicular to each other.

19. The method for forming a semiconductor layout pattern as described in claim 11, wherein the second metal layer includes a plurality of second patterns, and one of the plurality of magnetic tunneling interface elements is located on one of the plurality of second patterns.

20. The method for forming a semiconductor layout pattern as described in claim 11, further comprising a transistor located below the first metal layer, the transistor comprising a gate, a source and a drain, wherein the herringbone pattern is electrically connected to a source of the transistor, and one of the plurality of first patterns is electrically connected to a drain of the transistor.

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