Device for managing device memory

Abstract

The present invention provides an apparatus comprising: a device memory; and device functional circuitry, wherein at least a portion of the device functional circuitry is capable of accessing at least a portion of the device memory; and control circuitry configured to provide information, wherein the information is capable of instructing at least a portion of the device functional circuitry to access at least a portion of the device memory. Alternatively or additionally, the control circuitry may be configured to receive at least one request and perform a configuration operation based on the at least one request, wherein the configuration operation may include configuring at least a portion of the device memory to be accessed by at least a portion of the device functional circuitry.

Description

Systems, Methods, and Devices for Managing Device Memory and Programs This disclosure is generally related to devices, and more particularly, to systems, methods, and devices for managing device memory and programs. [Cross - reference to Related Applications] This application claims the benefit and priority of U.S. Provisional Patent Application Serial No. 63 / 339,506, filed May 8, 2022, which is incorporated herein by reference. Devices such as accelerators, storage devices, and / or the like may perform one or more operations for another device such as a host. For example, an accelerator may perform calculations using data provided by the host. As another example, a storage device may store data provided by the host. Devices such as accelerators, storage devices, and / or the like may use device memory to implement one or more operations. The above information disclosed in this background section is only for enhancing the understanding of the background of the principles of the present invention, and thus it may contain information that does not constitute prior art. A device may include: a device memory; and device functional circuitry, wherein at least a portion of the device functional circuitry may be able to access at least a portion of the device memory; and control circuitry configured to provide information, wherein the information indicates that at least a portion of the device functional circuitry may be able to access at least a portion of the device memory. The information may further indicate characteristics of at least a portion of the device memory. The device may further include a communication interface, wherein the control circuitry may be configured to provide the information using the communication interface. The control circuitry may be configured to receive a request using the communication interface and provide the information based on the request. A portion of the device memory may be a first portion of the device memory, and the information may indicate that at least a portion of the device functional circuitry may be able to access a second portion of the device memory. A portion of the device functional circuitry may be a first portion of the device functional circuitry, and the information may indicate that a second portion of the device functional circuitry may be able to access at least a portion of the device memory. A first portion of at least a portion of the device functional circuitry may be configured as a first namespace, and a second portion of at least a portion of the device memory may be configured as a second namespace. A device may include: a device memory; and device functional circuitry, where at least a portion of the device functional circuitry may be able to access at least a portion of the device memory; and control circuitry configured to receive at least one request and perform a configuration operation based on the at least one request, where the configuration operation may include configuring at least a portion of the device memory to be accessed by at least a portion of the device functional circuitry. The configuration operation may include receiving configuration information and providing the configuration information to a memory control device associated with at least a portion of the device functional circuitry. The configuration operation may include allocating at least a portion of the device memory to at least a portion of the device functional circuitry. The device may further include a communication interface, where the control circuitry may be configured to receive requests using the communication interface. The portion of the device memory may be a first portion of the device memory, and the control circuitry may be configured to configure a second portion of the device memory to be accessed by at least a portion of the device functional circuitry based on the at least one request. The portion of the device functional circuitry may be a first portion of the device functional circuitry, and the control circuitry may be configured to configure at least a portion of the device memory to be accessed by a second portion of the device functional circuitry based on the at least one request. A first portion of at least a portion of the device functional circuitry may be configured as a first namespace, and a second portion of at least a portion of the device memory may be configured as a second namespace. The portion of the device functional circuitry may include a computing engine and a program configured to use the computing engine. The device may include at least one computing resource and control circuitry configured to receive a program, associate the program with a first computing namespace of the at least one computing resource, and associate the program with a second computing namespace of the at least one computing resource. The device may further include a communication interface, where the control circuitry may be configured to receive the program using the communication interface. The control circuitry may be configured to provide information about the program using the communication interface. The control circuitry may be configured to configure at least a first portion of the at least one computing resource as a first computing namespace and configure at least a second portion of the at least one computing resource as a second computing namespace. The control circuitry may be configured to receive a command and receive the program based on the command. A method may include: receiving, at a device, a request for information, where the device includes a device memory and device functional circuitry, and providing the information based on the request, where the information indicates that at least a portion of the device functional circuitry may be able to access at least a portion of the device memory. The information may further indicate a characteristic of at least a portion of the device memory. The device may further include a communication interface, and the providing may be performed at least in part using the communication interface. The receiving may be performed at least in part using the communication interface. At least a portion of the device memory may include a first portion of the device memory, and where the information may indicate that at least a portion of the device functional circuitry may be able to access a second portion of the device memory. At least a portion of the device functional circuitry may include a first portion of the device functional circuitry, and where the information may indicate that a second portion of the device functional circuitry may be able to access at least a portion of the device memory. The first portion of at least a portion of the device functional circuitry may be configured as a first namespace, and the second portion of at least a portion of the device memory may be configured as a second namespace. A method may include: receiving, at a device, at least one request, where the device may include a device memory and device functional circuitry, and performing a configuration operation based on the at least one request, where the configuration operation may include configuring at least a portion of the device memory to be accessed by at least a portion of the device functional circuitry. The configuration operation may include receiving configuration information at the device and providing the configuration information to a memory control device associated with at least a portion of the device functional circuitry. The configuration operation may include allocating at least a portion of the device memory to at least a portion of the device functional circuitry. The device may further include a communication interface, and the at least one request may be received at least in part using the communication interface. The portion of the device memory may be a first portion of the device memory, and the method may further include configuring a second portion of the device memory to be accessed by at least a portion of the device functional circuitry based on the at least one request. The portion of the device functional circuitry may be a first portion of the device functional circuitry, and the method may further include configuring at least a portion of the device memory to be accessed by a second portion of the device functional circuitry based on the at least one request. The first portion of at least a portion of the device functional circuitry may be configured as a first namespace, and the second portion of at least a portion of the device memory may be configured as a second namespace. The portion of the device functional circuitry may include a computing engine and a program configured to use the computing engine. A method may include: receiving a program at a device, where the device may include at least one computing resource, and associating the program with a first computing namespace of the at least one computing resource and associating the program with a second computing namespace of the at least one computing resource. The device may further include a communication interface, and the program may be received at least in part using the communication interface. The method may further include providing information about the program using the communication interface. The method may further include configuring at least a first portion of the at least one computing resource as the first computing namespace and configuring at least a second portion of the at least one computing resource as the second computing namespace. The method may further include receiving a command at the device, and the receiving of the program may be based on the command. Devices such as accelerators, storage devices, and / or the like may use device memory to perform one or more operations. For example, an accelerator may use device memory to store input and / or output data for computing. As another example, a storage device may use device memory as a cache memory for data that may be stored in a storage medium. Some inventive principles of the present disclosure relate to the management of device memory. For example, a device may implement an exploration mechanism that enables the device to provide information about the device memory (e.g., to a device such as a host). Additionally or alternatively, the device may implement a management mechanism that enables the device memory to be managed (e.g., by a device such as a host) based on memory information provided by the device (e.g., using the exploration mechanism). In some embodiments, the exploration mechanism may implement one or more requests to provide information about the device memory. For example, the device may receive a request for information about the device memory (e.g., an exploration command from a device such as a host). The device may respond to the request by returning a list of device memory resources, a log page that may include information about the device memory resources, and / or the like. The information may include one or more indications of one or more portions of the device functionality that may be able to access one or more portions of the device memory. Additionally or alternatively, the information may include an indication of one or more characteristics (e.g., type, amount, configuration, access characteristics, performance characteristics, and / or the like) of one or more portions of the device memory. In some embodiments, the device memory may be managed by configuring one or more portions of the device memory to be accessed by one or more portions of the device functionality. For example, in a device having computing resources, the management mechanism may enable a host to configure one or more first portions of the device memory to be accessed by a first computing resource and configure one or more second portions of the device memory to be accessed by a second computing resource. In some embodiments, access to one or more portions of a device memory may be subject to various restrictions, permissions, physical and / or logical connections, locality, and / or the like. For example, a particular device memory may be integrated with a specific computing resource (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or the like) and accessible only by it, while a particular device memory may be more widely accessible (e.g., to any one or more portions of the device functionality). In some embodiments, one or more portions of device resources may be configured using one or more namespaces. For example, one or more portions of device memory resources, device computing resources, and / or device storage resources may be configured as one or more memory namespaces, computing namespaces, and / or storage namespaces, respectively. Some of the inventive principles of the present disclosure relate to receiving a computing device program at a computing device that is accessible by multiple computing resources. For example, a computing device program may be downloaded (e.g., from a device such as a host) to the computing device. The downloaded computing device program may be stored, for example, in a repository (e.g., a repository that may be at least partially public, global, and / or the like), which may be accessible by one or more first computing resources configured as a first computing namespace and one or more second computing resources configured as a second computing namespace. In some embodiments, the device may enable a computing device program to be downloaded, discovered, launched, and / or the like (e.g., by a device such as a host) using a command mechanism. In some embodiments, the device may enable the visibility and / or accessibility of the downloaded computing device program to be configured. For example, a device such as a host may configure the downloaded computing device program to appear as a native computing program (e.g., having at least partially public, global, and / or the like accessibility). Additionally or alternatively, the downloaded computing device program may be configured to have restricted access (e.g., by one or more specific computing resources). The present disclosure encompasses numerous inventive principles related to the management of device memory and / or programs. The principles disclosed herein may have independent utility and may be implemented alone, and not every embodiment may utilize every principle. Additionally, the principles may also be implemented in various combinations, some of which may augment the benefits of individual principles in a collaborative manner. For illustrative purposes, some embodiments may be described in the context of a computing device (e.g., a computing storage device) and / or computing resources. However, the principles may be applied to any device and / or device functionality that may utilize device memory and / or programs received at the device. FIG. 1 illustrates an embodiment of a device having a device memory in accordance with an exemplary embodiment of the present disclosure. The device 102 shown in FIG. 1 may include a device functional device 104 (which may also be referred to as device functionality, device functional resources, or functional resources), a device memory 106 (which may also be referred to as device memory resources or memory resources), one or more controllers 110 (which may be individually and / or collectively referred to as the controller), and / or one or more communication interfaces 112 (which may be individually and / or collectively referred to as the communication interface). The device functionality 104 may include any type of resources (e.g., hardware and / or software) that enable the device 102 to perform one or more functions of the device (e.g., primary functions). For example, if the device 102 is at least partially implemented as a storage device, the device functionality 104 may include any type of non-volatile storage media, media translation layer, one or more channel controllers, and / or the like. Examples of storage media may include solid state media, magnetic media, optical media, and / or the like, or combinations thereof. For example, a storage device may be implemented as a solid state drive (SSD) having NAND flash memory and a media translation layer implemented as a flash translation layer (FTL). Other examples of solid state media may include persistent memory, such as cross-grid non-volatile memory, memory with body resistance change, phase change memory (PCM), and / or the like, or any combination thereof. As another example, if the device 102 is at least partially implemented as a computing device (e.g., an accelerator, a compute storage device, and / or the like), the device functionality 104 may include any type of hardware and / or software computing resources, such as one or more computing engines, one or more programs, and / or the like. Examples of computing engines can include complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), central processing units (CPUs) including complex instruction set computers (CISCs) such as x86 processors and / or reduced instruction set computers (RISCs) such as ARM processors, graphics processing units (GPUs), data processing units (DPUs), neural processing units (NPUs), tensor processing units (TPUs), and / or the like, which can execute instructions stored in any type of memory and / or implement any type of execution environment, such as containers, virtual machines, operating systems such as Linux, Extended Berkeley Packet Filter (eBPF) environments, and / or the like, or combinations thereof. In some embodiments, the computing engine can include combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, and / or the like. In some embodiments, some or all of the computing resources can be implemented as a system-on-chip (SOC). Examples of programs can include any type of instructions executable by one or more computing resources, such as algorithms, data movement, data management, data selection, filtering, encryption and / or decryption, compression and / or decompression, encoding and / or decoding (e.g., erasure coding), checksum calculation, hash value calculation, cyclic redundancy check (CRC), and / or the like. In some embodiments, the program can perform operations using data stored in the device memory 106, data streamed to the program, and / or the like. As another example, if device 102 is at least partially implemented as a communication device, such as a network interface card (NIC), a wireless access point (AP), a station (STA), a wireless base station, a wireless user equipment (UE), and / or the like, then device functionality 104 may include one or more components for receiving and / or transmitting wired and / or wireless (e.g., RF) signals, such as amplifiers, filters, modulators and / or demodulators, A / D and / or D / A converters, antennas, switches, phase shifters, detectors, couplers, conductors, transmission lines, modems, network interfaces, a physical layer (PHY), a medium access control layer (MAC), and / or the like. Device memory 106 may include one or more volatile and / or non-volatile (e.g., persistent) memory resources that may have a wide variety of characteristics such as memory type, bandwidth, capacity, latency, access granularity, write endurance, power consumption, and / or the like. Examples of volatile memory may include dynamic random access memory (DRAM), static random access memory (SRAM), and / or the like. Examples of non-volatile memory may include NAND flash memory, crossbar non-volatile memory, memory with body resistance change, PCM, magnetoresistive random-access memory (MRAM), resistive random-access memory (ReRAM), and / or the like. In some embodiments, one or more portions of the device memory may be configured as one or more memory name spaces. In some embodiments, a memory name space may refer to a set of one or more addresses, address ranges, and / or the like of memory cells, lines, rows, bytes, words, pages, blocks, and / or the like. In some embodiments, access to one or more portions of the device memory may be subject to various restrictions, permissions, physical and / or logical connections, locality, and / or the like. For example, a certain device memory may be integrated with a specific computing resource (e.g., FPGA, ASIC, and / or the like) and accessible only by it, while a certain device memory may be more widely accessible (e.g., to any one or more portions of the device functionality). The device memory 106 can be implemented in any physical configuration, including single inline memory modules (SIMMs), dual inline memory modules (DIMMs), individual memory devices (e.g., integrated circuits (ICs)), stacks of memory devices, embedded in one or more other components such as FPGAs, ASICs, and / or the like. The device memory 106 can be located within, on, at, and / or near the device 102. For example, one or more portions of the device memory 106 can be attached to (e.g., soldered, connected using connectors, and / or the like) a circuit board that can be used to implement the device 102, attached to the device 102, and / or positioned adjacent to or near the device 102 in a manner that can be controlled and / or accessed by the device 102, such as in a memory buffer, cache memory, and / or the like, which can be accessed by the device 102 using interfaces and / or protocols such as CXL.cache, CXL.io, CXL.mem, and / or the like (e.g., coherent interfaces and / or protocols). Although the device functionality 104 and the device memory 106 are shown as separate components, in some embodiments, one or more portions of the device functionality 104 and one or more portions of the device memory 106 can overlap. For example, one or more portions of the device memory 106 can be at least partially located within one or more portions of the device functionality 104 (e.g., an FPGA or ASIC can include local DRAM). Similarly, while a local memory can be located within a compute engine (and potentially only accessible by the compute engine), one or more compute resources 104 can be located within one or more portions of the device memory 106. For example, in some embodiments, a memory device or a stack of memory devices can include processing in memory (PIM) hardware that can be located within the memory device or the stack of memory devices (and potentially only able to access the memory device or the stack of memory devices). The controller 110 may include any type of resource (e.g., hardware and / or software) that can control the operation of one or more parts of the device 102. For example, the controller 110 may include one or more processors, state machines, combinational logic, sequential logic, CPLDs, FPGAs, ASICs, dedicated logic, and / or the like. In some embodiments, if the device 102 is at least partially implemented as a storage device, one or more controllers 110 may include one or more FTLs, channel controllers, Nonvolatile Memory (NVMe) controllers, Peripheral Component Interconnect Express (PCIe) controllers, Compute Express Link (CXL) controllers, and / or the like, or combinations thereof. In some embodiments, if the device 102 is at least partially implemented as a communication device, one or more controllers 110 may include one or more MAC controllers. The communication interface 112 can be implemented by any type of wired and / or wireless communication media, interfaces, networks, interconnects, protocols, and / or the like, including PCIe, NVMe, NVMe over Fabric (NVMe-oF), CXL, and / or coherent protocols (such as CXL.mem, CXL.cache, CXL.IO, and / or the like), Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), and / or the like, Advanced eXtensible Interface (AXI), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Advanced Message Queuing Protocol (AMQP), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), FibreChannel, InfiniBand, Serial ATA (SATA), Small Computer Systems Interface (SCSI), Serial Attached SCSI (SAS), iWARP, any generation of wireless network including 2G, 3G, 4G, 5G, 6G, and / or the like, any generation of Wi-Fi, Bluetooth, near-field communication (NFC), and / or the like, or any combination thereof. The device 102 can be implemented with any physical form factor. Examples of form factors can include the form factor of a 3.5-inch storage device, the form factor of a 2.5-inch storage device, the form factor of a 1.8-inch storage device, the M.2 device form factor, the Enterprise and Data Center Standard Form Factor (EDSFF) (which can include, for example, E1.S, E1.L, E3.S, E3.L, E3.S 2T, E3.L 2T, and / or the like), an add-in card (AIC) (e.g., the form factor of a PCIe card (such as a PCIe expansion card), including half-height (HH), half-length (HL), half-height half-length (HHHL), and / or the like), the Next-generation Small Form Factor (NGSFF), the NF1 form factor, the compact flash (CF) card form factor, the secure digital (SD) card form factor, the Personal Computer Memory Card International Association (PCMCIA) device form factor, and / or the like, or a combination thereof. In some embodiments, any of the devices disclosed herein can be connected to a system using one or more connectors, such as SATA connectors, SCSI connectors, SAS connectors, M.2 connectors, EDSFF connectors (e.g., 1C, 2C, 4C, 4C+, and / or the like), U.2 connectors (which can also be referred to as SSD form factor (SSF) SFF-8639 connectors), U.3 connectors, PCIe connectors (e.g., card-edge connectors), and / or the like. In some embodiments, any of the devices disclosed herein can be implemented in whole or in part with and / or used in combination with: a server chassis, a server rack, a data machine room, a data center, an edge data center, a mobile edge data center, and / or any combination thereof. FIG. 2 shows an embodiment of a compute storage device with a namespace according to an exemplary embodiment of the present disclosure. The device 202 shown in FIG. 2 can be used, for example, to implement the device 102 shown in FIG. 1. The device 202 can include some elements similar to the elements shown in FIG. 1, where the similar elements can have reference numerals ending with similar numbers. However, in the device 202 shown in FIG. 2, one or more portions of the device functionality can be implemented as a compute engine 211 and / or a program 207, and one or more portions of the device functionality can be implemented as a storage medium 213. In the device 202 shown in FIG. 2, one or more portions of the device resources may be configured as one or more namespaces. For example, one or more portions of the device memory resources, device computing resources, and / or device storage resources may be configured as one or more memory namespaces, computing namespaces, and / or storage namespaces, respectively. In some embodiments, a namespace may refer to a collection of one or more resources. In some embodiments, a collection of one or more resources configured as a namespace may be at least partially isolated from other collections of resources configured as other namespaces. In some embodiments, a namespace may provide logical and / or physical isolation between namespaces and / or resources that may be configured as namespaces. In some embodiments, a namespace may indicate a collection of one or more resources that can be accessed as a unit, such as by a device such as a host. In some embodiments, a namespace may be configured, treated, and / or the like as a virtual construct (e.g., a virtual namespace). Depending on the implementation details, this may enable a namespace (e.g., a computing namespace) to be mapped (e.g., directly) into a virtual environment such as a virtual machine (VM). In some embodiments, a virtual machine may control the loading (e.g., downloading) of a program into a computing namespace associated with the virtual machine. This may contrast with using a central entity such as a hypervisor to load a program. Depending on the implementation details, enabling a virtual machine to control the loading of a program may provide flexibility, such as to remove the loaded program (e.g., when the virtual machine is terminated and shut down). In the context of storage resources, a namespace may refer to a collection of one or more logical block addresses (LBAs). The LBAs may be mapped to one or more physical block addresses (PBAs) that may be located at different physical locations such as cylinders, tracks, channels, pages, and / or the like. Depending on the implementation details, a namespace may be presented (e.g., to a device such as a host) as a separate storage device. In the device 202 shown in FIG. 2, one or more portions of the storage medium 213 may be configured as one or more storage namespaces 246. In the context of computing resources, a computing namespace may refer to a collection of, for example, one or more computing engines, programs, and / or the like as described above with respect to FIG. 1. In the device 202 shown in FIG. 2, one or more computing resources such as the computing engine 211 and / or the program 207 may be configured as one or more computing namespaces 244. In the context of memory resources, a memory name space may refer to a collection of, for example, one or more memories and / or portions thereof as described above with respect to FIG. 1. For example, a memory name space is configured as a collection of one or more addresses, address ranges, and / or the like of memory cells, lines, rows, bytes, words, pages, blocks, and / or the like. In the device 202 shown in FIG. 2, one or more portions of the device memory 206 may be configured as one or more memory name spaces 248. Referring again to FIG. 1, in some embodiments, one or more of the portions of the device memory 106 may be used by one or more of the portions of the device functionality 104. For example, in an embodiment where the device 102 is implemented as a compute storage device, the device functionality 104 may include compute resources (e.g., one or more compute engines and / or compute programs) and storage resources (e.g., storage media). In this embodiment, one or more portions of the device memory 106 may be used, for example, for any number of the following operations: storing input data copied from a host, a storage media (e.g., one or more portions of a storage media configured as a storage name space), and / or the like; buffering and / or outputting data for a program running on a compute engine; buffering intermediate data used by a program running on a compute engine; copying output data to a host memory, a storage media (e.g., one or more portions of a storage media configured as a storage name space), and / or the like; exchanging data between programs; exchanging data between virtual machines (e.g., running on one or more compute resources); and / or the like. Some inventive principles of the present disclosure relate to mechanisms (which may also be referred to as schemes) that can be used to obtain information about and / or manage the device memory 106. For example, in some embodiments, the device 102 may implement a discovery mechanism that enables a host to obtain information about one or more portions of the device memory 106 that may be located in, on, at, and / or near the device 102. Additionally or alternatively, the device 102 may implement a management mechanism that enables the host to use information about the device memory (e.g., obtained using the discovery mechanism) to manage one or more portions of the device memory 106. In some embodiments, one or more portions of the device memory 106 may be managed by configuring one or more portions of the device memory 106 to access one or more portions of the device functionality 104. For example, in a device 102 where at least a portion of the device functionality 104 is implemented by compute resources, the management mechanism may enable the host to configure one or more first portions of the device memory 106 to access a first compute resource and configure one or more second portions of the device memory 106 to access a second compute resource. In some embodiments, the host may be implemented by any component or combination of components that can use one or more of the device functionality 104, the device memory 106, the discovery mechanism of the device 102, and / or the management mechanism. For example, the host may include one or more of a client device, a server, a storage node, a CPU, a personal computer, a tablet computer, a smartphone, and / or the like. For illustrative purposes, some exemplary embodiments may be described in the context of a system where the host can use discovery and / or management schemes to obtain information about and / or manage the device memory. However, the principles are not limited to use by a host as described above. For example, any of the schemes for obtaining information about and / or managing the device memory may be used at least in part by the device itself, by another device, and / or any other entity that may include hardware, software, programs, services, and / or the like. Thus, in some embodiments, and depending on the context and / or implementation details, the host may refer to any entity, including the device itself and / or a part of another device, that can use discovery and / or management schemes to obtain information about the device memory according to the disclosure and / or manage the device memory. FIG. 3 shows an embodiment of a device including a discovery mechanism according to an exemplary embodiment of the present disclosure. The device 302 may include some elements similar to those shown in FIGS. 1 and / or 2, where similar elements may have reference numerals ending with similar digits. However, in the embodiment shown in FIG. 3, the controller 310 may include discovery logic 314 that may implement a discovery mechanism to enable the device 302 to provide information 316 (which may be referred to as memory information) about the device memory 306 (e.g., to a device such as a host). Memory information 316 may include an indication of one or more characteristics (e.g., type, quantity, configuration, access characteristics, performance characteristics, and / or the like) of one or more portions of the device memory. For example, device memory 306 may include one or more types of volatile memory (e.g., DRAM, SRAM, and / or the like) and / or non-volatile (e.g., persistent) memory resources (e.g., flash memory, PCM, and / or the like). Various portions of device memory 306 may have different bandwidths (e.g., read and / or write bandwidths), capacities (e.g., size in bytes such as kilobytes (KB), megabytes (MB), gigabytes (GB), etc.), latencies, access granularities (e.g., persistent memory may be byte-addressable while flash memory may be written and / or read in pages but erased in blocks), namespace configurations (e.g., one or more portions of any memory resource may be configured as one or more namespaces, address ranges within a namespace, and / or the like), write durability, power consumption, and / or the like. In some embodiments, memory information 316 may include one or more indications of any of these or other characteristics of one or more portions of device memory 306. Additionally or alternatively, memory information 316 may include one or more indications of one or more portions of device functionality that may be able to access one or more portions of the device memory. For example, one or more portions of device functionality 304 and one or more portions of device memory 306 may be connected via one or more connections (e.g., the structure or configuration of the connections). Some of the connections may only implement restricted access (e.g., local or private access) to one or more portions of device memory 306, while some of the connections may enable one or more portions of device memory 306 to be accessed in an unrestricted or less restricted manner (e.g., global or public access) by one or more portions of device functionality 304. For example, an FPGA may include local (e.g., internal) memory and a configuration of connections that only allows the local memory to be accessed by computing resources within the FPGA. Similarly, a computing engine (e.g., CPU circuitry such as ARM circuitry) may include local memory and a configuration of connections that only allows the local memory to be accessed by the CPU. In some embodiments, memory information 316 may include one or more indications of any of these or other characteristics, connections, restrictions, configurations, and / or the like of device functionality 304 and / or device memory 306. In some embodiments, the discovery mechanism may issue one or more memory information requests (e.g., commands) 315 to provide information about the device memory 306. For example, the device may receive a discovery command (e.g., from a device such as a host) requesting information about the device memory 306. The device 302 may respond to the discovery command by returning a data structure (e.g., a list, table, and / or the like), a pointer to the data structure, a log page, and / or the like that may contain information about the device memory resource 306. As another example, the device 302 may implement a command line interface (CLI) that enables the device to provide memory information (e.g., to a device such as a host). FIG. 4 illustrates an exemplary embodiment of a discovery device memory command according to an exemplary embodiment of the present disclosure. The discovery device memory command 418 shown in FIG. 4 may be used, for example, to implement the memory information request 315 shown in FIG. 3. The discovery device memory command 418 may be sent, for example, to the controller 310 of the device 302 (e.g., by a host) to cause the controller 310 to provide memory information 316 (e.g., to the host). In some embodiments, the controller 310 may send a response (e.g., a data structure containing the requested memory information 316 embedded in the response) that may contain the requested memory information 316 in response to the discovery device memory command 418. Alternatively or additionally, the discovery device memory command 418 shown in FIG. 4 may include a data location 420 that may indicate (e.g., by a pointer) the location (e.g., a buffer location) where the controller 310 may write the requested memory information 316. In some embodiments, the discovery device memory command 418 may be implemented, for example, as an NVMe command, a CXL command, and / or the like. Table 1 illustrates an exemplary embodiment of a data structure that may be used to provide information about the device memory according to an exemplary embodiment of the present disclosure. The embodiment shown in Table 1 may be used, for example, to respond to the discovery device memory command 418 shown in FIG. 4 and provide device memory information 316 in the context of the device 302 shown in FIG. 3. In the embodiment shown in Table 1, one or more portions of the device functionality 304 may be implemented as a compute engine (CE) as shown in row 2, but the principles may apply to any other type of device functionality. Referring to Table 1, the columns may correspond to one or more portions of the device memory 306. The rows within a column may provide the following information: Row 1 may indicate a memory identifier (Memory ID or Mem ID) for a portion of the device memory 306 (e.g., a memory device); Row 2 may indicate an identifier for one or more portions of the device functionality 304 that may be capable of accessing the portion of the device memory 306 identified by the Mem ID (in this example, a Compute Engine ID or CEID); Row 3 may indicate one or more characteristics of the portion of the device memory 306 indicated by the Mem ID (in this example, memory type (e.g., DRAM or persistent), latency, bandwidth, and / or power characteristics); Rows 4 and 5 may include one or more sub-columns that may include a Namespace identifier (Namespace ID or NSID) and / or a Range identifier (Range ID or RID) that indicate one or more namespaces and / or the range of memory that may be configured to correspond to the namespace; Row 6 may indicate the range of memory addresses associated with the corresponding Namespace ID and / or Range ID; and Row 7 may indicate whether the corresponding memory address range has been allocated (e.g., to a compute engine, a program, and / or the like). Table 1 As mentioned above, for illustrative purposes, in the embodiments shown in Table 1, one or more portions of the device functionality 304 may be implemented as a compute engine as shown in Row 2, but the principles may apply to any other type of device functionality. For example, in other specific instances, Row 2 may indicate the identifier for one or more portions of the device functionality 304 as a Device Functionality ID or DFID. For illustrative purposes, the embodiments shown in Table 1 may provide an example of information regarding the device memory corresponding to the embodiments shown in FIG. 9, but the principles are not limited to these or any other implementation details. FIG. 5 shows an embodiment of a device including a management mechanism according to an exemplary embodiment of the present disclosure. The device 502 shown in FIG. 5 may include some elements similar to those shown in FIGS. 1, 2, and / or 3, where the similar elements may have reference numerals ending with similar digits. However, in the embodiment shown in FIG. 5, the controller 510 may include management logic 518 that may implement a management mechanism to enable the device memory 506 to be managed based on memory information provided by the device, such as using a discovery mechanism. The management logic 518 may manage the device memory 506, for example, by configuring one or more portions of the device memory 506 to be accessed by one or more portions of the device functionality 504. In some embodiments, the management logic 518 may configure one or more portions of the device memory 506 by receiving configuration information 523 (e.g., from a device such as a host) and providing the configuration information 523 to a memory control device associated with one or more portions of the device functionality 504 that can implement the configuration information. For example, in some embodiments, a device such as a host may allocate one or more portions of the device memory 506 to one or more portions of the device functionality 504. Thus, the configuration information 523 may include a list, table, or other data structure indicating one or more portions of the device functionality 504 and one or more corresponding portions of the device memory 506 that can be configured to be accessed by one or more portions of the device functionality 504. Examples of memory control devices associated with one or more portions of the device functionality 504 may include memory controllers in a processor (e.g., a CPU), memory configuration registers in an FPGA or ASIC, and / or the like. Additionally or alternatively, the management logic 518 may configure one or more portions of the device memory 506 by allocating one or more portions of the device memory 506 to one or more portions of the device functionality 504. In this embodiment, the configuration information 523 may include one or more specifications, requirements, and / or the like for one or more portions of the device functionality 504 such that the management logic 518 can allocate one or more appropriate portions of the device memory 506 to one or more portions of the device functionality 504 based on, for example, one or more types, amounts, access granularities, performance characteristics, and / or the like of the memory. In some embodiments, the management logic 518 may configure the device memory 506 in response to a configuration request 522. In some embodiments, the configuration request 522 may be implemented, for example, by a command received by the management logic 518 (e.g., from a device such as a host). Additionally or alternatively, the device 502 may implement the management logic 518 and / or the configuration request 522 at least in part via a command line interface (CLI). In some embodiments, one or more portions of the device functionality 504 and one or more portions of the device memory 506 may be connected using one or more connections (e.g., the structure or configuration of the connections) that can affect the ability of one or more portions of the device functionality 504 to access one or more portions of the device memory 506. For example, as described above, some portions of the device memory 506 may be located in certain portions of the device functionality 504 (e.g., local memory in an FPGA, ASIC, and / or the like) and may only be accessible by certain portions of the device functionality 504, while other portions of the device memory 506 may have less restrictive access (e.g., global memory may be publicly accessible). Thus, a host or other device may use memory information (e.g., the memory information 316 shown in FIG. 3 and / or the memory information in Table 1) to determine which portions of the device memory 506 can be configured to be accessed by which portions of the device functionality 504. FIG. 6 shows a first exemplary embodiment of a configuration memory command according to an exemplary embodiment of the present disclosure. The configuration memory command 622 shown in FIG. 6 may be used, for example, to implement the configuration request 522 shown in FIG. 5. The configuration memory command 622 shown in FIG. 6 may be sent, for example, to the controller 510 of the device 502 (e.g., by a host) to cause the management logic 518 to configure one or more portions of the device memory 506 to be accessed by one or more portions of the device functionality 504. For illustrative purposes, the configuration memory command 622 shown in FIG. 6 may be described in the context of one or more portions of the device functionality 504 that can be implemented by a computing engine, but the principles can be applied to any other type of device functionality. In some embodiments, the configuration memory command 622 may be implemented, for example, by an NVMe command, a CXL command, and / or the like. The configuration memory command 622 may include configuration information 623 that enables the management logic 518 to configure one or more portions of the device memory 506 to be accessed by one or more portions of the device functionality 504. (In some embodiments, the configuration information 623 may be implemented by a pointer or other reference scheme to access the configuration information.) For example, in some embodiments, the configuration information 623 may include a list, table, or other data structure (or a pointer to a data structure) that may include one or more indications of one or more portions of the device memory 506 that the management logic 518 may configure to be accessed by one or more portions of the device functionality 504 (e.g., based on one or more memory allocations determined by a device such as a host). As another example, in some embodiments, the configuration information 623 may include one or more specifications, requirements, and / or the like for one or more portions of the device functionality 504, such that the management logic 518 can allocate one or more appropriate portions of the device memory 506 to one or more portions of the device functionality 504, for example, based on one or more types, amounts, access granularities, performance characteristics, and / or the like of the memory. Table 2 shows an exemplary embodiment of a data structure that can be used to send (e.g., from a device such as a host) the configuration information 623 to the management logic 518 of the device 502. In some embodiments, Table 2 may be received by the management logic 518 and used to configure one or more portions of the device memory 506 to be accessed by one or more portions of the device functionality 504. For example, Table 2 may be embedded within the configuration memory command 622, referred to by a pointer within the configuration memory command 622, or otherwise conveyed in combination with the configuration memory command 622. In the embodiment shown in Table 2, one or more portions of the device functionality 504 may be implemented by a compute engine as shown in row 1, but the principles may apply to any other type of device functionality. The embodiment shown in Table 2 may use identifiers similar to those used in Table 1 (e.g., Compute Engine ID, Mem ID, Namespace ID, and / or the like). Referring to Table 2, row 1 may indicate a compute engine. Row 2 may indicate a program that may be instantiated, launched, and / or the like to run on the corresponding compute engine. Rows 3, 4, and 5 may respectively indicate a memory (e.g., a memory device), a namespace, and / or an address range that may be configured to be accessed by the corresponding compute engine and / or program. Table 2 For illustrative purposes, the examples shown in Table 2 may provide examples of configuration information that can be used with the examples shown in FIG. 8. For example, row 3 may not include an entry for Mem A for CE3 because Mem A may not be accessible by CE3 in the example shown in FIG. 9. However, the principles are not limited to these or any other implementation details. FIG. 7 shows a second exemplary embodiment of a configuration memory command according to an exemplary embodiment of the present disclosure. The configuration memory command 722 shown in FIG. 7 can be used, for example, to implement the configuration request 522 shown in FIG. 5. The configuration memory command 722 shown in FIG. 7 can be sent, for example, to the controller 510 of the device 502 (e.g., by a host) to cause the management logic 518 to configure one or more portions of the device memory 506 to be accessible by one or more portions of the device functionality 504. For illustrative purposes, the configuration memory command 722 shown in FIG. 7 can be described in the context of one or more portions of the device functionality 504 that can be implemented by a compute engine, but the principles can be applied to any other type of device functionality. In some embodiments, the configuration memory command 722 can be implemented, for example, by an NVMe command, a CXL command, and / or the like. The configuration memory command 722 can include a Memory ID (Mem ID) 724 indicating a portion of the device memory 506 to be configured, and a Compute Engine ID (CEID) 728 indicating a portion of the device functionality 504 by which the memory can be configured to be accessed. Additionally or alternatively, the configuration memory command 722 can include a Namespace ID (NSID) 726 (e.g., a subset of the Namespace ID) indicating a portion of the device memory 506 to be configured. Additionally or alternatively, the configuration memory command 722 can include a Range ID (RID) 727 (e.g., a subset of the Namespace ID) indicating a portion of the device memory 506 to be configured. Additionally or alternatively, the configuration memory command 722 can include a Program ID (Prog ID or PID) 730 indicating a specific program by which the memory can be configured to be accessed (e.g., by running on one of the compute engines indicated by the Prog ID). FIG. 8 shows an embodiment of a device including an exploration mechanism and a management mechanism according to an exemplary embodiment of the present disclosure. The device 802 shown in FIG. 8 may include some elements similar to those shown in FIGS. 1, 2, 3, and / or 5, where the similar elements may have reference numerals ending with similar numbers. However, in the embodiment shown in FIG. 8, the controller 810 may include both exploration logic 814 and management logic 818. Additionally, in the embodiment shown in FIG. 8, one or more connections 832 are shown between one or more portions of the device functionality 804 and one or more portions of the device memory 806. (The one or more connections 832 may also be referred to as a fabric, configuration, or network of connections). The embodiment shown in FIG. 8 may also include a host 801 connected to the device 802 via a communication fabric 803. In some embodiments, the host 801 may send one or more tasks to the device 802, and the device 802 may execute the one or more tasks, for example, using at least one of one or more portions of the device functionality 804. In some embodiments, the host 801 may run one or more applications 805 that may utilize one or more portions of the device functionality 804. The one or more connections 832 may be implemented using a wide variety of different conductors, interconnects, networks, interfaces, protocols, and / or the like. Examples may include using circuit board traces, buffers, line drivers, latches, relays, retimers, switches, multiplexers, and / or demultiplexers, any generation of double data rate (DDR) interfaces (e.g., DDR2, DDR3, DDR4, DDR5, etc.), low power DDR (LPDDR), open memory interface (OMI), common flash interface (CFI), open NAND flash interface (ONFI), PCIe, NVMe, NVMe-oF, CXL, Gen-Z, OpenCAPI, CCIX, AXI, DMA, RDMA, ROCE, AMQP, Ethernet, TCP / IP, FibreChannel, InfiniBand, SATA, SCSI, SAS, iWARP, and / or the like for wired connections. Although device functionality 804, device memory 806, and one or more connections 832 may be shown as separate elements, in some implementations, some or all of these elements may overlap. For example, in an embodiment where at least a portion of device functionality 804 is implemented by an FPGA, at least a portion of at least one device memory (e.g., local memory in the FPGA) and memory interconnects may be included within the FPGA. Additionally, although one or more connections 832 may be shown as a single element, it may include one or more first connections between a first set of components and one or more second connections between a second set of components, where there may be no connection between the first set of components and the second set of components. For example, a first ASIC may include a first processor, a first local device memory, and a first connection between the first processor and the first local device memory, and a second ASIC may include a second processor, a second local device memory, and a second connection between the second processor and the second local device memory. However, there may be no connection between the first ASIC and the second ASIC. In the embodiment shown in FIG. 8, one or more portions of device memory 806 may be used, for example, for any of the operations described above with respect to FIG. 1: storing input data replicated from a host, a storage medium (e.g., one or more portions of a storage medium configured to store a namespace), and / or the like; buffering and / or outputting data for a program running on a computing engine; buffering intermediate data used by a program running on a computing engine; copying output data to a host memory, a storage medium (e.g., one or more portions of a storage medium configured to store a namespace), and / or the like; exchanging data between programs; exchanging data between virtual machines (e.g., running on one or more computing resources); and / or the like. As other examples, one or more portions of device memory 806 shown in FIG. 8 may be used for any number of the following purposes, operations, and / or the like: drive management (e.g., storing metadata and / or looking up metadata for use, such as key-value storage, file system information, cache management, and / or the like); copy buffers (e.g., intermediate buffers for copying data between namespaces), parity buffers (e.g., storing checksums or other data for redundant operations such as redundant array of independent disks (RAID)), temporary buffers (e.g., for one or more application programs that may run, for example, at a host, at a device, and / or the like), command processing, translation, and / or lookup buffers, checksum and / or encryption key buffers, and / or the like. Examples of command processing may include processing NVMe command queues and / or entries (e.g., submission queue (SQ), submission queue entry (SQE), completion queue (CQ), and / or completion queue entry (CQE)). For example, a control memory buffer (CMB) in an NVMe system may be implemented as a PCIe base address register (BAR) in a memory-mapped space that can be accessed (e.g., directly) by a host, and the host may use the CMB for tasks such as placing SQEs in the buffer, enabling the device to place CQEs in the buffer, and / or the like. In some embodiments, device memory may be used for one or more functions of the CMB, such as processing one or more commands at the device. Depending on the implementation details, this may provide improved utility, performance, and / or the like. In an exemplary embodiment of using device memory for encryption keys according to the present disclosure, a host may pre-download a data structure of an encryption key into the device memory (e.g., for a key-per-IO (KPIO) implementation). With this configuration, the host may issue an IO and provide a pointer to an index in the data structure to retrieve the corresponding encryption key for the IO, and the device may use the corresponding encryption key to encrypt and / or decrypt the IO. Depending on the implementation details, placing the encryption key in a buffer in the device memory may protect the key from exposure (e.g., to the host), e.g., because the key may not be part of the IO command. FIG. 9 shows an exemplary embodiment of a device having device memory configured according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 9 may be implemented by or used to implement the embodiments shown in, for example, FIGS. 1, 3, 5, 8, and / or Table 1, in which like elements may have附图 reference numerals ending with like digits. For illustrative purposes, the embodiment shown in FIG. 9 may be described in the context of a device functional unit implemented by a computing engine, but the principles may be applied to any other type of device functionality. Referring to FIG. 9, the device may include device functionality implemented by three computing engines 934 identified as CE1, CE2, and CE3 and device memory implemented by memory devices 936 identified as Mem A, Mem B, and Mem C. Computing engine CE1, computing engine CE2, and memory device Mem A may be included in ASIC 940. Computing engine CE1 and computing engine CE2 may be implemented, for example, by a processor (e.g., an ARM processor), a gate array, a logic device, and / or the like, while computing engine CE3 may be implemented by a CPU. Programs P1 and P2 may be instantiated, loaded, launched, and / or the like on CE1. Programs P4 and P5 may be instantiated, loaded, launched, and / or the like on CE2. Programs P8 and P9 may be instantiated, loaded, launched, and / or the like on CE3. Memory device Mem A and memory device Mem B may be implemented by volatile memory (e.g., DRAM), while memory device Mem C may be implemented by persistent memory. Some or all of memory device Mem A may be subdivided (e.g., configured as) into namespace NS100, namespace NS101, and / or namespace NS102, and the namespaces may be further subdivided into range Range 1 and range Range 2. Some or all of memory device Mem B may be subdivided (e.g., configured as) into namespace NS200, namespace NS201, and / or namespace NS202, and the namespaces may be further subdivided into range Range 1 and range Range 2. Some or all of memory device Mem C may be subdivided (e.g., configured as) into namespace NS300, namespace NS301, and / or namespace NS302, and the namespaces may be further subdivided into range Range 1 and range Range 2. The number, type, characteristics, and / or the like of memory devices 936 shown in FIG. 9 are for illustrative purposes, and in other embodiments, memory devices with any other number, type, characteristics, and / or the like may be used. Connection structure 932 may include connections between computing engines 934 and memory devices 936. Specifically, Mem A may be connected to CE1 and CE2 by connections 932-1 and 932-2, respectively. Mem B may be connected to CE1, CE2, and CE3 by connections 932-3, 932-4, and 932-5, respectively. Mem C may be connected to CE1, CE2, and CE3 by connections 932-6, 932-7, and 932-8, respectively. Since CE3 is outside ASIC 940, there may be no connection between CE3 and Mem A. Therefore, CE1 and / or CE2 may be able to access Mem A, Mem B, and / or Mem C, while CE3 may be able to access Mem A and / or Mem B, but not Mem C. In the exemplary embodiment shown in FIG. 9, the following set 942 of indicated memory resources may be configured (e.g., by management logic 518 in FIG. 5 and / or management logic 818 in FIG. 8) to be accessed by program P1 (as shown, for example, in Table 1): Range 1 and Range 2 of NS101 in Mem A, Range 1 and Range 2 of NS200 in Mem B, and / or Range 1 and Range 2 of NS302 in Mem C. Thus, P1 may use any one of the memory resources in set 942 for program execution. In contrast, program P8 may not be able to access the memory resources in Mem A for program execution. In some embodiments, and depending on implementation details, a device having device memory and / or device functionality according to an exemplary embodiment of the present disclosure may implement any number of the following features and / or provide any number of the following benefits. The device memory (e.g., memory local to the device) may be used to access device functionality (e.g., one or more compute storage engines). One or more portions of the device memory may be subdivided into one or more namespaces, where a namespace may provide a virtual representation of one or more portions of the device memory. A device such as a host may be made aware of one or more portions of the device memory and / or one or more portions of the device functionality that may be able to access one or more portions of the device memory, e.g., using a discovery mechanism. In some embodiments, one or more portions of the device memory may be partitioned into one or more groups (e.g., based on different memory characteristics). The device may implement a discovery mechanism that may enable the device to provide (e.g., to the host) information (memory information) about which group or groups of memory a portion of the device functionality (e.g., a compute engine) may be able to access. One or more portions of the device functionality (e.g., a compute engine) may be able to access one or more groups of memory, storage, and / or the like. One or more portions of the device functionality (e.g., a compute engine) may be able to access one or more sub-portions of one or more groups that the one or more portions of the device functionality may be able to access. A device such as a host may use the memory information to indicate (e.g., using a list, table, or other data structure) that a particular memory resource may be used by a program (e.g., running on a compute engine) for program execution. In some embodiments, and depending on implementation details, a device having device memory and / or device functionality according to an exemplary embodiment of the present disclosure may implement any number of the following features and / or provide any number of the following benefits. Device memory (e.g., local memory within the device) may be used for private access by one or more computing engines and / or logic that may implement device functionality for other types of devices. Device memory (e.g., local memory within the device) may be used for public access within the device, e.g., for public access by one or more (e.g., all) computing engines and / or logic that may implement device functionality for other types of devices. One or more types of memory may be distinguished by characteristics such as volatility, latency, power, and / or the like. Memory may be partitioned into one or more namespaces having access to one or more portions of specific device functionality, e.g., based on access location, which may be managed, for example, by a host. A namespace may be subdivided into one or more subgroups having one or more offsets (e.g., address ranges), which may be configured to be accessed by one or more programs for program execution. One or more of the subgroups may be grouped together to form larger groups, e.g., for managing data streams by a device such as a host. One or more portions of device functionality (e.g., computing engines) may be configured to access one or more memory namespaces and / or range groups. Any number of these features and / or benefits may be provided by a computing storage device according to an exemplary embodiment of the present disclosure. In some embodiments, device memory may be implemented by various types of accessibility. For example, access to some portions of device memory may be restricted to specific portions of device functionality, while other portions of device memory may be accessed by any portion of device functionality. Thus, in some implementations, a memory management mechanism may configure some portions of device functionality and / or some portions of device memory for overlapping access. Additionally or alternatively, the memory management mechanism may configure one or more portions of device memory for various types of accessibility. In some embodiments, a memory management mechanism may use memory namespaces to configure one or more portions of device memory. In some embodiments, a memory namespace may refer to a logical representation of one or more portions of device memory. Thus, in some embodiments, a memory namespace may be implemented as a collection of one or more portions of device memory. Depending on implementation details, a memory namespace may or may not include overlapping portions of memory. In some embodiments, one or more commands may be attached to one or more namespaces. FIG. 10 shows an embodiment of a system including a computing device having computing resources and program resources according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 10 may include a host 1001 and a computing device 1002 connected by a communication network fabric 1003. The computing device 1002 may include a device controller 1010, a program repository 1009, a device memory 1006, one or more computational resources 1008 (which may also be referred to as compute resources), and / or device functional circuitry 1004. The device controller 1010 may control the overall operation of the computing device 1002 including any of the operations, features, and / or the like described herein. For example, in some embodiments, the device controller 1010 may parse, process, and invoke commands received from the host 1001 and / or the like. The device functional circuitry 1004 may include any hardware that implements the main functions of the computing device 1002. For example, if the computing device 1002 is implemented as a storage device, the device functional circuitry 1004 may include storage media such as one or more flash memory devices, a flash translation layer (FTL), and / or the like. In some embodiments, the computational storage device may be implemented as a computational storage drive (CSD), a computational storage processor (CSP), and / or a computational storage array (CSA). As another example, if the computing device 1002 is implemented as a network interface card (NIC), the device functional circuitry 1004 may include one or more modems, network interfaces, a physical layer (PHY), a media access control layer (MAC), and / or the like. As another example, if the computing device 1002 is implemented as an accelerator, the device functional circuitry 1004 may include one or more computational resources such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an embedded processor, and / or the like. The host 1001 may be implemented by any component or combination of components that can utilize the computational resources 1008 of the computing device 1002. For example, the host 1001 may include one or more of a client device, a server, a storage node, a central processing unit (CPU), a personal computer, a tablet computer, a smart phone, and / or the like. Additionally, the embodiment shown in FIG. 10 may include any number of hosts. The communication mesh architecture 1003 can be implemented using any type of interface and / or protocol via one or more interconnects, one or more networks, a network in the network (e.g., the Internet), and / or the like or a combination thereof. For example, the mesh architecture 1003 can be implemented by PCIe, NVMe, NVMe-oF, CXL, Gen-Z, OpenCAPI, CCIX, AXI, DMA, RDMA, ROCE, AMQP, Ethernet, TCP / IP, FibreChannel, InfiniBand, SATA, SCSI, SAS, iWARP, and / or the like or any combination thereof. For example, in an embodiment where the computing device 1002 is implemented as a storage device, the controller 1010 can implement storage protocols such as NVMe, CXL, and / or the like, which can enable the host 1001 and the computing device 1002 to exchange commands, data, and / or the like via the communication mesh architecture 1003. In some embodiments, the communication mesh architecture 1003 can include one or more switches, hubs, nodes, routers, and / or the like. In some embodiments, one or more of the computing engines 1011 can include one or more processing resources, such as CPLDs, FPGAs (illustrated as computing engine 1011a), ASICs (illustrated as computing engine 1011b), CPUs (e.g., CISC, RISC, and / or the like, or their cores, illustrated as computing engine 1011c), GP DP NPU TP, and / or the like, and the one or more processing resources can execute instructions stored in any type of memory and / or implement any type of execution environment, such as containers, virtual machines, operating systems such as Linux, extended Berkeley packet filter (eBPF) environments, and / or the like, or a combination thereof. In some embodiments, the computing engine can include combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, and / or the like. In some embodiments, some or all of the computing resources can be implemented as a system-on-chip (SOC). The program repository 1009 can include one or more program slots for storing one or more executable computing device programs 1007. In some embodiments, a computing device program (which can also be referred to as a computing program, computational program, or depending on the context, a program) can refer to any type of program that can be executed by one or more computing resources of a computing device, such as algorithms, data movement, data management, data selection, filtering, encryption and / or decryption, compression and / or decompression, checksum calculation, hash value calculation, cyclic redundancy check (CRC), and / or the like. In some embodiments, a computing device program can refer to a program that is intended to be executed by, suitable for execution by, and / or the like a computing device. In some embodiments, a computing engine can refer to a component or combination of components that can execute one or more computing device programs. One or more programs 1007 may be executed, for example, using one or more of the computing engines 1011 in the computing resources 1008. In some embodiments, the device memory 1006 may be used by one or more of the programs 1007 when executed in conjunction with one or more of the computing engines 1011. For example, the device memory 1006 may be used to hold input data, output data, intermediate data, and / or the like for one or more of the programs 1007. In some embodiments, contexts, and / or the like, the programs 1007 may be referred to as functions. In some embodiments, the host 1001 may offload one or more tasks to a computing device 1002 that can execute the one or more tasks, for example, using one or more of the programs 1007 that can be executed by the computing resources 1008. For example, the host 1001 may run one or more application programs 1005 that can utilize one or more of the programs 1007 and / or the computing engines 1011 of the computing device 1002. In some embodiments, one or more of the computing engines may provide a full or partial (e.g., hybrid) hardware implementation of one or more of the programs 1007. For example, in some embodiments, one or more of the computing engines 1011 may include combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more CPLDs, FPGAs, ASICs, and / or combinations thereof configured to process bitstreams for the programs 1007, which may be implemented, for example, as soft FPGA functions. FIG. 11 illustrates an embodiment of a system including a computing device having loadable program resources according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 11 may include some elements similar to those shown in FIG. 10, where similar elements may have reference numerals ending with similar digits. Referring to FIG. 11, in the computing device 1102, one or more of the computing resources 1108 may be configured to access one or more computing namespaces 1144 and / or use one or more computing namespaces 1144, which are identified as Compute Namespace A (CN A or CNS A), Compute Namespace B (CN B or CNS B), Compute Namespace C (CN C or CNS C), and / or Compute Namespace D (CN D or CNS D). One or more in the compute namespace 1144 can be configured to use compute resources 1150 (identified as CR A, CR B, CR C, and / or CR D) that can be mapped from the compute resources 1108 to the compute namespace 1144. For example, as shown by the arrows in FIG. 11, Compute Namespace A can be configured to use two CPU cores, Compute Namespace B can be configured to use one CPU core and one FPGA, Compute Namespace C can be configured to use one CPU core, and Compute Namespace D can be configured to use one ASIC. In some embodiments, the utilization of one or more of the compute resources 1108 may not be exclusive to a compute namespace. For example, resources (e.g., FPGA, ASIC, CPU core, and / or the like) mapped to a first compute namespace can be reused (e.g., mapped) to another compute namespace. The computing device 1102 can include a program repository 1109 having one or more program slots for storing programs 1107 identified as Program 1, Program 2, Program 3, Program 4, and / or Program 5, and the programs 1107 can be executed, for example, by one or more of the compute resources 1150 mapped to one or more of the compute namespaces 1144. The programs 1107 can be placed in the program repository 1109 using various techniques. As a first example technique (which can be referred to as a built-in technique), the programs 1107 can be built into the program repository 1109 by a vendor (e.g., a manufacturer, a distributor, and / or the like) in the form of an ASIC. As a second example technique (which can be referred to as a preloading technique), the programs 1107 can be preloaded by a vendor into the program repository 1109, for example, when the device 1102 is manufactured, distributed, and / or the like. As a third example (which may be referred to as the download technique), program 1107 may be loaded (e.g., downloaded) into program repository 1109 as part of firmware installation and / or modification. For example, a device vendor may provide firmware content (e.g., firmware image, file, and / or the like) that may include yet another program 1107 (e.g., all or part of program repository 1109 that includes one or more programs 1107). The firmware content may be loaded (e.g., downloaded) into program repository 1109 as part of a manufacturing process, a modification process (e.g., an update process, an upgrade process, and / or the like), a distribution process, and / or the like. In some embodiments, the firmware content may be loaded into device 1102 using a vendor-specific mechanism (including loading one or more programs 1107 into program repository 1109). For example, the firmware content may be loaded into device 1102 using a download firmware command (e.g., an NVMe download firmware command), which may initiate a vendor-specific mechanism for loading the firmware content into device 1102. In some embodiments, this mechanism may load the firmware image of the entire device 1102, and thus, it may be difficult or impossible to determine which part of the firmware image may include one or more programs 1107 for program repository 1109. Thus, a user of computing resources 1108 of device 1102 (e.g., a host, an application, a process, a service, and / or the like) may not be able to load program 1107 into program repository 1109 using any of the first (built-in) example techniques, the second (pre-loaded) example techniques, and / or the third (download) example techniques described above. In some embodiments, the vendor-specific mechanism for loading the program may decode the encrypted firmware package into device firmware and / or one or more computing programs for device 1102. A program 1107 loaded into program repository 1109 using any of the first example techniques, the second example techniques, and / or the third example techniques described above may be referred to as a native program (or a fixed program or a pre-loaded program). In some embodiments, using a third (download) technique to load program 1107 into the program repository (e.g., downloading a firmware image, package, and / or the like to device 1102) may provide one or more benefits similar to the second (preload) technique. However, depending on the implementation details, using the third (download) technique may involve placing device 1102 and / or one or more executing programs in a static state (e.g., sleep state or disconnected, turned off, paused, stopped, hibernated, terminated, interrupted, and / or the like). Additionally, depending on the implementation details, using the third (download) technique may involve: (1) restarting one or more virtual machines of an assigned compute namespace; (2) reloading (e.g., downloading) one or more previously downloaded programs 1107; and / or (3) completing, aborting one or more computations and / or the like that may be in progress (e.g., by one or more executing programs 1107). Program repository 1109 may be implemented, for example, as part of device memory 1106 by volatile and / or non-volatile memory and / or by memory that may be at least partially dedicated to program repository 1109. In some embodiments, program repository 1109 may be implemented at least partially virtual rather than physical. For example, one or more portions of program repository 1109 may be implemented as a virtual instantiation across any memory implementation mechanism used by device 1102 (e.g., using any scheme for memory virtualization, paging, mapping, and / or the like). Compute namespace 1144 may include one or more program slots available for storing programs 1152, which may be executed, for example, by mapping to one or more of compute resources 1150 of the corresponding compute namespace 1144. For example, Compute Namespace A may include one or more slots that may store programs Program A1, Program A2... Program An; Compute Namespace B may include one or more slots that may store programs Program B1, Program B2... Program Bn; and so on. In some embodiments, program 1152 may be loaded (e.g., downloaded) into namespace 1144 as shown by arrow 1154 (e.g., by a user of the namespace, such as an application, process, service, and / or the like). The program 1152 loaded (e.g., downloaded) into the compute namespace 1144 and / or stored in the compute namespace 1144 may be referred to as a compute namespace program, a namespace program, or a local program. In some embodiments, the compute namespace program 1152 may be downloaded using a command referred to as a "load program to namespace command" (which may also be referred to as a load_program_to_namespace command or a load local program command). In some embodiments, the load local program instruction may be accessed, for example, using an application programming interface (API). In some embodiments, this API may be implemented, for example, using one or more NVMe commands as part of the architecture of the computing device. Depending on the implementation details, the virtual machine to which the compute namespace is mapped may control the download of the program to the compute namespace. In some embodiments, the compute namespace 1144 may use one or more mapped compute resources 1150 to execute one or more programs 1107 from the program repository 1107 (as shown by arrow 1156) and / or one or more programs 1152 stored locally at the namespace 1144 (as shown by arrow 1158). In some embodiments, the compute namespace 1144 may use one or more portions of the device memory 1106 (e.g., configured as one or more memory namespaces 1148) and / or one or more portions of the storage medium (e.g., implemented as a portion of the device functionality and configured as one or more storage namespaces 1146). In some embodiments, the compute namespace program 1152 may have a scope that may be limited to the compute namespace to which it can be downloaded and / or stored. (This scope may be referred to as a local or private scope.) In some embodiments, the programs 1107 in the program repository 1109 may have a scope that may extend to the following: the entire device 1102 (which may be referred to as the device global scope); a subsystem of the device 1102 (e.g., an NVMe subsystem) (which may be referred to as the subsystem global scope); and / or any other portion of the device 1102. Thus, in some embodiments, the native programs 1107 in the program repository 1109 may have a device global scope (which may also be referred to as device common), a subsystem global scope (which may also be referred to as subsystem common), and / or the like. In some embodiments, one or more native programs may not be overwritten and / or removed, but may be deactivated and / or not used. In some embodiments, one or more native programs may be overwritten (e.g., replaced) by one or more loaded global programs, for example. In some embodiments, to utilize, one or more programs (e.g., native program 1107 and / or local program 1152) may be associated with one or more compute name spaces 1144. An association between the program and the name space may be established, for example, by launching a program within the name space (e.g., native program 1107 and / or local program 1152). In some embodiments, launching the program may cause the program to be scheduled for execution by a device such as a host. In some embodiments, one or more of the operations described herein with respect to FIG. 11 may be implemented, for example, using one or more commands (e.g., NVMe commands in the context of the NVMe framework and / or using the NVMe API), which may be received using communication interface 1112 and / or processed by controller 1110 (which may be implemented at least in part as an NVMe controller). In some embodiments, a compute program framework (e.g., the NVMe framework) may perform a type check on a program 1152 that can be loaded into name space 1144. For example, a user may attempt to load program 1152 into Namespace D. However, if program 1152 indicates (e.g., announces) that the program has a type intended to operate with a CPU, the framework may prohibit (e.g., block) the loading of program 1152 into Namespace D because, in the embodiment shown in FIG. 11, Namespace D may not have a CPU mapped to compute resource CR D, and thus, program 1152 may not be supported by any of the compute engines in compute resource CR D. In some embodiments, one or more program types and / or the like may be implemented and defined by a standard specification. In contrast, in some embodiments, one or more programs 1107 in program repository 1109 may not indicate a program type and / or may not be subject to type checking, for example, because the type of compute resource 1150 that may be mapped to name space 1144 that may attempt to use one or more programs 1107 may not be known (e.g., when one or more programs 1107 are placed in program repository 1109). FIG. 12 shows an embodiment of a system including a computing device capable of loading program resources into a program repository according to an exemplary embodiment of the present disclosure. The embodiment shown in FIG. 12 may include some elements similar to those shown in FIG. 11, where similar elements may have reference numerals ending with similar digits. Referring to FIG. 12, the computing device 1202 can implement a program loading mechanism (which can be referred to as a global program loading mechanism) that enables one or more programs 1207a to be loaded (e.g., downloaded) into the program repository 1209, as shown by arrow 1260. For example, a user (e.g., a host, an application, a process, a service, and / or the like) can use a command called "load program to repository command" (which can also be referred to as a load global program command or a load_program_to_repository command) to load one or more programs 1207a into the program repository 1209. In some embodiments, the load global program instruction can be accessed using an API, for example. In some embodiments, this API can be implemented as part of the architecture of the computing device using one or more NVMe commands, for example. The program 1207a loaded (e.g., downloaded) into the program repository 1209 can be referred to as a loaded program (or a downloaded program or a loaded global program), while the program 1207b placed in the program repository 1209 using any one of the first (built-in) example techniques, the second (pre-loaded) example techniques, and / or the third (downloaded) example techniques described above can be referred to as a native program (or a fixed program or a pre-loaded program). In some embodiments, a particular loaded global program 1207a may not be visible in a particular computing namespace 1244 because the particular computing namespace 1244 may not have a computing engine that supports the particular loaded global program mapped to it (as described above). For example, an FPGA core program may not be visible in a computing namespace that only contains ARM CPU computing resources. In some embodiments, and depending on implementation details, the global program loading mechanism according to the exemplary embodiments of the present disclosure can provide one or more benefits similar to those of using pre-constructed and / or pre-loaded techniques, and / or can reduce or eliminate one or more potential problems associated with the download techniques (e.g., the third example technique) described above. For example, the global program loading mechanism can enable one or more programs to be downloaded into the program repository 1209, for example, to compensate for one or more programs that may not have been included (e.g., pre-loaded) during manufacturing and / or as part of a firmware update. As another example, the global program loading mechanism according to the exemplary embodiments of the present disclosure can enable one or more loaded global programs to be accessed at the device global scope, the subsystem global scope, and / or the like. Therefore, depending on implementation details, a loaded global program can be accessed by more than one computing namespace within the same device, subsystem, and / or the like. As another example, a global program loading mechanism according to an exemplary embodiment of the present disclosure may utilize one or more existing program implementation techniques. For example, loading a global program may be initiated using a startup command, which may be the same as or similar to the startup commands used for native programs, local programs, and / or the like. As yet another example, a loaded global program that has been loaded using a global program loading mechanism according to an exemplary embodiment of the present disclosure may not be subject to type checking. Thus, in some embodiments, and depending on implementation details, a loaded global program 1207a may be loaded (e.g., into a program repository 1209) regardless of whether any computing resources 1208 that may support the loaded global program 1207a to be loaded have been mapped to computing resources 1250 in any computing name space 1244, or even exist among the computing resources 1208. Thus, depending on implementation details, a loaded global program that has been loaded using a global program loading mechanism according to an exemplary embodiment of the present disclosure may appear the same as or similar to a built-in program and / or a pre-loaded program. In addition, a loaded global program that has been loaded using a global program loading mechanism according to an exemplary embodiment of the present disclosure may not indicate (e.g., announce) the program type. Depending on implementation details, this may further enable the loaded global program to avoid one or more type checking operations. This potential benefit may be particularly advantageous, for example, in enabling a customized program to be loaded as a loaded global program without revealing how the customized program may be structured, executed, and / or the like. Additionally, depending on implementation details, a global program loading mechanism according to an exemplary embodiment of the present disclosure may enable and / or support larger sets of usage scenarios and / or programs that may be unloaded to a device. In some embodiments, and depending on implementation details, a program that has been loaded into a program repository 1209 using a global program loading mechanism according to an exemplary embodiment of the present disclosure may behave in the same or similar manner as a program that has been placed in the program repository 1209 using a first (built-in) technique and / or a second (pre-loaded) technique. Thus, the computing name space 1244 may not be able to distinguish between the loaded global program 1207a and the native program 1207b. In some embodiments, a device such as a host may determine one or more programs (e.g., the loaded global program 1207a and / or the native program 1207b) from the program repository 1209 to a computing name space 1244 for startup, mapping, and / or the like. In some embodiments, the global program loading mechanism can enable a program to be loaded into the program repository 1209 without involving a reset at the system, device, subsystem, and / or similar levels. Thus, depending on the implementation details, the global loader 1207a can be loaded into the program repository 1209 without involving the device 1202 and / or one or more executing programs entering a static state, without restarting one or more virtual machines with an assigned computational name space, without reloading (e.g., downloading) one or more previously downloaded programs, and / or without completing or aborting one or more computations and / or the like that may be in progress. In some embodiments, and depending on the implementation details, the global program loading mechanism according to the exemplary embodiments of the present disclosure can implement any number of the following features and / or provide any number of the following benefits. A program can be loaded (e.g., downloaded) into a program repository (e.g., a global repository) using a loader instruction, which can be implemented by administrative privileges. The loader instruction can be implemented to load a program into a program repository with a subsystem-level scope, a device-level scope, and / or the like. The loader command can be implemented without a reset at the system, device, and / or subsystem levels. One or more loader commands can be coordinated by a host, a virtual machine, and / or the like. The contents of the program repository can be explored, for example, using a log page command. The loader can be instantiated in the computational name space, for example, based on starting in the computational name space. A program loaded in the program repository can be presented as the same or similar to a built-in program and / or a preloaded program, depending on the implementation details, which can enable programming to avoid type checking. One or more commands for loading a program into the program repository, exploring the contents of the program repository, starting the program, and / or the like can be implemented using an API to the host, an application, a procedure, a service, and / or the like. Any number of the features and / or benefits disclosed herein can be implemented in the context of a computing storage device. Any of the functionality disclosed herein, including, for example, a controller, exploration logic, management logic, or any other functionality implemented at a host, device, and / or the like, can be implemented by hardware, software, firmware, or any combination thereof, including combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more complex programmable logic devices CPLDs, FPGAs, ASICs, CPUs, GPUs, NPUs, TPUs, and / or the like, which execute instructions stored in any type of memory, or any combination thereof. In some embodiments, one or more components can be implemented as a system-on-chip (SOC). In some embodiments, and depending on the context, the terms logic, circuit, device, and / or the like can be used interchangeably. FIG. 13 shows an exemplary embodiment of a host device according to an exemplary embodiment of the present disclosure. The host device shown in FIG. 13 can be used to implement, for example, any of the hosts disclosed herein. The host device 1300 shown in FIG. 13 may include a processor 1302, which may include a memory controller 1304, a system memory 1306, a host logic 1308, and / or a communication interface 1310. Any or all of the components shown in FIG. 13 may communicate via one or more system buses 1312. In some embodiments, one or more of the components shown in FIG. 13 may be implemented using other components. For example, in some embodiments, the host control logic 1308 may be implemented by a processor 1302 that executes instructions stored in the system memory 1306 or other memory. In some embodiments, the host logic 1308 may implement any of the host functionality disclosed herein, including, for example, running an application, sending commands to a computing device, and / or receiving responses from a computing device, and utilizing device functionality as disclosed herein for the host 1300 and / or the applications running thereon. FIG. 14 shows an exemplary embodiment of a device according to an exemplary embodiment of the present disclosure. The embodiment 1400 shown in FIG. 14 can be used to implement, for example, any of the devices disclosed herein. The device 1400 may include a device controller 1402, one or more computing resources 1408, a device logic 1416, device functional circuitry 1406, and a communication interface 1410. The components shown in FIG. 14 may communicate via one or more device buses 1412. The device logic 1416 may be used, for example, to implement any of the discovery logic, management logic, program download mechanism, and / or the like disclosed herein. The device functional circuitry 1406 may include any hardware that implements the main functions of the device 1400. For example, if the device 1400 is implemented as a storage device, the device functional circuitry 1406 may include storage media, such as one or more flash memory devices, FTL, and / or the like. As another example, if the device 1400 is implemented as a network interface card (NIC), the device functional circuitry 1406 may include one or more modems, network interfaces, physical layer (PHY), media access control layer (MAC), and / or the like. As another example, if the device 1400 is implemented as an accelerator, the device functional circuitry 1406 may include one or more accelerator circuits, memory circuits, and / or the like. FIG. 15 illustrates an embodiment of a method for providing device memory information according to an exemplary embodiment of the present disclosure. The method may begin at operation 1502. At operation 1504, the method may receive a request for information at a device, where the device may include a device memory and device functional circuitry. For example, the device functional circuitry may include devices for implementing the device as a computing device, a storage device, a communication device, and / or the like as described above with respect to FIGS. 3, 8, and / or 9. At operation 1506, the method may provide the information based on the request, where the information may indicate that at least a portion of the device functional circuitry is capable of accessing at least a portion of the device memory as described above with respect to FIGS. 3, 8, and / or 9. For example, the information may indicate that an FPGA may be capable of accessing memory within the FPGA and / or memory external to the FPGA as described above with respect to FIG. 9. The method may end at operation 1508. FIG. 16 illustrates an embodiment of a method for configuring a device memory according to an exemplary embodiment of the present disclosure. The method may begin at operation 1602. At operation 1604, the method may receive at least one request at a device, where the device may include a device memory and device functional circuitry. For example, the device functional circuitry may include devices for implementing the device as a computing device, a storage device, a communication device, and / or the like as described above with respect to FIGS. 3, 8, and / or 9. At operation 1606, the method may perform a configuration operation based on the at least one request, where the configuration operation may include configuring at least a portion of the device memory to be accessed by at least a portion of the device functional circuitry. For example, the device may configure a portion of the device memory to be accessed by a CPU by receiving configuration information (e.g., from a device such as a host) and providing the configuration information to the memory controller of the CPU as described above with respect to FIG. 5. The method may end at operation 1608. FIG. 17 illustrates an embodiment of a method for loading program resources into a device according to an exemplary embodiment of the present disclosure. The method may begin at operation 1702. At operation 1704, the method may receive a program at a device, where the device may include at least one computing resource. For example, the device may receive a load program 1207a at a program repository 1209, and the device may include at least one computing resource 1208 shown in FIG. 12. At operation 1706, the method may associate the program with a first computing namespace of the at least one computing resource, and at operation 1708, the method may associate the program with a second computing namespace of the at least one computing resource. For example, the first and second namespaces 1244 may be associated with the load program 1207a by starting the load program 1207a with the first and second namespaces 1244 shown in FIG. 12. The method may end at operation 1708. The embodiments shown in FIGS. 13, 14, 15, 16, and / or 17 and all other embodiments described herein are example operations and / or components. In some embodiments, some operations and / or components may be omitted, and / or other operations and / or components may be included. Additionally, in some embodiments, the temporal and / or spatial order of operations and / or components may vary. Although some components and / or operations may be shown as individual components, in some embodiments, some components and / or operations shown separately may be integrated into a single component and / or operation, and / or some components and / or operations shown as a single component and / or operation may be implemented using multiple components and / or operations. Although not limited to any particular application, the principles of the present invention related to the management of device memory and / or programs as used with a compute storage may be particularly beneficial, where the compute storage may be implemented, for example, with NVMe. In the case of adding compute resources available within a device, one or more compute operations may be offloaded from a host to the device in which data for one or more computations may reside. Depending on implementation details, a device according to an exemplary embodiment of the present disclosure may provide one or more benefits over a model: data may be fetched, for example, from a storage medium or network resource into host memory and then the CPU may be allowed to run compute operations on the fetched data (e.g., count zip codes that may have a tendency to virus infection). This method may become, for example, this is because data may be transferred across a mesh architecture (e.g., a directly attached PCIe bus and / or network mesh that may increase latency). Additionally, if multiple such configurations are meshed, the total throughput may be lower per device than the total throughput of a single device, for example, this is because the bus may not be able to utilize the total performance provided by one or more devices (e.g., NVMe devices). A compute storage according to an exemplary embodiment of the present disclosure may enable one or more compute operations to be performed at or near the storage, which may reduce transfer latency depending on implementation details. Additionally, in contrast to source data that may be substantially larger in some use cases, only the results may be replicated. The inventive principles of the present disclosure may provide one or more benefits, for example, when used with a compute storage device that may implement compute resources by an embedded CPU, a dedicated ASIC, an FPGA, a GPU, and / or the like. Some of the embodiments disclosed above have been described in the context of various implementation details, but the principles of this disclosure are not limited to these or any other specific details. For example, some functionality has been described as being implemented by certain components, but in other embodiments, the functionality may be distributed among different systems and components at different locations and have various user interfaces. Certain embodiments have been described as having specific processes, operations, etc., but such terms also encompass embodiments in which the specific processes, operations, etc. may be implemented by multiple processes, operations, etc. or in which multiple processes, operations, etc. may be integrated into a single process, step, etc. A reference to a component or element may refer only to a part of the component or element. For example, a reference to a block may refer to the entire block or one or more sub-blocks. In this disclosure and the claims, the use of terms such as "first" and "second" may be for the sole purpose of differentiating the modified elements and may not indicate any spatial or temporal order unless otherwise apparent from the context. In some embodiments, a reference to an element may refer to at least a part of the element, e.g., "based on" may mean "at least partially based on" and / or the like. A reference to a first element may not imply the existence of a second element. The principles disclosed herein have independent utility and may be implemented alone, and not every embodiment may utilize every principle. However, the principles may also be implemented in various combinations, some of which may amplify the benefits of the individual principles in a collaborative manner. The various details and embodiments described above may be combined to produce additional embodiments in accordance with the inventive principles of this patent disclosure. Since the configuration and details of the inventive principles of this patent disclosure may be modified without departing from the concept of the invention, such changes and modifications are considered to fall within the scope of the following claims. 102, 202, 302, 502, 802, 1400: Device 104: Device functional equipment 106, 206, 306, 506, 806, 1006, 1106: Device memory 110, 310, 510, 810, 1110: Controller 112, 1112, 1310, 1410: Communication interface 207, 1107, 1152, P1, P2, P4, P5, P8, P9: Program 211, 934, 1011, CE1, CE2, CE3: Computing engine 213: Storage medium 244, 1144, 1244: Computing namespace 246, 1146: Storage namespace 248, 1148: Memory namespace 304, 504, 804: Device functionality 314, 814: Discovery logic 315: Memory information request 316: Memory information 418: Discovery device memory command 420: Data location 518, 818: Management logic 522: Configuration request 523, 623: Configuration information 622, 722: Configuration memory command 724: Memory ID 726: Namespace ID 727: Range ID 728: Computing engine identifier 730: Program identifier 832, 932-1, 932-2, 932-3, 932-4, 932-5, 932-6, 932-7, 932-8: Connection 801, 1001: Host 803, 1003: Communication network 805, 1005: Application 932: Connection structure 936, Mem A, Mem B, Mem C: Memory device 940, 1011b: ASIC 942: Set 1002, 1102, 1202: Computing device 1004, 1406: Device functional circuit 1007: Computing device program 1008, 1108, 1150, 1208, 1250, 1408, CR A, CR B, CR C, CR D: Computing resource 1009, 1109, 1209: Program repository 1010, 1402: Device controller 1011a: FPGA 1011c: CPU core 1154, 1156, 1158, 1260: Arrow 1207a: Load global program 1207b: Native program 1300: Host device 1302: Processor 1304: Memory controller 1306: System memory 1308: Host logic 1312: System bus 1412: Device bus 1416: Device logic 1502, 1504, 1506, 1508, 1602, 1604, 1606, 1608, 1702, 1704, 1706, 1708: OperationNS100, NS101, NS102, NS200, NS201, NS202, NS300, NS301, NS302: Name Spaces Range 1, Range 2: Ranges Throughout the figures, for purposes of illustration, the figures are not necessarily drawn to scale and elements of similar structure or function may generally be represented by like reference numerals or portions thereof. The figures are only intended to facilitate the description of the various embodiments described herein. The figures do not depict every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the figures from becoming cluttered, not all components, connections, and the like may be shown, and not all components may have reference numerals. However, the pattern of the component configuration may be apparent from the figures. The accompanying figures, together with the specification, illustrate exemplary embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. FIG. 1 illustrates an embodiment of a device having a device memory according to an exemplary embodiment of the present disclosure. FIG. 2 illustrates an embodiment of a computing storage device having a namespace according to an exemplary embodiment of the present disclosure. FIG. 3 illustrates an embodiment of a device including a discovery mechanism according to an exemplary embodiment of the present disclosure. FIG. 4 illustrates an exemplary embodiment of a discovery device memory command according to an exemplary embodiment of the present disclosure. FIG. 5 illustrates an embodiment of a device including a management mechanism according to an exemplary embodiment of the present disclosure. FIG. 6 illustrates a first exemplary embodiment of a configure memory command according to an exemplary embodiment of the present disclosure. FIG. 7 illustrates a second exemplary embodiment of a configure memory command according to an exemplary embodiment of the present disclosure. FIG. 8 illustrates an embodiment of a device including a discovery mechanism and a management mechanism according to an exemplary embodiment of the present disclosure. FIG. 9 illustrates an exemplary embodiment of a device having a device memory configured according to an exemplary embodiment of the present disclosure. FIG. 10 illustrates an embodiment of a system including a computing device having computing resources and program resources according to an exemplary embodiment of the present disclosure. FIG. 11 illustrates an embodiment of a system including a computing device having loadable program resources according to an exemplary embodiment of the present disclosure. FIG. 12 illustrates an embodiment of a system including a computing device capable of loading program resources into a program repository according to an exemplary embodiment of the present disclosure. FIG. 13 illustrates an exemplary embodiment of a host device according to an exemplary embodiment of the present disclosure. FIG. 14 illustrates an exemplary embodiment of a device according to an exemplary embodiment of the present disclosure. FIG. 15 illustrates an embodiment of a method for providing device memory information according to an exemplary embodiment of the present disclosure. FIG. 16 illustrates an embodiment of a method for configuring a device memory according to an exemplary embodiment of the present disclosure. FIG. 17 illustrates an embodiment of a method for loading program resources into a device according to an exemplary embodiment of the present disclosure. 502: Device 504: Device functionality 506: Device memory 510: Controller 518: Management logic 522: Configuration request 523: Configuration information

Claims

1. An apparatus for managing device memory, the apparatus comprising: The device memory; And device functional circuitry, wherein at least a portion of the device functional circuitry is capable of accessing at least a portion of the device memory via a connection structure; And control circuitry configured to provide information about the device memory in response to a request sent from the host to the control circuitry to obtain the information, wherein the information indicates that at least a portion of the device functional circuitry is capable of accessing at least a portion of the device memory.

2. The apparatus as claimed in claim 1, wherein the information further indicates the characteristics of the at least portion of the apparatus memory.

3. The apparatus as claimed in claim 1 further includes a communication interface, wherein the control circuitry is configured to provide the information using the communication interface.

4. The apparatus of claim 3, wherein the control circuitry is configured to: receive a request using the communication interface; and provide the information based on the request.

5. The apparatus of claim 1, wherein the portion of the device memory is a first portion of the device memory, and wherein the information indicates that at least a portion of the device functional circuitry is capable of accessing a second portion of the device memory.

6. The apparatus of claim 1, wherein the portion of the device functional circuit is a first portion of the device functional circuit, and wherein the information indicates that a second portion of the device functional circuit is capable of accessing the at least portion of the device memory.

7. The apparatus as claimed in claim 1, wherein: A first portion of the at least part of the device's functional circuitry is configured as a first namespace; And the second portion of the at least part of the device memory is configured as a second namespace.

8. An apparatus for managing device memory, the apparatus comprising: The device memory; And device functional circuitry, wherein at least a portion of the device functional circuitry is capable of accessing at least a portion of the device memory via a connection structure; and control circuitry configured to: receive at least one request sent from the host to the control circuitry for configuration operations; And perform the configuration operation based on the at least one request, wherein the configuration operation includes configuring the at least a portion of the device memory for access by the at least a portion of the device functional circuitry.

9. The apparatus as claimed in claim 8, wherein the configuration operation includes: Receive configuration information; And to provide the configuration information to a memory control device associated with at least a portion of the device's functional circuitry.

10. The apparatus of claim 8, wherein the configuration operation includes allocating at least a portion of the apparatus memory to at least a portion of the apparatus functional circuitry.

11. The apparatus of claim 8 further includes a communication interface, wherein the control circuitry is configured to receive the request using the communication interface.

12. The apparatus of claim 8, wherein the portion of the device memory is a first portion of the device memory, and wherein the control circuitry is configured to configure a second portion of the device memory for access by the at least one portion of the device functional circuitry based on the at least one request.

13. The apparatus of claim 8, wherein the portion of the apparatus functional circuitry is a first portion of the apparatus functional circuitry, and wherein the control circuitry is configured to configure the at least one portion of the apparatus memory to be accessed by a second portion of the apparatus functional circuitry based on the at least one request.

14. The apparatus as claimed in claim 8, wherein: A first portion of the at least part of the device's functional circuitry is configured as a first namespace; And the second portion of the at least part of the device memory is configured as a second namespace.

15. The apparatus of claim 8, wherein the portion of the apparatus functional circuitry comprises: Computing engine; And the program, configured to use the computing engine.

16. An apparatus for managing device memory, the apparatus comprising: At least one computing resource; Device memory, configured as one or more memory namespaces; And control circuitry, configured to: receive a first program and a second program different from the first program; map a first computing namespace to the at least one computing resource; And mapping a second computing namespace, different from the first computing namespace, to the at least one computing resource, wherein the at least one computing resource executes the first program and the second program, and wherein at least one of the first computing namespace or the second computing namespace uses the one or more memory namespaces.

17. The apparatus of claim 16 further includes a communication interface, wherein the control circuitry is configured to use the communication interface to receive one of the first program and the second program.

18. The apparatus of claim 17, wherein the control circuitry is configured to use the communication interface to provide information about one of the first program and the second program.

19. The apparatus of claim 16, wherein the control circuitry is configured to: configure at least a first portion of the at least one computing resource as the first computing namespace; and configure at least a second portion of the at least one computing resource as the second computing namespace.

20. The apparatus of claim 16, wherein the control circuitry is configured to: receive a command; and receive one of a first program and a second program based on the command.

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