Semiconductor device and method of forming EMI shielding material in two-step process to avoid contaminating electrical connector

Abstract

This invention discloses a semiconductor device having a substrate and an encapsulant deposited on the substrate. An electrical connector is disposed on the substrate outside the encapsulant. An antenna can be formed on the substrate. A first shielding material is disposed on a portion of the encapsulant, but does not cover the electrical connector. The first shielding material is disposed on the portion of the encapsulant and the portion of the substrate using a direct-jet printer. A cover is disposed on the electrical connector. A second shielding material is disposed on the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps with the first shielding material and covers the side surfaces of the encapsulant and the substrate. The cover is removed to expose the electrical connector without shielding material.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device and method for forming electromagnetic interference (EMI) shielding material in a two-step process to prevent contamination of electrical connectors. Prior Art

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, generating photoelectric effects, and generating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also used in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices, particularly in high-frequency applications such as radio frequency (RF) wireless communications, often contain one or more integrated passive devices (IPDs) to perform the necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a system-in-package (SiP) module to achieve higher density and expanded electrical functionality in a small space. In a SIP module, the semiconductor die and IPD are placed on a substrate for structural support and electrical interconnection. An encapsulant is deposited over the semiconductor die, IPD, and substrate. Electrical connectors are placed on the substrate to enable electrical communication between the electrical components and external devices. SIP modules are partially molded because the encapsulant does not extend to the electrical connectors. The electrical connectors are independent of the substrate.

[0004] SIP modules contain high-speed digital and RF electronic components that are highly integrated to achieve a small size and low profile, and operate at high clock frequencies. Electromagnetic shielding material is typically conformally applied over the encapsulant. The shielding layer reduces or suppresses electromagnetic interference (EMI), radio frequency interference (RFI), and other inter-device interference (e.g., such as that radiated by high-speed digital devices) from affecting adjacent devices within or adjacent to the SIP module.

[0005] However, it is important that electrical connectors remain free of spurious shielding material to avoid malfunctions. Conformal application of EMI shielding materials is difficult to control for partially molded devices, especially for stand-alone electrical connectors. Conformal shielding materials can easily intrude into the space surrounding the electrical connector and penetrate into the connector's contacts, causing electrical shorts or discontinuities when attempting to mate the connector. Attempts have been made to mask or tape off the electrical connectors while forming the shielding material. In some applications, due to the close component spacing, masks and tapes cannot reliably isolate the electrical connectors and may damage the connectors. Summary of the Invention

[0006] In one aspect, the present invention discloses a semiconductor device comprising a substrate, an encapsulant, an electrical connector, a first shielding material, a cover, and a second shielding material. The encapsulant is deposited over a first surface of the substrate. The electrical connector is disposed above the first surface of the substrate outside the encapsulant. The first shielding material is disposed over a portion of the encapsulant, without covering the electrical connector with the first shielding material. The cover is disposed over the electrical connector. The second shielding material is disposed over the encapsulant, wherein the cover prevents the second shielding material from reaching the electrical connector.

[0007] In another aspect, the present invention discloses a semiconductor device comprising a substrate, an electrical connector, a first shielding material, a cover, and a second shielding material. The electrical connector is disposed above the substrate. The first shielding material is disposed above a portion of the substrate and spaced apart from the electrical connector. The cover is disposed above the electrical connector. The second shielding material is disposed above the substrate, wherein the cover prevents the second shielding material from reaching the electrical connector.

[0008] In another embodiment, the present invention discloses a method for manufacturing a semiconductor device, comprising providing a substrate; disposing an electrical connector above a first surface of the substrate; disposing a first shielding material above a portion of the substrate and spaced a distance from the electrical connector; disposing a cover above the electrical connector; and disposing a second shielding material above the substrate, wherein the cover prevents the second shielding material from reaching the electrical connector. Simple diagram description

[0009] [FIG. 1a] to [FIG. 1c] illustrate a semiconductor wafer having a plurality of semiconductor dies separated by scribe lines; [Figure 2a] to [Figure 2d] illustrate the process of forming a SiP module; [Figures 3a] to [Figure 3d] illustrate the process of forming an AoP module; [Figure 4] illustrates the combination of a SIP module as a wafer and an RF antenna substrate; [Figures 5a] to [Figure 5h] illustrate applying shielding material to an AoP module using a two-step process; [Figures 6a] to [Figure 6c] illustrate the use of a two-step process to alternately apply shielding materials to the AoP module; [Figures 7a] to [Figure 7d] illustrate the use of a two-step process to alternately apply shielding materials to the AoP module; [Figures 8a] to [Figure 8d] illustrate the use of a two-step process to alternately apply shielding materials to the AoP module; [Figure 9] illustrates the two-step shielding material on the AoP module of Figure 4; and [Figure 10] illustrates a printed circuit board (PCB) with different types of packages arranged on the surface of the PCB. Implementation Method

[0010] In the following description, the present invention is described in one or more embodiments with reference to the accompanying drawings, in which like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for carrying out the objectives of the present invention, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents as can be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word and, therefore, can refer to both a single semiconductor device and a plurality of semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end-of-line (FOL) and back-end-of-line (BOL). FOL involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, establish the relationship between voltage and current necessary for the circuit to function.

[0012] Back-end manufacturing involves dicing or singulating the finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and broken along non-functional areas of the wafer, called saw streets or scribes. Wafer singulation is performed using a laser dicing tool or saw blade. After singulation, the individual semiconductor dies are placed on a packaging substrate, which contains pins or contact pads for interconnection with other system components. Contact pads formed above the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made using a conductive layer, bumps, stud bumps, conductive paste, or wire bonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, making the semiconductor device functionality available to other system components.

[0013] FIG1a shows a semiconductor wafer 100 having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on wafer 100, separated by inactive inter-die wafer regions or scribe lines 106. Scribe lines 106 provide dicing areas for singulating semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm).

[0014] Figure 1b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110. The active surface contains analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry can include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), memory, or other signal processing circuitry. Semiconductor die 104 may also contain integrated passive devices (IPDs) such as inductors, capacitors, and resistors for radio frequency (RF) signal processing.

[0015] Conductive layer 112 is formed over active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 serves as a contact pad electrically connected to the circuitry on active surface 110.

[0016] Conductive bump material is deposited over the conductive layer 112 using evaporation, electrolytic plating, electroless plating, shot drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, plumbum (Pb), bismuth (Bi), Cu, solder, or a combination of two or more thereof, optionally with a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over an underbump metallization (UBM) having a wetting layer, a barrier layer, and an adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. Bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. The interconnect structure can also use bonding wires, conductive paste, stub bumps, micro bumps, or other electrical interconnects.

[0017] 1c, a saw blade or laser cutting tool 118 is used to singulate the semiconductor wafer 100 through the scribe lines 106 into individual semiconductor dies 104. After singulation, the individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or units (KGD / KGU).

[0018] Figures 2a through 2d illustrate the process of disposing electrical components and connectors above an interconnect substrate. Figure 2a shows a cross-sectional view of an interconnect substrate 120 including a conductor layer 122 and an insulating layer 124. Conductor layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer can be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductor layer 122 provides horizontal electrical interconnects across substrate 120 and vertical electrical interconnects between top surface 126 and bottom surface 128 of substrate 120. Depending on the design and function of semiconductor die 104 and other electrical components, portions of conductor layer 122 can be electrically shared or electrically isolated. Insulating layer 124 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 124 provides isolation between conductive layers 122. Multiple conductive layers, such as conductive layer 122, can exist, separated by insulating layer 124.

[0019] In FIG2b , a plurality of electrical components 130a through 130d are disposed on surface 126 of interconnect substrate 120 and electrically and mechanically connected to conductive layer 122. Electrical components 130a through 130d are each positioned over substrate 120 using a pick-and-place operation. For example, electrical components 130a and 130c can be similar to semiconductor die 104 of FIG1c , with active surface 110 and bumps 114 positioned toward surface 126 of substrate 120. Electrical components 130b and 130d can be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors, with terminals 132 disposed on surface 126 of interconnect substrate 120 and electrically and mechanically connected to conductive layer 122. Alternatively, electrical components 130a through 130d can comprise other semiconductor dies, semiconductor packages, surface-mount devices, discrete electrical devices, or IPDs.

[0020] Electrical components 130a through 130d are brought into contact with surface 126 of substrate 120. FIG2c illustrates electrical components 130a through 130d electrically and mechanically connected to conductive layer 122 of substrate 120. Electrical connectors 134 and 136 are disposed on surface 126 of interconnect substrate 120 and electrically and mechanically connected to conductive layer 122 via bumps or conductive paste 138. Electrical connector 134 is electrically connected to electrical components 130a through conductive layer 122 of substrate 120. Electrical connector 136 is electrically connected to electrical components 130c through conductive layer 122 of substrate 120. In one embodiment, connectors 134 and 136 are board-to-board (B2B) connectors.

[0021] In FIG2 d , encapsulant or molding compound 140 is deposited over and around electrical components 130 a - 130 b and substrate 120 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable application equipment. Encapsulant 140 is also deposited over and around electrical components 130 c - 130 d. Encapsulant 140 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with a suitable filler. Encapsulant 140 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0022] Conductive bump material is deposited over the conductive layer 122 on the surface 128 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations of two or more thereof, and optionally a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating it above its melting point to form balls or bumps 144. In one embodiment, the bumps 144 are formed over a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bumps 144 can also be compression bonded or thermocompressed bonded to the conductive layer 122. In one embodiment, the bumps 144 are copper core bumps to improve durability and maintain their height. Bumps 144 represent one type of interconnect structure that can be formed over conductive layer 122. The interconnect structure can also use bonding wires, conductive paste, stub bumps, micro bumps, or other electrical interconnects.

[0023] As shown in FIG. 2 d , the combination of the electrical components 130 a to 130 d disposed on the substrate 120 and covered by the encapsulant 140 constitutes a system-in-package (SiP) module 148 .

[0024] In another embodiment, as shown in FIG. 3 a , a cross-sectional view of an interconnect substrate 150 is shown, including a conductor layer 152 and an insulating layer 154. Conductor layer 152 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer can be formed using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. Conductor layer 152 provides horizontal electrical interconnects across substrate 150 and vertical electrical interconnects between top and bottom surfaces 156 and 158 of substrate 150. Depending on the design and function of semiconductor die 104 and other electrical components, portions of conductor layer 152 can be electrically shared or isolated. Insulating layer 154 can contain one or more layers of SiO 2 , Si 3 N 4 , SiON, Ta 2 O 5 , Al 2 O 3 , solder resist, prepreg, polyimide, polymer, BCB, PBO, or other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 154 provides isolation between conductive layers 152. There can be multiple conductive layers, such as conductive layer 152, separated by insulating layer 154.

[0025] Conductive layer 160 is formed over surface 158 of substrate 150 and is electrically connected to conductive layer 152. Conductive layer 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0026] Figure 3b is a top view of a conductive layer 160 on surface 158 of an RF antenna interposer substrate 168. Conductive layer 160 comprises an array of islands of conductive material suitable for providing transmission and reception of RF signals, i.e., RF antennas. Conductive layer 160 functions as a plurality of RF antennas 166a and 166b exposed from surface 158 of RF antenna substrate 168. Specifically, an array of islands 162a and 162b of conductive layer 160 is exposed from surface 158 to improve RF transmission and reception performance and quality. In one embodiment, islands 162a of a first group of conductive layers 160 function as first antennas 166a, electrically connected through conductive layer 152 to provide RF transmission and reception for a first electrical component. Island 162b of a second group of conductive layers 160 function as second antennas 166b, electrically connected through conductive layer 152 to provide RF transmission and reception for a second electrical component. Although two RF antennas 166a-166b are shown in FIG. 3a-3b for the purpose of simplifying the description, the RF antenna substrate 168 can have any number of RF antennas, such as the RF antennas 166a-166b.

[0027] In FIG3c , a plurality of electrical components 130a through 130d are disposed on surface 156 of RF antenna substrate 168 and mechanically connected to conductive layer 152. Similar to FIG2b through FIG2c , electrical components 130a through 130d are each positioned above substrate 120 using a pick-and-place operation. Elements with similar functions are designated by the same reference numerals in the figures. Electrical connectors 134 and 136 are disposed on surface 156 of RF antenna substrate 168 and electrically and mechanically connected to conductive layer 152 via bumps or conductive paste 138. Electrical connector 134 is electrically connected to electrical components 130a through conductive layer 152. Electrical connector 136 is electrically connected to electrical components 130c through conductive layer 152.

[0028] In FIG3 d , encapsulant or molding compound 170 is deposited over and around electrical components 130 a and 130 b of interposer 168 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable application equipment. Encapsulant 170 is also deposited over and around electrical components 130 c and 130 d. Encapsulant 170 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with a suitable filler. Encapsulant 170 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0029] 3d, the combination of electrical components 130a to 130d disposed on RF antenna substrate 168 and covered by encapsulant 170 constitutes RF antenna SiP wafer 174. In one embodiment, RF antenna SiP wafer 174 contains millimeter wave devices suitable for 5G cellular networks.

[0030] FIG4 illustrates another embodiment in which the SiP module 148 of FIG2d is disposed on an RF antenna substrate 168, collectively referred to as an antenna-on-package (AoP) wafer 172. Electrical components 130a through 130d are electrically connected to RF antennas 166a through 166b, and electrical connectors 134 and 136, respectively, via interconnect substrate 120 and bumps 144.

[0031] Referring back to FIG3d , a saw blade or laser cutting tool 175 is used to singulate RF antenna SiP wafer 174 into individual RF AoP modules 176a and 176b, as shown in FIG5a . AoP wafer 172 of FIG4 can be singulated into individual RF AoP modules in a similar manner. While the same description applies to RF AoP module 176b and the RF AoP modules from AoP wafer 172 , the following discussion focuses on RF AoP module 176a . As described below, RF AoP module 176a includes an electrical connector 134 , which serves as a B2B connector. This connector (which may contain other electrical components) provides electrical connections to electrical components 130a and 130b, RF antenna substrate 168 , and other PCBs.

[0032] Electrical components 130a-130b can contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs contained within electrical components 130a-130b provide the electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetric Hi-Q resonant transformers, and tuning capacitors. In another embodiment, electrical components 130a-130b contain digital circuits that switch at high frequencies, which could interfere with the operation of the IPDs within RF AOP module 176a.

[0033] To address EMI, RFI, harmonic distortion, and inter-device interference, the RF antenna SiP module 176a will be conformally covered with shielding material. However, the electrical connector 134 must remain shield-free and will need to be covered to protect the connector and avoid introducing shielding material into the connector's contacts.

[0034] In a first step, electromagnetic shielding material 180 is applied over a portion of encapsulant 170 and a portion of surface 156 of substrate 150, as shown in FIG5b. Electromagnetic shielding material 180 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 180 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electrical connector 134 is mechanically and electrically connected to conductive layer 152 of substrate 150 via bumps or conductive paste 138. Electromagnetic shielding material 180 is applied in a maskless manner, for example, by direct jet printing using direct jet printer 181, with sufficient control to prevent shielding material from remaining on electrical connector 134. Shielding material 180 provides partial coverage of RF AoP module 176a without encroaching on the area occupied by electrical connector 134. In one embodiment, the applied shielding material 180 is maintained a distance D separated from the electrical connector 134 by at least 50 micrometers (μm).

[0035] In FIG5c , cover shield 184 is positioned over electrical connector 134. Cover shield 184 is brought into contact with shielding material 180. FIG5d shows cover shield 184 covering or enclosing electrical connector 134, with vertical portion 184a contacting lower surface 180a of shielding material 180. FIG5e is a perspective view of cover shield 184, which encloses electrical connector 134 on all sides in a manner that prevents subsequently applied shielding material from reaching the connector.

[0036] In a second step, as shown in FIG. 5 f , an electromagnetic shielding layer 186 is formed or disposed over surface 188 of encapsulant 170 by conformally applying a shielding material. Electromagnetic shielding material 186 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 186 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electromagnetic shielding material 186 overlaps a first portion of electromagnetic shielding material 180, while a second portion of shielding material 180 remains beneath cover 184. Furthermore, electromagnetic shielding material 186 covers side surfaces 190 of encapsulant 170 and side surfaces 192 of substrate 150. At least to some extent, electromagnetic shielding material 186 covers cover shroud 184, which protects electrical connector 134. During this second step, the electrical connector 134 remains free of shielding material.

[0037] In FIG5g , cover mask 184 is removed, leaving shielding material 180 and shielding material 186 covering the RF-sensitive portion of RF AoP module 176a. Electrical connector 134 remains free of shielding material 180 and shielding material 186. FIG5h shows RF AoP module 176a with shielding material 180 and shielding material 186 covering the RF-sensitive portion of the RF AoP module, and no shielding material on electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or for devices that are incompatible with EMI shielding using a cover-and-shroud approach.

[0038] In another embodiment, continuing from FIG. 5 b , a cover shield 184 is positioned over the electrical connector 134, as shown in FIG. 6 a . The cover shield 184 covers or encloses the electrical connector 134, with vertical portions 184 a contacting the upper surface 180 b of the shielding material 180. The cover shield 184 covers or encloses the electrical connector 134 on all sides, similar to FIG. 5 e , in a manner that prevents subsequently applied shielding material from reaching the connector.

[0039] In an alternative second step, as shown in FIG6b , electromagnetic shielding layer 190 is formed or disposed over surface 193 of encapsulant 170 by conformally applying a shielding material. Electromagnetic shielding material 190 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 190 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electromagnetic shielding material 190 overlaps a first portion of electromagnetic shielding material 180, while a second portion of shielding material 180 remains beneath cover 184. Furthermore, electromagnetic shielding material 190 covers side surfaces 194 of encapsulant 170 and side surfaces 196 of substrate 150. At least to some extent, electromagnetic shielding material 190 covers cover shroud 184, which protects electrical connector 134. During this alternative second step, the electrical connector 134 remains free of shielding material.

[0040] In FIG6c , cover mask 184 is removed, leaving shielding material 180 and shielding material 190 covering the RF-sensitive portion of RF AoP module 176a. Electrical connector 134 remains free of shielding material 180 and shielding material 190. RF AoP module 176a, with shielding material 180 and shielding material 190 covering the RF-sensitive portion of the RF AoP module, and no shielding material on electrical connector 134, is similar to FIG5h . The two-step shielding process described above is suitable for devices with strict design rules or for devices that are incompatible with EMI shielding using a cover-and-shroud approach.

[0041] In another embodiment, continuing from FIG5a , a cover shield 184 is disposed over the electrical connector 134, as shown in FIG7a . The cover shield 184 covers or encloses the electrical connector 134, with vertical portions 184a contacting the surface 156 of the substrate 150. The cover shield 184 covers or encloses the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding material from reaching the connector, similar to FIG5e .

[0042] In a first step, as shown in FIG7 b , an electromagnetic shielding layer 200 is formed or disposed over a surface 202 of the encapsulant 170 by conformally applying a shielding material. The electromagnetic shielding material 200 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the electromagnetic shielding material 200 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 200 covers a side surface 204 of the encapsulant 170 and a side surface 206 of the substrate 150. At least to some extent, the electromagnetic shielding material 200 covers the cover 184 protecting the electrical connector 134. During this first step, the electrical connector 134 remains free of the shielding material.

[0043] In FIG. 7 c , the cover mask 184 is removed, leaving the shielding material 200 covering the RF sensitive portions of the RF AoP module 176 a .

[0044] In a second step, electromagnetic shielding material 210 is applied over a portion of electromagnetic shielding material 200 and a portion of surface 156 of substrate 150, as shown in FIG7 d . Electromagnetic shielding material 210 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 210 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electromagnetic shielding material 210 is applied in a maskless manner, for example, by direct jet printing using direct jet printer 212, with sufficient control to prevent the shielding material from remaining on electrical connector 134. Shielding material 210 provides partial coverage of RF AoP module 176 a without encroaching on the area occupied by electrical connector 134. Electrical connector 134 remains free of shielding material 200 and shielding material 210. RF AoP module 176a, wherein shielding material 200 and shielding material 210 cover the RF sensitive portion of the RF AoP module, and no shielding material is present on the electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or devices that are incompatible with EMI shielding using a cover-and-shroud approach.

[0045] In another embodiment, continuing from FIG5 a, a cover shield 184 is disposed over the electrical connector 134, as shown in FIG8 a. The cover shield 184 covers or encloses the electrical connector 134, with the vertical portion 184 a contacting the surface 214 of the encapsulant 170. The cover shield 184 covers or encloses the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding material from reaching the connector.

[0046] In a first step, as shown in FIG8b , an electromagnetic shielding layer 220 is formed or disposed over surface 214 of encapsulant 170 by conformally applying a shielding material. Electromagnetic shielding material 220 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 220 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electromagnetic shielding material 220 covers side surfaces 224 of encapsulant 170 and side surfaces 226 of substrate 150. At least to some extent, electromagnetic shielding material 220 covers cover mask 184 protecting electrical connector 134. During this first step, electrical connector 134 remains free of shielding material.

[0047] In FIG. 8 c , the cover mask 184 is removed, leaving the shielding material 220 covering the RF sensitive portions of the RF AoP module 176 a .

[0048] In a second step, electromagnetic shielding material 230 is applied over a portion of electromagnetic shielding material 220 and a portion of surface 156 of substrate 150, as shown in FIG8 d . Electromagnetic shielding material 230 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, electromagnetic shielding material 230 can be carbonyl iron, stainless steel, nickel silver, mild steel, silicon steel, foil, conductive resin, carbon black, aluminum flakes, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. Electromagnetic shielding material 230 is applied in a maskless manner, for example, by direct jet printing using direct jet printer 232, with sufficient control to prevent the shielding material from remaining on electrical connector 134. Shielding material 230 provides partial coverage of RF AoP module 176 a without encroaching on the area occupied by electrical connector 134. Electrical connector 134 remains free of shielding material 220 and shielding material 230. RF AoP module 176a, wherein shielding material 220 and shielding material 230 cover the RF sensitive portion of the RF AoP module, and no shielding material is present on the electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or devices that are incompatible with EMI shielding using a cover-and-shroud approach.

[0049] The two-step shielding process is applicable to the semiconductor packages of Figures 2a-2d and 4. For example, Figure 9 shows the RF AoP module from Figure 4 being singulated using a first step of shielding material 180 and a second step of shielding material 186. Similarly, electrical connector 134 remains free of shielding material 180 and shielding material 186.

[0050] FIG10 illustrates an electronic device 300 having a wafer carrier substrate or PCB 302. A plurality of semiconductor packages are disposed on a surface of PCB 302, including SiP module 148, RF AoP modules 176a through 176b, and AoP modules from AoP wafer 172. In the two-step process of the present invention, all modules include shielding materials 180, 186, 190, 200, 210, 220, and 230. Depending on the application, electronic device 300 can have one type of semiconductor package or multiple types of semiconductor packages.

[0051] Electronic device 300 can be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 can be a subcomponent of a larger system. For example, electronic device 300 can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages can contain microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for market acceptance of products. The distance between semiconductor devices can be reduced to achieve higher density.

[0052] In FIG10 , a printed circuit board 302 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of printed circuit board 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical connectivity between semiconductor packages, mounted components, and other external system components. Traces 304 also provide power and ground connections to the semiconductor packages.

[0053] In some embodiments, a semiconductor device has two levels of packaging. First-level packaging involves mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second-level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, a semiconductor device may have only first-level packaging, where the die is mechanically and electrically attached directly to the PCB. For illustrative purposes, several types of first-level packaging, including wire bond packaging 306 and flip chip 308, are shown on printed circuit board 302. Additionally, several types of second-level packages, including a ball grid array (BGA) 310, a bump chip carrier (BCC) 312, a land grid array (LGA) 316, a multi-chip module (MCM) or SIP module 318, a quad flat non-leaded package (QFN) 320, a quad flat package 322, an embedded wafer level ball grid array (eWLB) 324, and a wafer level chip scale package (WLCSP) 326, are shown disposed on printed circuit board 302. In one embodiment, eWLB 324 is a fan-out wafer level package (Fo-WLP), and WLCSP 326 is a fan-in wafer level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured with first and second-level packaging styles, as well as any combination of other electrical components, can be connected to printed circuit board 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages contain complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to malfunction and are less expensive to manufacture, thereby reducing costs for consumers.

[0054] Although one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

[0055] 100:Semiconductor wafer / wafer 102: Base substrate material 104:Semiconductor grains / components 106: Cutting Road 108: Inactive surface 110: Active Surface 112: Conductor layer 114: Bump 118:Laser cutting tools 120:Interconnect substrate / substrate 122: Conductor layer 124: Insulation layer 126: Top surface / surface 128: bottom surface / surface 130a: Electrical components 130b: Electrical components 130c: Electrical components 130d: Electrical components 132:Terminal 134:Electrical connector 136:Electrical connector 138: Conductive paste 140: Encapsulant / Molding Compound 144: Bump 148:SiP module 150:Interconnect substrate / substrate 152: Conductor layer 154: Insulation layer 156: Top surface / surface 158: bottom surface / surface 160: Conductor layer 162a: Island 162b: Island 166a: RF antenna / first antenna 166b:RF antenna / second antenna 168:RF antenna intermediate substrate / RF antenna substrate / intermediary 170: Molding compound / encapsulant 172:AoP Wafer 174:RF Antenna SiP Wafer 175:Laser cutting tools 176a:RF AoP module 176b:RF AoP module 180: Shielding material 180a: lower surface 180b: Upper surface 181: Direct Inkjet Printer 184: Covering mask / cover 184a: Vertical section 186:Electromagnetic shielding layer / shielding material 188: Surface 190: Side surface electromagnetic shielding layer / shielding material 192: side surface 193: Surface 194: Side surface 196: side surface 200:Electromagnetic shielding layer / shielding material 202: Surface 204: side surface 206: side surface 210: Shielding material 212: Direct inkjet printer 214: Surface 220:Electromagnetic shielding layer / shielding material 224: side surface 226: side surface 230: Shielding material 232: Direct Inkjet Printer 300: Electronic devices 302: Printed Circuit Board / PCB 304: Conductive signal trace 306: Bonding wire package 308: Flip Chip 310:Ball Grid Array (BGA) 312: Bump wafer carrier BCC 316: Land grid array LGA 318: Multi-chip module or SIP module SIP module / MCM 320: Quad Flat No-Wire Package QFN 322: Quad Flat Pack 324:Embedded Wafer Level Ball Grid Array eWLB 326: Wafer-Level Chip Scale Packaging

Claims

1. A semiconductor device comprising: substrate; Encapsulating agent, which is deposited on the first surface of the substrate; An electrical connector disposed above the first surface of the substrate outside the encapsulant; a first shielding material disposed above a portion of the encapsulant and smaller than the entire surface of the encapsulant, and not disposed above the electrical connector; a cover disposed above the electrical connector, and the cover is separated from the encapsulant; and a second shielding material disposed above the encapsulant, wherein the cover prevents the second shielding material from reaching the electrical connector.

2. The semiconductor device of claim 1, further comprising an electrical component disposed above the substrate.

3. The semiconductor device of claim 1, further comprising an antenna formed above a second surface of the substrate opposite to the first surface of the substrate.

4. The semiconductor device of claim 1, wherein the first shielding material covers the portion of the encapsulant and a portion of the substrate while maintaining separation from the electrical connector.

5. The semiconductor device of claim 1, wherein the second shielding material is disposed above the side surface of the encapsulant and the side surface of the substrate.

6. A semiconductor device comprising: substrate; Encapsulating agent, which is disposed above the first surface of the substrate; An electrical connector disposed above the substrate outside the encapsulant; A first shielding material is disposed on a portion but not all of the surface of the substrate and spaced apart from the electrical connector, and the first shielding material is disposed on a portion of the surface of the encapsulant and smaller than the entire surface of the encapsulant, and the first shielding material is not disposed on the electrical connector; a cover is disposed on the electrical connector and is separated from the encapsulant; and a second shielding material is disposed on the substrate, wherein the cover prevents the second shielding material from reaching the electrical connector.

7. The semiconductor device of claim 6, further comprising: an electrical component disposed above the substrate, wherein the encapsulant is deposited above the electrical component and the substrate.

8. The semiconductor device of claim 6, further comprising an antenna formed above the substrate.

9. The semiconductor device of claim 6, wherein the second shielding material overlaps with the first shielding material.

10. The semiconductor device of claim 6, wherein the first shielding material is deposited on the portion of the substrate using a direct inkjet printer.

11. A method for manufacturing a semiconductor device, comprising: Provide substrate; An encapsulating agent is deposited on the first surface of the substrate; The electrical connector is disposed above the first surface of the substrate outside the encapsulant; A first shielding material is disposed above a portion of the surface of the encapsulant and is smaller than the entire surface of the encapsulant, and the first shielding material is not disposed above the electrical connector; a cover is disposed above the electrical connector, and the cover and the encapsulant are separated; and a second shielding material is disposed above the encapsulant, wherein the cover prevents the second shielding material from reaching the electrical connector.

12. The method of claim 11, further comprising disposing an electrical component above the substrate.

13. The method of claim 11, further comprising forming an antenna above a second surface of the substrate opposite to the first surface of the substrate.

14. The method of claim 11, further comprising disposing the second shielding material above the side surface of the encapsulant and above the side surface of the substrate.

15. The method of claim 11, wherein the first shielding material covers the portion of the encapsulant and a portion of the substrate, thereby maintaining separation from the electrical connector.

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