Integrated circuit device and method of manufacturing thereof

Abstract

An integrated circuit (IC) device includes: a substrate; a first semiconductor device and a second semiconductor device, correspondingly located in different first and second doped regions within the substrate. The gate of the first semiconductor device is electrically coupled to the source / drain of the second semiconductor device. The IC device further includes: a first protection device configured as one of a first positive diode and a first negative diode; and a second protection device configured as the other of the first positive diode and the first negative diode. The first positive diode and the first negative diode are electrically coupled in series between the substrate and a doped well. The doped well is located in the first doped region, and the source / drain of the first semiconductor device is located in the doped well. Alternatively, the doped well is located in the second doped region, and the source / drain of the second semiconductor device is located in the doped well.

Description

Integrated circuit device and manufacturing method thereof The recent trend toward miniaturization of integrated circuit (IC) devices has resulted in smaller semiconductor devices that consume less power while providing more functionality at higher speeds. This miniaturization process has also increased the susceptibility of semiconductor devices to damage due to various factors, such as thinner gate dielectric thickness, lower dielectric breakdown voltage, and similar factors. The antenna effect is one of the causes of circuit damage in IC devices and is a consideration in advanced semiconductor technology. The following disclosure provides different embodiments or examples for implementing the various features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the disclosure. Of course, these are merely examples and are not limiting. Other components, materials, values, steps, arrangements, etc. are also contemplated. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed. Source / drain regions may refer to the source or drain individually or collectively, depending on the context. Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. During the manufacturing process of an integrated circuit (IC) device, transistors are formed on a substrate. Each transistor includes a gate electrode and a gate dielectric located between the gate electrode and the substrate. The gate dielectric is an oxide or another gate dielectric material. In subsequent manufacturing operations after the transistors are formed, various dielectric and metal layers are deposited and patterned to obtain vias and / or patterns that are electrically coupled to the gate electrodes of the transistors. Deposition and / or patterning operations often include plasma operations, such as plasma etching operations, plasma deposition operations, or the like. During plasma operations, sufficient charge may accumulate in the conductive patterns, vias, and / or doped wells that are coupled to the gate electrodes, causing breakdown of the underlying gate dielectric and damage to the corresponding transistors. This problem, known as plasma-induced gate oxide damage (PID) or the "antenna effect," can potentially cause yield and / or reliability issues during the semiconductor manufacturing process. PID issues include metal PID and well PID. Metal PID is associated with charge accumulation on metal features (such as conductive patterns and / or vias). Well PID is associated with charge accumulation in doped wells on which gates and gate dielectrics are formed, or which are electrically coupled to gates. PID protection circuits and / or PID protection devices are included in IC devices to protect other transistors and / or circuits from damage caused by antenna effects or PID. In some embodiments, a PID protection circuit in an IC device includes at least one pair of PID protection devices, each configured as a forward diode and a reverse diode, respectively, electrically coupled in series between a doped well and a substrate (the doped well is formed on the substrate). Examples of PID protection devices include, but are not limited to, an N-type diode, a P-type diode, a diode-connected metal-oxide semiconductor (MOS) transistor, a diode-connected bipolar junction transistor (BJT), or any device having a PN junction or a PN junction configuration. In at least one embodiment, the reverse diode is configured to discharge charge accumulated in the doped well during IC device fabrication to the substrate via leakage current from the reverse diode. Consequently, in one or more embodiments, well-PID issues can be avoided or mitigated, particularly in certain process nodes and / or circuit designs where well-PID issues are a concern due to significant variations in well size. In at least one embodiment, the forward diode is configured to withstand the operating voltage applied across the doped well and the substrate during operation of the IC device, either by itself or in combination with the reverse diode. Thus, in one or more embodiments, in addition to the PID requirement, direct current (DC) requirements related to the operating voltage can also be met. This is an improvement over other methods in which a single diode for discharging the charge accumulated in the doped well may not be sufficient to maintain the high operating voltage (e.g., 36 volts) during operation. In some embodiments, one or more further advantages can be achieved, including but not limited to low chip area impact, no impact on the function and / or operation of the IC device, no electrostatic discharge (ESD) issues, applicability to various designs with different voltage applications, applicability to each technology node (or process node), or the like. FIG. 1A is a schematic cross-sectional view of an IC device 100A, according to some embodiments. IC device 100A includes a substrate 110 having a front surface 111 and a back surface 112 along the thickness direction of IC device 100A. The thickness direction is designated as the Z-axis in the drawings. In the exemplary configuration shown in FIG1A , substrate 110 is a P-type substrate (also referred to as a P-substrate). In some embodiments, substrate 110 comprises: an elemental semiconductor including silicon or germanium in a crystalline, polycrystalline, or amorphous structure; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; combinations thereof; or similar materials. In some embodiments, the alloy semiconductor substrate comprises a gradient SiGe feature, in which the Si to Ge composition changes from one ratio at one location within the gradient SiGe feature to another ratio at another location. In some embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, substrate 110 comprises a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure. In at least one embodiment, substrate 110 includes an N-type substrate (also referred to as an N-substrate). One of N-type and P-type is an example of a first conductivity, and the other of N-type and P-type is an example of a second conductivity opposite to the first conductivity. A region having P-type conductivity is a P-type region. Examples of P-type regions include, but are not limited to, a region of a P-type substrate, a P-doped region, a P-well, or the like. A region having N-type conductivity is an N-type region. Examples of N-type regions include, but are not limited to, a region of an N-type substrate, an N-doped region, an N-well, or the like. The IC device 100A further includes a first doped region NBL-A and a second doped region NBL-B located on the front side 111 of the substrate 110. The doped region NBL-B is different from the doped region NBL-A. For example, the doped region NBL-B is physically and / or electrically separated from the doped region NBL-A by an isolation structure (such as a shallow trench isolation (STI) region). In another example, the doped region NBL-B is not continuous with the doped region NBL-A. In the exemplary configuration in Figure 1A, each of the doped region NBL-A and the doped region NBL-B is an N-type doped region, which is a volume within the substrate 110 that includes one or more N-type dopants (such as phosphorus or arsenic) and has a doping concentration sufficient to form a PN junction with the surrounding portion of the substrate 110. In some embodiments, the N-type doped region is referred to as an N+ buried layer (NBL) or a deep N-well (DNW), and the doped region NBL-A and the doped region NBL-B are sometimes referred to as the doped region DNW-A and the doped region DNW-B, respectively. In at least one embodiment, for example, when the substrate 110 is an N-type substrate, at least one of the doped region NBL-A or the doped region NBL-B is a P-type doped region, such as a deep P-well (DPW). The number and / or conductivity type of doped regions located above the substrate 110 are examples. Other doped region configurations are also within the scope of various embodiments. Doped region NBL-A includes a P-well PW1 and an N-well NW1. Doped region NBL-B includes a P-well PW2 and an N-well NW2. In some embodiments, IC device 100A further includes an isolation structure (not shown) that electrically isolates adjacent P-wells and N-wells (e.g., electrically isolating P-well PW1 from N-well NW1 and / or P-well PW2 from N-well NW2). In at least one embodiment, P-well PW1 and N-well NW1 together form a PN junction, and / or P-well PW2 and N-well NW2 together form a PN junction. A P-well (e.g., P-well PW1 or P-well PW2) is a volume within a corresponding doped region that contains one or more P-type dopants at a doping concentration sufficient to form one or more N-type semiconductor devices therein. An N-well (e.g., N-well NW1 or N-well NW2) is a volume within a corresponding doped region that contains one or more N-type dopants at a doping concentration sufficient to form one or more P-type semiconductor devices therein. A p-well (indicated in the figures by the label "PW") and an N-well (indicated in the figures by the label "NW") are examples of doped wells. In the example configuration of FIG1A , transistors P1 and P2 are examples of P-type semiconductor devices formed on corresponding N-wells NW1 and NW2, and transistors N1 and N2 are examples of N-type semiconductor devices formed on corresponding P-wells PW1 and PW2. Other semiconductor device configurations, such as diodes, are also within the scope of various embodiments. As described herein, semiconductor devices located in the P-well and / or N-well over substrate 110 are electrically coupled to each other to form one or more functional circuits. The functional circuits are configured to implement the intended functions of IC device 100A, such as data processing, data storage, input / output (I / O), or the like. Examples of the one or more circuits, logic, or cells included in the functional circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), multiplexers (MUXs), flip-flops, buffers (BUFFs), latches, delays, clocks, memories such as static random-access memory (SRAM), decoupling capacitors, analog amplifiers, logic drivers, digital drivers, or the like. In some embodiments, the circuits, logic, or cells included in the functional circuit include functional transistors or core transistors to be protected from the antenna effect during fabrication of the IC device 100A. Examples of transistors in the functional circuit, as well as transistors in other circuits described herein, include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors (PMOS), N-channel metal oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), fin field effect transistors (FinFETs), planar MOS transistors with raised source / drain terminals, nanosheet FETs, nanowire FETs, or the like. In addition to the functional circuits, IC device 100A further includes one or more PID protection circuits, as described herein. A semiconductor device includes a gate and a source / drain. A detailed description of transistor N1 is given herein. Specifically, transistor N1 includes a gate structure 120 having a gate dielectric 121 located on a P-well PW, and a gate electrode or gate 122 located on the gate dielectric 121. Example conductive materials for the gate 122 include, but are not limited to, polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or similar materials. Example materials for the gate dielectric 121 include, but are not limited to, silicon dioxide, silicon nitride (SiN), silicon nitride (SiO2), ... 3N 4) Low-k materials with k values ​​less than 3.8, high-k materials with k values ​​greater than 3.8 (such as aluminum oxide (Al 2O 3) Hafnium oxide (HfO 2) Tantalum pentoxide (Ta 2O 5) or titanium oxide (TiO 2), or similar materials. In some embodiments, IC device 100A further includes sidewalls (not shown in FIG. 1A ) located on opposite sides of gate structure 120. Example sidewalls are described with reference to FIG. 4A and FIG. 4B . Transistor N1 further includes source / drain electrodes 123 and 124 located above P-well PW1. Each of source / drain electrodes 123 and 124 is an N-type doped region having an N-type dopant implanted in P-well PW1. In some embodiments, one or more of source / drain electrodes 123 and 124 extend above front surface 111 of substrate 110. In some embodiments, IC device 100A further includes a lightly doped region (not shown in FIG. 1A ) adjacent to source / drain electrodes 123 and 124 and located below the sidewalls. In some embodiments, a first element and a second element being adjacent to each other includes a situation where the first element and the second element are directly adjacent to each other. In some embodiments, a first element and a second element being adjacent to each other includes a situation where an intermediate element is located between the first element and the second element. In some embodiments, the lightly doped region is configured to maintain low leakage current of transistor N1. Example lightly doped regions are described with respect to FIG. 4A and FIG. 4B . IC device 100A further includes a body contact 125 located in P-well PW1 as a P-doped region. In some embodiments, body contact 125 is configured and / or manufactured in the same manner as and / or simultaneously with the source / drain of P-type semiconductor devices, such as transistors P1 and P2. A body contact located in a doped well is sometimes referred to as a well tap. A body contact located in a substrate is sometimes referred to as a substrate tap. The body contact is configured to provide an electrical connection to the corresponding doped well or substrate. For example, body contact 125 is configured to provide an electrical connection to P-well PW1. In the exemplary configuration of FIG. 1A , body contact 125 is configured to provide an electrical connection between P-well PW1 and PID protection circuit 171, as described herein. In some embodiments, P-well PW1 further includes another body contact configured to electrically couple P-well PW1 to a reference voltage (e.g., ground voltage VSS) to prevent leakage from transistor N1 and / or other N-type semiconductor devices formed above P-well PW1. In some embodiments, body contact 125 is configured as a common electrical connection from P-well PW1 to both PID protection circuit 171 and VSS. In some embodiments, VSS is provided to P-well PW1 from a VSS power rail (not shown) located on back side 112 of substrate 110, with or without a well tap located on front side 111. In some embodiments, source / drain 124 is electrically coupled to body contact 125. Transistor P1 located above P-well PW1 is configured similarly to transistor N1, except that the N-type and P-type features (e.g., doped regions, doped wells, or the like) of transistor P1 correspond to the P-type and N-type features of transistor N1. For example, transistor P1 includes a gate dielectric 131, gate 132, source / drain 133, 134, and body contact 135 that correspond to the gate dielectric 121, gate 122, source / drain 123, 124, and body contact 125 of transistor N1. Body contact 135 is an N-doped region that is configured to electrically couple N-well NW1 to a power supply voltage (e.g., VDD) to prevent leakage from transistor P1 and / or other P-type semiconductor devices formed above N-well NW1. In some embodiments, N-well NW1 further includes another body contact configured to provide an electrical connection between N-well NW1 and the PID protection circuit, for example, as described with respect to FIG. 1B . In some embodiments, body contact 135 is configured as a common electrical connection from N-well NW1 to both the PID protection circuit and VDD. In some embodiments, VDD is provided to N-well NW1 from a VDD power rail (not shown) located on the back side 112 of substrate 110, with or without a well tap located on front side 111. In the example configuration of FIG. 1A , source / drain 134 of transistor P1 is electrically coupled to body contact 135. Other configurations are also within the scope of various embodiments. For example, in one or more embodiments, source / drain 134 is not electrically coupled to body contact 135. Transistor N2, located above P-well PW2, is configured similarly to transistor N1 and includes source / drain electrodes 143, 144 and body contact 145 corresponding to source / drain electrodes 123, 124 and body contact 125 of transistor N1. In the exemplary configuration shown in FIG1A , body contact 145 is a P-doped region configured to electrically couple P-well PW2 to VSS. In some embodiments, P-well PW2 further includes another body contact configured to provide an electrical connection between P-well PW2 and the PID protection circuit, for example, as described with respect to FIG1B . In some embodiments, body contact 145 is configured as a common electrical connection from P-well PW2 to both the PID protection circuit and VSS. In some embodiments, VSS is provided to P-well PW2 from a VSS power rail (not shown) located on back side 112 of substrate 110, with or without a well tap located on front side 111. In the exemplary configuration shown in FIG1A , source / drain 144 of transistor N2 is electrically coupled to body contact 145. Other configurations are also within the scope of various embodiments. For example, in one or more embodiments, source / drain 144 is not electrically coupled to body contact 145. Transistor P2, located above N-well NW2, is configured similarly to transistor P1 and includes source / drain electrodes 153, 154 and a body contact 155 corresponding to the source / drain electrodes 133, 134 and body contact 135 of transistor P1. In the exemplary configuration shown in FIG1A , body contact 155 is configured to electrically couple N-well NW2 to an N-doped region of PID protection circuit 172, as described herein. In some embodiments, N-well NW2 further includes another body contact configured to provide an electrical connection between N-well NW2 and VDD. In some embodiments, body contact 155 is configured as a common electrical connection from N-well NW2 to both PID protection circuit 172 and VDD. In some embodiments, VDD is provided to N-well NW2 from a VDD power rail (not shown) on back side 112 of substrate 110, with or without a well tap on front side 111. In some embodiments, source / drain 154 is electrically coupled to body contact 155. IC device 100A further includes contact structures (not shown) located above and in electrical contact with the corresponding sources / drains of transistors N1, P1, N2, and P2. These contact structures are sometimes referred to as metal-to-device (MD) contact structures. The MD contact structures include conductive material (e.g., metal) formed above the corresponding sources / drains to define electrical connections between the semiconductor devices in IC device 100A, thereby forming one or more functional circuits and / or PID protection circuits. In some embodiments, the MD contact structures are formed above one or more of body contacts 125, 135, 145, and 155. IC device 100A further includes vias (not shown) located above and in electrical contact with corresponding gate and MD contact structures. Vias located above and in electrical contact with MD contact structures are sometimes referred to as via-to-device (VD) vias. Vias located above and in electrical contact with gates are sometimes referred to as via-to-gate (VG) vias. Example materials for VD and / or VG vias include metal. Other configurations are also within the scope of various embodiments. IC device 100A further includes a redistribution structure 160 located above the VD and VG vias. Redistribution structure 160 includes multiple metal layers and multiple via layers sequentially and alternately arranged above the VD and VG vias. Redistribution structure 160 further includes various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The metal layers and via layers of redistribution structure 160 are configured to electrically couple the various components or circuits of IC device 100A to each other and to electrically couple the various components or circuits of IC device 100A to external circuit systems. In redistribution structure 160, the lowest metal layer immediately above and in electrical contact with the VD and VG vias is the M0 (metal-zero) layer. The next metal layer immediately above the M0 layer is the M1 layer. The next metal layer immediately above the M1 layer is the M2 layer, and so on. The conductive pattern located in the M0 layer is referred to as the M0 conductive pattern, the conductive pattern located in the M1 layer is referred to as the M1 conductive pattern, etc. The via layer Vm is arranged between the Mm layer and the Mm+1 layer and electrically couples the Mm layer and the Mm+1 layer, wherein m is an integer of zero or greater. For example, the via-zero (V0) layer is the lowest via layer, which is arranged between the M0 layer and the M1 layer and electrically couples the M0 layer and the M1 layer. Other via layers are V1, V2, or similar via layers. Vias in the V0 layer are referred to as V0 vias, vias in the V1 layer are referred to as V1 vias, and so on. For the sake of simplicity, the metal layers and via layers in the redistribution structure 160 are not fully illustrated in FIG. 1A . In the exemplary configuration of FIG1A , the redistribution structure 160 includes a conductive structure 161 including conductive patterns in various metal layers and corresponding vias in various via layers and electrically coupled to the source / drain 134 and the body contact 135 located on the N-well NW1. The redistribution structure 160 further includes a conductive structure 162 including conductive patterns in various metal layers (e.g., M0 to Mn, wherein 1 ( n is a positive integer) and corresponding vias in various via layers (e.g., V0 to Vn) and electrically coupled to source / drain 144 and body contact 145 located above P-well PW2. In some embodiments, conductive structure 161 is configured to electrically couple the VDD power rail to N-well NW1, and / or conductive structure 162 is configured to electrically couple the VSS power rail to P-well PW2. In some embodiments, IC device 100A includes conductive structures similar to conductive structures 161 and 162 that are electrically coupled to P-well PW1 and / or N-well NW2. The redistribution structure 160 further includes an interconnect 163. In some embodiments, the interconnect is a set of one or more conductive patterns and one or more through-holes located on the substrate 110, which together electrically couple circuit elements (e.g., semiconductor devices). In the exemplary configuration of FIG. 1A , the interconnect 163 includes metal layers (e.g., M0 to Mk, where The conductive patterns in the Mk layer (where k is a positive integer) and corresponding vias in various via layers electrically couple source / drain 143 and 153 to gates 122 and 132. The Mk layer is the highest metal layer containing the conductive patterns. Interconnect 163 is an example of a signal path from one or more semiconductor devices (e.g., transistors N1 and P1) to one or more further semiconductor devices (e.g., transistors N2 and P2). Interconnect 163 also illustrates how an N-well (e.g., N-well NW2) or a P-well (e.g., P-well PW2) can be electrically connected to a gate (e.g., 122) located above another P-well (e.g., P-well PW1) and / or a gate (e.g., 132) located above another N-well (e.g., N-well NW1). In some embodiments, interconnect 163 is electrically coupled to one but not both of source / drain 143, 153 and / or is electrically coupled to one but not both of gate 122, 132. Other configurations are within the scope of various embodiments. During the manufacturing / fabrication process of the IC device 100A, particularly during the manufacturing / fabrication process of the redistribution structure 160 from the M0 layer upward, positive and / or negative charges may potentially accumulate in one or more of the N-well NW1, the P-well PW1, the N-well NW2, and the P-well PW2. For example, when the conductive structure 161 is being fabricated, charge may potentially accumulate in the N-well NW1 due to the electrical connection between the N-well NW1 and the conductive structure 161 via the source / drain 134 and / or the body contact 135. For example, when the conductive structure 162 is being fabricated, charge may potentially accumulate in the P-well PW2 due to the electrical connection between the P-well PW2 and the conductive structure 162 via the source / drain 144 and / or the body contact 145. Similarly, charge may potentially accumulate in the P-well PW1 and / or the N-well NW2. In some cases, negative charge tends to accumulate in the P-well and / or positive charge tends to accumulate in the N-well. When interconnect 163 is fabricated, the potential of the charges accumulated in P-well PW2 and / or N-well NW2 is applied to gates 122 and 132 via completed interconnect 163. This potential, combined with the potential of the charges accumulated in P-well PW1 or N-well NW1, creates an undesirably high voltage across the corresponding gate dielectric 121 or 131, thereby causing undesirable PID of gate dielectric 121 or 131. In some cases, the negative charge accumulated in the P-wells (e.g., P-well PW1 and P-well PW2) can potentially damage the gate dielectric of an N-type semiconductor device (e.g., transistor N1), and / or the positive charge accumulated in the N-wells (e.g., N-well NW1 and N-well NW2) can potentially damage the gate dielectric of a P-type semiconductor device (e.g., transistor P1). One of the positive charge and the negative charge is an example of charge of a first polarity, and the other of the positive charge and the negative charge is an example of charge of a second polarity opposite to the first polarity. A semiconductor device (e.g., transistors N2 and P2) that potentially causes PID in other semiconductor devices is sometimes referred to as a PID aggressor. A semiconductor device (e.g., transistors N1 and P1) that is potentially susceptible to PID caused by other semiconductor devices is sometimes referred to as a PID victim. In some embodiments, to prevent or at least mitigate PID issues, charges in one or more of the N-well NW1, P-well PW1, N-well NW2, and P-well PW2 are discharged by one or more corresponding PID protection circuits before completing the fabrication of the interconnect 163. In the exemplary configuration of FIG1A , IC device 100A includes PID protection circuits 171 and 172 corresponding to the P-well PW1 and N-well NW2. In at least one embodiment, one or more of the N-well NW1 and P-well PW2 also include one or more corresponding PID protection circuits, for example, as described with respect to FIG1B . PID protection circuit 171 includes PID protection devices 175 and 176 electrically coupled in series between substrate 110 and P-well PW1. PID protection devices 175 and 176 are schematically shown in FIG1A and, in one or more embodiments, are formed in or on substrate 110. For example, PID protection devices 175 and 176 include one or more of an N-doped region, a P-doped region, a body contact (or tap), an N-well, and / or a P-well configured and / or fabricated similarly to one or more of the N-doped region, the P-doped region, the body contact (or tap), the N-well, and / or the P-well described for transistors N1, P1, N2, and P2. Examples of PID protection devices include, but are not limited to, an N-type diode, a P-type diode, a diode-connected MOS transistor, a diode-connected BJT, or any device having or configuring a PN junction. In a PID protection circuit, one of the PID protection devices is configured as a forward diode, while the other PID protection device is configured as a reverse diode. For example, in PID protection circuit 171, PID protection device 175 is configured as a forward diode, while PID protection device diode 176 is configured as a reverse diode, or vice versa. For simplicity, PID protection devices are sometimes referred to herein as protection devices or diodes. Diode 175 has an anode 165 electrically coupled to P-well PW1 via body contact 125, and a cathode (not numbered) coupled to the cathode (not numbered) of diode 176. Diode 176 has an anode 166 electrically coupled to substrate 110, for example, at region 116 outside doped regions NBL-A and NBL-B. In some embodiments, the anode 165 of the diode 175 is electrically coupled to the body contact 125 via one or more MD contact structures, a VD via, and a first interconnect. In some embodiments, the anode 166 of the diode 176 is electrically coupled to a body contact or substrate tap located on the front surface 111 of the substrate 110 via one or more MD contact structures, a VD via, and a second interconnect. For simplicity, the second interconnect is not fully shown. The Mi layer is the highest metal layer that includes the conductive pattern of the first or second interconnect, wherein i is less than k is an integer. For example, in one or more embodiments, k = 3, and i = 0. Therefore, when the Mi layer is formed (for example, the M0 layer, where i = 0) and before completing the interconnect 163 (for example, before forming the M3 layer, where k = 3), PID protection circuit 171 is electrically coupled between P-well PW1 and substrate 110. In the exemplary configuration of FIG1A , the highest Mi conductive pattern is located in the first interconnect between anode 165 and body contact 125. In another example, the highest Mi conductive pattern is located in the second interconnect (not shown) between anode 166 and substrate 110. In yet another example, each of the first and second interconnects includes a corresponding Mi conductive pattern. In at least one embodiment, at least one of the first or second interconnects is omitted. For example, in one or more embodiments, region 116 of substrate 110 forms part of diode 176, and the second interconnect is omitted. PID protection circuit 171, electrically coupled between P-well PW1 and substrate 110, is configured to discharge charge accumulated in P-well PW1 to substrate 110. For example, when the potential of P-well PW1 is higher than the potential of substrate 110 due to, for example, positive charge accumulated in P-well PW1, diode 175 is turned on. Positive charge accumulated in P-well PW1 passes through turned-on diode 175 and is then discharged to substrate 110 via leakage current through diode 176, as schematically illustrated by the arrows in FIG. 1A . For another example, when the potential of P-well PW1 is lower than the potential of substrate 110 due to, for example, negative charge accumulated in P-well PW1, diode 176 is turned on. Negative charge accumulated in P-well PW1 is discharged via leakage current through diode 175 and then passes through turned-on diode 176 to substrate 110. PID protection circuit 172 includes PID protection devices 177 and 178 electrically coupled in series between substrate 110 and N-well NW2. PID protection devices 177 and 178 are schematically shown in FIG1A and, in one or more embodiments, are formed in or on substrate 110. For example, PID protection devices 177 and 178 include one or more of an N-doped region, a P-doped region, a body contact (or tap), an N-well, and / or a P-well configured and / or fabricated similarly to one or more of the N-doped region, the P-doped region, the body contact (or tap), the N-well, and / or the P-well described for transistors N1, P1, N2, and P2. Examples of PID protection devices include, but are not limited to, an N-type diode, a P-type diode, a diode-connected MOS transistor, a diode-connected BJT, or any device having or configuring a PN junction. In PID protection circuit 172, PID protection device 177 is configured as a reverse diode, while PID protection device diode 178 is configured as a forward diode, or vice versa. For simplicity, PID protection devices 177 and 178 are sometimes referred to herein as protection devices or diodes. Diode 177 has a cathode 167 electrically coupled to N-well NW2 via body contact 155, and an anode (not numbered) coupled to the anode (not numbered) of diode 178. Diode 178 has a cathode 168 electrically coupled to substrate 110, for example, at region 118 outside doped regions NBL-A and NBL-B. In other words, unlike protection circuit 171, in which diodes 175 and 176 electrically couple their corresponding cathodes, in PID protection circuit 172, diodes 177 and 178 electrically couple their corresponding anodes. These are examples. In some embodiments, diodes 177 and 178 electrically couple corresponding cathodes together, and / or diodes 175 and 176 electrically couple corresponding anodes together. In some embodiments, the cathode 167 of the diode 177 is electrically coupled to the body contact 155 via one or more MD contact structures, a VD via, and a third interconnect. In some embodiments, the cathode 168 of the diode 178 is electrically coupled to a body contact or substrate tap located on the front surface 111 of the substrate 110 via one or more MD contact structures, a VD via, and a fourth interconnect. For simplicity, the fourth interconnect is not fully shown. The Mj layer is the highest metal layer that includes the conductive pattern of the third or fourth interconnect, wherein j is less than In some embodiments, J and i is the same. In at least one embodiment, j is different from i. For example, in one or more embodiments, k = 3 and j = 0. Therefore, when forming an Mj layer (for example, an M0 layer, where j = 0) and before completing the interconnect 163 (for example, before forming the M3 layer, where k = 3), PID protection circuit 172 is electrically coupled between N-well NW2 and substrate 110. In the exemplary configuration of FIG1A , the highest Mj conductive pattern is located in the third interconnect between cathode 167 and body contact 155. In another example, the highest Mj conductive pattern is located in the fourth interconnect (not shown) between cathode 168 and substrate 110. In yet another example, each of the third and fourth interconnects includes a corresponding Mj conductive pattern. In at least one embodiment, at least one of the third or fourth interconnects is omitted. For example, in one or more embodiments, region 118 of substrate 110 forms part of diode 178, and the fourth interconnect is omitted. PID protection circuit 172, electrically coupled between N-well NW2 and substrate 110, is configured to discharge charge accumulated in N-well NW2 to substrate 110. For example, when the potential of N-well NW2 is lower than the potential of substrate 110 due to, for example, negative charge accumulated in N-well NW2, diode 177 is turned on. Negative charge accumulated in N-well NW2 passes through turned-on diode 177 and is then discharged to substrate 110 via leakage current through diode 178. For another example, when the potential of N-well NW2 is higher than the potential of substrate 110 due to, for example, positive charge accumulated in N-well NW2, diode 178 is turned on. Positive charge accumulated in N-well NW2 is discharged via leakage current through diode 177 and then reaches substrate 110 via turned-on diode 178. The illustrated configurations in which the cathodes of two diodes coupled in series are electrically coupled together (e.g., in PID protection circuit 171) or in which the anodes of two diodes coupled in series are electrically coupled together (e.g., in PID protection circuit 172) are examples of configurations sometimes referred to herein as dual reverse junction configurations. In some embodiments, IC device 100A further includes a PID protection circuit similar to protection circuit 171 and electrically coupled between P-well PW2 and substrate 110, and / or a PID protection circuit similar to protection circuit 172 and electrically coupled between N-well NW1 and substrate 110. In at least one embodiment, positive and / or negative charges accumulated in N-well NW1 and / or P-well PW2 are discharged to substrate 110 via the corresponding PID protection circuits in a manner similar to that described for protection circuit 171 and / or protection circuit 172. In some embodiments, during the manufacturing process of the IC device 100A, the electrical connections or interconnects between the PID protection circuit and the substrate 110 and the corresponding doped wells are completed at one or more metal layers below the Mk layer, that is, before the completion of the interconnect 163. Therefore, in one or more embodiments, before the completion of the interconnect 163, the charge accumulated in one or more of the N-well NW1, the P-well PW1, the N-well NW2, and the P-well PW2 is discharged to the substrate 110 by the corresponding one or more PID protection circuits, thereby preventing an undesirable high voltage from being applied across one or more of the gate dielectrics 121 and 131 and avoiding or at least mitigating the PID problem. In some embodiments, during operation of IC device 100A, an operating voltage is applied across one or more of the PID protection circuits. For example, when N-well NW2 is electrically coupled to or biased by VDD, and substrate 110 is electrically coupled to or biased by VSS, an operating voltage of VDD-VSS is applied between N-well NW2 and substrate 110 (i.e., across protection circuit 172). In some cases, this operating voltage is a high DC voltage, such as 36 volts. Other operating voltage values ​​are also within the scope of various embodiments. In some embodiments, the presence of multiple PID protection devices 177, 178 in protection circuit 172 enables protection circuit 172 to maintain a high operating voltage without causing damage and / or reliability issues to IC device 100A. This is an improvement over other approaches in which a single diode used to discharge charge accumulated in a doped well may not be sufficient to maintain a high operating voltage (e.g., 36 volts) during operation. In at least one embodiment, the PID protection circuit does not affect the functionality and / or operation of various functional circuits within IC device 100A. In some embodiments, one or more further advantages can be achieved, including, but not limited to, reduced chip area impact, no ESD issues, or the like. PID protection circuits according to some embodiments are applicable to various designs with varying voltage applications and / or to each technology node (or process node). PID protection circuits according to some embodiments can meet all DC, ESD, and PID requirements. 1B is a schematic circuit diagram of an IC device 100B according to some embodiments. In some embodiments, IC device 100B corresponds to IC device 100A. For simplicity, corresponding components of IC devices 100A, 100B are indicated by the same reference numerals. The IC device 100B includes a doping region NBL-A and a doping region NBL-B. The doping region NBL-A includes an N-well NW1 and a P-well PW1. The doping region NBL-B includes an N-well NW2 and a P-well PW2. IC device 100B further includes one or more semiconductor devices formed above doped region NBL-A and constituting potential PID victims. In the exemplary configuration shown in FIG1B , potential PID victims include an NMOS transistor 181 located above P-well PW1 and / or a PMOS transistor 182 located above N-well NW1. In some embodiments, NMOS transistor 181 corresponds to transistor N1 and / or PMOS transistor 182 corresponds to transistor P1. The gate (unnumbered) of NMOS transistor 181 and the gate (unnumbered) of PMOS transistor 182 are electrically coupled together and to electrical connection 183. In some embodiments, electrical connection 183 is a signal path and / or corresponds to interconnect 163. In some embodiments, electrical connection 183 is electrically coupled to one, but not both, of the gates of NMOS transistor 181 and PMOS transistor 182. In FIG1B , electrical connections that exist in some designs or circuits but not in other designs or circuits are schematically illustrated by dot-dotted lines (dashed lines). For example, in one or more embodiments, the source / drain 180 of the NMOS transistor 181 is electrically coupled to the P-well PW1, or in one or more other embodiments, the source / drain 180 of the NMOS transistor 181 is not electrically coupled to the P-well PW1. IC device 100B further includes one or more semiconductor devices formed above doped region NBL-B and constituting potential PID aggressors. In the exemplary configuration shown in FIG1B , the potential PID aggressors include one or more diodes 184 and 185, and / or one or more MOS devices (e.g., PMOS transistor 186 and NMOS transistor 187), and / or one or more BJTs (e.g., NPN BJT 188 and PNP BJT 190). In some embodiments, the PID aggressor comprises any PN junction electrically coupled to the gate of the PID victim. In the exemplary configuration shown in FIG1B , electrical connection 183 is electrically coupled to the base of PNP BJT 190. In still other examples, electrical connection 183 is electrically coupled to one or more of junction 191 between diodes 184 and 185, junction 192 between PMOS transistor 186 and NMOS transistor 187, and / or junction 193 between NPN BJT 188 and PNP BJT 189. In some embodiments, PMOS transistor 186 corresponds to transistor P2, and / or NMOS transistor 187 corresponds to transistor N2. IC device 100B further includes PID protection circuits 171-174 electrically coupled between substrate 110 and the corresponding P-well PW1, N-well NW2, N-well NW1, and P-well PW2. Each of PID protection circuits 171-174 includes a pair of PID protection devices, each configured as a forward diode and a reverse diode, for example, as described with respect to FIG. 1A . In the exemplary configuration of FIG. 1B , similar to diodes 175 and 176 of PID protection circuit 171 , the forward diodes and reverse diodes (not numbered) of PID protection circuits 173 and 174 have their corresponding cathodes electrically coupled together. In some embodiments, similar to diodes 177 and 178 of PID protection circuit 172 , in at least one of PID protection circuits 173 and 174 , the forward diode and reverse diode have their corresponding anodes electrically coupled together. Other configurations are also within the scope of various embodiments. In at least one embodiment, one or more of the PID protection circuits 171 - 174 are omitted. In the example configuration of FIG1B , each of PID protection circuits 171-174 is shown as including a pair of diodes. This is an example. In some embodiments, the PID protection circuit includes more than one forward diode and / or more than one reverse diode. For example, PID protection circuit 179 includes a pair of forward diodes (e.g., 146 and 147) and a pair of reverse diodes 148 and 149 electrically coupled in series between substrate 110 and a doped well. PID protection circuit 179 is electrically coupled to the doped well at a first end corresponding to anode 156 of diode 146. For example, anode 156 is electrically coupled to a body contact located in the doped well in a manner similar to that described for body contact 125 or body contact 155 in FIG1A . PID protection circuit 179 is electrically coupled to substrate 110 at a second end corresponding to anode 158 of diode 148. For example, anode 158 is electrically coupled to substrate 110 in a manner similar to that described for anode 166 in FIG. 1A . In the example configuration of FIG. 1B , diodes 146-149 are coupled in a manner similar to diodes 175 and 176 in PID protection circuit 171. Specifically, the cathode of diode 146 is electrically coupled to the anode of diode 147, the cathodes of diodes 147 and 149 are electrically coupled together, and the anode of diode 149 is electrically coupled to the cathode of diode 148. In some embodiments, the cathodes and anodes of diodes 146-149 are swapped, thereby achieving a configuration similar to that described for PID protection circuit 172. In some embodiments, PID protection circuit 179, or a PID protection circuit having multiple forward diodes and / or multiple reverse diodes, replaces one or more of PID protection circuits 171-174. In some embodiments, the number of forward diodes in a PID protection circuit is different from the number of reverse diodes in the same PID protection circuit. In at least one embodiment, PID protection circuit 179, or a PID protection circuit having multiple forward diodes and / or multiple reverse diodes, is configured to operate in a manner similar to PID protection circuits 171-174, namely, to discharge charge accumulated in the corresponding doped wells to the substrate during fabrication of IC device 100B, before electrical connection 183 or the corresponding signal path is formed. The increased number of diodes in PID protection circuit 179, compared to PID protection circuits 171-174, improves PID protection circuit 179's ability to maintain a high operating voltage during operation, as the impedance in the leakage current path used to discharge charge from the doped wells during fabrication is correspondingly increased. In at least one embodiment, the number and / or configuration of diodes in the PID protection circuit are design considerations and are selected to ensure that the PID protection circuit provides the desired PID protection against antenna effects during fabrication while remaining sufficiently robust at the desired operating voltage during operation. IC device 100B further includes a local PID protection circuit 194 formed in doped region NBL-A. Local PID protection circuit 194 includes an NMOS transistor 195 and a PMOS transistor 196. In at least one embodiment, NMOS transistor 195 is formed above P-well PW1 and / or PMOS transistor 196 is formed above N-well NW1. NMOS transistor 195 is electrically connected in a configuration sometimes referred to as grounded-gate NMOS (ggNMOS), in which the gate, first source / drain, and bulk of NMOS transistor 195 are electrically coupled together and to P-well PW1. PMOS transistor 196 is electrically connected in a configuration sometimes referred to as gate-VDD PMOS (gdPMOS), in which the gate, first source / drain, and bulk of PMOS transistor 196 are electrically coupled together and to N-well NW1. The second source / drain of the NMOS transistor 195 and the second source / drain of the PMOS transistor 196 are electrically coupled together, electrically coupled to the electrical connection 183 and electrically coupled to the gates of the NMOS transistor 181 and the PMOS transistor 182 which are potential PID victims. During the manufacture of IC device 100B, before electrical connection 183 is completed, NMOS transistor 195 and PMOS transistor 196 are electrically coupled to the gate of a potential PID victim. NMOS transistor 195 and / or PMOS transistor 196 are configured to discharge the charge on electrical connection 183 upon completion of electrical connection 183, thereby protecting the gate dielectric of the potential PID victim from PID issues. During operation of IC device 100B, NMOS transistor 195 and PMOS transistor 196 are turned off and do not affect the function or operation of one or more functional circuits including the potential PID victim to be protected. In some embodiments, one of NMOS transistor 195 and PMOS transistor 196 is omitted. In at least one embodiment, local PID protection circuit 194 is omitted. IC device 100B further includes a cross-well PID protection circuit 197. Cross-well PID protection circuit 197 includes a diode 198 and a diode 199 formed on substrate 110. Diode 198 has an anode electrically coupled to P-well PW1 and a cathode electrically coupled to P-well PW2. Diode 199 has an anode electrically coupled to P-well PW2 and a cathode electrically coupled to P-well PW1. In some embodiments, diodes 198 and 199 are electrically coupled to P-wells PW1 and PW2 at corresponding body contacts, as described with respect to FIG. 1A . During the fabrication of IC device 100B, before electrical connection 183 is completed, diodes 198 and 199 are formed and electrically coupled to P-wells PW1 and PW2, with at least one of diodes 198 and 199 configured to transfer charge between P-wells PW1 and PW2. Therefore, a high voltage generated by the potential difference between P-wells PW1 and PW2 is less likely to be applied across the gate dielectric of a potential PID victim located above doped region NBL-A. Diodes 198 and 199 do not affect the function or operation of one or more functional circuits, including the potential PID victim to be protected. In some embodiments, one of diodes 198 and 199 is omitted. In at least one embodiment, cross-well PID protection circuit 197 is omitted. In at least one embodiment, one or more of the advantages described herein can be achieved by IC device 100B. 2 includes schematic circuit diagrams of various PID protection devices 203 through 209 according to some embodiments. In some embodiments, any of the PID protection devices 203 through 209 corresponds to any of the PID protection circuits described herein (e.g., PID protection circuits 171 through 174, 179). PID protection device 203 includes a diode D3. In some embodiments, diode D3 is an N-type diode, i.e., a diode formed on or in a P-well or P-doped region. In some embodiments, diode D3 is a P-type diode, i.e., a diode formed on or in an N-well or N-doped region. In the figures, an N-type diode is schematically indicated by the label "N" or "N diode." In the figures, a P-type diode is schematically indicated by the label "P" or "P diode." In the figures, a diode that can be either an N-type diode or a P-type diode is schematically indicated by the label "N / P" or "N / P diode." Examples of N-type and P-type diodes are described with reference to Figures 3A to 3E. PID protection device 204 includes a diode-connected NMOS transistor, sometimes referred to herein as diode-connected NMOS 204. Diode-connected NMOS 204 has a gate GN, a source SN, and a drain DN. Gate GN is electrically coupled to source SN and to the bulk of diode-connected NMOS 204. Therefore, diode-connected NMOS 204 includes a diode D4 having an anode corresponding to gate GN, source SN, and bulk, and a cathode corresponding to drain DN. An example of a diode-connected NMOS transistor is described with reference to FIG. 4A . PID protection device 205 includes a diode-connected PMOS transistor, sometimes referred to herein as diode-connected PMOS 205. Diode-connected PMOS 205 has a gate GP, a source SP, and a drain DP. Gate GP is electrically coupled to source SP and to the bulk of diode-connected PMOS 205. Therefore, diode-connected PMOS 205 includes a diode D5 having a cathode corresponding to gate GP / source SP / bulk, and an anode corresponding to drain DP. An example of a diode-connected PMOS transistor is described with reference to FIG4B . PID protection device 206 includes a diode-connected NPN BJT, sometimes referred to herein as diode-connected NPN BJT 206. Diode-connected NPN BJT 206 includes a base BN, a collector CN, and an emitter EN. Base BN is electrically coupled to emitter EN. Therefore, diode-connected NPN BJT 206 includes a diode D6 having an anode corresponding to base BN / emitter EN and a cathode corresponding to collector CN. PID protection device 207 includes a diode-connected NPN BJT, sometimes referred to herein as diode-connected NPN BJT 207. Like diode-connected NPN BJT 206, diode-connected NPN BJT 207 includes a base BN, a collector CN, and an emitter EN. However, diode-connected NPN BJT 207 has different electrical connections than diode-connected NPN BJT 206. Specifically, in diode-connected NPN BJT 207, base BN is electrically coupled to collector CN. Therefore, diode-connected NPN BJT 207 includes diode D7, which has an anode corresponding to base BN / collector CN and a cathode corresponding to emitter EN. An example of a diode-connected NPN BJT is described with reference to Figures 5A and 5B. PID protection device 208 includes a diode-connected PNP BJT, sometimes referred to herein as diode-connected PNP BJT 208. Diode-connected PNP BJT 208 includes a base BP, a collector CP, and an emitter EP. Base BP is electrically coupled to emitter EP. Therefore, diode-connected PNP BJT 208 includes a diode D8 having a cathode corresponding to base BP / emitter EP and an anode corresponding to collector CP. PID protection device 209 includes a diode-connected PNP BJT, sometimes referred to herein as diode-connected PNP BJT 209. Like diode-connected PNP BJT 208, diode-connected PNP BJT 209 includes a base BP, a collector CP, and an emitter EP. Compared to diode-connected PNP BJT 208, diode-connected PNP BJT 209 includes different electrical connections. Specifically, in diode-connected PNP BJT 209, base BP is electrically coupled to collector CP. Therefore, diode-connected PNP BJT 209 includes diode D9, which has a cathode corresponding to base BP / collector CP and an anode corresponding to emitter EP. An example of a diode-connected PNP BJT is described with reference to Figures 6A and 6B. The N-type diode, diode-connected NMOS, and diode-connected NPN BJT described herein are examples of N-type PID protection devices. The P-type diode, diode-connected PMOS, and diode-connected PNP BJT described herein are examples of P-type PID protection devices. In at least one embodiment, one or more advantages described herein can be achieved by a PID protection circuit including any one or more of the PID protection devices 203 to 209, and / or in an IC device including such a PID protection circuit. FIG3A is a schematic cross-sectional view of a PID protection device 300A according to some embodiments. In some embodiments, PID protection device 300A corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). In one or more embodiments, PID protection device 300A is a P-type diode corresponding to PID protection device 203. PID protection device 300A is referred to herein as P-type diode 300A. P-type diode 300A is formed on substrate 310. In some embodiments, substrate 310 corresponds to substrate 110. In at least one embodiment, P-type diode 300A is formed on a doped region (e.g., a deep well as described with respect to FIG. 1A ). P-type diode 300A includes an N-well 311, a P-doped region 315, an N-doped region 316, and conductive structures 317 and 318. In some embodiments, N-well 311 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG1A . In some embodiments, P-doped region 315 and N-doped region 316 correspond to or are similar to the P-doped region and N-doped region described with respect to FIG1A . In some embodiments, P-type diode 300A further includes one or more STI regions (not shown). A diode 319 is configured at the PN junction between the P-doped region 315 and the N-well 311. The P-doped region 315 corresponds to the anode of the diode 319, and the N-well 311 corresponds to the cathode of the diode 319. In some embodiments, the diode 319 corresponds to the diode D3, which is a P-type diode. Conductive structure 317 is electrically coupled to P-doped region 315 to provide an electrical connection to the anode of diode 319. Conductive structure 318 is electrically coupled to N-doped region 316 to provide an electrical connection to the cathode of diode 319. In some embodiments, each or at least one of conductive structures 317 and 318 comprises one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located beneath the Mk layer. In some embodiments, each of conductive structures 317 and 318 is configured to electrically couple to the anode or cathode of another PID protection device, a doped well, or substrate 310. FIG3B is a schematic cross-sectional view of a PID protection device 300B according to some embodiments. In some embodiments, PID protection device 300B corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). In one or more embodiments, PID protection device 300B is an N-type diode corresponding to PID protection device 203. PID protection device 300B is referred to herein as N-type diode 300B. N-type diode 300B is formed on substrate 310. In at least one embodiment, N-type diode 300B is formed on a doped region (e.g., a deep well as described with respect to FIG. 1A ). N-type diode 300B includes P-well 321, N-doped region 325, P-doped region 326, and conductive structures 327 and 328. In some embodiments, P-well 321 is omitted, and substrate 310 is a P-type substrate configured as an anode for N-type diode 300B. In some embodiments, the P-well 321 corresponds to or is similar to the P-well PW1 or P-well PW2 described with respect to FIG1A . In some embodiments, the N-doped region 325 and the P-doped region 326 correspond to or are similar to the N-doped region and the P-doped region described with respect to FIG1A . In some embodiments, the N-type diode 300B further includes one or more STI regions (not shown). A diode 329 is configured at the PN junction between the N-doped region 325 and the P-well 321 (or, if the P-well 321 is omitted, between the N-doped region 325 and the P-type substrate). The N-doped region 325 corresponds to the cathode of diode 329, and the P-well 321 (or, if the P-well 321 is omitted, the P-type substrate) corresponds to the anode of diode 329. In some embodiments, diode 329 corresponds to diode D3. Conductive structure 327 is electrically coupled to N-doped region 325 to provide an electrical connection to the cathode of diode 329. Conductive structure 328 is electrically coupled to P-doped region 326 to provide an electrical connection to the anode of diode 329. In some embodiments, each or at least one of conductive structures 327 and 328 comprises one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located beneath the Mk layer. In some embodiments, each of conductive structures 327 and 328 is configured to electrically couple to the anode or cathode of another PID protection device, a doped well, or substrate 310. FIG3C is a schematic cross-sectional view of a PID protection device 300C according to some embodiments. PID protection device 300C includes two P-type diodes electrically coupled in series in a manner similar to diodes 146, 147 or diodes 148, 149 described with respect to FIG1B . For simplicity, components of PID protection device 300C having corresponding components in P-type diode 300A are indicated by the same reference numerals or by incrementing the reference numeral of P-type diode 300A by 20. The first P-type diode of PID protection device 300C corresponds to P-type diode 300A and includes an N-well 311, a P-doped region 315, an N-doped region 316, a conductive structure 317, and a diode 319. The second P-type diode of PID protection device 300C is similar to P-type diode 300A and includes an N-well 331, a P-doped region 335, an N-doped region 336, a conductive structure 338, and a diode 339. PID protection device 300C further includes a conductive structure 337 that electrically couples N-doped region 316 and P-doped region 335, i.e., electrically couples the cathode of diode 319 to the anode of diode 339. In some embodiments, each or at least one of conductive structures 337 and 338 comprises one or more of an MD contact structure, a VD via, a conductive pattern, and a via located entirely beneath the Mk layer. In some embodiments, each of the conductive structures 317 , 338 is configured to be electrically coupled to another PID protection device, a doped well, or an anode or cathode of the substrate 310 . FIG3D is a schematic cross-sectional view of a PID protection device 300D according to some embodiments. PID protection device 300D includes two N-type diodes electrically coupled in series in a manner similar to diodes 146, 147 or diodes 148, 149 described with respect to FIG1B . For simplicity, components of PID protection device 300D having corresponding components in N-type diode 300B are indicated by the same reference numerals or by incrementing the reference numeral of N-type diode 300B by 20. The first N-type diode of PID protection device 300D corresponds to N-type diode 300B and includes a P-well 321, an N-doped region 325, a P-doped region 326, a conductive structure 327, and a diode 329. The second N-type diode of PID protection device 300D is similar to N-type diode 300B and includes a P-well 341, an N-doped region 345, a P-doped region 346, a conductive structure 348, and a diode 349. PID protection device 300D further includes a conductive structure 347 that electrically couples P-doped region 326 and N-doped region 345, i.e., electrically couples the anode of diode 329 to the cathode of diode 349. In some embodiments, each or at least one of conductive structures 347 and 348 comprises one or more of an MD contact structure, a VD via, a conductive pattern, and a via located entirely beneath the Mk layer. In some embodiments, each of the conductive structures 327 , 348 is configured to be electrically coupled to another PID protection device, a doped well, or an anode or cathode of the substrate 310 . 3E is a schematic cross-sectional view of a PID protection circuit 300E according to some embodiments. In some embodiments, the PID protection circuit 300E corresponds to the PID protection circuit 703 described with respect to FIG. 7A . PID protection circuit 300E includes a P-type diode 300A and an N-type diode 300B electrically coupled in a dual reverse junction. In the exemplary configuration shown in FIG3E , the P-well 321 of N-type diode 300B is omitted. N-doped region 316 of P-type diode 300A is electrically coupled to N-doped region 325 of N-type diode 300B via conductive structure 357, thereby electrically coupling the cathodes of diodes 319 and 329 together. Conductive structure 317 is configured to electrically couple to the doped well where charge is to be discharged, and conductive structure 328 corresponds to the substrate tap of substrate 310. PID protection circuit 300E is an example in which interconnects between the substrate and the PID protection circuit are omitted. This is because substrate 310 is a P-type substrate configured as the anode of N-type diode 300B. During the manufacturing process of an IC device including PID protection circuit 300E, charge accumulated in a doped well (not shown) electrically coupled to conductive structure 317 is discharged to substrate 310 via diode 319, conductive structure 357, and diode 329. During operation of an IC device including PID protection circuit 300E, substrate 310 is biased using an operating voltage applied to conductive structure 328. The operating voltage of the doped well is applied to conductive structure 317. In the event that the operating voltage of substrate 310 is higher than the operating voltage of the doped well (at conductive structure 317), PN junction 358 between substrate 310 and N-well 311 will be forward biased, as schematically indicated by arrow 359, potentially inducing undesirable current flow. In one or more embodiments, this is a reason for using PID protection circuit 300E in circuit designs or applications where a lower operating voltage is applied to substrate 310 and a higher operating voltage is applied to the doped well, from which charge is discharged during manufacturing. For similar reasons, in one or more embodiments, for IC devices, applications, or circuit designs in which different operating voltages are applied to the substrate and the doped well, a PID protection circuit electrically coupled between the substrate and the doped well is selected such that the PID protection circuit includes an N-type PID protection device (i.e., a device having a P-type region (e.g., a P-type substrate or P-well) or located above a P-type region) located on the lower operating voltage side, and a P-type PID protection device (i.e., a device having an N-type region (e.g., an N-type substrate or N-well) or located above an N-type region) located on the higher operating voltage side. For example, in one or more embodiments, when the substrate has a lower operating voltage than the doped well, the N-type PID protection device (e.g., an N-type diode, NMOS, or NPN BJT) is electrically coupled to the substrate with the lower operating voltage, and the P-type PID protection device (e.g., a P-type diode, PMOS, or PNP BJT) is electrically coupled to the doped well with the higher operating voltage. Various examples are described with respect to one or more of Figures 7A to 7E. FIG4A is a schematic cross-sectional view of a PID protection device 400A according to some embodiments. In some embodiments, PID protection device 400A corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 400A is a diode-connected NMOS transistor, which, in one or more embodiments, corresponds to diode-connected NMOS 204. PID protection device 400A is referred to herein as diode-connected NMOS 400A. A diode-connected NMOS transistor 400A is formed on a substrate 410. In some embodiments, substrate 410 corresponds to substrate 110. In at least one embodiment, diode-connected NMOS transistor 400A is formed on a doped region (e.g., the deep well described with respect to FIG. 1A ). Diode-connected NMOS transistor 400A includes a P-well 411, STI regions 412, 413, and 414 of dielectric material, a P-doped region 415, N-doped regions 416-419, a gate dielectric 421, a gate 422, sidewalls 423, lightly doped regions 424 and 425, and conductive structures 435, 436, 438, and 439. In some embodiments, P-well 411 corresponds to or is similar to P-well PW1 or P-well PW2 described with respect to FIG. 1A . Gate dielectric 421 and gate 422 are similar to gate dielectric 121 and gate 122 described with respect to FIG. Gate 422 corresponds to gate GN of diode-connected NMOS 204 . P-doped region 415 and N-doped regions 416 through 419 correspond to or are similar to the P-doped and N-doped regions described with respect to FIG. 1A . N-doped regions 417 and 418 correspond to source SN and drain DN of diode-connected NMOS 204 . P-doped region 415 is a body contact in P-well 411, similar to body contacts 125 and 145, and is sometimes referred to as a body tap. N-doped regions 416 and 419 are body contacts in substrate 410 or DNW, and are sometimes referred to as substrate taps or well taps. Conductive structures 435, 436, 438, and 439 are respectively located above the P-doped region 415 and the N-doped regions 416, 418, and 419. In some embodiments, each or at least one of the conductive structures 435, 436, 438, and 439 includes one or more of an MD contact structure, a VD via, a VG via, a conductive pattern, and a via, all located below the Mk layer. Conductive structure 435 electrically couples gate GN, source SN, and body tap of diode-connected NMOS 400A. Thus, diode-connected NMOS 400A includes diode 449 at the PN junction between N-doped region 418 and P-well 411. N-doped region 418 corresponds to the cathode of diode 449, and P-well 411 corresponds to the anode of diode 449. In some embodiments, diode 449 corresponds to diode D4. Conductive structure 435 is electrically coupled to P-doped region 415 to provide an electrical connection to the anode of diode 449. Conductive structure 438 is electrically coupled to N-doped region 418 to provide an electrical connection to the cathode of diode 449. In some embodiments, each of conductive structures 435 and 438 is configured to be electrically coupled to the anode or cathode of another PID protection device, a doped well, or substrate 410. For example, when conductive structure 436 or 439 is a substrate tap of substrate 410, the substrate tap is electrically coupled to conductive structure 435 or 438, for example, via a conductive pattern in a metal layer located below the Mk layer. FIG4B is a schematic cross-sectional view of a PID protection device 400B according to some embodiments. In some embodiments, PID protection device 400B corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 400B is a diode-connected PMOS transistor, which, in one or more embodiments, corresponds to diode-connected PMOS 205. PID protection device 400B is referred to herein as diode-connected PMOS 400B. A diode-connected PMOS transistor 400B is formed on a substrate 410. In at least one embodiment, the diode-connected PMOS transistor 400B is formed on a doped region (e.g., a deep well as described with respect to FIG. 1A ). The diode-connected PMOS transistor 400B includes an N-well 461, STI regions 462 , 463 , and 464 of dielectric material, an N-doped region 465 , P-doped regions 466 to 469 , a gate dielectric 471 , a gate 472 , sidewalls 473 , lightly doped regions 474 and 475 , and conductive structures 485 , 486 , 488 , and 489 . In some embodiments, N-well 461 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG. 1A . Gate dielectric 471 and gate 472 are similar to gate dielectric 121 and gate 122 described with respect to FIG. Gate 472 corresponds to gate GP of diode-connected PMOS 205 . N-doped region 465 and P-doped regions 466 through 469 correspond to or are similar to the N-doped and P-doped regions described with respect to FIG. 1A . P-doped regions 467 and 468 correspond to source SP and drain DP of diode-connected PMOS 205 . N-doped region 465 is a body contact located in N-well 461, similar to body contacts 135 and 155, and is sometimes referred to as a body tap. P-doped regions 466 and 469 are body contacts located in substrate 410 or DNW, and are sometimes referred to as substrate taps or well taps. Conductive structures 485, 486, 488, and 489 are respectively located above the N-doped region 465 and the P-doped regions 466, 468, and 469. In some embodiments, each or at least one of the conductive structures 485, 486, 488, and 489 includes one or more of an MD contact structure, a VD via, a VG via, a conductive pattern, and a via, all located below the Mk layer. Conductive structure 485 electrically couples gate GP, source SP, and body tap of diode-connected PMOS 400B. Thus, diode-connected PMOS 400B includes diode 499 at the PN junction between P-doped region 468 and N-well 461. P-doped region 468 corresponds to the anode of diode 499, and N-well 461 corresponds to the cathode of diode 499. In some embodiments, diode 499 corresponds to diode D5. Conductive structure 485 is electrically coupled to N-doped region 465 to provide an electrical connection to the cathode of diode 499. Conductive structure 488 is electrically coupled to P-doped region 468 to provide an electrical connection to the anode of diode 499. In some embodiments, each of conductive structures 485 and 488 is configured to be electrically coupled to the anode or cathode of another PID protection device, a doped well, or substrate 410. For example, when conductive structure 486 or 489 is a substrate tap of substrate 410, the substrate tap is electrically coupled to conductive structure 485 or 488, for example, via a conductive pattern in a metal layer located below the Mk layer. FIG5A is a schematic cross-sectional view of a PID protection device 500A according to some embodiments. In some embodiments, PID protection device 500A corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 500A is a diode-connected NPN BJT, which, in one or more embodiments, corresponds to diode-connected NPN BJT 206. PID protection device 500A is referred to herein as diode-connected NPN BJT 500A. Diode-connected NPN BJT 500A is formed on substrate 510. In some embodiments, substrate 510 corresponds to substrate 110. In at least one embodiment, substrate 510 comprises an N-type substrate. In some embodiments, diode-connected NPN BJT 500A is formed on an N-type doped region (e.g., a DNW as described with respect to FIG. 1A ). The DNW or N-type substrate forms part of diode-connected NPN BJT 500A. Diode-connected NPN BJT 500A further includes a P-well 511, an N-doped region 516, and conductive structures 517 and 518. In some embodiments, P-well 511 corresponds to or is similar to P-well PW1 or P-well PW2 described with respect to FIG. 1A . N-type doped region 516 corresponds to or is similar to the N-type doped region described with respect to FIG. In at least one embodiment, diode-connected NPN BJT 500A further includes one or more body contacts (e.g., substrate taps and / or well taps) for electrically connecting conductive structure 517 to the DNW or substrate 510, and for electrically connecting conductive structure 518 to P-well 511. In some embodiments, each or at least one of conductive structures 517 and 518 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located below the Mk layer. DNW or substrate 510 corresponds to the collector CN of diode-connected NPN BJT 206. P-well 511 corresponds to the base BN of diode-connected NPN BJT 206. N-doped region 516 corresponds to the emitter EN of diode-connected NPN BJT 206. Conductive structure 518 electrically couples base BN and emitter EN of diode-connected NPN BJT 500A. Thus, diode-connected NPN BJT 500A is configured with diode 519 at the PN junction between P-well 511 and DNW or substrate 510. DNW or substrate 510 corresponds to the cathode of diode 519, and P-well 511 corresponds to the anode of diode 519. In some embodiments, diode 519 corresponds to diode D6. Conductive structure 517 provides an electrical connection to the cathode of diode 519. Conductive structure 518 provides an electrical connection to the anode of diode 519. In some embodiments, each of conductive structures 517, 518 is configured to be electrically coupled to an anode or cathode of another PID protection device, doped well, or substrate 510. FIG5B is a schematic cross-sectional view of a PID protection device 500B according to some embodiments. In some embodiments, PID protection device 500B corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 500B is a diode-connected NPN BJT, which, in one or more embodiments, corresponds to diode-connected NPN BJT 207. PID protection device 500B is referred to herein as diode-connected NPN BJT 500B. For simplicity, components of diode-connected NPN BJT 500B that have corresponding components in diode-connected NPN BJT 500A are indicated by the same reference numerals or by incrementing the reference numeral of diode-connected NPN BJT 500A by 10. Compared to diode-connected NPN BJT 500A, diode-connected NPN BJT 500B includes different electrical connections. Specifically, in diode-connected NPN BJT 500B, conductive structure 527 electrically couples base BN and collector CN. Therefore, diode-connected NPN BJT 500B includes diode 529 at the PN junction between P-well 511 and N-doped region 516. N-doped region 516 corresponds to the cathode of diode 529, and P-well 511 corresponds to the anode of diode 529. In some embodiments, diode 529 corresponds to diode D7. Conductive structure 527 provides an electrical connection to the anode of diode 529. Conductive structure 528, located above and in electrical contact with N-doped region 516, provides an electrical connection to the cathode of diode 529. In some embodiments, each or at least one of the conductive structures 527 and 528 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located below the Mk layer. In some embodiments, each of the conductive structures 527 and 528 is configured to be electrically coupled to another PID protection device, a doped well, or an anode or cathode of the substrate 510. FIG6A is a schematic cross-sectional view of a PID protection device 600A according to some embodiments. In some embodiments, PID protection device 600A corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 600A is a diode-connected PNP BJT, which, in one or more embodiments, corresponds to diode-connected PNP BJT 208. PID protection device 600A is referred to herein as diode-connected PNP BJT 600A. Diode-connected PNP BJT 600A is formed on substrate 610. In some embodiments, substrate 610 corresponds to substrate 110. In at least one embodiment, substrate 610 comprises a P-type substrate. In some embodiments, diode-connected PNP BJT 600A is formed on a P-type doped region (e.g., a deep P-well (DPW)). The DPW or P-type substrate forms part of diode-connected PNP BJT 600A. Diode-connected PNP BJT 600A further includes an N-well 611, a P-doped region 616, and conductive structures 617 and 618. In some embodiments, N-well 611 corresponds to or is similar to N-well NW1 or N-well NW2 described with respect to FIG. 1A . P-doped region 616 corresponds to or is similar to the P-doped region described with respect to FIG. In at least one embodiment, diode-connected PNP BJT 600A further includes one or more body contacts (e.g., substrate taps and / or well taps) for electrically connecting conductive structure 617 to the DPW or substrate 610, and for electrically connecting conductive structure 618 to N-well 611. In some embodiments, each or at least one of conductive structures 617 and 618 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located below the Mk layer. DPW or substrate 610 corresponds to the collector CP of diode-connected PNP BJT 208. N-well 611 corresponds to the base BP of diode-connected PNP BJT 208. P-doped region 616 corresponds to the emitter EP of diode-connected PNP BJT 208. Conductive structure 618 electrically couples base BP and emitter EP of diode-connected PNP BJT 600A. Thus, diode-connected PNP BJT 600A is configured with diode 619 at the PN junction between N-well 611 and DPW or substrate 610. DPW or substrate 610 corresponds to the anode of diode 619, and N-well 611 corresponds to the cathode of diode 619. In some embodiments, diode 619 corresponds to diode D8. Conductive structure 617 provides an electrical connection to the anode of diode 619. Conductive structure 618 provides an electrical connection to the cathode of diode 619. In some embodiments, each of conductive structures 617, 618 is configured to be electrically coupled to an anode or cathode of another PID protection device, doped well, or substrate 610. FIG6B is a schematic cross-sectional view of a PID protection device 600B according to some embodiments. In some embodiments, PID protection device 600B corresponds to any PID protection device in any of the PID protection circuits described herein (e.g., PID protection circuits 171-174, 179). PID protection device 600B is a diode-connected PNP BJT, which, in one or more embodiments, corresponds to diode-connected PNP BJT 209. PID protection device 600B is referred to herein as diode-connected PNP BJT 600B. For simplicity, components of diode-connected PNP BJT 600B that have corresponding components in diode-connected PNP BJT 600A are indicated by the same reference numerals or by incrementing the reference numeral of diode-connected PNP BJT 600A by 10. Compared to diode-connected PNP BJT 600A, diode-connected PNP BJT 600B includes different electrical connections. Specifically, in diode-connected PNP BJT 600B, conductive structure 627 electrically couples base BP and collector CP. Therefore, diode-connected PNP BJT 600B includes diode 629 at the PN junction between N-well 611 and P-doped region 616. P-doped region 616 corresponds to the anode of diode 629, and N-well 611 corresponds to the cathode of diode 629. In some embodiments, diode 629 corresponds to diode D9. Conductive structure 627 provides an electrical connection to the cathode of diode 629. Conductive structure 628, located above and in electrical contact with P-doped region 616, provides an electrical connection to the anode of diode 629. In some embodiments, each or at least one of the conductive structures 627 and 628 includes one or more of an MD contact structure, a VD via, a conductive pattern, and a via, all located below the Mk layer. In some embodiments, each of the conductive structures 627 and 628 is configured to be electrically coupled to another PID protection device, a doped well, or an anode or cathode of the substrate 610. 7A-7F include schematic circuit diagrams of PID protection circuits 701-716, 717N-724N, 717P-724P, 725-732 according to some embodiments. In some embodiments, any of the PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 corresponds to any of the PID protection circuits 171-174. For simplicity, corresponding components in Figures 7A-7F are indicated by the same reference numerals as in Figure 2. Although all of the PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are shown in Figures 7A-7F as being electrically coupled between a substrate 751 and a doped well 752 (e.g., an N-well or a P-well), this is for illustrative purposes. In some embodiments, not all of the PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are included in the same IC device. In some embodiments, any two of PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are included in the same IC device and electrically coupled to the same substrate of the IC device, but are correspondingly coupled to two different doped wells above the substrate. In some embodiments, any two of PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are included in different IC devices and are electrically coupled to different substrates and different doped wells. In some embodiments, substrate 751 corresponds to one or more of substrates 110, 310, 410, 510, and 610, and doped well 752 corresponds to one or more of the described N-wells and / or P-wells above the corresponding substrates. In at least one embodiment, one or more diodes in one or more of the PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 correspond to one or more of the PID protection device 203, the P-type diode 300A, and the N-type diode 300B. In at least one embodiment, one or more MOS transistors in one or more of the PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 correspond to one or more of the PID protection devices 204, 205, the diode-connected NMOS 400A, and the diode-connected PMOS 400B. In at least one embodiment, one or more of the BJTs located in one or more of the PID protection circuits 701 to 716, 717N to 724N, 717P to 724P, 725 to 732 corresponds to one or more of the PID protection devices 206 to 209, the diode-connected NPN BJTs 500A, 500B, and the diode-connected PNP BJTs 600A, 600B. FIG. 7A includes a schematic circuit diagram of PID protection circuits 701 - 704 configured by diodes according to some embodiments. The PID protection circuit 701 includes two P-type diodes with cathodes electrically coupled together. The anode of one of the two P-type diodes is electrically coupled to the substrate 751 , and the anode of the other P-type diode is electrically coupled to the doped well 752 . The PID protection circuit 702 includes two N-type diodes with cathodes electrically coupled together. The anode of one of the two N-type diodes is electrically coupled to the substrate 751 , and the anode of the other N-type diode is electrically coupled to the doped well 752 . PID protection circuit 703 includes an N-type diode electrically coupled to substrate 751 and a P-type diode electrically coupled to doped well 752. The cathodes of the N-type diode and the P-type diode are electrically coupled together. The anode of the N-type diode is electrically coupled to substrate 751. The anode of the P-type diode is electrically coupled to doped well 752. PID protection circuit 704 includes a P-type diode electrically coupled to substrate 751 and an N-type diode electrically coupled to doped well 752. The cathodes of the N-type diode and the P-type diode are electrically coupled together. The anode of the P-type diode is electrically coupled to substrate 751. The anode of the N-type diode is electrically coupled to doped well 752. 7A , the diodes in each of the PID protection circuits 701-704 are electrically coupled in a manner similar to that described for the PID protection circuit 171. In some embodiments, the diodes in each of the PID protection circuits 701-704 are electrically coupled in a manner similar to that described for the PID protection circuit 172. PID protection circuits 701 and 702 include diodes of the same type (i.e., two P-type diodes or two N-type diodes) electrically coupled to substrate 751 and doped well 752, and, according to some embodiments, are selected for inclusion in an IC device, application, or circuit design that does not have operating voltage limitations related to the operating voltages of substrate 751 and doped well 752 during operation. PID protection circuits 703 and 704 include diodes of different types (i.e., one P-type diode and one N-type diode) electrically coupled to substrate 751 and doped well 752, and, according to some embodiments, are selected for inclusion in an IC device, application, or circuit design that has operating voltage limitations. In some embodiments, the operating voltage of substrate 751 is the operating voltage of a region outside of doped well 752 and outside of the doped region containing doped well 752. For example, as described with respect to FIG. 1A , the operating voltage of substrate 110 is the operating voltage of region 116 or region 118. In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, the PID protection circuit 703 is selected because in this PID protection circuit, the P-type PID protection device (e.g., a P-type diode) is located on the higher voltage side (e.g., the doped well 752) and the N-type PID protection device (e.g., an N-type diode) is located on the lower voltage side (e.g., the substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, the PID protection circuit 704 is selected because in this PID protection circuit, the P-type PID protection device (e.g., a P-type diode) is located on the higher voltage side (e.g., substrate 751) and the N-type PID protection device (e.g., an N-type diode) is located on the lower voltage side (e.g., doped well 752). FIG. 7B includes a schematic circuit diagram of PID protection circuits 705 - 710 configured by MOS transistors according to some embodiments. The PID protection circuit 705 includes two diode-connected PMOS 205 electrically coupled such that the corresponding diodes D5 have their anodes electrically coupled together. The cathode of one of the two diodes D5 is electrically coupled to the substrate 751. The cathode of the other diode D5 is electrically coupled to the doped well 752. The PID protection circuit 706 includes two diode-connected NMOS 204 electrically coupled such that the cathodes of the corresponding diodes D4 are electrically coupled together. The anode of one of the two diodes D4 is electrically coupled to the substrate 751. The anode of the other diode D4 is electrically coupled to the doped well 752. PID protection circuit 707 includes a diode-connected PMOS 205 electrically coupled to a doped well 752, and a diode-connected NMOS 204 electrically coupled to a substrate 751. Diode-connected PMOS 205 and diode-connected NMOS 204 are electrically coupled such that the cathodes of corresponding diodes D5 and D4 are electrically coupled together. The anode of diode D5 is electrically coupled to doped well 752, and the anode of diode D4 is electrically coupled to substrate 751. PID protection circuit 708 includes a diode-connected PMOS 205 electrically coupled to a doped well 752, and a diode-connected NMOS 204 electrically coupled to a substrate 751. Diode-connected PMOS 205 and diode-connected NMOS 204 are electrically coupled such that the anodes of corresponding diodes D5 and D4 are electrically coupled together. The cathode of diode D5 is electrically coupled to doped well 752, and the cathode of diode D4 is electrically coupled to substrate 751. PID protection circuit 709 includes a diode-connected PMOS 205 electrically coupled to substrate 751, and a diode-connected NMOS 204 electrically coupled to doped well 752. Diode-connected PMOS 205 and diode-connected NMOS 204 are electrically coupled such that the cathodes of corresponding diodes D5 and D4 are electrically coupled together. The anode of diode D5 is electrically coupled to substrate 751, and the anode of diode D4 is electrically coupled to doped well 752. PID protection circuit 710 includes a diode-connected PMOS 205 electrically coupled to substrate 751, and a diode-connected NMOS 204 electrically coupled to doped well 752. Diode-connected PMOS 205 and diode-connected NMOS 204 are electrically coupled such that the anodes of corresponding diodes D5 and D4 are electrically coupled together. The cathode of diode D5 is electrically coupled to substrate 751, and the cathode of diode D4 is electrically coupled to doped well 752. In at least one embodiment in which there are no operating voltage limitations related to the operating voltages of the substrate 751 and the doped well 752 in operation, one of the PID protection circuits 705, 706 is selected because in those PID protection circuits, the two PID protection devices are of the same type, i.e., the two PID protection devices are P-type devices (e.g., two PMOS) or the two PID protection devices are N-type devices (e.g., two NMOS). In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 707, 708 is selected because in those PID protection circuits, a P-type PID protection device (e.g., PMOS) is located on the higher voltage side (e.g., doped well 752) and an N-type PID protection device (e.g., NMOS) is located on the lower voltage side (e.g., substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, one of the PID protection circuits 709, 710 is selected because in those PID protection circuits, a P-type PID protection device (e.g., PMOS) is located on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., NMOS) is located on the lower voltage side (e.g., doped well 752). FIG. 7C includes a schematic circuit diagram of PID protection circuits 711 - 716 configured by BJTs according to some embodiments. PID protection circuit 711 includes diode-connected NPN BJT 206 electrically coupled to substrate 751, and diode-connected NPN BJT 207 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected NPN BJT 207 are electrically coupled such that the cathodes of corresponding diodes D6 and D7 are electrically coupled together. The anode of diode D6 is electrically coupled to substrate 751, and the anode of diode D7 is electrically coupled to doped well 752. PID protection circuit 712 includes diode-connected PNP BJT 209 electrically coupled to substrate 751, and diode-connected PNP BJT 208 electrically coupled to doped well 752. Diode-connected PNP BJT 208 and diode-connected PNP BJT 209 are electrically coupled such that the anodes of corresponding diodes D8 and D9 are electrically coupled together. The cathode of diode D9 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752. PID protection circuit 713 includes a diode-connected NPN BJT 206 electrically coupled to substrate 751 and a diode-connected PNP BJT 209 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected PNP BJT 209 are electrically coupled such that the cathodes of corresponding diodes D6 and D9 are electrically coupled together. The anode of diode D6 is electrically coupled to substrate 751. The anode of diode D9 is electrically coupled to doped well 752. PID protection circuit 714 includes a diode-connected NPN BJT 207 electrically coupled to substrate 751 and a diode-connected PNP BJT 208 electrically coupled to doped well 752. Diode-connected NPN BJT 207 and diode-connected PNP BJT 208 are electrically coupled such that the anodes of corresponding diodes D7 and D8 are electrically coupled together. The cathode of diode D7 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752. PID protection circuit 715 includes a diode-connected PNP BJT 209 electrically coupled to substrate 751, and a diode-connected NPN BJT 206 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected PNP BJT 209 are electrically coupled such that the cathodes of corresponding diodes D6 and D9 are electrically coupled together. The anode of diode D9 is electrically coupled to substrate 751. The anode of diode D6 is electrically coupled to doped well 752. PID protection circuit 716 includes a diode-connected PNP BJT 208 electrically coupled to substrate 751 and a diode-connected NPN BJT 207 electrically coupled to doped well 752. Diode-connected NPN BJT 207 and diode-connected PNP BJT 208 are electrically coupled such that the anodes of corresponding diodes D7 and D8 are electrically coupled together. The cathode of diode D8 is electrically coupled to substrate 751. The cathode of diode D7 is electrically coupled to doped well 752. In at least one embodiment in which there are no operating voltage limitations related to the operating voltages of the substrate 751 and the doped well 752 in operation, one of the PID protection circuits 711, 712 is selected because in those PID protection circuits, the two PID protection devices are of the same type, i.e., the two PID protection devices are P-type devices (e.g., two PNP BJTs) or the two PID protection devices are N-type devices (e.g., two NPN BJTs). In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 713, 714 is selected because in those PID protection circuits, a P-type PID protection device (e.g., a PNP BJT) is located on the higher voltage side (e.g., the doped well 752) and an N-type PID protection device (e.g., an NPN BJT) is located on the lower voltage side (e.g., the substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, one of the PID protection circuits 715, 716 is selected because in those PID protection circuits, a P-type PID protection device (e.g., a PNP BJT) is located on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., an NPN BJT) is located on the lower voltage side (e.g., doped well 752). FIG. 7D includes a schematic circuit diagram of PID protection circuits 717N to 720N configured with N-type diodes and MOS transistors according to some embodiments. PID protection circuit 717N includes an N-type diode electrically coupled to substrate 751 and a diode-connected PMOS 205 electrically coupled to a doped well 752. The anode of the N-type diode and the corresponding N-type diode D5 of the diode-connected PMOS 205 are electrically coupled. The cathode of the N-type diode is electrically coupled to substrate 751. The cathode of N-type diode D5 is electrically coupled to doped well 752. PID protection circuit 718N includes an N-type diode electrically coupled to a doped well 752 and a diode-connected NMOS 204 electrically coupled to a substrate 751. The cathode of the N-type diode is electrically coupled to a corresponding N-type diode D4 of the diode-connected NMOS 204. The anode of the N-type diode is electrically coupled to the doped well 752. The anode of the N-type diode D4 is electrically coupled to the substrate 751. PID protection circuit 719N includes an N-type diode electrically coupled to a doped well 752 and a diode-connected PMOS 205 electrically coupled to a substrate 751. The anode of the N-type diode is electrically coupled to a corresponding N-type diode D5 of the diode-connected PMOS 205. The cathode of the N-type diode is electrically coupled to the doped well 752. The cathode of the N-type diode D5 is electrically coupled to the substrate 751. PID protection circuit 720N includes an N-type diode electrically coupled to substrate 751 and a diode-connected NMOS 204 electrically coupled to a doped well 752. The cathode of the N-type diode and a corresponding N-type diode D4 of diode-connected NMOS 204 are electrically coupled. The anode of the N-type diode is electrically coupled to substrate 751. The anode of N-type diode D4 is electrically coupled to doped well 752. According to some embodiments, FIG. 7D further includes a schematic circuit diagram of PID protection circuits 721N to 724N configured by N-type diodes and BJTs. PID protection circuit 721N includes an N-type diode electrically coupled to a doped well 752 and a diode-connected NPN BJT 206 electrically coupled to a substrate 751. The cathode of the N-type diode and the corresponding N-type diode D6 of the diode-connected NPN BJT 206 are electrically coupled. The anode of the N-type diode is electrically coupled to the doped well 752. The anode of the N-type diode D6 is electrically coupled to the substrate 751. PID protection circuit 722N includes an N-type diode electrically coupled to a doped well 752 and a diode-connected NPN BJT 207 electrically coupled to a substrate 751. The N-type diode and a corresponding N-type diode D7 of the diode-connected NPN BJT 207 are electrically coupled to each other. The cathode of the N-type diode is electrically coupled to the doped well 752. The cathode of N-type diode D7 is electrically coupled to the substrate 751. PID protection circuit 723N includes an N-type diode electrically coupled to substrate 751 and a diode-connected PNP BJT 208 electrically coupled to a doped well 752. The anode of the N-type diode and the corresponding N-type diode D8 of the diode-connected PNP BJT 208 are electrically coupled. The cathode of the N-type diode is electrically coupled to substrate 751. The cathode of N-type diode D8 is electrically coupled to doped well 752. PID protection circuit 724N includes an N-type diode electrically coupled to substrate 751 and a diode-connected PNP BJT 209 electrically coupled to a doped well 752. The cathode of the N-type diode and the corresponding N-type diode D9 of the diode-connected PNP BJT 209 are electrically coupled. The anode of the N-type diode is electrically coupled to substrate 751. The anode of N-type diode D9 is electrically coupled to doped well 752. In at least one embodiment in which there are no operating voltage limitations related to the operating voltages of the substrate 751 and the doped well 752 during operation, one of the PID protection circuits 718N, 720N, 721N, 722N is selected because in these PID protection circuits, the two PID protection devices are of the same type, i.e., both PID protection devices are N-type devices (e.g., an N-type diode and an NMOS, or an N-type diode and an NPN BJT). In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 717N, 723N, and 724N is selected because in these PID protection circuits, a P-type PID protection device (e.g., a PMOS or PNP BJT) is located on the higher voltage side (e.g., the doped well 752), and an N-type PID protection device (e.g., an N-type diode) is located on the lower voltage side (e.g., the substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, the PID protection circuit 719N is selected because in this PID protection circuit, a P-type PID protection device (e.g., a PMOS) is located on the higher voltage side (e.g., the substrate 751), while an N-type PID protection device (e.g., an N-type diode) is located on the lower voltage side (e.g., the doped well 752). 7E includes schematic circuit diagrams of PID protection circuits 717P to 720P configured with P-type diodes and MOS transistors according to some embodiments. FIG7E further includes schematic circuit diagrams of PID protection circuits 721P to 724P configured with P-type diodes and BJTs according to some embodiments. The PID protection circuits 717P to 724P correspond to the PID protection circuits 717N to 724N, except that the N-type diodes in the PID protection circuits 717N to 724N are replaced by P-type diodes in the PID protection circuits 717P to 724P. In at least one embodiment in which there are no operating voltage limitations related to the operating voltages of the substrate 751 and the doped well 752 during operation, one of the PID protection circuits 717P, 719P, 723P, 724P is selected because in these PID protection circuits, the two PID protection devices are of the same type, i.e., both PID protection devices are P-type devices (e.g., a P-type diode and a PMOS, or a P-type diode and a PNP BJT). In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 718P, 721P, and 722P is selected because in these PID protection circuits, a P-type PID protection device (e.g., a P-type diode) is located on the higher voltage side (e.g., the doped well 752) and an N-type PID protection device (e.g., an NMOS or NPN BJT) is located on the lower voltage side (e.g., the substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, the PID protection circuit 720P is selected because in this PID protection circuit, a P-type PID protection device (e.g., a P-type diode) is located on the higher voltage side (e.g., substrate 751) and an N-type PID protection device (e.g., NMOS) is located on the lower voltage side (e.g., doped well 752). FIG. 7F includes a schematic circuit diagram of PID protection circuits 725 - 732 configured with BJTs and MOS transistors according to some embodiments. PID protection circuit 725 includes a diode-connected NPN BJT 207 electrically coupled to substrate 751 and a diode-connected PMOS 205 electrically coupled to doped well 752. Diode-connected NPN BJT 207 and diode-connected PMOS 205 are electrically coupled such that the anodes of corresponding diodes D7 and D5 are electrically coupled together. The cathode of diode D7 is electrically coupled to substrate 751. The cathode of diode D5 is electrically coupled to doped well 752. PID protection circuit 726 includes a diode-connected NPN BJT 206 electrically coupled to substrate 751 and a diode-connected PMOS 205 electrically coupled to doped well 752. Diode-connected NPN BJT 206 and diode-connected PMOS 205 are electrically coupled such that the cathodes of corresponding diodes D6 and D5 are electrically coupled together. The anode of diode D6 is electrically coupled to substrate 751. The anode of diode D5 is electrically coupled to doped well 752. PID protection circuit 727 includes a diode-connected NMOS 204 electrically coupled to substrate 751 and a diode-connected PNP BJT 208 electrically coupled to doped well 752. Diode-connected NMOS 204 and diode-connected PNP BJT 208 are electrically coupled such that the anodes of corresponding diodes D4 and D8 are electrically coupled together. The cathode of diode D4 is electrically coupled to substrate 751. The cathode of diode D8 is electrically coupled to doped well 752. PID protection circuit 728 includes a diode-connected NMOS 204 electrically coupled to substrate 751 and a diode-connected PNP BJT 209 electrically coupled to doped well 752. Diode-connected NMOS 204 and diode-connected PNP BJT 209 are electrically coupled such that the cathodes of corresponding diodes D4 and D9 are electrically coupled together. The anode of diode D4 is electrically coupled to substrate 751. The anode of diode D9 is electrically coupled to doped well 752. PID protection circuit 729 includes a diode-connected PMOS 205 electrically coupled to substrate 751 and a diode-connected NPN BJT 207 electrically coupled to doped well 752. Diode-connected PMOS 205 and diode-connected NPN BJT 207 are electrically coupled such that the anodes of corresponding diodes D5 and D7 are electrically coupled together. The cathode of diode D5 is electrically coupled to substrate 751. The cathode of diode D7 is electrically coupled to doped well 752. PID protection circuit 730 includes a diode-connected PMOS 205 electrically coupled to substrate 751 and a diode-connected NPN BJT 206 electrically coupled to doped well 752. Diode-connected PMOS 205 and diode-connected NPN BJT 206 are electrically coupled such that the cathodes of corresponding diodes D5 and D6 are electrically coupled together. The anode of diode D5 is electrically coupled to substrate 751. The anode of diode D6 is electrically coupled to doped well 752. PID protection circuit 731 includes a diode-connected PNP BJT 208 electrically coupled to substrate 751, and a diode-connected NMOS 204 electrically coupled to doped well 752. Diode-connected NMOS 204 and diode-connected PNP BJT 208 are electrically coupled such that the anodes of corresponding diodes D4 and D8 are electrically coupled together. The cathode of diode D8 is electrically coupled to substrate 751. The cathode of diode D4 is electrically coupled to doped well 752. PID protection circuit 732 includes a diode-connected PNP BJT 209 electrically coupled to substrate 751, and a diode-connected NMOS 204 electrically coupled to doped well 752. Diode-connected PNP BJT 209 and diode-connected NMOS 204 are electrically coupled such that the cathodes of corresponding diodes D9 and D4 are electrically coupled together. The anode of diode D9 is electrically coupled to substrate 751. The anode of diode D4 is electrically coupled to doped well 752. In at least one embodiment where the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751, one of the PID protection circuits 725 to 728 is selected because in those PID protection circuits, a P-type PID protection device (e.g., a PMOS or a PNP BJT) is located on the higher voltage side (e.g., the doped well 752) and an N-type PID protection device (e.g., an NMOS or an NPN BJT) is located on the lower voltage side (e.g., the substrate 751). In at least one embodiment where the operating voltage of the doped well 752 is lower than the operating voltage of the substrate 751, one of the PID protection circuits 729 to 732 is selected because in those PID protection circuits, a P-type PID protection device (e.g., a PMOS or a PNP BJT) is located on the higher voltage side (e.g., the substrate 751) and an N-type PID protection device (e.g., an NMOS or an NPN BJT) is located on the lower voltage side (e.g., the doped well 752). In at least one embodiment, the PID protection provided by a PID protection device is related to its resistance to leakage current. That is, a PID protection device with a lower resistance to leakage current provides better PID protection than a PID protection device with a higher resistance to leakage current. In some embodiments, a BJT has a lower resistance to leakage current (i.e., better PID protection) than a diode, which in turn has a lower resistance to leakage current (i.e., better PID protection) than a MOS transistor. However, a MOS transistor occupies a smaller chip area than a diode, which in turn occupies a smaller chip area than a BJT. In some embodiments, PID protection circuits 711-716 configured with BJTs provide better PID protection than PID protection circuits 701-704 configured with diodes, but occupy a larger chip area. Furthermore, PID protection circuits 701-704 configured with diodes provide better PID protection than PID protection circuits 705-710 configured with MOS transistors, but occupy a larger chip area. In at least one embodiment, when selecting one or more PID protection circuits for an IC device, a balance between the desired level of PID protection and the die area occupied by the PID protection circuit (i.e., die area unavailable for functional circuitry) is a design consideration. For example, in applications or circuit designs where strong PID protection is a more important design consideration than the die area occupied by the PID protection circuit, one or more of the PID protection circuits 711-716 configured with BJTs are selected for inclusion in the IC device to be designed and / or manufactured. For another example, in applications or circuit designs where minimizing the die area occupied by the PID protection circuit is a more important design consideration, one or more of the PID protection circuits 705-710 configured with MOS transistors are selected for inclusion in the IC device. In yet another example where PID protection and die area occupied by the PID protection circuit are approximately equally important design considerations, one or more of the PID protection circuits 701-704 configured with diodes are selected for inclusion in the IC device. In some embodiments, another design consideration for selecting a particular PID protection circuit for an IC device includes operating voltage limitations, or the lack thereof. As described herein, the operating voltage limitations are related to the operating voltage of the substrate and the doped wells located above the substrate. For example, in the absence of operating voltage limitations, one or more of PID protection circuits 701-702, 705-706, 711-712, 718N, 720N, 721N, 722N, 717P, 719P, 723P, and 724P (sometimes referred to herein as a first set of PID protection circuits) are selected. For another example, when the operating voltage of the doped wells is higher than the operating voltage of the substrate, one or more of PID protection circuits 703, 707-708, 713-714, 717N, 723N, 724N, 718P, 721P, 722P, and 725-728 (sometimes referred to herein as a second set of PID protection circuits) are selected to discharge charge in the doped wells to the substrate. In yet another example where the operating voltage of the doped well is lower than the operating voltage of the substrate, one or more of the PID protection circuits 704, 709-710, 715-716, 719N, 720P, 729-732 (sometimes referred to herein as a third set of PID protection circuits) are selected for discharging the charge in the doped well to the substrate. In some embodiments, another design consideration for selecting a particular PID protection circuit includes minimizing the number of masks used in fabrication. To this end, in one or more embodiments, one or more "hybrid solutions" are selected, i.e., PID protection circuits 717N to 724N, 717P to 724P, and 725 to 732, each configured from a different type of PID protection device. As described herein, PID protection devices and circuits according to some embodiments include many features similar to those of functional circuits, such as doped regions, doped wells, substrate taps, well taps, vias, interconnects, or the like. Therefore, in one or more embodiments, the PID protection circuit can be fabricated together with the functional circuitry of an IC device using the same masks or with a minimal number of additional masks. In some embodiments, one or more of the "hybrid" PID protection circuits 717N to 724N, 717P to 724P, and 725 to 732 are selected based on the type of semiconductor device in which the functional circuits in the wafer region where the PID protection circuits are to be formed and / or the layout of the functional circuits in or around the wafer region to minimize the number of masks added. Other considerations for determining which PID protection circuit configuration to use to discharge a particular doping well into the substrate are also within the scope of various embodiments. PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are examples of PID protection circuits that can be configured from various combinations of PID protection devices 203-209. PID protection circuits 701-716, 717N-724N, 717P-724P, and 725-732 are not intended to constitute an exhaustive list of all PID protection circuits that can be configured from PID protection devices 203-209. Other PID protection circuit configurations are also within the scope of various embodiments. For example, in one or more embodiments, PID protection circuits each including more than two of the PID protection devices 203-209 can be configured, as described for PID protection circuit 179. In at least one embodiment, one or more of the advantages described herein can be achieved by an IC device that includes one or more of the described PID protection circuits. FIG8A is a flow chart of a method 800A for manufacturing an IC device according to some embodiments. In some embodiments, the IC device corresponds to one or more of the IC devices described with respect to FIG1A-FIG1B , as well as any IC device including the PID protection device and / or PID protection circuit described with respect to FIG2-FIG7F . In some embodiments, method 800A is performed during a design phase. In at least one embodiment, method 800A is performed by a processor of a computer system. The computer system further includes a non-transitory computer-readable storage medium coupled to the processor and configured to store computer-executable instructions that, when executed by the processor, cause the processor to perform method 800A. An example of such a computer system is an electronic design automation (EDA) system. At operation 805, a determination is made as to whether operating voltage limitations exist for the substrate and the doped well located above the substrate. For example, as described with respect to FIG. 7A through FIG. 7F , a determination is made as to whether operating voltage limitations exist for substrate 751 and doped well 752 located above the substrate. In some embodiments, this determination is made based on the circuit design of the IC device and / or the layout of the IC device. At operation 810, a PID protection circuit to be coupled between the doped well and the substrate is selected from the first group of PID protection circuits in response to a negative determination (i.e., "No") indicating that there is no operating voltage limitation associated with the substrate and the doped well at operation 805. For example, as described with respect to Figures 7A to 7F, in response to a determination that there is no operating voltage limitation associated with the substrate 751 and the doped well 752, a PID protection circuit to be coupled between the substrate 751 and the doped well 752 is selected from the first group of PID protection circuits including PID protection circuits 701-702, 705-706, 711-712, 718N, 720N, 721N, 722N, 717P, 719P, 723P, and 724P. At operation 815, in response to a positive determination (i.e., "yes") at operation 805 indicating that there are operating voltage limitations associated with the substrate and the doped well, a determination is made as to whether the operating voltage of the doped well is higher than the operating voltage of the substrate. For example, as described with respect to Figures 7A to 7F, a determination is made as to whether the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751. At operation 820, a PID protection circuit to be coupled between the doped well and the substrate is selected from a second group of PID protection circuits different from the first group of PID protection circuits in response to a positive determination (i.e., "yes") at operation 815 indicating that the operating voltage of the doped well is higher than the operating voltage of the substrate. For example, as described with respect to Figures 7A to 7F, a PID protection circuit to be coupled between the substrate 751 and the doped well 752 is selected from the second group of PID protection circuits including PID protection circuits 703, 707-708, 713-714, 717N, 723N, 724N, 718P, 721P, 722P, 725-728 in response to a determination that the operating voltage of the doped well 752 is higher than the operating voltage of the substrate 751. At operation 830, a PID protection circuit to be coupled between the doped well and the substrate is selected from a third group of PID protection circuits, different from the first and second groups of PID protection circuits, in response to a negative determination (i.e., "No") at operation 815 indicating that the operating voltage of the doped well is not higher than the operating voltage of the substrate. For example, as described with respect to Figures 7A to 7F, a PID protection circuit to be coupled between the substrate 751 and the doped well 752 is selected from the third group of PID protection circuits, including PID protection circuits 704, 709 to 710, 715 to 716, 719N, 720P, and 729 to 732, in response to a determination that the operating voltage of the doped well 752 is not higher than the operating voltage of the substrate 751. In some embodiments, a PID protection circuit to be coupled between substrate 751 and doped well 752 is selected from one of the first through third groups based on one or more additional considerations as described herein. For example, such additional considerations include, but are not limited to, the desired level of PID protection, the wafer area occupied by the PID protection circuit, the type and / or layout of adjacent semiconductor devices for mask minimization, or the like. In some embodiments, when a PID protection circuit is selected from one of the first through third groups, the process proceeds to subsequent operations (e.g., for manufacturing an IC device). FIG8B is a flow chart of a method 800B for manufacturing an IC device according to some embodiments. In some embodiments, the method 800B can be used to manufacture one or more of the IC devices described with respect to FIG1A-FIG1B , as well as any IC device including the PID protection device and / or PID protection circuit described with respect to FIG2-FIG7F . At operation 840, dopant implantation is performed to form a first doped well, a second doped well, a first PN junction, and a second PN junction over the substrate. In some embodiments, as described with respect to FIG. 1A , the first doped well comprises either a P-well PW1 or an N-well NW1, and the second doped well comprises either a P-well PW2 or an N-well NW2. In some embodiments, as described with respect to one or more of FIG. 3A to FIG. 6B , the first PN junction or the second PN junction comprises any PN junction of any of configuration diodes 319, 329, 339, 349, 449, 499, 519, 529, 619, and 629. For example, the first PN junction corresponds to one of diodes 175 and 176, and the second PN junction corresponds to the other of diodes 175 and 176. For another example, the first PN junction corresponds to one of the diodes 177 , 178 , and the second PN junction corresponds to the other of the diodes 177 , 178 . At operation 845, a gate is deposited and patterned over the first doped well. In examples, as described with respect to FIG. 1A , the gate comprises gate 122 when the first doped well comprises P-well PW1 or gate 132 when the first doped well comprises N-well NW1. At operations 850 and 855 , a redistribution structure is fabricated by depositing and patterning various metal layers and via layers to form interconnects on the substrate. In this example, the redistribution structure 160 is fabricated on the substrate 110 as described with respect to FIG. 1A . At operation 850, the rewiring structure is fabricated to form one or more interconnects that electrically couple the first PN junction and the second PN junction in series and in a dual inverted junction configuration between another region of the substrate and one of the first and second doped wells. In one example, as described with respect to FIG1A , the first and second PN junctions include diodes 175 and 176 electrically coupled in series between another region 116 of the substrate 110 and the first doped well, serving as the P-well PW1. Diodes 175 and 176 are electrically coupled in a dual inverted junction configuration, in which the cathodes (e.g., N-type regions) of diodes 175 and 176 are coupled together. In another example, as described with respect to FIG1A , the first and second PN junctions include diodes 177 and 178 electrically coupled in series between another region 118 of the substrate 110 and the second doped well, serving as the N-well NW2. Diodes 177 and 178 are electrically coupled in a dual reverse-junction configuration, in which the anodes (e.g., P-type regions) of diodes 177 and 178 are coupled together. In some embodiments, as a result of operation 850, charge accumulated in the first doped well or the second doped well is discharged to the substrate via the dual reverse-junction configuration, thereby avoiding or at least mitigating PID issues in subsequent manufacturing operations. Following operation 850, at operation 855, a redistribution structure is fabricated to form an interconnect that electrically couples a gate located above the first doped well to a second doped well. In one example, as described with respect to FIG. 1A , interconnect 163 is formed to electrically couple gate 122 or gate 132 located above the first doped well (i.e., P-well PW1 or N-well NW1) to the second doped well (i.e., P-well PW2 or N-well NW2). Interconnect 163 is formed in a higher Mk layer than the electrical connections or interconnects described with respect to operation 850. In other words, interconnect 163 is formed after a dual back-contact junction (e.g., PID protection circuit 171 or PID protection circuit 172) has been formed and electrically coupled between substrate 110 and either the first doped well of a potential PID victim or the second doped well of a potential PID aggressor. Since the charge accumulated in the first doped well or the second doped well has been discharged to the substrate as described with respect to operation 850, PID problems associated with the formation of interconnect 163 and / or subsequent interconnects are avoided or at least mitigated. In at least one embodiment, one or more of the advantages described herein can be achieved by fabricating an IC device using one or more of methods 800A and 800B. The described methods include example operations, but unless otherwise specifically stated herein, the operations do not necessarily need to be performed in the order shown. Operations may be added, replaced, changed in order, and / or deleted, as appropriate, consistent with the spirit and scope of the disclosed embodiments. Embodiments incorporating different features and / or different embodiments are within the scope of the disclosed embodiments and will be apparent to those skilled in the art after reading this disclosure. In some embodiments, an integrated circuit (IC) device includes: a substrate; a first semiconductor device located in a first doped region in the substrate; and a second semiconductor device located in a second doped region in the substrate. The first doped region and the second doped region are different from each other. The gate of the first semiconductor device is electrically coupled to the source / drain of the second semiconductor device. The IC device further includes: a first protection device configured as one of a first forward diode and a first reverse diode; and a second protection device configured as the other of the first forward diode and the first reverse diode. The first forward diode and the first reverse diode are electrically coupled in series between the substrate and a doped well. The doped well is located in the first doped region and the source / drain of the first semiconductor device is located in the doped well. Alternatively, the doped well is located in the second doped region and the source / drain of the second semiconductor device is located in the doped well. In some embodiments, an integrated circuit (IC) device includes: a substrate; a first doped well located above the substrate; a first diode located above the substrate; a second diode located above the substrate; a first electrical connection electrically coupling an anode or cathode of the first diode to the first doped well; and a second electrical connection electrically coupling an anode or cathode of the second diode to the substrate. The anode of the first diode and the anode of the second diode are electrically coupled to each other, or the cathode of the first diode and the cathode of the second diode are electrically coupled to each other. In a method of manufacturing an integrated circuit (IC) device according to some embodiments, dopant implantation is performed to form a first doped well, a second doped well, a first PN junction, and a second PN junction over a substrate. The substrate includes a further region located outside the first doped well and the second doped well. A gate is deposited over the first doped well and patterned. An interconnect is deposited over the substrate and patterned to electrically couple the first PN junction and the second PN junction in series between the further region of the substrate and one of the first doped well and the second doped well, and then electrically couple the gate over the first doped well to the second doped well. A P-type region of the first PN junction and a P-type region of the second PN junction are electrically coupled to each other, or an N-type region of the first PN junction and an N-type region of the second PN junction are electrically coupled to each other. The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. 100A, 100B: Integrated circuit (IC) device 110, 310, 410, 510, 610, 751: Substrate 111: Front surface 112: Back surface 116, 118: Region 120: Gate structure 121, 131, 421, 471: Gate dielectric 122, 132, 422, 472, GN, GP: Gate 123, 124, 133, 134, 143, 144, 153 , 154, 180: source / drain 125, 135, 145, 155: body contact 146, 147: forward diode / diode 148, 149: reverse diode / diode 156, 158, 165, 166: anode 160: redistribution structure 161, 162, 317, 318, 327, 328, 337, 338, 347, 348, 357, 435, 436, 438, 439, 485, 486, 488, 489, 517, 518, 527, 528, 617, 618, 627, 628: Conductive structure 163: Internal connection 167, 168: Cathode 171, 172: PID protection circuit / protection circuit 173, 174, 179, 300E: PID protection circuit 175, 176, 177, 178: Diode / PID protection device 181, 187, 195: NMOS transistors 182, 186, 196: PMOS transistors 183: Electrical connection 184, 185, 198, 199, 319, 329, 339, 349, 449, 499, 519, 529, 619, 629, D3, D4, D5, D6, D7, D8, D9: Diodes 188: NPN bipolar junction transistor (BJT) 189, 190: PNP bipolar junction transistor (BJT) 191, 192, 193: Junction 194: Local PID protection circuit 197: Cross-well PID protection circuit 203: PID protection device 204, 400A: Diode-connected NMOS / PID protection device 205, 400B: Diode-connected PMOS / PID protection device 206, 207, 500A, 500B: PID protection device / diode-connected NPN BJT 208, 209, 600A, 600B: PID protection device / diode-connected PNP BJT 300A: P-type diode / PID protection device 300B: N-type diode / PID protection device 300C, 300D: PID protection devices 311, 331, 461, 611, NW1, NW2: N-wells 315, 326, 335, 346, 415, 466, 467, 468, 469, 616: P-doped regions 316, 325: N-doped regions 321, 341, 411, 511, PW1, PW2: P-wells336, 345, 416, 417, 418, 419, 465, 516: N-doped regions 358: PN junction 359: arrows 412, 413, 414, 462, 463, 464: shallow trench isolation (STI) regions 423, 473: sidewalls 424, 425, 474, 475: lightly doped regions 701, 702, 703, 704, 705 05, 706, 707, 708, 709, 710, 711, 712, 713, 714, 715, 716, 717N, 717P, 718N, 718P , 719N, 719P, 720N, 720P, 721N, 721P, 722N, 722P, 723N, 723P, 724N, 724P, 725, 72 6, 727, 728, 729, 730, 731, 732: PID protection circuit 752: Doped well 800A, 800B: Method 805, 810, 815, 820, 830, 840, 845, 850, 855: Operation BN, BP: Base CN, CP: Collector DN, DP: Drain DNW-A, DNW-B: Doped region EN, EP: Emitter M0, M1, M2, M3, Mi, Mj, Mk: Layer / Metal layer NBL-A: First doped region / doped region NBL-B: Second doped region / doped region Mn: Metal layer N, NW, P: Marking N1, N2, P1, P2: Transistor PW: Marking / P well SN, SP: Source V0, V1: Via layer / via / layer V2~Vn: Via layer Z: Axis The various aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG1A is a schematic cross-sectional view of an IC device according to some embodiments. FIG1B is a schematic circuit diagram of an IC device according to some embodiments. FIG2 includes schematic circuit diagrams of various protection devices according to some embodiments. FIG3A to FIG3E, FIG4A to FIG4B, FIG5A to FIG5B, and FIG6A to FIG6B are schematic cross-sectional views of various protection devices according to some embodiments. FIG7A to FIG7F include schematic circuit diagrams of various protection circuits according to some embodiments. FIG8A to FIG8B are flow charts of various methods of manufacturing IC devices according to some embodiments. 100A: Integrated Circuit (IC) Device 110: Base 111: Positive 112: Back 116, 118: District 120: Gate structure 121, 131: Gate dielectric 122, 132: Gate 123, 124, 133, 134, 143, 144, 153, 154: Source / Drain 125, 135, 145, 155: body contact parts 160: Rewiring structure 161, 162: conductive structure 163:Internal connection 165, 166: Anode 167, 168: cathode 171, 172: PID protection circuit / protection circuit 175, 176, 177, 178: Diode / PID protection device DNW-A, DNW-B: doped area M0, M1, M2, M3, Mi, Mj, Mk: layer / metal layer NBL-A: first doping region / doping region NBL-B: Second doping region / doping region Mn: Metal layer N, P: mark N1, N2, P1, P2: transistors NW1, NW2: N well PW1, PW2: P well V0, V1: via layer / via / layer V2~Vn: through-hole layer Z: axis

Claims

1. An integrated circuit (IC) device, comprising: Base; A first semiconductor device is located in a first doped region within the substrate; A second semiconductor device is located in a second doped region in the substrate, wherein the first doped region and the second doped region are different from each other, and the gate of the first semiconductor device is electrically coupled to the source / drain of the second semiconductor device; a first protection device is configured as one of a first positive diode and a first negative diode; And a second protection device, configured as the other of the first positive diode and the first negative diode, the first positive diode and the first negative diode being electrically coupled in series between the substrate and the doped well, wherein the doped well is located in the first doped region and the source / drain of the first semiconductor device is located in the doped well, or the doped well is located in the second doped region and the source / drain of the second semiconductor device is located in the doped well.

2. The integrated circuit device as claimed in claim 1, wherein each of the first protection device and the second protection device comprises at least one of the following: a P-type diode, an N-type diode, a diode-connected metal-oxide-semiconductor (MOS) transistor, or a diode-connected bipolar junction transistor (BJT).

3. The integrated circuit arrangement of claim 1, wherein the doped well is configured to receive a voltage higher than that of the substrate, and one of the following is true: the first protection device includes a P-type diode having an anode electrically coupled to the doped well, and the second protection device includes an N-type diode having an anode electrically coupled to the substrate; the first protection device includes a diode-connected P-channel metal-oxide-semiconductor (PMOS) transistor electrically coupled to the doped well, and the second protection device includes a diode-connected N-channel metal-oxide-semiconductor (NMOS) transistor electrically coupled to the substrate; or the first protection device includes a diode-connected PNP bipolar junction transistor (BJT), and the second protection device includes a diode-connected NPN bipolar junction transistor; or the first protection device includes a diode-connected P-channel metal-oxide-semiconductor (PMOS) transistor electrically coupled to the doped well, and the second protection device includes a diode having a cathode electrically coupled to the substrate; the first protection device includes a diode having an anode electrically coupled to the doped well. The first protection device includes a diode having a cathode electrically coupled to the doped well, and the second protection device includes a diode-connected P-channel metal-oxide-semiconductor (NMOS) transistor electrically coupled to the substrate; or the first protection device includes a diode-connected NMOS transistor electrically coupled to the doped well and the second protection device includes a diode having an anode electrically coupled to the substrate; or the first protection device includes a diode-connected PMOS transistor electrically coupled to the doped well and the second protection device includes a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the substrate; or the first protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the doped well and the second protection device includes a diode-connected NMOS transistor electrically coupled to the substrate.

4. The integrated circuit arrangement of claim 1, wherein the doped well is configured to receive a voltage lower than that of the substrate, and one of the following is true: the first protection device includes an N-type diode having an anode electrically coupled to the doped well, and the second protection device includes a P-type diode having an anode electrically coupled to the substrate; the first protection device includes a diode-connected N-channel metal-oxide-semiconductor (NMOS) transistor electrically coupled to the doped well, and the second protection device includes a diode-connected P-channel metal-oxide-semiconductor (PMOS) transistor electrically coupled to the substrate; or the first protection device includes a diode-connected NPN bipolar junction transistor (BJT), and the second protection device includes a diode-connected PNP bipolar junction transistor; or the first protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the substrate. The first protection device includes a diode connected to a doped well, and the second protection device includes a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the substrate; or the first protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the doped well, and the second protection device includes a diode electrically coupled to the substrate; or the first protection device includes a diode-connected NPN bipolar junction transistor (BJT) electrically coupled to the doped well, and the second protection device includes a diode-connected P-channel metal-oxide-semiconductor (PMOS) transistor electrically coupled to the substrate; or the first protection device includes a diode-connected N-channel metal-oxide-semiconductor (NMOS) transistor electrically coupled to the doped well, and the second protection device includes a diode-connected PNP bipolar junction transistor electrically coupled to the substrate.

5. The integrated circuit device as claimed in claim 1, wherein both the first protection device and the second protection device are: a P-type diode, an N-type diode, a diode-connected N-channel metal-oxide-semiconductor (NMOS) transistor, a diode-connected P-channel metal-oxide-semiconductor (PMOS) transistor, a diode-connected NPN bipolar junction transistor (BJT), or a diode-connected PNP bipolar junction transistor.

6. The integrated circuit device of claim 1, wherein the doped well is a first doped well located in a second doped region, the second doped region further comprising a second doped well having a conductivity opposite to that of the first doped well, the gate of the first semiconductor device being electrically coupled to the second doped well, and the integrated circuit device further comprising: Second positive diode; And a second reverse diode, wherein the second forward diode and the second reverse diode are electrically coupled in series between the substrate and the second doped well.

7. The integrated circuit device of claim 1, wherein the doped well is a first doped well located in the first doped region, the first doped region further comprising a second doped well having a conductivity opposite to that of the first doped well, and the integrated circuit device further comprising: A third semiconductor device having a gate electrically coupled to the gate of the first semiconductor device; and a second positive diode; And a second reverse diode, wherein the second forward diode and the second reverse diode are electrically coupled in series between the substrate and the second doped well.

8. An integrated circuit (IC) device, comprising: Base; A first doped well is located on the substrate; A first diode is located on the substrate; A second diode is located on the substrate; The first electrical connection portion electrically couples the anode or cathode of the first diode to the first doped well; And a second electrical connection portion electrically couples the anode or cathode of the second diode to the substrate, wherein the anode of the first diode is electrically coupled to the anode of the second diode, or the cathode of the first diode is electrically coupled to the cathode of the second diode.

9. The integrated circuit device of claim 8, wherein one of the first diode and the second diode is a reverse diode configured to discharge charge from the first doped well to the substrate by means of the leakage current of the reverse diode, and the other of the first diode and the second diode is a forward diode configured to maintain an operating voltage applied across the first doped well and the substrate during operation of the integrated circuit device.

10. A method of manufacturing an integrated circuit (IC) device, the method comprising: Dopant implantation is performed to form a first doped well, a second doped well, a first PN junction, and a second PN junction on a substrate, wherein the substrate includes a further region located outside the first doped well and the second doped well; a gate is deposited on the first doped well and the gate is patterned; and an interconnect is deposited on the substrate and the interconnect is patterned to: electrically couple the first PN junction and the second PN junction in series between the further region of the substrate and one of the first doped well and the second doped well, wherein the P-type region of the first PN junction is electrically coupled to each other, or the N-type region of the first PN junction is electrically coupled to each other, and then the gate located on the first doped well is electrically coupled to the second doped well.

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