Image sensor and electronic device

Abstract

This invention provides an image sensor, comprising: a pixel array including a first pixel connected to a first row line and a second pixel connected to a second row line, each of the first and second pixels including a first photodiode (PD) and a second PD sharing a driving transistor, configured to operate in a first mode and a second mode based on the first PD according to a conversion gain, and configured to operate in a third mode and a fourth mode based on the second PD; and an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit for reading pixel signals output via the first and second row lines. The first CDS circuit is connected to the first and second row lines in a time-division multiplexing manner.

Description

Technical Field

[0001] [Cross - reference to Related Applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2022 - 0087798, filed on July 15, 2022, and Korean Patent Application No. 10 - 2023 - 0020816, filed on February 16, 2023, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entireties.

[0003] Various exemplary embodiments relate to an image sensor, and more particularly to an image sensor that provides an image having an extended dynamic range and high quality, and / or an electronic device including the image sensor. Prior Art

[0004] An image sensor is or includes a device that captures two - dimensional and / or three - dimensional images of an object. The image sensor uses a photoelectric conversion element to generate an image of the object, and the photoelectric conversion element reacts according to the intensity of the light reflected from the object. With the development of complementary metal - oxide semiconductor (CMOS) technology, CMOS image sensors using CMOS are widely used. Recently, since image sensors are installed in various devices, there is a need or desire for an image sensor having improved characteristics such as a high dynamic range (HDR) and / or a signal - to - noise ratio (SNR) at low and high illuminations. Summary of the Invention

[0005] Various exemplary embodiments provide an image sensor and an electronic device including the image sensor, the image sensor including pixels that include a plurality of photoelectric conversion elements sharing a driving transistor and support a dual - conversion gain mode, and generate image data having a high dynamic range and an improved signal - to - noise ratio.

[0006] According to some example embodiments, there is provided an image sensor including: a pixel array including a first pixel connected to a first row line and a second pixel connected to a second row line, wherein each of the first pixel and the second pixel includes a first photodiode (PD) and a second PD sharing a driving transistor, the first pixel and the second pixel being configured to operate in a first mode and a second mode based on respective first PDs according to a conversion gain, and the first pixel and the second pixel being configured to operate in a third mode and a fourth mode based on respective second PDs; and an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals output via the first row line and the second row line. The first CDS circuit is configured to be connected to the first row line and the second row line in a time-division manner.

[0007] Alternatively or additionally, according to some example embodiments, there is provided an image sensor including: a pixel array including a plurality of pixels, a plurality of column lines configured to provide control signals to the plurality of pixels, and a plurality of row lines configured to output a plurality of pixel signals generated from the plurality of pixels, wherein each of the plurality of pixels includes a first photodiode (PD) and a second PD sharing a driving transistor; an analog-to-digital converter configured to convert the plurality of pixel signals output via the plurality of row lines and including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received via a first row line and a second row line among the plurality of row lines; and a switch circuit configured to connect the first row line to the first CDS circuit and the second CDS circuit and connect the second row line to the third CDS circuit in a time-division manner in a first period, and connect the second row line to the first CDS circuit and the second CDS circuit and connect the first row line to the third CDS circuit in a time-division manner in a second period.

[0008] Alternatively or additionally, according to some example embodiments, there is provided an electronic device including: a pixel array including a plurality of pixels, a plurality of column lines configured to provide control signals to the plurality of pixels, and a plurality of row lines configured to output a plurality of pixel signals generated from the plurality of pixels, wherein each of the plurality of pixels includes a first photodiode (PD) and a second PD sharing a driving transistor; an analog-to-digital converter configured to convert the plurality of pixel signals output via the plurality of row lines, and including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received via a first row line and a second row line among the plurality of row lines; and a switch circuit configured to分时地 connect the first row line to the first CDS circuit and the second CDS circuit and connect the second row line to the third CDS circuit in a first period, and分时地 connect the second row line to the first CDS circuit and the second CDS circuit and connect the first row line to the third CDS circuit in a second period. Brief Description of the Drawings

[0009] Various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of an image sensor according to various example embodiments. FIGS. 2A and 2B are circuit diagrams showing pixel structures according to various example embodiments. FIGS. 3A and 3B are views showing split photodiode structures of pixels according to various example embodiments. FIGS. 4A and 4B are circuit diagrams of a correlated double sampling (CDS) circuit included in an image sensor according to various example embodiments. FIGS. 5A and 5B schematically show connections between pixels and a CDS circuit in an image sensor according to various example embodiments. FIG. 6 is a timing diagram showing operations of the pixels and the CDS circuit in FIGS. 5A and 5B. FIG. 7 is a timing diagram showing pixel signal readout schemes of pixels in an image sensor of a comparative example of an image sensor according to various example embodiments in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode. FIG. 8 shows signal-to-noise ratio (SNR) characteristics of each illuminance of a readout method of an image sensor according to various example embodiments and a readout method according to a comparative example. FIG. 9A shows connections between pixels and a CDS circuit in an image sensor according to various example embodiments, and FIG. 9B is a timing diagram showing readout of the pixels in FIG. 9A. FIG. 10A shows the connection between pixels and a CDS circuit in an image sensor according to various example embodiments, and FIG. 10B is a timing diagram showing the readout of the pixels of FIG. 10A. FIGS. 11A and 11B show the connection between pixels and a CDS circuit in an image sensor according to various example embodiments, and FIG. 11C is a timing diagram showing the readout of the pixels of FIGS. 11A and 11B. FIGS. 12A and 12B show the connection between pixels and a CDS circuit in an image sensor according to various example embodiments, and FIG. 12C is a timing diagram showing the readout of the pixels of FIGS. 12A and 12B. FIG. 13A shows the connection between pixels and a CDS circuit in an image sensor according to various example embodiments, and FIG. 13B is a timing diagram showing the readout of the pixels of FIG. 13A. FIGS. 14A and 14B show the stacked structure of an image sensor according to various example embodiments. FIG. 15 is a block diagram schematically showing an electronic device including an image sensor according to various example embodiments. Embodiments

[0010] Hereinafter, various example embodiments will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram of an image sensor 100 according to various example embodiments.

[0012] The image sensor 100 may be mounted on an electronic device having an imaging and / or light sensing function. For example, the image sensor 100 may be mounted on an electronic device such as one or more of the following: a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a household electrical appliance, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation system, a drone, and an advanced driver assistance system (ADAS). In addition, the image sensor 100 may be mounted on an electronic device provided as a component in one or more of a vehicle, furniture, a manufacturing facility, a door, various measuring devices, and the like.

[0013] Referring to FIG. 1, the image sensor 100 may include a pixel array 110, a column driver 120, an analog-to-digital conversion circuit 130 (hereinafter referred to as the ADC circuit), a ramp signal generator 140, a timing controller 150, and an image signal processor 160. The column driver 120, the ADC circuit 130, the ramp signal generator 140, and the timing controller 150 may be referred to as the readout circuit.

[0014] The pixel array 110 includes a plurality of column lines RL, a plurality of row lines CL, and a plurality of pixels PX. The plurality of pixels are connected to the plurality of column lines RL and the plurality of row lines CL and are arranged in columns and rows. The plurality of pixels PX may be active pixel sensors (APS). The number of the plurality of column lines RL may be the same as, greater than, or less than the number of the plurality of row lines CL.

[0015] In various exemplary embodiments, the pixels PX arranged in the same row may be connected to a plurality of row lines CL. For example, the pixels PX arranged in the same row may be alternately connected to two row lines, for example, a first row line CL1 and a second row line CL2. However, the exemplary embodiments are not limited thereto, and the pixels PX arranged in the same row may be connected to the same row line CL.

[0016] Each of the plurality of pixels PX may sense light by using a photoelectric conversion element and output an image signal as an electrical signal according to the sensed light. The photoelectric conversion element may be or may include a photosensing element, and the photosensing element includes an organic or inorganic material, such as one or more of a photodiode (inorganic photodiode), an organic optical film, a perovskite photodiode, a photoelectric crystal, a photogate, or a pinhole photodiode. Hereinafter, the photodiode will be described as an example of the photoelectric conversion element; however, the exemplary embodiments are not limited thereto.

[0017] The microlenses for light concentration can be disposed above each of the plurality of pixels PX or above each of the pixel groups formed by adjacent pixels PX. The color filters for transmitting light in a certain spectral region can be disposed above each of the plurality of pixels PX, and each of the plurality of pixels PX can sense light in a certain spectral region based on the corresponding color filter from the light received via the microlens. For example, the pixel array 110 can include red pixels for converting light in the red spectral region into an electrical signal, green pixels for converting light in the green spectral region into an electrical signal, and blue pixels for converting light in the blue spectral region into an electrical signal. However, the exemplary embodiments are not limited thereto, and the pixel array 110 can further include white pixels, or the pixel array 110 can include pixels according to other color combinations, such as cyan pixels, yellow pixels, green pixels, and magenta pixels. The pixels PX can be arranged in a Bayer pattern; however, the exemplary embodiments are not limited thereto.

[0018] In the pixel array 110 according to various exemplary embodiments, the pixel PX can have a pixel structure in which several photodiodes (e.g., a first photodiode and a second photodiode) share some circuit elements of the pixel PX, e.g., the reset transistor RX in FIG. 2A, the drive transistor DX in FIG. 2A, and the selection transistor SX in FIG. 2A. The light receiving areas of the photodiodes can be different from each other; for example, the light receiving area of the first photodiode can be larger than the light receiving area of the second photodiode. The first photodiode can be referred to as the large photodiode LPD in FIG. 2A, and the second photodiode can be referred to as the small photodiode SPD in FIG. 2A. Alternatively or additionally, the pixel PX can include a large capacitor CLOF (see FIG. 2A) for storing the charge overflowing from the second photodiode (i.e., the small photodiode SPD).

[0019] Since the large photodiode LPD has a relatively large light receiving area, the large photodiode LPD can generate more charge (e.g., more electron-hole pairs) than the small photodiode SPD under the same light receiving conditions. For example, the large photodiode LPD can have higher sensitivity than the small photodiode SPD. Due to this characteristic, in the case of low illuminance, the image signal can be generated using the pixel signal based on the charge generated by the large photodiode LPD, and in the case of high illuminance, the image signal can be generated using the pixel signal based on the charge generated by the small photodiode SPD. Hereinafter, for convenience of description, it is assumed that the pixel PX includes the large photodiode LPD and the small photodiode SPD; however, the exemplary embodiments are not limited thereto. The pixel PX can include a plurality of photodiodes having the same or different light receiving areas.

[0020] The pixel PX can be sequentially operated according to multiple modes (operation modes). In various example embodiments, the pixel PX can be operated based on a first photodiode in a first mode and a second mode, and can be operated based on a second photodiode in a third mode and a fourth mode. The first mode and the second mode are distinguished from each other according to a conversion gain, where the conversion gain represents the rate at which the charge generated by a photodiode (e.g., the first photodiode) is converted into an electrical signal (e.g., converted into a pixel voltage). The conversion gain can vary according to the capacitance of a parasitic capacitor connected to a floating diffusion node (hereinafter simply referred to as the capacitance of the floating diffusion node). For example, the pixel PX supports a dual conversion gain mode, the first mode can be a low conversion gain mode based on the first photodiode, and the second mode can be a high conversion gain mode based on the first photodiode. The third mode and the fourth mode can be distinguished from each other based on whether a signal according to the overflow charge of the second photodiode stored in a large capacitor provided in the pixel PX is read out (or read). The structure and modes of the pixel PX will be described in detail below with reference to FIGS. 2A to 3B and FIGS. 5A to 6.

[0021] The pixel signals read according to the first mode to the fourth mode can correspond to different illuminance ranges. For example, the second mode pixel signal according to the second mode can correspond to a first illuminance section that is the lowest illuminance section, the first mode pixel signal according to the first mode can correspond to a second illuminance section higher than the first illuminance section, and the third mode pixel signal according to the third mode and the fourth mode pixel signal according to the fourth mode can respectively correspond to a third illuminance section and a fourth illuminance section greater than the second illuminance section. The fourth illuminance section can be the maximum illuminance section. The first mode pixel signal to the fourth mode pixel signal can be generated within one frame period scanned after the pixel array 110 is exposed once.

[0022] At least four digital signals, such as the first mode digital signal to the fourth mode digital signal respectively generated based on the first mode pixel signal to the fourth mode pixel signal output from each of the multiple pixels of the pixel array 110, can be combined into one image, and the combined image can have a high dynamic range.

[0023] In some example embodiments, each of the plurality of pixels PX may operate in a single-exposure method that performs one exposure or in a multiple-exposure method that performs multiple exposures. For example, the pixel PX may operate in a single-exposure method to generate a pixel signal via the first photodiode and / or the second photodiode after one exposure operation. Alternatively or additionally, the pixel PX may operate in a multiple-exposure method, where a pixel signal is generated via the first photodiode and / or the second photodiode in response to a first exposure operation, and then another pixel signal is additionally generated via the first photodiode and / or the second photodiode in response to a second exposure operation.

[0024] The column driver 120 drives the pixel array 110 in units of one column or multiple columns. The column driver 120 may decode column control signals (e.g., column addresses) received from the timing controller 150, and may select at least one pixel column to be read out from among the multiple pixel columns of the pixel array 110 in response to the decoded column control signals.

[0025] The column driver 120 may provide control signals (e.g., one or more of a selection signal, a transfer control signal, a conversion control signal, and a switch control signal) to two or more than two selected pixel columns via the column lines RL. The pixels PX included in the pixel columns selected by the selection signal provided by the column driver 120 output pixel signals, such as pixel voltages. The pixel PX may operate sequentially according to the first mode to the fourth mode. The pixel PX may operate according to the first mode and the second mode, and then according to the third mode and the fourth mode. The pixel PX may output a first-mode pixel signal to a fourth-mode pixel signal corresponding to the first mode to the fourth mode, respectively. The column driver 120 may generate control signals for controlling the pixel PX to operate in the first mode to the fourth mode and provide the generated control signals to the pixel array 110.

[0026] In various example embodiments, the column driver 120 may simultaneously select one or more columns for fast readout of the pixel array 110. Two or more pixels included in two or more selected columns and arranged in the same row may be connected to different row lines CL. The readout periods of two or more than two pixels connected to different row lines CL may at least partially overlap each other. For example, when the pixels PX included in one column operate in the first mode and the second mode, the pixels PX included in another column may operate in the third mode and the fourth mode. Thus, multiple columns of the pixel array 110 may be read out interleaved, as described below with reference to FIGS. 11C, 12B, and 13B.

[0027] The ramp signal generator 140 can generate a ramp signal RAMP that increases or decreases at a certain slope (e.g., a dynamically determined or predetermined slope), and can provide the ramp signal RAMP to each of the plurality of ADCs 135 in the ADC circuit 130. In various example embodiments, the ramp signal generator 140 can generate a first ramp signal and a second ramp signal, can provide the first ramp signal to the first correlated double sampling (CDS) circuit 131 and the second CDS circuit 132 of the ADC 135, and can provide the second ramp signal to the third CDS circuit 133 of the ADC 135. In various example embodiments, the ramp signal generator 140 can generate a first ramp signal, a second ramp signal, and a third ramp signal, and provide the first to third ramp signals to the first to third CDS circuits 131 to 133.

[0028] The ADC circuit 130 can convert the pixel signals (e.g., pixel voltages such as analog pixel values) output from the pixel array 110 into pixel values of digital signals. The ADC circuit 130 can include a plurality of ADCs 135 and a switch circuit (SWC), and each of the plurality of ADCs 135 can convert the pixel signals into pixel values by using the CDS method. The pixel signals received via each of the plurality of row lines CL can be converted into pixel values by the corresponding ADC among the plurality of ADCs 135.

[0029] Each of the ADCs 135 can include a CDS circuit, such as the second CDS circuit (e.g., CDS2) 132 and / or the third CDS circuit (e.g., CDS3) 133, and a counter 134. In addition, two adjacent ADCs 135 corresponding to two adjacent row lines CL (e.g., the first row line CL1 and the second row line CL2) can share the first CDS circuit (i.e., CDS1) 131. In other words, two adjacent row lines CL can share the first CDS circuit 131.

[0030] In various example embodiments, two adjacent ADCs 135 corresponding to two adjacent row lines CL can share the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 (i.e., CDS1, CDS2, and CDS3).

[0031] The switch circuit SWC may include multiple switches and may provide each of the outputs in the row line CL to the corresponding ADC 135. In this case, the switch circuit SWC may provide each of the outputs in two adjacent row lines CL to the first CDS circuit 131 in a time-division manner, and / or may provide each of the outputs in two adjacent row lines CL to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner. For example, the switch circuit SWC may provide the output of the first row line CL1 and the output of the second row line CL2 to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner. This will be described in detail below with reference to FIGS. 5A to 6.

[0032] In this way, according to the operation of the switch circuit SWC, each of the two adjacent row lines CL may be connected to the first CDS circuit 131 shared by two adjacent ADCs 135 in a time-division manner, and / or may be connected to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 shared by two adjacent ADCs 135 in a time-division manner.

[0033] The CDS circuit (e.g., each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133) may compare the pixel signal received via the row line CL with the ramp signal RAMP and output a comparison result. When the voltage level of the ramp signal RAMP is the same as the voltage level of the pixel signal, the CDS circuit may output a comparison result signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low). The time point at which the level of the comparison result signal transitions may be determined based on the voltage level of the pixel signal.

[0034] The CDS circuit may sample and hold the pixel signal provided from the pixel PX according to the CDS method and may double-sample a certain noise level (e.g., the reset level and / or the signal level). The CDS circuit may generate a comparison result signal corresponding to the reset level and a comparison result signal corresponding to the signal level. In this case, the method of reading the signal level after reading the reset level may be referred to as the full CDS method, and the method of reading the reset level after reading the signal level may be referred to as the incomplete CDS method and / or the delta reset sampling (DRS) method.

[0035] To read the first-mode pixel signal and the second-mode pixel signal from a pixel PX by means of the full CDS method, two CDS circuits corresponding to the first mode and the second mode respectively are required or used. For example, based on the low conversion gain mode and the high conversion gain mode of the first photodiode, and among the two CDS circuits, the CDS circuit corresponding to the second mode can correspond to the third mode and the fourth mode. Alternatively, one or more CDS circuits corresponding to the third mode and the fourth mode may be required or used separately from the two CDS circuits.

[0036] As described above, when the first-mode pixel signal and the second-mode pixel signal are output via one of two adjacent row lines CL according to the interleaved readout, the third-mode pixel signal and the fourth-mode pixel signal can be output via the other row line CL. Therefore, the first CDS circuit 131 corresponding to the first mode can be shared by two adjacent ADCs 135. Alternatively, the first CDS circuit 131 and the second CDS circuit 132 corresponding to the first mode and the second mode respectively, and the third CDS circuit 133 corresponding to the third mode and the fourth mode can be shared by two adjacent ADCs 135.

[0037] A counter (e.g., counter CNT) 134 can count the time points of the level transitions of the comparison result signals output from the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 respectively. Therefore, a reset value and / or a signal value can be obtained for each of the first mode to the fourth mode, and a value obtained by subtracting the reset value from the signal value can be generated as the pixel value.

[0038] The control signals provided to the ADC circuit 130, e.g., the switch signal provided to the switch circuit SWC and the auto-zero signal provided to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be provided from the timing controller 150 or can be provided from the column driver 120 under the control of the timing controller 150.

[0039] The timing controller 150 can output timing control signals to each of the column driver 120, the ADC circuit 130, and the ramp signal generator 150 and the column driver 120, and can control the operations and operation timings of the column driver 120, the ADC circuit 130, and the ramp signal generator 150.

[0040] The image signal processor 160 can perform various signal processes on the image data output from the ADC circuit 130. For example, the first to fourth image data corresponding to the first to fourth mode pixel signals respectively. For example, the image signal processor 160 can perform signal processes on the received image data, such as one or more of image quality compensation, pixel merging, and miniaturization. The image quality compensation can include, for example, one or more of black level compensation, lens shadow compensation, crosstalk compensation, and defective pixel correction.

[0041] The image data IDT output from the image signal processor 160 can be transmitted to an external processor. For example, the external processor can be the host processor of the electronic device on which the image sensor 100 is installed. For example, the external processor can be or can include the application processor of a mobile terminal or be included in the application processor. The image sensor 100 can transmit the image data to the external processor according to a data communication method based on a set interface (for example, the mobile industry processor interface (MIPI)). The external processor can generate a high dynamic range (HDR) image by merging the first to fourth images.

[0042] FIG. 2A and FIG. 2B are circuit diagrams showing pixel structures according to various example embodiments. The pixel PXa and the pixel PXb in FIG. 2A and FIG. 2B can be applied as the pixel PX of the pixel array 110 in FIG. 1.

[0043] Referring to FIG. 2A, the pixel PXa can include a plurality of photodiodes, such as a large photodiode LPD and a small photodiode SPD. The pixel PXa can include a plurality of transistors, such as a first transfer transistor LTX, a second transfer transistor STX, a reset transistor RX, a drive transistor DX, a selection transistor SX, a gain control transistor DRX (also referred to as a conversion gain control transistor), and a switch transistor SWT, and a capacitor C LOF. The control signals STS, the control signal LTS, the control signal RS, the control signal SEL, the control signal GCS, and the control signal SWS can be applied to the pixel PXa, and the control signals STS, the control signal LTS, the control signal RS, the control signal SEL, the control signal GCS, and the control signal SWS can be provided from the column driver 120 in FIG. 1.

[0044] The large photodiode LPD and the small photodiode SPD can generate photo charges (e.g., electron-hole pairs) that vary according to the intensity of light. For example, the large photodiode LPD and the small photodiode SPD can generate charges proportional to the amount of incident light, such as negative charges or electrons and positive charges or holes. The photo charges generated by the large photodiode LPD and the small photodiode SPD can be transferred to and accumulated in at least one of the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3. Parasitic capacitors (not shown) can be formed at each of the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3. Alternatively or additionally, actual capacitor elements (not shown) can be connected to each of the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3.

[0045] The first transfer transistor LTX can be connected between the large photodiode LPD and the first floating diffusion node FD1 and can be turned on or off in response to a first transfer control signal LTS. The first transfer transistor LTX can be turned on to transfer the photo charges generated by the large photodiode LPD to the first floating diffusion node FD1.

[0046] The pixel PXa can include a conversion gain control transistor DRX. The conversion gain control transistor DRX can be connected to the first floating diffusion node FD1 and the second floating diffusion node FD2. The conversion gain control transistor DRX can be turned on or off in response to a gain control signal GCS. The conversion gain control transistor DRX can be turned on to connect the first floating diffusion node FD1 and the second floating diffusion node FD2 to each other. When the first floating diffusion node FD1 and the second floating diffusion node FD2 are connected to each other (e.g., connected in series with each other), the capacitance of the first floating diffusion node FD1 can increase and the conversion gain can decrease. When the conversion gain control transistor DRX is turned on, the pixel PXa can operate in a low conversion gain mode (hereinafter, referred to as the LCG mode). Conversely, when the conversion gain control transistor DRX is turned off, the pixel PXa can operate in a high conversion gain mode (hereinafter, referred to as the HCG mode).

[0047] The second transfer transistor STX can be connected between the small photodiode SPD and the second floating diffusion node FD2. The second transfer transistor STX can be turned on or off in response to a second transfer control signal STS and can be turned on to transfer the photo charges generated by the small photodiode SPD to the third floating diffusion node FD3.

[0048] A first end of the capacitor C_LOF can be connected to the third floating diffusion node FD3, and a reset voltage VRD can be applied to a second end of the capacitor C_LOF. In various example embodiments, the reset voltage VRD can be equal to the pixel power supply voltage VPIX. The capacitance of the capacitor C_LOF can be greater than the capacitances of the parasitic capacitors generated at the first floating diffusion node FD1 and the second floating diffusion node FD2, respectively. For example, the capacitor C_LOF can be a large-capacitance capacitor. Charge overflowing from the small photodiode SPD can be accumulated in the capacitor C_LOF through the third floating diffusion node FD3.

[0049] The switch transistor SWT can be connected to the second floating diffusion node FD2 and the third floating diffusion node FD3. The switch transistor SWT can be turned on or off in response to a switch control signal SWS. When the switch transistor SWT is turned on, the second floating diffusion node FD2 and the third floating diffusion node FD3 can be connected to each other and the capacitor C_LOF can be connected in parallel with the parasitic capacitor formed at the second floating diffusion node FD2. Accordingly, the capacitance of the second floating diffusion node FD2 can be increased.

[0050] A first end of the reset transistor RX can be connected to the second floating diffusion node FD2, and a reset voltage VRD can be applied to a second end of the reset transistor RX. The reset transistor RX can be turned on and off in response to a reset control signal RS. When the reset transistor RX is turned on, the conversion gain control transistor DRX can be turned on. Since the reset voltage VRD is applied to the first floating diffusion node FD1 and the second floating diffusion node FD2, the first floating diffusion node FD1 and the second floating diffusion node FD2 can be reset. For example, the charge accumulated in the parasitic capacitors of the first floating diffusion node FD1 and the second floating diffusion node FD2 can be completely or at least partially removed. When the reset transistor RX is turned on, the conversion gain control transistor DRX and the switch transistor SWT can be turned on. When the reset voltage VRD is applied to the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3, the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 can be reset.

[0051] The first terminal of the driving transistor DX can be connected to the selection transistor SX, and the pixel power supply voltage VPIX can be applied to the second terminal of the driving transistor DX. The first terminal of the selection transistor DX can be connected to the driving transistor DX, and the second terminal of the selection transistor DX can be connected to the row line CL. The selection transistor SX can be turned on or off in response to the selection signal SEL. When the selection transistor SX is turned on during a read operation, the driving transistor DX can operate as a source follower based on the bias current IL generated by the current source CS connected to the row line CL, and the driving transistor DX can output a voltage corresponding to the charge accumulated in the first floating diffusion node FD1 as a pixel signal.

[0052] According to various example embodiments, the conversion gain control transistor DRX can be turned on or off during the read cycle of the large photodiode LPD, and thus, the pixel PX can operate in a first mode or a second mode. When the conversion gain control transistor DRX is turned on, the first floating diffusion node FD1 can be connected to the second floating diffusion node FD2, and the pixel PX can operate in the LCG mode. When the conversion gain control transistor DRX is turned off, the first floating diffusion node FD1 can be electrically disconnected from the second floating diffusion node FD2, and thus, the pixel PX can operate in the HCG mode.

[0053] During the read cycle of the small photodiode SPD, the conversion gain control transistor DRX and the switch transistor SWT can be turned on. During the read cycle of the small photodiode SPD, the small photodiode SPD can be read twice.

[0054] In this case, the pixel PX can operate in a third mode or a fourth mode based on whether a signal according to the overflow charge accumulated in the capacitor CLOF is read. After resetting the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 after the read signal level, when the reset level is read, a signal according to the overflow charge accumulated in the capacitor CLOF can be read. Therefore, in the read cycle of the small photodiode SPD, when the signal level is read after the read reset level, the pixel PX can operate in the third mode, and when the reset level is read after the read signal level, the pixel PX can operate in the fourth mode. The third mode can be referred to as the CDS mode, and the fourth mode can be referred to as the lateral overflow integration capacitor (LOFIC) mode.

[0055] Referring now to FIG. 2B, pixel PXb may include a plurality of photodiodes, such as large photodiode LPD and small photodiode SPD. Pixel PXb may include a plurality of transistors, such as first transfer transistor LTX, second transfer transistor STX, reset transistor RX, drive transistor DX, select transistor SX, gain control transistor DRX (also referred to as conversion gain control transistor), and switch transistor SWT, and capacitor C LOF. Control signal STS, control signal LTS, control signal RS, control signal SEL, control signal GCS, and control signal SWS may be applied to pixel PXb, and control signal STS, control signal LTS, control signal RS, control signal SEL, control signal GCS, and control signal SWS may be provided from column driver 120 in FIG. 1.

[0056] The structure and / or operation of pixel PXb in FIG. 2B may be similar to the structure and / or operation of pixel PXa in FIG. 2A. However, in pixel PXb of FIG. 2B, second transfer transistor STX may be connected between small photodiode SPD and second floating diffusion node FD2. During the readout period of small photodiode SPD, switch transistor SWT may be turned on or off, and a signal according to the overflow charge accumulated in capacitor C LOF may be read out when switch transistor SWT is turned on. Therefore, when switch transistor SWT is turned on, pixel PXb may operate in the fourth mode, and when switch transistor SWT is turned off, pixel PXb may operate in the third mode.

[0057] Each of the transistors shown in FIG. 2A, such as first transfer transistor LTX, second transfer transistor STX, reset transistor RX, drive transistor DX, select transistor SX, gain control transistor DRX, and switch transistor SWT, may have electrical properties and / or physical properties the same as or different from the corresponding transistors included in FIG. 2B. In addition, each of the photodiodes shown in FIG. 2A, such as large photodiode LPD and small photodiode SPD, may have electrical properties and / or physical properties the same as or different from the corresponding photodiodes included in FIG. 2B. In addition, capacitor C LOF included in FIG. 2A may have electrical properties and / or physical properties the same as or different from capacitor C LOF included in FIG. 2B. The example embodiments are not limited thereto.

[0058] FIGS. 3A and 3B are views showing split photodiode structures of pixels according to various example embodiments.

[0059] Referring to FIG. 3A, the pixel array 110a may include a plurality of pixels PX arranged in columns and rows in an X-Y plane diagram. Each of the plurality of pixels PX may include a photoelectric conversion portion and a pixel circuit portion. The photoelectric conversion portion may be vertically overlapped with the pixel circuit portion.

[0060] The photoelectric conversion portion may include a microlens, a color filter, and a photodiode. In some exemplary embodiments, the photoelectric conversion portion may further include a color filter, a protective layer, and an insulating structure. The microlens may be disposed above the photodiode and may be configured to collect light incident from the outside and form or focus the light incident on the photoelectric conversion element.

[0061] The pixel PX may include a large photodiode LPD and a small photodiode SPD. The region forming the large photodiode LPD and the region forming the small photodiode SPD may be separated from each other by an isolation region such as a deep trench isolation (DTI) structure. The large photodiode LPD of each pixel PX may have a relatively large light receiving area, and the small photodiode SPD of each pixel PX may have a relatively small light receiving area. The shape of either or both of the large photodiode LPD and the small photodiode SPD may be polygonal; however, the exemplary embodiments are not limited thereto. As shown in FIG. 3A, the large photodiode LPD and the small photodiode SPD may each have a quadrilateral shape, such as a square shape. As shown in FIG. 3B, the large photodiode LPD may have an octagonal shape, such as a regular octagonal shape, and the small photodiode SPD may have a quadrilateral shape, such as a square shape. However, the exemplary embodiments are not limited thereto, and the shapes of the large photodiode LPD and the small photodiode SPD may be modified differently.

[0062] The microlens for collecting light incident from the outside may be disposed above each of the large photodiode LPD and the small photodiode SPD, and the color filter, the protective layer, and the insulating structure may be disposed between the microlens and the large photodiode LPD and the small photodiode SPD.

[0063] The pixel circuit portion may be formed below the large photodiode LPD and the small photodiode SPD, and the pixel circuit portion may include a floating diffusion node, source / drain and gate of a transistor, a load resistor, a via contact window, and a wiring structure.

[0064] FIGS. 4A and 4B are circuit diagrams of a CDS circuit included in an image sensor according to various exemplary embodiments.

[0065] The CDS circuits CDSCa and CDSCb in FIGS. 4A and 4B can be applied to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in FIG. 1.

[0066] Referring to FIG. 4A, the CDS circuit CDSCa may include a comparator 11, a first auto-zero switch SAZ1 and a second auto-zero switch SAZ2, and a first capacitor C1 and a second capacitor C2.

[0067] The comparator 11 can be implemented as a differential amplifier, such as an operational transconductance amplifier (OTA). The first auto-zero switch SAZ1 can be connected to the first input terminal INP and the second output terminal ON of the comparator 11, and the second auto-zero switch SAZ2 can be connected to the second input terminal INN and the first output terminal OP of the comparator 11. The first auto-zero switch SAZ1 and the second auto-zero switch SAZ2 can be turned on and off in response to an auto-zero signal AZ. In various exemplary embodiments, the first auto-zero switch SAZ1 and the second auto-zero switch SAZ2 can be implemented as transistors.

[0068] A ramp signal RAMP can be applied to one end of the first capacitor C1, and the other end of the first capacitor C1 can be connected to the first input terminal INP of the comparator 11. A pixel signal VPS can be applied to the end of the second capacitor C2, and the other end of the second capacitor C2 can be connected to the second input terminal INN of the comparator 11. For example, the ramp signal RAMP and the pixel signal VPS can be provided to the first input terminal INP and the second input terminal INN of the comparator 11 via the first capacitor C1 and the second capacitor C2, respectively. In this case, the first capacitor C1 and the second capacitor C2 are coupling capacitors and can block the DC components of the ramp signal RAMP and the pixel signal VPS completely or at least partially, and provide the AC components of the ramp signal RAMP and the pixel signal VPS to the first input terminal INP of the comparator 11 and the second input terminal INN of the comparator 11.

[0069] The CDS circuit CDSCa can perform an auto-zeroing operation based on a reset level provided as a pixel signal VPS before a comparison operation (i.e., a reset level in the LCG mode or a reset level in the HCG mode). The first auto-zeroing switch SAZ1 and the second auto-zeroing switch SAZ2 can be turned on in response to an auto-zeroing signal AZ, and thus the first input terminal INP and the second output terminal ON of the comparator 11 can be connected to each other, and the second input terminal INN and the first output terminal OP can be connected to each other. Therefore, the offset of the comparator 11 can be canceled or reduced, and the DC operating level of the comparator 11 can be determined.

[0070] When the first auto-zeroing switch SAZ1 and the second auto-zeroing switch SAZ2 are turned on, the voltage levels of the first input terminal INP, the second input terminal INN, the first output terminal OP, and the second output terminal ON of the comparator 11 can be the same. The voltage levels of the first input terminal INP, the second input terminal INN, the first output terminal OP, and the second output terminal ON can be referred to as auto-zeroing voltages. The auto-zeroing voltages can be determined according to the pixel signal VPS, the ramp signal RAMP, and the offset of the comparator 11. The auto-zeroing voltages can be at the DC operating level of the comparator 11.

[0071] During a comparison operation after the auto-zeroing operation, the first auto-zeroing switch SAZ1 and the second auto-zeroing switch SAZ2 can be turned on, and the AC components of the ramp signal RAMP and the pixel signal VPS can be added to the auto-zeroing voltages and applied to the first input terminal INP and the second input terminal INN of the comparator 11. During the comparison operation, when the ramp signal RAMP having a voltage level obtained by adding an offset to the voltage level during the auto-zeroing operation is applied to the first input terminal INP via the first capacitor C1, the voltage level of the first input terminal INP is higher than the voltage level of the second input terminal INN, and thus the comparator 11 can output a logic high signal. Thereafter, when the ramp signal RAMP decreases at a certain slope, the voltage level of the first input terminal INN can decrease. When the voltage level of the first input terminal INP drops to or is less than the voltage level of the second input terminal INP, the comparator 11 can output a logic low signal. The period from the time when the ramp signal RAMP starts to decrease to the time when the comparator 11 outputs a logic low signal can be generated by the counter 134 in FIG. 1 as a digital value corresponding to a pixel signal (e.g., a reset level or a signal level).

[0072] Referring to FIG. 4B, the CDS circuit CDSCb can include a comparator 11, a first auto-zeroing switch SAZ1 and a second auto-zeroing switch SAZ2, a first capacitor C1 and a second capacitor C2, and an amplifier 12.

[0073] Compared with the CDS circuit CDSCa in FIG. 4A, the CDS circuit CDSCb may further include an amplifier 12. The amplifier 12 may be implemented as, for example, an OTA. The amplifier 12 may operate as an inverter or a buffer. The amplifier 12 may amplify or invert and amplify the comparison result signal output from the comparator 11 and output the amplified signal.

[0074] FIGS. 5A and 5B schematically show the connection between pixels and a CDS circuit in an image sensor according to various exemplary embodiments.

[0075] Referring to FIG. 5A, a switch circuit SWC may be disposed between the first CDS circuit 131 to the third CDS circuit 133 and the first row line CL1 and the second row line CL2, and a plurality of switches SW11, switch SW12, switch SW21, switch SW22, switch SW31, and switch SW32 provided in the switch circuit SWC may connect the first CDS circuit 131 to the third CDS circuit 133 to the first row line CL1 and the second row line CL2 in a time-division manner.

[0076] The switches SW11, SW21, and SW31 may be turned on or off in response to switch signals SS11, SS21, and SS31, respectively, and the switches SW12, SW22, and SW32 may be turned on or off in response to switch signals SS12, SS22, and SS32, respectively.

[0077] The switch SW11 may be turned on to connect the first row line CL1 to the first CDS circuit 131, the switch SW21 may be turned on to connect the first row line CL1 to the second CDS circuit 132, and the switch SW31 may be turned on to connect the first row line CL1 to the third CDS circuit 133. The switches SW11, SW21, and SW31 may not be turned on simultaneously, but may be turned on in a time-division manner at different periods. Therefore, the first pixel signal VPS1 output from the first pixel PX1 via the first row line CL1 may be provided to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in a time-division manner.

[0078] The switches SW12, SW22, and SW32 can be turned on or off in response to the switch signals SS12, SS22, and SS32 respectively. The switch SW12 can be turned on to connect the second row line CL2 to the first CDS circuit 131, the switch SW22 can be turned on to connect the second row line CL2 to the second CDS circuit 132, and the switch SW32 can be turned on to connect the second row line CL2 to the third CDS circuit 133. The switches SW12, SW22, and SW32 cannot be turned on simultaneously, but can be turned on at different times. Therefore, the second pixel signal VPS2 output from the second pixel PX2 via the second row line CL2 can be provided to the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 at different times.

[0079] Here, the switches SW11 and SW12 cannot be turned on simultaneously, but can be turned on at different cycles to selectively connect the first CDS circuit 131 to the first row line CL1 or the second row line CL2. The switches SW21 and SW22 cannot be turned on simultaneously, but can be turned on at different cycles to selectively connect the second CDS circuit 132 to the first row line CL1 or the second row line CL2. The switches SW31 and SW32 cannot be turned on simultaneously, but can be turned on at different cycles to selectively connect the third CDS circuit 133 to the first row line CL1 or the second row line CL2.

[0080] According to the switching operations of the multiple switches SW11, SW12, SW21, SW22, SW31, and SW32, the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be connected to the first row line CL1 and the second row line CL2 at different times, and the pixels connected to the first row line CL1 and the second row line CL2, such as the first pixel PX1 and the second pixel PX2, can be read. The first CDS circuit 131 can generate a comparison result signal R_LCG in the LCG mode based on the pixel signals indicating the reset level of the LCG mode from the first pixel PX1 and the second pixel PX2, and the second CDS circuit 132 can generate a comparison result signal R_LCG in the HCG mode based on the pixel signals indicating the reset level of the HCG mode from the first pixel PX1 and the second pixel PX2. The third CDS circuit 133 can generate a comparison result signal R_SPD in the reading mode of the small photodiode SPD (e.g., the SC mode or the SLOF mode to be described below) based on the pixel signals indicating the level according to the small photodiode SPD from the first pixel PX1 and the second pixel PX2.

[0081] Since the first row line CL1 and the second row line CL2 share the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133, the readout periods of the pixels connected to the first row line CL1 and the second row line CL2 (e.g., the first pixel PX1 and the second pixel PX2) can partially overlap with each other, as described below with reference to FIG. 9B. The pixel signals output via the first row line CL1 and the second row line CL2 (e.g., the first pixel signal VPS1 and the second pixel signal VPS2) can be time-divisionally applied to the second input terminal INN1 of the first comparator 11_1, the second input terminal INN2 of the second comparator 11_2, and the third input terminal INN3 of the third comparator 11_3 via the capacitor C12, the capacitor C22, and the capacitor C32, respectively. In this case, the first ramp signal RAMP1 can be applied to the first input terminal INP1 of the first comparator 11_1 and the first input terminal INP2 of the second comparator 11_2 via the capacitor C11 and the capacitor C21, and the second ramp signal RAMP2 can be applied to the first input terminal INP3 of the third comparator 11_3 via the capacitor C31.

[0082] Referring to FIG. 5B, the plurality of switches SW11, SW12, SW21, and SW32 can time-divisionally connect the first CDS circuit 131 and the second CDS circuit 132 to the first row line CL1, and connect the first CDS circuit 131 and the third CDS circuit 133 to the second row line CL2.

[0083] The switches SW11 and SW12 can connect the first CDS circuit 131 to the first row line CL1 or the second row line CL2 in response to the switch signal SS11 and the switch signal SS12. Here, the switches SW11 and SW12 cannot be turned on simultaneously, and can selectively connect the first CDS circuit 131 to the first row line CL1 or the second row line CL2.

[0084] The switch SW21 can be turned on to connect the first row line CL1 to the second CDS circuit 132. The switches SW11 and SW21 cannot be turned on simultaneously, but can be turned on time-divisionally at different periods. Therefore, the first pixel signal VPS1 output from the first pixel PX1 via the first row line CL1 can be provided to the first CDS circuit 131 and the second CDS circuit 132 time-divisionally.

[0085] Switch SW32 can be turned on to connect the first row line CL1 to the second CDS circuit 132. Switch SW12 and switch SW32 cannot be turned on simultaneously, but can be turned on in a time-division manner at different cycles. Therefore, the second pixel signal VPS2 output from the second pixel PX2 via the second row line CL2 can be provided to the first CDS circuit 131 and the third CDS circuit 133 in a time-division manner.

[0086] FIG. 6 is a timing diagram showing the operations of pixels and CDS circuits in an image sensor according to various exemplary embodiments.

[0087] The readout operation of the pixel PX (e.g., the first pixel PX1) of FIG. 1 will be described with reference to FIGS. 5A and 6. The readout operation of the first pixel PX1 can be similarly applied to other pixels PX.

[0088] In FIG. 6, it is assumed that the active level of the control signals (e.g., switch signals SS11 to switch signal SS23, selection signal SEL, reset signal RS, gain control signal GCS, switch control signal SWS, first transfer control signal LTS, second transfer control signal STS, first auto-zero signal AZ1, second auto-zero signal AZ2, and third auto-zero signal AZ3) is a logical high level (first level), and the non-active level of the control signals is a logical low (second level).

[0089] The readout period of the first pixel PX1 can be referred to as one horizontal period, and one horizontal period can be identified by a vertical synchronization signal. During the readout period of the first pixel PX1, the selection transistor SX can be turned on in response to the selection signal SEL having a logical high level. Therefore, the first pixel PX1 can be connected to the first row line CL1, and thus, the first pixel PX1 can be read out. The readout period of the first pixel PX1 can include a first period P1 and a second period P2. During the first period P1, the large photodiode LPD can be read out, and during the second period P2, the small photodiode SPD can be read out.

[0090] The first period P1 may include a first sub-period S11, a second sub-period S12, a third sub-period S13, and a fourth sub-period S14. In the first sub-period S11 and the fourth sub-period S14, the first pixel PX1 may operate based on the large photodiode LPD in the LCG mode. In response to the active level of the switch signal SS11, the switch SW11 may be turned on to provide the first pixel signal VPS1 to the first CDS circuit 131 via the first row line CL1. In the first sub-period S11, the first CDS circuit 131 may read the reset level LCG RST (hereinafter referred to as the LCG reset level) in the LCG mode, and in the fourth sub-period S14, the first CDS circuit 131 may read the signal level LCG SIG (hereinafter referred to as the LCG signal level) in the LCG mode.

[0091] In the second sub-period S12 and the third sub-period S13, the first pixel PX1 may operate based on the large photodiode LPD in the HCG mode. In response to the active level of the switch signal SS12, the switch SW12 may be turned on to provide the first pixel signal VPS1 to the second CDS circuit 132 via the first row line CL1. In the second sub-period S12, the second CDS circuit 132 may read the reset level HCG RST (hereinafter referred to as the HCG reset signal) in the HCG mode, and in the third sub-period S13, the second CDS circuit 132 may read the signal level HCG SIG (hereinafter referred to as the HCG image signal) in the HCG mode.

[0092] In response to the reset signal RS transitioning from a logic high to a logic low in the first sub-period S11, the reset transistor RX may change from an on state to an off state. The conversion gain control transistor DRX may be turned on in response to the gain control signal GCS having a logic high level. The pixel PX may operate in the LCG mode, and the LCG reset level may be output as the first pixel signal VPS1.

[0093] In the first sub - period S11, the switch SW11 can be turned on in response to the active level of the switch signal SS11, and thus the first line CL1 can be connected to the second input terminal INN1 of the first CDS circuit 131. The first auto - zero signal AZ1 can be bistable - triggered to the active level, and in response to the first auto - zero signal AZ1, the first auto - zero switch SAZ11 and the second auto - zero switch SAZ12 of the first CDS circuit 131 can be turned on, and thus the first CDS circuit 131 can perform an auto - zero operation. When performing the auto - zero operation, the voltage levels of the first input terminal INP1 and the second input terminal INN1 of the comparator 11_1 of the first CDS circuit 131 can be equal to the first auto - zero level.

[0094] Thereafter, the voltage level of the first input terminal INP1 can increase according to the change of the first ramp signal RAMP1 and then decrease at a certain slope. When the voltage level of the first input terminal INP1 is less than or equal to the voltage level of the second input terminal INN1, the output of the first CDS circuit 131 (and, the first comparison result signal) can change from logic high to logic low. Thus, according to the comparison operation of the comparator 11_1, the LCG reset level of the first pixel PX1 can be read out.

[0095] In the second sub - period S12, the switch SW11 can be turned off in response to the non - active level of the switch signal SS11, and the switch SW12 can be turned on in response to the active level of the switch signal SS12. The first line CL1 can be connected to the second input terminal INN2 of the second CDS circuit 132. The gain control signal GCS can change from logic high to logic low, and the conversion gain control transistor DRX can be turned off in response to the gain control signal GCS. The pixel PX can operate in the HCG mode, and the HCG reset level can be output as the first pixel signal VPS1.

[0096] The second auto - zero signal AZ2 can be bistable - triggered to the active level, and in response to the second auto - zero signal AZ2, the first auto - zero switch SAZ21 and the second auto - zero switch SAZ22 of the second CDS circuit 132 can be turned on, and thus the second CDS circuit 132 can perform an auto - zero operation. When performing the auto - zero operation, the voltage levels of the first input terminal INP2 and the second input terminal INN2 of the comparator 11_2 of the second CDS circuit 132 can be equal to the second auto - zero level. Thereafter, the HCG reset level of the first pixel PX can be read out according to the comparison operation of the comparator 11_2.

[0097] In the third sub-period S13, the first row line CL1 can be connected to the second input terminal INN2 of the second CDS circuit 132. In the third sub-period S13, the first pixel PX1 can operate in the HCG mode, and the HCG image signal can be output as the pixel signal VPS. In the third sub-period S13, the first transfer control signal LTS can be bistate-triggered to the active level, and the first transfer control transistor LTX can be turned on in response to the first transfer control signal LTS. The charges (electrons and / or holes) generated by the large photodiode LPD can be transferred to the first floating diffusion node FD1 and accumulated in the first floating diffusion node FD1, specifically, the parasitic capacitor connected to the first floating diffusion node FD1. The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1 (i.e., the HCG signal level of the first pixel PX1) can be applied to the second input terminal INN2 of the second CDS circuit 132 via the first row line CL1. Therefore, the voltage level of the second input terminal INN2 can be lower than the second auto-zero level. Thereafter, the HCG signal level of the first pixel PX1 can be read out according to the comparison operation of the comparator 11_2. The counter 134 in FIG. 1 can calculate the difference between the value corresponding to the HCG signal level and the value corresponding to the HCG reset level as the pixel value in the HCG mode.

[0098] In the fourth sub-period S14, the switch SW12 can be turned off in response to the inactive level of the switch signal SS12, and the switch SW11 can be turned on in response to the active level of the switch signal SS11. The first row line CL1 can be connected to the second input terminal INN1 of the first CDS circuit 131 again. The gain control signal GCS can transition from logic low to logic high, and the conversion gain control transistor DRX can be turned on in response to the gain control signal GCS. The first floating diffusion node FD1 and the second floating diffusion node FD2 can be connected to each other, and thus, the first pixel PX1 can operate in the LCG mode and the LCG signal level can be output as the first pixel signal VPS1.

[0099] The first transfer control signal LTS can be bistate-triggered to the active level, and the first transfer control transistor LTX can be turned on in response to the first transfer control signal LTS. The remaining charges in the large photodiode LPD can be transferred to the first floating diffusion node FD1 and can be accumulated in the first floating diffusion node FD1.

[0100] The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1 (i.e., the LCG signal level of the first pixel PX1) can be applied to the second input terminal INN1 of the second CDS circuit 132 via the first row line CL1. The voltage level of the second input terminal INN1 of the first CDS circuit 131 can be lower than the first auto-zero level determined in the first sub-period S11. Thereafter, the LCG signal level of the first pixel PX1 can be read out according to the comparison operation of the comparator 11_1. The counter 134 in FIG. 1 can calculate the difference between the value corresponding to the LCG signal level and the value corresponding to the LCG reset level as the pixel value in the LCG mode.

[0101] During the second period P2, the small photodiode SPD can be read out. The second period P2 can include a fifth sub-period S21, a sixth sub-period S22, a seventh sub-period S23, and an eighth sub-period S24. In the fifth sub-period S21 and the sixth sub-period S22, the pixel PX can operate based on the small photodiode SPD in the CDS mode (hereinafter referred to as the SC mode), and in the seventh sub-period S23 and the eighth sub-period S24, the pixel PX can operate based on the small photodiode SPD in the LOFIC mode (hereinafter referred to as the SLOF mode).

[0102] During the second period P2, the switch SW11 can be turned off in response to the inactive level of the switch signal SS11, and the switch SW13 can be turned on in response to the active level of the switch signal SS13. The third CDS circuit 133 can be connected to the first row line CL1, and thus, the third CDS circuit 133 can read out the reset level SC RST and the signal level SC SIG (hereinafter referred to as the SC reset signal and the SC image signal) in the SC mode, and can read out the reset level SLOF RST and the signal level SLOF SIG (hereinafter referred to as the SLOF reset signal and the SLOF image signal) in the SLOF mode.

[0103] The first pixel signal VPS1 output via the first row line CL1 can be provided to the second input terminal INN3 of the third comparison circuit 11_3 via the capacitor C32, and the second ramp signal RAMP2 can be provided to the first input terminal INP3 of the third comparison circuit 11_3 via the capacitor C31.

[0104] In the fifth sub-period S21, the reset transistor RX can be turned off in response to the low logic level of the reset signal RS, and the switch transistor SW can be turned on in response to the high logic level of the switch control signal SWS. Therefore, the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 can be electrically connected to each other to form a floating diffusion node. Thus, the first pixel PX1 can operate in the SC mode, and the SC reset level can be output as the first pixel signal VPS1.

[0105] The third auto-zero signal AZ3 can be bistate-triggered to the active level, and in response to the third auto-zero signal AZ3, the first auto-zero switch SAZ31 and the second auto-zero switch SAZ32 of the third CDS circuit 133 can be turned on, and thus, the third CDS circuit 133 can perform an auto-zero operation. When performing the auto-zero operation, the voltage levels of the first input terminal INP3 and the second input terminal INN3 of the comparator 11_3 of the third CDS circuit 133 can be equal to the third auto-zero level. Thereafter, the SC reset level can be read out according to the comparison operation of the comparator 11_3.

[0106] In the sixth sub-period S22, the first pixel PX1 can operate in the SC mode, and the SC signal level can be output as the first pixel signal VPS1. The second transfer control signal STS can be bistate-triggered to the active level, and the second transfer control transistor STX can be turned on in response to the second transfer control signal STS. The charge generated by the small photodiode SPD can be transferred to the floating diffusion node, that is, the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 that are electrically connected to each other. The first pixel signal VPS1 corresponding to the potential of the floating diffusion node (that is, the SC signal level of the first pixel PX1) can be applied to the second input terminal INN3 of the third CDS circuit 133 via the first row line CL1. Therefore, the voltage level of the second input terminal INN3 can be lower than the third auto-zero level. Thereafter, the SC signal level of the first pixel PX1 can be read out according to the comparison operation of the comparator 11_3.

[0107] In the seventh sub-cycle S23, the first pixel PX1 can operate in the SLOF mode, and the SLOF signal level can be output as the first pixel signal VPS1. The second transfer control signal STS can be bistable-triggered to the active level, and the second transfer control transistor STX can be turned on in response to the second transfer control signal STS. The remaining charge in the small photodiode SPD can be transferred to the floating diffusion node. The first pixel signal VPS1 corresponding to the potential of the first floating diffusion node FD1 (i.e., the SLOF signal level of the first pixel PX1) can be applied to the second input terminal INN3 of the third CDS circuit 133 via the first row line CL1.

[0108] The third auto-zero signal AZ3 can be bistable-triggered to the active level, and in response to the third auto-zero signal AZ3, the first auto-zero switch SAZ31 and the second auto-zero switch SAZ32 of the third CDS circuit 133 can be turned on, and thus, the third CDS circuit 133 can perform an auto-zero operation. When performing the auto-zero operation, the voltage levels of the first input terminal INP3 and the second input terminal INN3 of the comparator 11_3 of the third CDS circuit 133 can be equal to the fourth auto-zero level. Thereafter, the SLOF signal level can be read out according to the comparison operation of the comparator 11_3.

[0109] In the eighth sub-cycle S24, the first pixel PX1 can operate in the SLOF mode, and the SLOF reset level can be output as the first pixel signal VPS1.

[0110] The reset signal RS can be bistable-triggered to the active level, and the reset transistor RX can be turned on in response to the reset signal RS and apply the reset voltage VRD to the floating diffusion node, i.e., apply it to the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 that are electrically connected to each other. Therefore, the potential of the floating diffusion node increases. The SLOF reset level is output as the first pixel signal VPS1, and the voltage level of the second input terminal INN3 increases according to the change of the first pixel signal VPS1. Thereafter, the SLOF signal level of the first pixel PX1 can be read out according to the comparison operation between the voltage level of the first input terminal INP3 of the comparator 11_3 and the voltage level of the second input terminal INN3 of the comparator 11_3.

[0111] In addition, in the second period P2, when the third CDS circuit 133 is connected to the first pixel PX1 via the first row line CL1 and reads out the pixel signal VPS of the first pixel PX1 operating in the SC mode and the SLOF mode, the first CDS circuit 131 and the second CDS circuit 132 can be connected to another pixel such as the second pixel PX2 via the second row line CL2 and read out the second pixel PX2 operating in the LCG mode and the HCG mode.

[0112] In response to the switch signal SS21 having an active level in the fifth sub-period S21 and the eighth sub-period S24, the switch SW12 can be turned on and connect the second row line CL2 to the second input terminal INN1 of the first CDS circuit 131. The second pixel signal VPS2 from the second pixel PX2 according to the LCG mode can be provided to the first CDS circuit 131 via the second row line CL2. In response to the switch signal SS22 having an active level in the sixth sub-period S22 and the seventh sub-period S23, the switch SW22 can be turned on and connect the second row line CL2 to the second input terminal INN1 of the second CDS circuit 132. The second pixel signal VPS2 from the second pixel PX2 according to the HCG mode can be provided to the second CDS circuit 132 via the second row line CL2. The operation of the second pixel PX2 in the second period P2 is the same as the operation of the first pixel PX1 in the first period P1, and thus its repeated description is omitted.

[0113] In this way, the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 are shared by two row lines, and thus, the first pixel PX1 and the second pixel PX2 can be read out in a time-interleaved manner.

[0114] As described above, in the image sensor according to the embodiment, the first CDS circuit 131 can be used in the LCG mode, the second CDS circuit 132 can be used in the HCG mode, and the third CDS circuit 133 can be used in the SC mode and the SLOF mode. Since each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 operates in response to a specific mode, each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be customized according to the corresponding mode. For example, the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be designed to cover the input signal according to the corresponding mode and can have different operating ranges. Therefore, the sizes of the transistors disposed in each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be different from each other, and thus, the layout areas of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be different from each other. In this way, since each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 operates in response to a specific mode, the performance of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be improved and the circuit size (i.e., the layout area) of the ADC circuit 130 including the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in FIG. 1 can be reduced.

[0115] In addition, since the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 are shared by two adjacent row lines according to interleaved readout, the circuit size of the ADC circuit 130 can be reduced compared to the case where the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 are disposed in each row line.

[0116] As shown in FIG. 5B, when the first CDS circuit 131 and the second CDS circuit 132 are connected to the first row line CL1 and the first CDS circuit 131 and the third CDS circuit 133 are connected to the second row line CL2, the first CDS circuit 131 can perform reading of the LCG pixel signal of the pixel (e.g., the first pixel PX1) connected to the first row line CL1, and the second CDS circuit 132 can perform reading of the HCG pixel signal and the small SPD photodiode. In other words, in the first period P1, as shown in FIG. 6, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read the LCG pixel signal and the HCG pixel signal of the first pixel PX1, and in the second period P2, the second CDS circuit CDS2 can read the SC pixel signal and the SLOF pixel signal of the first pixel PX1. In the second period P2, the first CDS circuit 131 can perform reading of the LCG pixel signal of the second pixel PX2, and the third CDS circuit 133 can perform reading of the HCG pixel signal and the small photodiode SPD.

[0117] In this way, the corresponding CDS circuits (e.g., the second CDS circuit 132 and the third CDS circuit 133) can perform read operations on two row lines, and the first CDS circuit 131 can be shared by the two row lines and read the LCG pixel signal of the pixel PX connected to the two row lines. Therefore, the pixels PX connected to the two row lines can be read out alternately.

[0118] Examples in which two row lines share the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 (as shown in FIG. 5A) and various example embodiments in which two row lines share the first CDS circuit 131 (as shown in FIG. 5B) will be described below with reference to FIGS. 9A and 9B.

[0119] FIG. 7 is a timing diagram showing a pixel signal readout scheme of pixels in an image sensor in a comparison example of an image sensor according to various example embodiments in the HCG mode and the LCG mode.

[0120] Referring to FIG. 7, in the image sensor according to the comparative example, one CDS circuit can read the pixel PX. Therefore, one CDS circuit can operate in response to the HCG mode and the LCG mode.

[0121] As described with reference to FIG. 6, the large photodiode LPD can be read out in the first period P1 of the readout period. The first period P1 can include a first sub-period S11, a second sub-period S12, a third sub-period S13, and a fourth sub-period S14. The HCG reset level can be read out in the first sub-period S11, the HCG signal level can be read out in the second sub-period S12, the LCG signal level can be read out in the third sub-period S13, and the LCG reset level can be read out in the fourth sub-period S14. The operation of the second period P2 for reading the small photodiode SPD is the same as that of the second period P2 of the image sensor according to the embodiment described above with reference to FIG. 6, and thus its repeated description is omitted.

[0122] In the comparative example, since when the LCG pixel signal is read out after the HCG pixel signal is read out, one CDS circuit reads out both the HCG pixel signal and the LCG pixel signal, the signal level other than the reset level is read out first. Thereafter, in response to the reset signal RS having an active level, the reset transistor RX can apply the reset voltage VRD to the first floating diffusion node FD1 and the second floating diffusion node FD2, and thus the first floating diffusion node FD1 and the second floating diffusion node FD2 can be reset, and then the LCG reset level can be read out. In this way, when the pixel signal is read out in the incomplete CDS method, the first floating diffusion node FD1 and the second floating diffusion node FD2 are reset before the reset level is determined by the comparison operation of the CDS circuit. Therefore, the correlation between the signal level and the reset level is lost. When the pixel signal is analog-to-digital converted into a pixel value, the kT / C noise of the pixel PX cannot be removed, and thus, the signal-to-noise ratio (SNR) characteristic may not be good. Therefore, according to the comparative example, the SNR characteristic may not be good when the LCG pixel signal is read out.

[0123] However, as described with reference to FIGS. 5A and 6, since the image sensor according to various exemplary embodiments individually includes a first CDS circuit that operates in the LCG mode and is shared by two row lines, and different CDS circuits that operate in the HCG mode and the LCG mode, the pixel PX can be read out in the HCG mode and the LCG mode by the complete CDS method.

[0124] FIG. 8 shows the SNR characteristics of each illuminance of the readout method of the image sensor according to various exemplary embodiments and the readout method according to the comparative example.

[0125] Referring to FIG. 8, the HCG mode corresponds to the lowest illumination region, the LCG mode corresponds to an illumination region higher than the HCG mode, the SLOF mode corresponds to the highest illumination region, and the SC mode corresponds to an illumination region lower than the SLOF mode.

[0126] For example, an external processor of an application processor can generate an HDR image by synthesizing image data generated in each of the HCG mode, the LCG mode, the SC mode, and the SLOF mode.

[0127] As described with reference to FIG. 7, the image sensor according to the comparative example reads the LCG pixel signal in the LCG mode by an incomplete CDS method, and the image sensor according to various exemplary embodiments reads the LCG pixel signal in the LCG mode by a complete CDS method.

[0128] When reading the LCG pixel signal by an incomplete CDS method, an SNR drop may occur between the HCG mode and the LCG mode. The SNR drop between the HCG mode and the LCG mode may further increase as the analog gain of the HCG mode increases.

[0129] As described with reference to FIGS. 5 and 6, in the image sensor according to various exemplary embodiments, when the first CDS circuit 131 reads the LCG pixel signal and the second CDS circuit 132 reads the HCG pixel signal, both the LCG pixel signal and the HCG pixel signal can be read by a complete CDS method. Therefore, the SNR characteristic of the LCG pixel signal is good, and the SNR drop between the HCG mode and the LCG mode can be reduced. As the SNR characteristic of the LCG mode is improved, the quality of the HDR image can be improved. Also, the reduced SNR drop between the HCG mode and the LCG mode makes it possible to use a high analog gain in the HCG mode. Therefore, the HDR performance can be improved by reducing quantization noise, and the apparent sensitivity can be increased due to the improvement of the low illumination SNR.

[0130] FIG. 9A shows the connection between the pixels and the CDS circuit in the image sensor according to various exemplary embodiments, and FIG. 9B is a timing diagram showing the reading of the pixels in FIG. 9A.

[0131] Referring to FIG. 9A, the Nth pixel PX_N, the (N + 1)th pixel PX_N+1, the (N + 2)th pixel PX_N+2, and the (N + 3)th pixel PX_N+3 of the pixel array 110a can be respectively arranged in the same row (at the same position in the X-axis direction) and in different columns, such as the Nth column R_N, the (N + 1)th column R_N+1, the (N + 2)th column R_N+2, and the (N + 3)th column R_N+3. The Nth pixel PX_N, the (N + 1)th pixel PX_N+1, the (N + 2)th pixel PX_N+2, and the (N + 3)th pixel PX_N+3 can be respectively connected to different row lines via the first contact CT1, that is, the first row line CL1, the second row line CL2, the third row line CL3, and the fourth row line CL4.

[0132] Each of the Nth pixel PX_N, the (N + 1)th pixel PX_N+1, the (N + 2)th pixel PX_N+2, and the (N + 3)th pixel PX_N+3 can be connected to the corresponding column lines of a plurality of column lines RL_N, RL_N+1, RL_N+2, and RL_N+3 via the second contact CT2. The Nth pixel PX_N and the (N + 2)th pixel PX_N+2 can respectively receive the same control signals (such as selection signals, transfer control signals, conversion control signals, and switch control signals) via the Nth column line RL_N and the (N + 2)th column line RL_N+2. The (N + 1)th pixel PX_N+1 and the (N + 3)th pixel PX_N+3 can respectively receive the same control signals via the (N + 1)th column line RL_N+1 and the (N + 3)th column line RL_N+3. Here, although one second contact CT2 and one column line are shown connected to each pixel, this is only for convenience of description. For example, a plurality of second contacts CT2 and a plurality of column lines can be connected to each pixel, and the number of second contacts CT2 and column lines connected to each pixel can be determined according to the number of control signals.

[0133] Each of the Nth pixel PX_N, the (N + 1)th pixel PX_N+1, the (N + 2)th pixel PX_N+2, and the (N + 3)th pixel PX_N+3 can include a large photodiode LPD and a small photodiode SPD as described with reference to FIGS. 2A and 2B.

[0134] The CDS circuits CDS11, CDS circuit CDS12, CDS circuit CDS13, CDS circuit CDS21, CDS circuit CDS22, and CDS circuit CDS23 can be disposed on both sides of the pixel array 110a. However, the exemplary embodiments are not limited thereto, and the CDS circuits CDS11, CDS circuit CDS12, CDS circuit CDS13, CDS circuit CDS21, CDS circuit CDS22, and CDS circuit CDS23 can be disposed on one side of the pixel array 110a.

[0135] The CDS circuits CDS11, CDS circuit CDS12, CDS circuit CDS13, CDS circuit CDS21, CDS circuit CDS22, and CDS circuit CDS23 can be connected to the first row line CL1, the second row line CL2, the third row line CL3, and the fourth row line CL4 via the switch circuit SWCa and the switch circuit SWCb (also referred to as a multiplexer). The CDS circuits CDS11, CDS circuit CDS12, and CDS circuit CDS13 can be connected to the first row line CL1 and the second row line CL2, and the CDS circuits CDS21, CDS circuit CDS22, and CDS circuit CDS23 can be connected to the third row line CL3 and the fourth row line CL4. As described with reference to FIG. 5A, the switch circuit SWCa and the switch circuit SWCb can each include a plurality of switches, and during the readout period of the Nth pixel PX N, the (N + 1)th pixel PX N+1, the (N + 2)th pixel PX N+2, and the (N + 3)th pixel PX N+3, the switch circuit SWCa and the switch circuit SWCb can connect the CDS circuits CDS11, CDS circuit CDS12, and CDS circuit CDS13 to the first row line CL1 and the second row line CL2 in a time-division manner, and can connect the CDS circuits CDS21, CDS circuit CDS22, and CDS circuit CDS23 to the third row line CL3 and the fourth row line CL4 in a time-division manner.

[0136] In a first period P1, which will be described below with reference to FIG. 9B, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 can be respectively connected to a first row line CL1 and a third row line CL2. For example, the CDS circuit CDS11 can be connected to the first row line CL1 during a period of outputting a pixel signal corresponding to the LCG reset level of the Nth pixel PX N, and then the CDS circuit CDS12 can be connected to the first row line CL1 during a period of outputting a pixel signal corresponding to the HCG reset level and the HCG signal level of the Nth pixel PX N. Thereafter, the CDS circuit CDS11 can be connected to the first row line CL1 again during a period of outputting a pixel signal corresponding to the LCG signal level of the Nth pixel PX N. Thus, in the first period P1, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 can be respectively connected to the first row line CL1 and the third row line CL2 in a time-division manner.

[0137] In a second period P2, the third CDS circuits CDS13 and CDS23 can be respectively connected to the first row line CL1 and the third row line CL2. Also, in the second period P2, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 can be respectively connected to a second row line CL2 and a fourth row line CL4. Thereafter, in a third period P3, the third CDS circuits CDS13 and CDS23 can be respectively connected to the second row line CL2 and the fourth row line CL4.

[0138] Therefore, the first row line CL1 and the second row line CL2 can share the CDS circuits CDS11, CDS12, and CDS13, and the third row line CL3 and the fourth row line CL4 can share the CDS circuits CDS21, CDS22, and CDS23.

[0139] The first CDS circuits CDS11 and CDS21 can read out the pixel signals of the LCG mode, the second CDS circuits CDS12 and CDS22 can read out the pixel signals of the HCG mode, and the third CDS circuits CDS13 and CDS22 can read out the pixel signals of the SC mode and the SLOF mode. For example, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 located below the pixel array 110a can read out the pixel signals according to the large photodiode LPD, and the third CDS circuits CDS13 and CDS23 located above the pixel array 110a can read out the pixel signals according to the small photodiode SPD.

[0140] Referring to FIG. 9B, in the first read period RD1, the pixels connected to the first row line CL1 and the third row line CL3 can be read out, such as the Nth pixel PX N and the (N + 2)th pixel PX N+2. In the second read period RD2, the pixels connected to the second row line CL2 and the fourth row line CL4 can be read out, such as the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3. The first read period RD1 includes a first period P1 and a second period P2, and the second read period RD2 includes the second period P2 and a third period P3. A part (the second period P2) of the first read period RD1 and a part (the second period P2) of the second read period RD2 can overlap each other.

[0141] In the first period P1, the LCG reset level LCG_RST, the HCG reset level HCG_RST, the HCG signal level HCG_SIG, and the LCG signal level LCG_SIG of each of the Nth pixel PX N and the (N + 2)th pixel PX N+2 can be read out in sequence, and the first CDS circuits CDS11 and CDS21 can read out the LCG reset level LCG_RST and the LCG signal level LCG_SIG. The second CDS circuits CDS12 and CDS22 can read out the HCG reset level HCG_RST and the HCG signal level HCG_SIG.

[0142] In the second period P2, the third CDS circuits CDS13 and CDS23 can sequentially read out the SC reset level SC_RST, SC signal level SC_SIG, SLOF signal level SLOF_SIG, and SLOF reset level SLOF_RST of each of the Nth pixel PX N and the (N + 2)th pixel PX N+2. Also, in the second period P2, the first CDS circuits CDS11 and CDS21 can sequentially read out the LCG reset level LCG_RST, HCG reset level HCG_RST, HCG signal level HCG_SIG, and LCG signal level LCG_SIG of each of the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3.

[0143] In the third period P3, the third CDS circuits CDS13 and CDS23 can sequentially read out the SC reset level SC_RST, SC signal level SC_SIG, SLOF signal level SLOF_SIG, and SLOF reset level SLOF_RST of each of the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3.

[0144] As shown in FIG. 9A, the Nth pixel PX N and the (N + 2)th pixel PX N+2 respectively disposed in the Nth column R N and the (N + 2)th column R N+2 receive the same control signal, and the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 respectively disposed in the (N + 1)th column R N+1 and the (N + 3)th column R N+3 receive the same control signal. Therefore, as shown in FIG. 9B, the Nth pixel PX N and the (N + 2)th pixel PX N+2 are read out simultaneously, and the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 are read out simultaneously. Since the first row line CL1 and the second row line CL2 respectively connected to the Nth pixel PX and the (N + 1)th pixel PX N+1 share the CDS circuits CDS11, CDS12, and CDS13, and the third row line CL3 and the fourth row line CL4 respectively connected to the (N + 2)th pixel PX N+2 and the (N + 3)th pixel PX N+3 share the CDS circuits CDS21, CDS22, and CDS23, the Nth pixel PX N and the (N + 2)th pixel PX N+2, and the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 can be read out simultaneously. Alternatively or additionally, the time points at which the Nth pixel PX N and the (N + 2)th pixel PX N+2 are read out and the time points at which the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 are read out may be staggered.

[0145] FIG. 10A shows the connection between pixels and a CDS circuit in an image sensor according to various exemplary embodiments, and FIG. 10B is a timing diagram showing the readout of the pixels of FIG. 10A.

[0146] The description of the pixel array 110a, the configuration of the CDS circuit, and the switch circuits SWCa and SWCb given with reference to FIG. 9A and the readout operation of the pixels of FIG. 9A can be similarly applied to FIGS. 10A and 10B, and thus their repeated description will be omitted and the differences will be described.

[0147] In a first period P1, which will be described below with reference to FIG. 10B, the first CDS circuits CDS11 and CDS21 and the second CDS circuits CDS12 and CDS22 can be connected to the first row line CL1 and the third row line CL2, respectively. In a second period P2, the second CDS circuits CDS12 and CDS22 can be connected to the first row line CL1 and the third row line CL2, respectively. Also, in the second period P2, the first CDS circuits CDS11 and CDS21 and the third CDS circuits CDS13 and CDS23 can be connected to the second row line CL2 and the fourth row line CL4, respectively. In a third period P3, the third CDS circuits CDS13 and CDS23 can be connected to the second row line CL2 and the fourth row line CL4, respectively.

[0148] Therefore, the first row line CL1 and the second row line CL2 can share the first CDS circuit CDS11, and the third row line CL3 and the fourth row line CL4 can share the first CDS circuit CDS21. The first CDS circuit CDS11 and the first CDS circuit CDS21 can read the pixel signals of the LCG mode of each of the Nth pixel PX N and the (N + 2)th pixel PX N+2 in the first period P1, and can read the pixel signals of the LCG mode of each of the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 in the second period P2. The second CDS circuit CDS12 and the second CDS circuit CDS22 can read the pixel signals of the HCG mode of each of the Nth pixel PX N and the (N + 2)th pixel PX N+2 in the first period P1, and can read the pixel signals of the SC mode and the SLOF mode of each of the Nth pixel PX N and the (N + 2)th pixel PX N+2 in the second period P2. The third CDS circuit CDS13 and the third CDS circuit CDS23 can read the pixel signals of the HCG mode of each of the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 in the second period P2, and can read the pixel signals of the SC mode and the SLOF mode of each of the (N + 1)th pixel PX N+1 and the (N + 3)th pixel PX N+3 in the third period P3.

[0149] For example, the second CDS circuit CDS12 and the third CDS circuit CDS13 can respectively read the pixels connected to the first row line CL1 and the second row line CL2, such as the Nth pixel PX N and the (N + 1)th pixel PX N+1, but the first CDS circuit CDS11 can be shared by the first row line CL1 and the second row line CL2, and thus can read the LCG pixel signals of each of the Nth pixel PX N and the (N + 1)th pixel PX N+1. Also, the second CDS circuit CDS12 and the third CDS circuit CDS13 can respectively read the pixels connected to the third row line CL1 and the fourth row line CL2, such as the (N + 2)th pixel PX N+2 and the (N + 3)th pixel PX N+3, but the first CDS circuit CDS11 can be shared by the third row line CL3 and the fourth row line CL4, and thus can read the LCG pixel signals of each of the (N + 2)th pixel PX N+2 and the (N + 3)th pixel PX N+3 connected to the third row line CL3 and the fourth row line CL4.

[0150] Since the first CDS circuit CDS11 is shared by the first row line CL1 and the second row line CL2, that is, since the first CDS circuit CDS11 is connected to the first row line CL1 and the second row line CL1 in a time-division manner, the Nth pixel PX N and the (N + 1)th pixel PX N+1 can be read out alternately. Since the first CDS circuit CDS21 is shared by the third row line CL3 and the fourth row line CL4, that is, since the first CDS circuit CDS21 is connected to the third row line CL3 and the fourth row line CL4 in a time-division manner, the (N + 2)th pixel PX N+2 and the (N + 3)th pixel PX N+3 can be read out alternately.

[0151] As described with reference to FIGS. 9A and 10A, in an image sensor according to various example embodiments, two adjacent row lines such as the first row line CL1 and the second row line CL2 and the third row line CL3 and the fourth row line CL4 can share the first CDS circuit CDS11 and the first CDS circuit CDS21 for reading the LCG pixel signals and read the pixels in an interleaved manner. Therefore, compared with the case of providing CDS circuits corresponding to each of the first row line CL1, the second row line CL2, the third row line CL3, and the fourth row line CL4 to read the LCG pixel signals, the layout area of the CDS circuits can be reduced.

[0152] FIGS. 11A and 11B show the connection between pixels and CDS circuits in an image sensor according to various example embodiments, and FIG. 11C is a timing diagram showing the reading of the pixels of FIGS. 11A and 11B.

[0153] Referring to FIG. 11A, the ADC circuit 130 can be disposed on one side of the pixel array 110 and includes a first CDS circuit CDS1, a second CDS circuit CDS2, and a third CDS circuit CDS3. The first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be arranged for each pixel pitch PPC.

[0154] In the pixel array 110, the pixels PX arranged in the same row can be alternately connected to two adjacent row lines CL. The switch circuit SWC can be disposed between the pixel array 110 and the ADC circuit 130 and connect the two row lines to the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 in a time-division manner.

[0155] Referring to FIG. 11B, the ADC circuit 130a and the ADC circuit 130b can be disposed on opposite sides of the pixel array 110. Additionally, the first CDS circuit CDS1 and the second CDS circuit CDS2 can be disposed on one side of the pixel array 110, and the third CDS circuit CDS3 can be disposed on the other side of the pixel array 110. The switch circuit SWCa can be disposed between the pixel array 110 and the ADC circuit 130a and can connect two row lines to the first CDS circuit CDS1 and the second CDS circuit CDS2 in a time-division manner. The switch circuit SWb can be disposed between the pixel array 110 and the ADC circuit 130b and can connect two row lines to the third CDS circuit CDS3 in a time-division manner.

[0156] Referring to FIG. 11C, pixels disposed in multiple columns (e.g., the Nth column RN, the (N + 1)th column RN+1, the (N + 2)th column RN+2, and the (N + 3)th column RN+3) of the pixel array 110 can be read out alternately.

[0157] In period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixel PX disposed in the Nth column RN. In period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS2) can read out the pixel signal SC in the SC mode and the pixel signal SL in the SLOF mode from the pixel PX disposed in the Nth column RN. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS3) can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixel PX disposed in the (N + 1)th column RN+1.

[0158] In period T3, the third CDS circuit CDS3 can read out the pixel signal SC in the SC mode and the pixel signal SL in the SLOF mode from the pixel PX disposed in the (N + 1)th column RN+1. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixel PX disposed in the (N + 2)th column RN+2.

[0159] In this manner, the first CDS circuit CDS1 can be shared by two adjacent row lines CL, or the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be shared by two adjacent row lines CL, and thus the pixels PX arranged in multiple columns can be read out alternately. In addition, since the pixels arranged in two columns are read out simultaneously, the frame rate can be increased.

[0160] FIGS. 12A and 12B illustrate the connection between pixels and CDS circuits in an image sensor according to various exemplary embodiments, and FIG. 12C is a timing diagram showing the readout of the pixels of FIGS. 12A and 12B.

[0161] Referring to FIG. 12A, the ADC circuit 130a can be disposed on one side of the pixel array 110a and includes a first CDS circuit CDS1, a second CDS circuit CDS2, and a third CDS circuit CDS3. Two pairs of the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be arranged for each pixel pitch PPC.

[0162] In the pixel array 110a, the pixels PX arranged in the same row can be alternately connected to four adjacent row lines CL. The switch circuit SWC can be disposed between the pixel array 110a and the ADC circuit 130a and connect two row lines to the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 in a time-division manner.

[0163] Referring to FIG. 12B, the ADC circuit 130a and the ADC circuit 130b can be disposed on opposite sides of the pixel array 110a. In addition, the first CDS circuit CDS1 and the second CDS circuit CDS2 can be disposed on one side of the pixel array 110a, and the third CDS circuit CDS3 can be disposed on the other side of the pixel array 110a. The switch circuit SWCa can be disposed between the pixel array 110a and the ADC circuit 130a and connect two row lines to the first CDS circuit CDS1 and the second CDS circuit CDS2 in a time-division manner. The switch circuit SWb can be disposed between the pixel array 110a and the ADC circuit 130b and connect two row lines to the third CDS circuit CDS3 in a time-division manner.

[0164] Referring to FIG. 12C, the pixels arranged in multiple columns (e.g., the Nth column RN, the (N + 1)th column RN+1, the (N + 2)th column RN+2, and the (N + 3)th column RN+3) of the pixel array 110a can be read out alternately.

[0165] During period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L of the LCG mode and the pixel signal H of the HCG mode from the pixels PX disposed in the Nth column RN and the (N + 2)th column RN+2. During period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS2) can read out the pixel signal SC of the SC mode and the pixel signal SL of the SLOF mode from the pixels PX disposed in the Nth column RN and the (N + 2)th column RN+2. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS3) can read out the pixel signal L of the LCG mode and the pixel signal H of the HCG mode from the pixels PX disposed in the (N + 1)th column RN+1 and the (N + 3)th column RN+3.

[0166] During period T3, the third CDS circuit CDS3 can read out the pixel signal SC of the SC mode and the pixel signal SL of the SLOF mode from the pixels PX disposed in the (N + 1)th column RN+1 and the (N + 3)th column RN+3. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L of the LCG mode and the pixel signal H of the HCG mode from the pixels PX disposed in the (N + 4)th column RN+4 and the (N + 6)th column RN+6.

[0167] In this way, the first CDS circuit CDS1 can be shared by two adjacent row lines CL, or the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be shared by two adjacent row lines CL, and thus the pixels PX disposed in multiple columns can be read out alternately. Alternatively or additionally, since the pixels disposed in four columns are read out simultaneously, the frame rate can be increased.

[0168] FIG. 13A shows the connection between the pixels and the CDS circuits in an image sensor according to various example embodiments, and FIG. 13B is a timing diagram showing the readout of the pixels of FIG. 13A.

[0169] Referring to FIG. 13A, the ADC circuit 130 can be disposed on one side of the pixel array 110b and includes the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3. The first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be disposed for each two pixel pitches PPC.

[0170] In the pixel array 110b, the pixels PX arranged in the same row can be connected to the same row line CL. The switch circuit SWC can be disposed between the pixel array 110c and the ADC circuit 130, and can connect two row lines to the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 in a time-division manner.

[0171] Referring to FIG. 13B, the pixels arranged in multiple columns (e.g., the Nth column RN, the (N + 1)th column RN+1, the (N + 2)th column RN+2, and the (N + 3)th column RN+3) of the pixel array 110b can be read out alternately.

[0172] In the period T1, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixels PX O arranged in the odd rows of the Nth column RN. In the period T2, the third CDS circuit CDS3 (or the second CDS circuit CDS2) can read out the pixel signal SC in the SC mode and the pixel signal SL in the SLOF mode from the pixels PX O arranged in the odd rows of the Nth column RN. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 (or the third CDS circuit CDS3) can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixels PX E arranged in the even rows of the Nth column RN.

[0173] In the period T3, the third CDS circuit CDS3 can read out the pixel signal SC in the SC mode and the pixel signal SL in the SLOF mode from the pixels PX arranged in the even rows of the Nth column RN. In this case, the first CDS circuit CDS1 and the second CDS circuit CDS2 can read out the pixel signal L in the LCG mode and the pixel signal H in the HCG mode from the pixels PX O arranged in the odd rows of the (N + 1)th column RN+1.

[0174] In this way, the first CDS circuit CDS1 can be shared by two adjacent row lines CL (e.g., the odd row line and the even row line), or the first CDS circuit CDS1, the second CDS circuit CDS2, and the third CDS circuit CDS3 can be shared by two adjacent row lines CL, and thus the pixels PX O arranged in the odd rows of multiple columns and the pixels PX E arranged in their even rows can be read out alternately.

[0175] FIGS. 14A and 14B illustrate the stacked structures of image sensors according to various example embodiments.

[0176] Referring to FIG. 14A, an image sensor 1 according to various example embodiments may include a plurality of stacked wafers. For example, the image sensor 1 may include: an upper wafer 40 including a pixel array region or a sensing region SA, an intermediate wafer 50 including a circuit region LC, and a lower wafer 60 including a memory region MC. In various example embodiments, the lower wafer 60 may include a dummy region DC. Dummy cells may be disposed in the dummy region DC. In some example embodiments, the upper wafer 40 and the intermediate wafer 50 may be stacked on top of each other at the wafer level, and the lower wafer 60 may be attached to the bottom of the intermediate wafer 50 at the wafer level.

[0177] The upper wafer 40 may include a sensing region SA configured with a plurality of pixels PX and a first pad region PA1 surrounding the sensing region SA. A plurality of upper pads PAD may be configured in the first pad region PA1. The plurality of upper pads PAD may be connected to pads configured in a second pad region PA2 of the intermediate wafer 50 via vias or the like, and thus connected to circuits in the circuit region LC.

[0178] The intermediate wafer 50 may include a circuit region LC configured with analog circuits and digital circuits and a second pad region PA2 surrounding the circuit region LC. The circuits in the circuit region LC may include circuits for driving pixel circuits disposed in the upper wafer 40, such as a column driver (e.g., the column driver 120 in FIG. 1), an ADC circuit (e.g., the ADC circuit 130 in FIG. 1), and a timing controller (e.g., the timing controller 150 in FIG. 1).

[0179] The lower wafer 60 may include a memory region MC and a dummy region DC. In some embodiments, the dummy region DC may be omitted. Also, in some embodiments, the lower wafer 60 may have a packaging structure. For example, each of the memory region MC and the dummy region DC may be manufactured or processed into a wafer and sealed together with a sealing material, and thus, the lower wafer 60 may have a packaging structure including two wafers. Memory elements such as dynamic random access memory (DRAM) elements and / or static random access memory (SRAM) elements may be disposed in the memory region MC. However, the memory elements disposed in the memory region MC are not limited to DRAM elements or SRAM elements. Memory elements may not be disposed in the dummy region DC. The dummy region DC may have a function of supporting the intermediate wafer 50 and the lower wafer 60 rather than a function of storing data. The memory elements of the memory region MC may be electrically connected to at least some of the circuits in the circuit region LC of the intermediate wafer 50 via bumps or vias.

[0180] Referring to FIG. 14B, an image sensor 2 according to various example embodiments may include an upper wafer 70 and a lower wafer 80. The upper wafer 70 may include a sensing region SA in which a plurality of pixels PX are provided, a circuit region LC in which devices for driving the plurality of pixels PX are provided, and a pad region surrounding the sensing region SA and the circuit region LC. A plurality of upper pads PAD may be disposed in the pad region PA, and the plurality of upper pads PAD may be connected to the memory elements in the memory region MC provided in the lower wafer 80 via vias or the like. The lower wafer 80 may include a memory region MC and a dummy region DC. The lower wafer 80 may be substantially the same as the lower wafer 60 of the image sensor 1 in FIG. 14A. Accordingly, a detailed description of the lower wafer 80 is omitted.

[0181] FIG. 15 is a block diagram schematically showing an electronic device including an image sensor according to various example embodiments.

[0182] Referring to FIG. 15, an electronic device 1000 may include an image sensor 1100 and an application processor (AP) 1200. The electronic device 1000 may further include various sensors such as an illuminance sensor and / or a communication module.

[0183] The application processor 1200 may provide a control signal for controlling the operation of the image sensor 1100 to the image sensor 1100. The transmission of the control signal may be performed based on an interface, such as I2C. The control signal may further include configuration data of the image sensor 1100, such as one or more of a lens shading correction value, a crosstalk coefficient, an analog gain, a digital gain, and a frame rate setting value.

[0184] The image sensor 1100 may generate image data IDT by capturing an image of an object based on the received control signal. The image data IDT may include a still image and a moving image. The image sensor 1100 may perform signal processing on the image data IDT, such as one or more of image quality compensation, pixel binning, and miniaturization, and the image quality compensation may include signal processing, such as one or more of black level compensation, lens shading compensation, crosstalk compensation, and defective pixel correction.

[0185] The image sensor 100 described with reference to FIGS. 1 to 14B may be applied as the image sensor 1100. Each of the plurality of pixels included in the pixel array of the image sensor 1100 (e.g., the pixel array 110 in FIG. 1) may include a first photodiode (e.g., a large photodiode) and a second photodiode (e.g., a small photodiode), and may operate based on the first photodiode in a first mode and a second mode (e.g., an LCG mode and an HCG mode), and operate based on the second photodiode in a third mode and a fourth mode (e.g., an SC mode and an SLOF mode).

[0186] The first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in FIG. 1 may read out pixels connected to two adjacent row lines, and the two row lines may share the first CDS circuit 131 for reading out pixel signals in the LCG mode, or may share the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133.

[0187] Since a CDS circuit does not read all pixel signals of the LCG mode, HCG mode, SC mode, and SLOF mode, but the first CDS circuit 131 reads the pixel signals of the LCG mode, the pixel signals of the LCG mode can be read out by a complete CDS method, and thus the SNR characteristics of the LCG mode can be improved. According to the interleaved readout method, the first CDS circuit 131 can be shared by two row lines, and thus the circuit size (i.e., the layout area of the CDS circuit) can be reduced compared to the case where the first CDS circuit 131 is connected to each row line. Alternatively or additionally, when the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 in FIG. 1 are shared by two adjacent row lines, each of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 operates to correspond to a certain mode and can thus be customized according to the corresponding mode. Therefore, the performance of the first CDS circuit 131, the second CDS circuit 132, and the third CDS circuit 133 can be improved and / or the circuit size can be reduced.

[0188] The image sensor 1100 can transmit the image data IDT or the signal-processed image data IDT to the application processor 1200. The image sensor 1100 can transmit the image data IDT including the first-mode image to the fourth-mode image corresponding to the first mode to the fourth mode to the application processor 1200.

[0189] The transmission of the image data IDT can be performed using, for example, a camera serial interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but the example embodiments are not limited thereto.

[0190] The application processor 1200 can perform image processing on the received image data IDT, such as one or more of defective pixel correction, 3A adjustment (autofocus correction, automatic white balance, and automatic exposure), noise reduction, sharpening, gamma control, remosaic, demosaic, and resolution scaling (video / preview).

[0191] Alternatively or additionally, the application processor 1200 can generate an image with a high dynamic range by performing high dynamic range (HDR) processing on the first-mode image to the fourth-mode image.

[0192] According to various example embodiments, in an image sensor having a pixel structure in which a plurality of photoelectric conversion elements share a driving transistor, an increase in the size of a readout circuit can be reduced or minimized, and / or a complete CDS can be supported in a low conversion gain mode. Accordingly, in the low conversion gain mode, the SNR characteristic can be improved to thereby improve the image quality of the image sensor and / or the high dynamic range (HDR) performance.

[0193] Any one of the elements and / or functional blocks disclosed above may be included or implemented in a processing circuitry, such as hardware including logic circuits, a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0194] Although the inventive concept has been specifically shown and described with reference to various example embodiments, it will be understood that various changes may be made in its form and details without departing from the spirit and scope of the following claims. In addition, example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more drawings, and may also include one or more other features described with reference to one or more other drawings.

[0195] 1, 2, 100, 1100: Image sensor 11: Comparator 11_1: First comparator 11_2: Second comparator 11_3: Third comparator 12: Amplifier 40, 70: Upper wafer 50: Intermediate wafer 60, 80: Lower wafer 110, 110a, 110b: Pixel array 120: Column driver 130, 130a, 130b: ADC circuit 131, CDS1, CDS11, CDS21: First CDS circuit 132, CDS2, CDS12, CDS22: Second CDS circuit 133, CDS3, CDS13, CDS23: Third CDS circuit 134: Counter 135: ADC 140: Ramp signal generator 150: Timing controller 160: Image signal processor 1000: Electronic device 1200: Application processor AZ: Auto-zero signal AZ1: First auto-zero signal AZ2: Second auto-zero signal AZ3: Third auto-zero signal C1: First capacitor C2: Second capacitor C11, C12, C21, C22, C31, C32, C LOF: Capacitor CDSCa, CDSCb: CDS circuit CL: Row line CL1: First row line CL2: Second row line CL3: Third row line CL4: Fourth row line CS: Current source CT1: First contact CT2: Second contact DC: dummy area DRX: Gain control transistor / Conversion gain control transistor DX: Drive transistor FD1: First floating diffusion node FD2: Second floating diffusion node FD3: Third floating diffusion node GCS: Gain control signal IDT: Image data IL: Bias current INN, INN1, INN2, INN3: Second input terminal INP, INP1, INP2, INP3: First input terminal LC: Circuit area LCG RST, HCG RST, SC RS, SLOF RST: Reset level LCG SIG, HCG SIG, SC SIG, SLOF SIG: Signal level LPD: Large photodiode LTS: First transfer control signal LTX: First transfer transistor MC: Memory area ON: Second output terminal OP: First output terminal P1: First period P2: Second period P3: Third period PA: Pad area PA1: First pad area PA2: Second pad area PAD: Upper pad PPC: Pixel pitch PX, Pxa, PXb, PX O, PX E: Pixel PX N: Nth pixel PX N+1: (N + 1)th pixel PX N+2: (N + 2)th pixel PX N+3: (N + 3)th pixel RAMP: Ramp signal RAMP1: First ramp signal RD1: First readout period RD2: Second readout period RL: Column line R N: Nth column / column line R N+1: (N + 1)th column / column line R N+2: (N + 2)th column / column line R N+3: (N + 3)th column / column line R N+4: (N + 4)th column R N+6: (N + 6)th column RS: Reset control signal RX: Reset Transistor R_LCG, R_SPD: Comparison Result Signal S11: First Sub - period S12: Second Sub - period S13: Third Sub - period S14: Fourth Sub - period S21: Fifth Sub - period S22: Sixth Sub - period S23: Seventh Sub - period S24: Eighth Sub - period SA: Sensing Area SAZ1, SAZ11: First Auto - Zero Switch SAZ2, SAZ12: Second Auto - Zero Switch SEL: Select Signal SPD: Small Photo - Diode SS11, SS12, SS21, SS22, SS31, SS32: Switching Signal STS: Second Transfer Control Signal STX: Second Transfer Transistor SW11, SW12, SW21, SW22, SW31, SW32: Switch SWC, SWCa, SWCb: Switching Circuit SWS: Switching Control Signal SWT: Switching Transistor SX: Selection Transistor T1, T2, T3, T4, T5: Period VPIX: Pixel Power Supply Voltage VPS, L, H, SC, SL: Pixel Signal VPS1: First Pixel Signal VPS2: Second Pixel Signal VRD: Reset Voltage

Claims

1. An image sensor, comprising: A pixel array including a first pixel connected to a first row line and a second pixel connected to a second row line, wherein each of the first pixel and the second pixel includes a first photodiode (PD) and a second PD sharing a driving transistor, the first pixel and the second pixel being configured to operate in a first mode and a second mode based on the respective first PD according to a conversion gain, and the first pixel and the second pixel being configured to operate in a third mode and a fourth mode based on the respective second PD; and an analog-to-digital converter including a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals output via the first row line and the second row line, wherein the first CDS circuit is configured to be connected to the first row line and the second row line in a time-division multiplexing manner, wherein the first CDS circuit is configured to read a first mode pixel signal of the first pixel output via the first row line in a first cycle, and is configured to read a first mode pixel signal of the second pixel output via the second row line in a second cycle after the first cycle. The third CDS circuit is configured to read the third mode pixel signal and the fourth mode pixel signal of the first pixel of the first signal output via the first row line in the second cycle.

2. The image sensor as claimed in claim 1, wherein: The first mode pixel signal includes a reset level and a signal level, and the first CDS circuit is configured to read the signal level after reading the reset level.

3. The image sensor of claim 1, wherein the second CDS circuit is configured to read a second mode pixel signal of the first pixel output via the first row line in the first cycle, and is configured to read a second mode pixel signal of the second pixel output via the second row line in the second cycle.

4. The image sensor of claim 3, wherein the first period includes a first sub-period, a second sub-period, a third sub-period, and a fourth sub-period, the first CDS circuit is configured to read the reset level of the first mode pixel signal in the first sub-period, the second CDS circuit is configured to read the reset level of the second mode pixel signal in the second sub-period, the second CDS circuit is configured to read the signal level of the second mode pixel signal in the third sub-period, the first CDS circuit is configured to read the signal level of the first mode pixel signal in the fourth sub-period, and a first conversion gain of the first mode is less than a second conversion gain of the second mode.

5. The image sensor of claim 1, wherein the layout area of ​​at least one of the first CDS circuit, the second CDS circuit, and the third CDS circuit is different from at least one of the other three CDS circuits.

6. The image sensor as claimed in claim 1, wherein the light-receiving area of ​​the first PD is greater than the light-receiving area of ​​the second PD.

7. The image sensor as claimed in claim 1, wherein each of the first pixel and the second pixel further comprises: A first transfer transistor is connected to the first PD and the first floating diffusion node (FD). A gain control transistor is connected to the first FD and the second FD; A reset transistor is connected to the second FD and has an end configured to receive a first power supply voltage; a second transfer transistor is connected to the second PD and the third FD; A switching transistor is connected to the second FD and the third FD; And a capacitor, connected to the third FD and having an end configured to receive the first power supply voltage.

8. The image sensor as claimed in claim 7, wherein the capacitor is configured to store charge overflowing from the second PD.

9. The image sensor as claimed in claim 7, wherein: In the first mode, the gain control transistor is configured to be turned on, and the switching transistor and the reset transistor are configured to be turned off. In the second mode, the gain control transistor, the switching transistor, and the reset transistor are configured to be turned off. In the third mode, the gain control transistor and the switching transistor are configured to be turned on, and the reset transistor is configured to be turned off. In the fourth mode, the control transistor and the switching transistor are configured to be turned on, and the reset transistor is configured to be triggered once in a dual-state configuration.

10. The image sensor as claimed in claim 1, wherein the first pixel and the second pixel are in the same row and adjacent columns.

11. The image sensor as claimed in claim 1, wherein the first pixel and the second pixel are in adjacent rows and the same column.

12. An image sensor, comprising: A pixel array includes a plurality of pixels, a plurality of column lines configured to provide control signals to the plurality of pixels, and a plurality of row lines configured to output a plurality of pixel signals generated from the plurality of pixels, wherein each of the plurality of pixels includes a first photodiode (PD) and a second PD sharing a driving transistor; an analog-to-digital converter is configured to convert the plurality of pixel signals output via the plurality of row lines, and includes a first correlated double sampling (CDS) circuit, a second CDS circuit, and a third CDS circuit configured to read pixel signals received via a first row line and a second row line of the plurality of row lines; and a switching circuit configured to connect the first row line to the first CDS circuit and the second CDS circuit and connect the second row line to the third CDS circuit in a time-division multiplexing manner during a first cycle, and to connect the second row line to the first CDS circuit and the second CDS circuit and connect the first row line to the third CDS circuit in a time-division multiplexing manner during a second cycle.

13. The image sensor of claim 12, wherein each of the plurality of pixels is configured to operate in a first mode and a second mode based on the first PD according to the conversion gain, and in a third mode and a fourth mode based on the second PD according to the output order of the reset level and the signal level.

14. The image sensor as claimed in claim 13, wherein: In the first cycle, the first CDS circuit is configured to read the first mode signal of the first pixel received via the first row line, the second CDS circuit is configured to read the second mode signal of the first pixel received via the first row line, and the third CDS circuit is configured to read the third mode signal and the fourth mode signal of the second pixel received via the second row line. In the second cycle, the first CDS circuit is configured to read the first mode signal of the third pixel received via the second row line, the second CDS circuit is configured to read the second mode signal of the third pixel received via the second row line, and the third CDS circuit is configured to read the third mode signal and the fourth mode signal of the first pixel received via the first row line.

15. The image sensor of claim 12, wherein the first CDS circuit and the second CDS circuit are on a first side of the pixel array, the third CDS circuit is on a second side of the pixel array, and the first side and the second side are sides perpendicular to the direction in which the first row line and the second row line extend.

16. An electronic device comprising: An image sensor is configured to generate a first-mode image, a second-mode image, a third-mode image, and a fourth-mode image, wherein each of the first-mode image to the fourth-mode image is configured to be generated based on an exposure; and an application processor is configured to receive each of the first-mode image, the second-mode image, the third-mode image, and the fourth-mode image from the image sensor, and to generate an image with high dynamic range by combining the first-mode image, the second-mode image, the third-mode image, and the fourth-mode image, wherein the image sensor includes... A pixel array includes a plurality of pixels, wherein each of the plurality of pixels includes a first photodiode (PD) and a second PD sharing a driving transistor, and is configured to output a first mode signal and a second mode signal as pixel signals generated based on charges from the first PD in a first mode and a second mode, and to output a third mode signal and a fourth mode signal as pixel signals generated based on charges from the second PD in a third mode and a fourth mode, wherein the light-receiving area of ​​the first PD is greater than the light-receiving area of ​​the second PD, and a first correlation double sampling (CDS), a second CDS circuit and a third CDS circuit are configured to read out a first pixel connected to a first row line and a second pixel connected to a second row line from the plurality of pixels in a time-division multiplexing manner.

17. The electronic device of claim 16, wherein the first CDS circuit is configured to read the first mode signal of the first pixel output via the first row line in a first cycle, and to read the first mode signal of the second pixel output via the second row line in a second cycle, wherein the first mode is a low conversion gain mode.

18. The electronic device of claim 17, wherein the first mode signal includes a reset level and a signal level, and the first CDS circuit is configured to read the signal level after reading the reset level.

Images