Memory device and operating method thereof

Abstract

This invention discloses a memory device comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell includes two P-type MOSFET devices for storing data bits and two access transistors acting as access switches. Compared to a conventional 6T-SRAM cell, the 4T-SRAM cell has fewer MOSFET devices, occupies a smaller area, and has less leakage current. The read circuit includes a latch and a discharge device. The latch, coupled between a supply voltage rail and a ground voltage rail, has two output nodes. The discharge device is coupled to the two output nodes, the bit line, and the ground voltage rail. Because one of the two storage nodes of the 4T-SRAM cell is in a floating state, reading the stored data in the 4T-SRAM cell using conventional read operations is prone to errors. The read circuit of this invention solves the aforementioned error-prone drawback of reading data from 4T-SRAM cells.

Description

Memory Device and Its Operating Method The present invention relates to a four transistor Static Random Access Memory (4T SRAM) and its operating method. The 4T SRAM cell includes two P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) (such as 201 and 202 in Figure 2) for storing data, and two N-type MOSFETs (such as 203 and 204 in Figure 2) acting as access switches, and the 4T SRAM cell can be used to form a memory array. A plurality of 4T SRAM cells can form a memory array. In particular, the present invention discloses a read circuit and a write circuit for operating the 4T SRAM cell. Semiconductor memories have been widely used in electronic systems. Electronic systems require semiconductor memories to store instructions and data, which are derived from the basic functions of controlling complex computing processes. Semiconductor memories can be divided into volatile memories and non-volatile memories. Volatile memories include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), and the data stored in them will disappear after the memory power is turned off. Non-volatile memories, such as Read Only Memory (ROM), Electrical Erasable Programmable Read Only Memory (EEPROM), and Flash, can still store data after the memory power is turned off. Because computer processors operate at high clock speeds (MHz to dozens of GHz), the access time for reading data from and changing data in memory needs to match the computing speed of the computer processor. Due to the fast random memory access time during read / write operations, non-volatile SRAM and DRAM have become the memory choices for computer processors. At the same time, a DRAM cell contains a MOSFET device and a capacitor, where the MOSFET device serves as an access switch and the capacitor serves as data storage. The DRAM cell can be manufactured with extremely high density at a very low manufacturing cost per-bit-storage using DRAM processes. Please refer to Figure 1. The conventional six-transistor static random access memory (6T SRAM) cell 100 includes six MOSFET devices: two N-type MOSFET devices (103 and 104) serving as data access switches, and two P-type and two N-type MOSFET devices (101, 102, 105, and 106) serving as data storage. The above-mentioned conventional 6T-SRAM cell 100 is manufactured using CMOS (complementary metal-oxide-semiconductor) process technology, which is the same as the process technology of digital processor circuits. However, the size of the traditional 6T-SRAM cell occupies a large silicon area, resulting in a very high manufacturing cost per-bit-storage. Therefore, the industry is highly anticipating being able to reduce the size of the SRAM cell to increase memory density and reduce the manufacturing cost per-bit-storage. On the other hand, for one-bit memory storage, the size of the 6T SRAM cell 100 in Figure 1 is typically reduced to the size of the 4T SRAM cell 200 in Figure 2 at a ratio of 25% to 35%, resulting in a higher SRAM density and a lower manufacturing cost per-bit-storage. Compared with the 6T SRAM cell 100, the 4T SRAM cell 200 not only has the advantage of a smaller size but also has less retention leakage current. For one-bit data storage, according to the schematic diagram of the 4T SRAM cell 200 in Figure 2, the data storage circuit 30L of the 4T SRAM cell 200 in Figure 3A includes two cross-connected P-type MOSFET devices 201 and 202, and there is no device channel diffusion leakage current (i.e., low voltage not connected to the ground voltage) from the high voltage rail Flows to the ground voltage; for the data storage of one bit, according to the schematic diagram of the 6T SRAM cell 100 in FIG. 1, the data storage circuit 30R of the 6T SRAM cell 100 in FIG. 3B includes two interconnected inverters 303 and 304, at nodes 31 and 32, having a path from the high voltage rail Flows to the ground voltage node The PFET device channel diffusion leakage current 35 and the NFET device channel diffusion leakage current 34, and vice versa. Generally, depending on the design of the MOSFET device and the applied high voltage The MOSFET device channel diffusion leakage current ranges from about dozens of picoamperes (pA) to 1 nanoampere (nA). The total standby leakage current of a conventional 6T SRAM array is equal to (the number of SRAM cells) (PFET device channel diffusion leakage current 35 + NFET device channel diffusion leakage current 34), while the 4T SRAM cell 200 only has N-drain / P-substrate (access NFET transistors 203 / 204) and P-drain / N-well (storage node) junction leakage currents, which are usually several orders of magnitude smaller than the strength of the MOSFET device channel diffusion leakage current. According to an aspect of the present invention, different from that of a conventional 6T SRAM cell where one storage node is always biased at the ground voltage, the low voltage node of the 4T SRAM cell 200 Is not connected to the ground voltage. Therefore, the write circuit 410 of the 4T SRAM cell 200 is designed to simultaneously set the voltage potentials of the two storage nodes 246 / 245 to a high voltage And the ground voltage . According to an aspect of the present invention, different from that of a conventional 6T SRAM cell where one storage node is always biased at the ground voltage, the low voltage node of the 4T SRAM cell 200 Is not connected to the ground voltage. Therefore, during the read process, a floating storage node of the 4T SRAM cell 200 must be restored to the ground voltage to retain the original stored data. The read circuit 510 is designed to have the ability to restore the floating storage node of the selected 4T SRAM cell 200 to the ground voltage during the read process. According to an aspect of the present invention, since the voltage potential of the floating storage node of the 4T SRAM cell 200 is lower than the high voltage potential of the other storage node , the read circuit 510 is designed to detect the asymmetric voltage difference between the two storage nodes of the selected 4T SRAM cell 200 ( ), in order to obtain a full digital voltage signal of the output signal, that is, a high voltage and a ground voltage , wherein, represents the voltage potential of the floating storage node of the 4T SRAM cell 200 during the data retention period, as shown in FIG. 6. The voltage potential of the floating storage node is lower than the supply voltage and higher than the ground voltage due to the channel diffusion current of the PFET devices 201 / 202 ( to stable ), and the reverse P-drain / N-well junction leakage current ( to stable ), as well as the detailed balance leakage current between the reverse N-drain / P-substrate junction leakage currents of the access NFET devices 203 / 204 (stable ), the voltage potential of the stable floating storage node of the 4T SRAM cell 200 can be obtained (curve 605 in FIG. 6). Generally speaking, the larger the reverse N-drain / P-substrate junction leakage current of the access NFET devices 203 / 204, the lower the voltage potential of the stable floating storage node approaching the ground voltage. According to another aspect of the present invention, different from the conventional 6T SRAM cell in which one storage node is always biased at the ground voltage, the read circuit 510 of the 4T SRAM cell 200 is designed to avoid changing the voltage potential of the floating storage node of the selected 4T SRAM cell 200 due to residual charges on the bit line / complementary bit line of the 4T SRAM array, thereby flipping the original stored data value to an incorrect inverted data value. FIG. 4 is a schematic diagram showing a memory device 400 according to an embodiment of the present invention. Referring to FIG. 4, the memory device 400 of the present invention includes the 4T SRAM cell 200 and a write circuit 410. The write circuit 410 includes two interconnected PFET devices 413 and 414, two NFET devices 415 and 416, a write-driver-enabled PFET device 411, and a write-driver-enabled NFET device 412. During data writing, a write-driver-enabled voltage signal WrDE is applied to the gates of the two devices 411 and 412 through node 431 to connect the write circuit 410 to the high voltage rail and the ground voltage. A voltage signal DI is input at node 432, representing the supply voltage of data 1 or the ground voltage of data 0, as the data to be stored in the 4T SRAM cell 200. To write data 1 into the memory cell 200, a voltage is applied at node 433 to turn on a word line W (the gates of the access NFET devices 203 and 204 of the 4T SRAM cell 200), and an input voltage signal is applied at node 432 to turn on and off the NFET devices 415 and 416 respectively. The node 45 on the complementary bit line with a load capacitance value 442 422 is connected to the ground voltage through the NFET device 412; the node 46 on the bit line BL 421 with a load capacitance value 441 is charged to through the PFET device 414 in the state where the NFET 416 is off. At the same time, the ground voltage of node 45 turns on the PFET device 202 in the memory cell 200 through the complementary bit line 422 and the access transistor 203. Then, through the PFET device 202, the voltage potential of node 246 is charged to the high voltage . Finally, the voltage potentials stored in nodes 246 and 245 in the memory cell 200 are respectively set to and the ground voltage. At this time, data 1 has been written into the memory cell 200. To write data 0 into the memory cell 200, a voltage is applied at node 433 to turn on the word line W (the gates of the access NFET devices 203 and 204 of the 4T SRAM cell 200), and an input ground voltage is applied at node 432 to turn on and off the NFET devices 416 and 415 respectively. The bit line with a load capacitance value 441 Node 46 on bit line BL 421 is connected to the ground voltage through NFET device 412; having a load capacitance value of 442 The complementary bit line Node 45 on 422 is charged to through PFET device 413 with NFET 415 turned off. At the same time, the ground voltage of node 46 turns on the PFET device 201 in memory cell 200 through bit line BL 421 and access transistor 204. Then, through PFET device 201, the voltage potential of node 245 is charged to Finally, the voltage potentials stored in nodes 245 and 246 in memory cell 200 are respectively set to and the ground voltage. At this time, data 0 has been written into memory cell 200. FIG. 5 shows a schematic diagram of a memory device 500 according to an embodiment of the present invention. Referring to FIG. 5, the memory device 500 of the present invention includes the 4T SRAM cell 200 and a read circuit 510. The read circuit 510 includes two interconnected inverters 513 and 514, a transmission enable PFET device 512, two bit line reset NFET devices 511, and a tri-state buffer 515. The above two bit line reset NFET devices 511 are used to discharge the residual charges on the complementary bit line with a load capacitance value of 542 522 and the bit line BL with a load capacitance value of 541. Before reading the data stored in the 4T SRAM cell 200, within a short period a voltage signal BLrst (equal to is applied to node 531 to turn on the two NFET devices 511, which are used to discharge the residual charges on the complementary bit line 522 and the bit line BL 521 to avoid interfering with the voltage potentials of the floating storage nodes 245 / 246 of the selected 4T SRAM cell 200. To read the stored data 1 in the 4T SRAM cell 200, a voltage is applied to node 433 to turn on a word line W (the gates of the access NFET devices 203 and 204 of the 4T SRAM cell 200), and the bit line BL is charged to a high voltage through PFET device 202, so that the voltage of the bit line BL is greater than the threshold voltage of the sense NFET device in inverter 513, so as to pass through the complementary bit line Access NFET device 522 and access NFET device 203 to transfer the ground voltage to node 245. The ground voltage on node 245 maintains the PFET device 202 in the conducting state, keeping the voltage on node 246 at . Apply a voltage signal Snd equal to to node 532 to turn on the tri-state buffer 515. Using the voltage on node 55 , send out the stored data signal to the data output bus line. At the same time, the PFET device 512 is turned on to accelerate the sensing process to charge the bit line BL 521 to a high voltage potential . Figure 6 shows the input voltage timing diagrams of the corresponding voltage potential curves 605 and 604 of the BLrst signal 601, Snd signal 602, W signal 603, nodes 245 and 246, bit line signals 606a and 606b, and complementary bit line signals 606a and 606c during the read process. Note that during the data retention period of the read process, node 245 (curve 605 in Figure 6), which was previously a floating storage node, is refreshed by the ground voltage. Therefore, from the previous floating storage node state, the total charge of the capacitance value between the grounded gate of the PFET device 202 connected to node 245 and the body with a high voltage bias can be retained. To read the stored data 0 in the 4T SRAM cell 200, apply a voltage to node 433 to turn on the word line W (the gates of the access NFET devices 203 and 204 of the 4T SRAM cell 200), and charge the complementary bit line 522 to a high voltage through the PFET device 201, making the voltage of the complementary bit line greater than the threshold voltage of the sensing NFET device in the inverter 514, so as to transfer the ground voltage to node 246 through the bit line BL and the access NFET device 202. The ground voltage on node 246 maintains the PFET device 201 in the conducting state, keeping the voltage on node 245 at . Apply a voltage signal Snd (equal to ) to node 532 to turn on the tri-state buffer 515. Using the voltage on node 55 , send out the stored data signal (data 0) to the data output bus line. At the same time, the PFET device 512 is turned on to accelerate the sensing process to charge the complementary bit line 522 to a high voltage potential Figure 6 shows the input voltage timing diagrams of the BLrst signal 601, Snd signal 602, W signal 603, corresponding voltage potential curves 605 and 604 of nodes 246 and 245, bit line signals 607a and 607c, and complementary bit line signals 607a and 607b during the read process. Note that during the data retention period in the read process, node 246 (curve 605 in Figure 6), which was previously a floating storage node, is refreshed with a ground voltage. Therefore, from the previous floating storage node state, the total charge of the capacitance value between the grounded gate connected to node 246 in the PFET device 201 and the base with a high voltage can be retained. The bias voltage of the base. The following detailed description is only an example and not a limitation. It should be understood that other embodiments may be used, and various deformations or changes may be made to the structure, all of which should fall within the scope of the claims of the present invention. Moreover, it should be understood that the grammar and terms used in this specification are only for the purpose of explanation and should not be regarded as a limitation. Those skilled in the art should understand that the embodiments of the methods and schematic diagrams in this specification are only examples and not limitations. Those skilled in the art who understand the spirit of the present invention through the disclosure of this specification may use other embodiments, all of which should fall within the scope of the claims of the present invention. For clarity and convenience of description, in the following examples and embodiments, circuit elements with the same function are denoted by the same reference symbols. Figure 7 shows, according to an embodiment of the present invention, an n m-bit 4T SRAM circuit device 700. Referring to Figure 7, the 4T SRAM circuit device 700 includes an n m-bit 4T SRAM array 710 (detailed in Figure 8), a word line address decoder and driver 740, a timing control circuit 750 (detailed in Figure 9), a sense amplifier 720 (detailed in Figure 10), and a write driver 730 (detailed in Figure 11). The n m-bit 4T SRAM array 710 is used to store n Data of m bits; the character line address decoder and driver 740 is used to decode the character line address code from the character line address input 741 to select a character line in the array 710. The timing control circuit 750 has a clock signal input node 751, a read enable signal input node 752 used during the read process, a read character line pulse signal output node 757, a transfer signal output node 755(722) and a bit line reset signal output node 756(721), and a write enable signal input node 753, a write character line pulse signal output node 757 and a write driver enable signal output node 754(731) used during the write process. The sense amplifier 720 is used to read a column of m 4T SRAM cells 200 in total and transmit the voltage signals of the m-bit data to the output bus line 723. The write driver 730 has a write driver enable signal output node 731 and an m-bit voltage signal input node 732 on the input bus line to write data into a column of m 4T SRAM cells 200. Since the structure and operation of the character line address decoder and driver 740 are both known, they will not be elaborated here. Referring to FIG. 8, n The m-bit 4T SRAM array 710 includes n columns of m rows of 4T SRAM cells 200. The gates of the access transistors 203 / 204 of each column of 4T SRAM cells 200 form n character lines WL(0) / 83(0), WL(1) / 83(1),...., WL(n - 2) / 83(n - 2) and WL(n - 1) / 83(n - 1). The sources of the access transistors 203 / 204 in each row form m bit lines BL(0) / 81(0), BL(1) / 81(1),..., BL(i) / 81(i),..., BL(m - 2) / 81(m - 2) and BL(m - 1) / 81(m - 1) of the m rows of 4T SRAM cells 200, and m complementary bit lines BLB(0) / 82(0), BLB(1) / 82(1),... BLB(i) / 82(i),... BLB(m - 2) / 82(m - 2) and (m - 1) / 82(m - 1). Figure 9 shows that the timing control circuit 750 has a clock signal Clk input node 751, a read enable signal RdE input node 752, a write enable signal WrE input node 753, a bit line reset signal BLrst output node 756, a send signal Snd output node 755, a write driver enable signal WrDE output node 754, and a word line pulse signal WLPls output node 757. Figure 10 shows a schematic diagram of the sense amplifier 720, which is used to read out a selected column of a total of m 4T SRAM cells 200. In Figure 10, the sense amplifier 720 includes m read circuits 510. Bit lines 100(0),..., 100(m - 1) and complementary bit lines 101(0),..., 101(m - 1) are respectively connected to bit lines 81(0),..., 81(m - 1) and complementary bit lines 82(0),..., 82(m - 1) of the 4T SRAM array 710 in Figure 8; output nodes QO(0) / 102(0),..., QO(m - 1) / 102(m - 1) are connected to the data output bus line 723. The input node 721 of the signal BLrst and the input node 722 of the signal Snd are connected to the output nodes 756 and 755 of the timing control circuit 750 in Figure 9. Figure 11 shows a schematic diagram of the write driver 730, which is used to write an m-bit data voltage signal to a selected column of 4T SRAM cells 200. In Figure 11, the write driver 730 includes m write circuits 410 and an inverter 451. Bit line nodes 110(0),..., 110(m - 1) and complementary bit line nodes 111(0),..., 111(m - 1) are respectively connected to bit lines 81(0),..., 81(m - 1) and complementary bit lines 82(0),..., 82(m - 1) of the 4T SRAM array 710 in Figure 8; input nodes 113(0),..., 113(m - 1) receive voltage signals DI(0),..., DI(m - 1) to prepare to write data from the data input bus line 732. The write driver enable signal WrDE from the timing control circuit 750 in Figure 9 is applied to the input node 731 to activate the write driver 730. Figure 12 shows a timing diagram for reading an m-bit byte within one clock period. When a character line address code is input to the character line address decoder and driver 740 to select a character line within the 4T SRAM array 710, the timing control circuit 750 is activated through the read enable signal RdE on node 752 and the clock signal clk on node 751, thereby generating the output voltage signals BLrst, Snd, and WLPls. The timing delay line 904 of Figure 9 includes n logic gates (inverters) to generate a delay time , as during the bit line discharge period of the signal BLrst in Figure 12, where the delay of each logic gate is and n is an even number. During the above period, after the residual charges of the bit line BL and the complementary bit line are discharged, since the applied signal WLPls is equal to and the selected character line is turned on, during half of the clock period, the m reading circuits 510 transfer the stored data voltage signals in the m-bit memory cells of the selected column to the data output bus line 723. Figure 13 shows a timing diagram for writing an m-bit byte within one clock period. When a character line address code is input to the character line address decoder and driver 740 to select a character line within the 4T SRAM array 710, the timing control circuit 750 is activated through the write enable signal WrE on node 753 and the clock signal clk on node 751, thereby generating the output voltage signal WrDE to turn on the m writing circuits 410 and generating the character line pulse signal WLPls to turn on the selected character line. The preferred embodiments provided above are only used to illustrate the present invention, rather than limiting the present invention to a specific type or exemplary embodiment. Therefore, this specification should be regarded as illustrative rather than restrictive. The preferred embodiments provided above are for effectively illustrating the gist of the present invention and its best mode of implementation and application, so as to enable those skilled in the art to understand the various embodiments and various modifications of the present invention to adapt to specific usage or implementation purposes. The scope of the present invention is defined by the appended claims and their equivalents, where all terms are intended to have the broadest reasonable meaning, unless otherwise specifically indicated. Therefore, terms such as "the present invention" do not limit the scope of the claims to a specific embodiment, and moreover, any reference to a specific preferred embodiment of the present invention does not mean a limitation of the present invention, and no such limitation is presumed. The present invention is only defined by the scope and spirit of the appended claims. A summary of the present invention is provided in accordance with the requirements of the regulations so that searchers can quickly confirm the subject matter of this technical disclosure from any patent approved by this specification, and it is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that those skilled in the art can make various deformations or changes, which should all fall within the scope of the present invention defined by the appended claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether these elements and components are listed in the appended claims.. 30L, 30R: Data storage circuits 34, 35: Channel diffusion leakage current 83(0)~83(m - 1): Word lines 100: 6T - SRAM cell 200: 4T - SRAM cell 101, 102, 201, 202: P - type MOSFET devices 102(0)~102(m - 1), QO(0)~Q0(m - 1): Output nodes 103, 104, 105, 106, 203, 204: N - type MOSFET devices 113(0)~113(m - 1), DI(0)~DI(m - 1): Input nodes 245, 246: Storage nodes 303, 304, 451, 513, 514: Inverters 400, 500: Memory devices 410: Write circuit 411: Write driver enable PFET device 412: Write driver enable NFET device 421, 521, 81(0)~81(m - 1), 100(0)~100(m - 1), 110(0)~110(m - 1): Bit lines 422, 522, 82(0)~82(m - 1), 101(0)~101(m - 1), 111(0)~111(m - 1): Complementary bit lines 413, 414: Interconnected PFET devices 415, 416: NFET devices 31, 32, 45, 46, 55, 56, 431, 432, 433, 531, 532, 533 nodes 441, 442, 541, 542: Load capacitance values 510: Read circuit 511: Bit line reset NFET device 515: Tri - state buffer 601: BLrst signal 602: Snd signal 603: W signal 606a and 606b: Bit line signals 606a and 606c: Complementary bit line signals 700: 4T SRAM circuit device 710: n : m - bit 4T SRAM array 720: Sense amplifier 721: Input node of signal BLrst 722: Input node of signal Snd 723: Data output bus line 732: Data input bus line 730: Write driver 740: Word line address decoder and driver 741: Word line address input 750: Timing control circuit 751: Clock signal Clk input node 752: Read enable signal RdE input node 753: Write enable signal WrE input node 754: Write driver enable signal WrDE output node 755: Transmission signal Snd output node 756: Bit line reset signal BLrst output node 757: Word line pulse signal WLPls output node 904: Timing delay line [FIG. 1] shows a structural diagram of a conventional 6T STAM cell 100. [FIG. 2] shows a structural diagram of a 4T STAM cell 200. [FIGS. 3A-3B] respectively show schematic diagrams of data storage circuits 30L and 30R of a 4T SRAM cell and a 6T STAM cell. [FIG. 4] shows a schematic diagram of a memory device 400 according to an embodiment of the present invention. [FIG. 5] shows a schematic diagram of a memory device 500 according to another embodiment of the present invention. [FIG. 6] shows an input voltage timing diagram of a read circuit 510. [FIG. 7] shows, according to an embodiment of the present invention, an n schematic diagram of an n m-bit 4T SRAM circuit device 700. [FIG. 8] shows, according to an embodiment of the present invention, an n 200: 4T-SRAM cell 201, 202: P-type MOSFET devices 203, 204: N-type MOSFETs acting as access switches 245, 246: Storage nodes 400: Memory device 410: Write circuit 411: Write driver enable PFET device 412: Write driver enable NFET device 421: Bit line 422: Complementary bit line 413, 414: Interconnected PFET devices 415, 416: NFET devices 45, 46, 431, 432: Nodes 441, 442: Load capacitance value 451: Inverter

Claims

1. A memory device comprising: a static random access memory (SRAM) cell having only four transistors, including: a pair of cross-coupled PMOS transistors coupled to a supply voltage rail and two storage nodes; two access transistors for responding to a word line and coupled to the two storage nodes and the pair of bit lines; and a write circuit comprising: a PMOS transistor for responding to one of a pair of control lines and coupled to the supply voltage rail; a pair of cross-coupled pull-up transistors coupled between the PMOS transistor and the corresponding bit line; an NMOS transistor for responding to the other control line corresponding to the control line and coupled to a ground voltage rail; and two set transistors for responding to a pair of data lines and coupled between the NMOS transistor, the corresponding bit line, and the pair of cross-coupled pull-up transistors; wherein, The supply voltage rail carries a supply voltage, and the write circuit is used to set the voltages of the two storage nodes to be equal to the supply voltage and a ground voltage, respectively, based on the pair of data lines and the pair of control lines.

2. The apparatus of claim 1, wherein the two access transistors include a first access transistor and a second access transistor for responding to the word line, wherein the first access transistor is coupled between one of the two storage nodes and one of the bit lines, and wherein the second access transistor is coupled between the other storage node of the two storage nodes and the other bit line of the bit line.

3. The apparatus of claim 1, wherein the two setting transistors comprise a first setting transistor and a second setting transistor, wherein the first setting transistor is coupled to the ground voltage rail, one of the pair of bit lines and one of the pair of mutually coupled pull-up transistors, and returns to one of the pair of data lines, and wherein the second setting transistor is coupled to the ground voltage rail, another bit line of the pair of bit lines and another pull-up transistor of the pair of mutually coupled pull-up transistors, and returns to the other data line of the pair of data lines.

4. A write method for writing a data bit into a static random access memory (SRAM) cell of a memory device, wherein the memory device includes a write circuit, wherein the SRAM cell has only four transistors, including a pair of mutually coupled PMOS transistors and two access transistors, wherein the pair of mutually coupled PMOS transistors is coupled to a supply voltage rail and two storage nodes, and the two access transistors are responsive to a word line and coupled to the two storage nodes and the pair of bit lines, wherein the write circuit includes a pair of mutually coupled pull-up transistors, a PMOS transistor, an NMOS transistor, and two setting transistors, wherein the pair of mutually coupled pull-up transistors is coupled between the PMOS transistor and the bit line, and wherein the two setting transistors are responsive to a pair of data lines and coupled between the NMOS transistor, the bit line, and the pair of mutually coupled pull-up transistors, the method comprising the following steps: (1) By activating the word line, the two access transistors are turned on to connect the two storage nodes to the pair of bit lines; (2) The data bits are input through the pair of data lines to turn on one of the two setting transistors and turn off the other setting transistor, thereby discharging one of the pair of bit lines to a ground voltage and charging the other bit line to a supply voltage; (3) After steps (1) and (2), one of the two storage nodes coupled to the discharged bit line has the ground voltage through one of the two turned-on access transistors; (4) After step (3), one of the pair of mutually coupled PMOS transistors is turned on to charge the other storage node of the two storage nodes to the supply voltage; and (5) Before step (2), the PMOS transistor is turned on to connect the supply voltage rail to the pair of mutually coupled pull-up transistors by activating a pair of control lines, and the NMOS transistor is turned on to connect a ground voltage rail to the two set transistors; wherein The PMOS transistor is used to respond to one of the control lines and is coupled between the supply voltage rail and the pair of mutually coupled pull-up transistors; and the NMOS transistor is used to respond to the other control line of the control line and is coupled between the ground voltage rail and the two set transistors.

Images