Image sensor

Abstract

An image sensor includes: a substrate having pixel-separating recesses; a plurality of photosensitive elements disposed in the substrate; and a pixel-separating region filling the pixel-separating recesses, wherein the pixel-separating region includes: a first insulating layer covering an inner wall of the pixel-separating recess; a first conductive layer covering at least a portion of a side surface of the first insulating layer within the pixel-separating recess; a second insulating layer covering a portion of a side surface of the first conductive layer within an internal space defined by the first conductive layer; and a second conductive layer filling all spaces within the internal space defined by the first conductive layer that are not filled by the second insulating layer and being connected to and in contact with the first conductive layer.

Description

Image sensor [Cross-reference to related applications] This application claims priority to Korean Patent Application No. 10-2023-0018981, filed with the Korean Intellectual Property Office on February 13, 2023, and claims priority to the Korean patent application under 35 U.S.C. § 119. The entire contents of the Korean patent application are incorporated herein by reference. The present inventive concept relates to an image sensor, and more particularly, to an image sensor including a plurality of unit pixels separated by pixel separation regions. An image sensor is configured by arranging a plurality of unit pixels in a two-dimensional array. Generally, each of the plurality of unit pixels may include a photosensitive element (e.g., a photodiode) and a plurality of pixel transistors. Pixel separation regions are disposed between the photosensitive elements included in the plurality of unit pixels. When electrons are generated due to heat emission or defects at the interface between the photosensitive element and the pixel separation region of the image sensor, the dark level (the dark level is noise generated by dark current) may increase and the performance of the image sensor may deteriorate or otherwise decrease. Therefore, research has been conducted on pixel separation regions that can improve the performance of the image sensor by reducing the dark level. According to some exemplary embodiments, the present inventive concept may provide an image sensor with reduced noise and enhanced sensitivity. According to some exemplary embodiments of the present inventive concept, there is provided an image sensor including: a substrate having a first surface and a second surface opposite to each other and having a pixel separation recess extending from the first surface to the second surface; a plurality of photosensitive elements located in the substrate; and a pixel separation region filling the pixel separation recess and surrounding at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow region between adjacent photosensitive elements facing each other among the plurality of photosensitive elements and having a wide region between edges of the adjacent photosensitive elements facing each other, and the pixel separation region including: a first insulating layer covering an inner wall of the pixel separation recess; a first conductive layer covering at least a portion of a side surface of the first insulating layer within the pixel separation recess; a second insulating layer covering a portion of the side surface of the first conductive layer within an internal space defined by the first conductive layer; and a second conductive layer filling all spaces within the internal space defined by the first conductive layer that are not filled by the second insulating layer such that the second conductive layer is connected to and in contact with the first conductive layer. According to some exemplary embodiments of the inventive concept, there is provided an image sensor including: a substrate having a first surface and a second surface opposite to each other, and having pixel separation recesses extending from the first surface to the second surface; a plurality of photosensitive elements located in the substrate; and a pixel separation region filling the pixel separation recesses and surrounding at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow region between sides of adjacent photosensitive elements facing each other among the plurality of photosensitive elements and having a wide region between edges of the adjacent photosensitive elements facing each other, and the pixel separation region including: a plurality of first insulating layers covering inner walls of the pixel separation recesses, spaced apart from each other and surrounding at least one of the plurality of photosensitive elements; a plurality of first conductive layers spaced apart from each other and covering at least a portion of side surfaces of each of the plurality of first insulating layers within the pixel separation recesses; a second insulating layer covering a portion of side surfaces of the plurality of first conductive layers within an internal space defined by the plurality of first conductive layers within the pixel separation recesses; and a second conductive layer covering the plurality of first conductive layers and the second insulating layer within the internal space defined by the plurality of first conductive layers within the pixel separation recesses, and the second conductive layer including: a connection portion adjacent to the first surface of the substrate and electrically connecting at least some of the plurality of first conductive layers spaced apart from each other; and an extension portion extending in a vertical direction from the connection portion toward the second surface of the substrate and spaced apart from the plurality of first conductive layers by the second insulating layer located between the extension portion and the plurality of first conductive layers. According to some exemplary embodiments of the inventive concept, there is provided an image sensor including: a substrate having a first surface and a second surface opposite to each other, and having pixel separation recesses extending from the first surface to the second surface; a plurality of photosensitive elements located in the substrate; and a pixel separation region filling the pixel separation recesses and surrounding at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow region between adjacent photosensitive elements facing each other among the plurality of photosensitive elements and having a wide region between edges of the adjacent photosensitive elements facing each other, and the pixel separation region including: a plurality of first insulating layers covering inner walls of the pixel separation recesses, spaced apart from each other and surrounding at least one of the plurality of photosensitive elements; a plurality of first conductive layers spaced apart from each other and covering at least a portion of side surfaces of each of the plurality of first insulating layers within the pixel separation recesses; a second insulating layer covering side surfaces of the plurality of first conductive layers within an inner space defined by the plurality of first conductive layers within the pixel separation recesses; and a second conductive layer covering the plurality of first conductive layers and the second insulating layer within the inner space defined by the plurality of first conductive layers within the pixel separation recesses, and the second conductive layer is located in the wide region of the pixel separation region and not in the narrow region of the pixel separation region, and the second conductive layer includes: a connection portion adjacent to the first surface of the substrate and electrically connecting at least some of the plurality of first conductive layers spaced apart from each other; and an extension portion extending in a vertical direction from the connection portion to the second surface of the substrate and spaced apart from the plurality of first conductive layers by the second insulating layer located between the extension portion and the plurality of first conductive layers. Hereinafter, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept is not limited thereto, and the inventive concept may be implemented in various other forms. The following exemplary embodiments are simply provided to fully convey the scope of the inventive concept to those skilled in the art. Therefore, the drawings and the description are considered to be illustrative rather than restrictive in nature. For example, unless otherwise explicitly stated, for the purpose of clarity and / or convenience of illustration, the elements shown in the drawings may have exaggerated sizes and / or may be simplified. Similarly, although the elements throughout the following description may be referred to as first, second or similar terms (as used herein), unless otherwise explicitly stated, these terms are used to distinguish one element from another and should not be construed as limiting the illustrated exemplary embodiments to any particular order and / or to any particular number of elements. In addition, as used herein, unless otherwise expressly indicated, the singular forms "a / an" are also intended to include the plural forms. Similarly, the terms "the" and similar directive terms can correspond to both the singular and the plural. Similarly, as used herein, terms referred to as "above" or "on" not only can include a direct contact manner, but also can include a non-contact manner. In addition, throughout the following description, each element may be listed as including one or more materials, comprising one or more materials, made of one or more materials, etc., but unless otherwise expressly indicated, the inventive concept should not be construed as being limited to the disclosed materials. For example, those of ordinary skill in the art should understand that, in addition to or in place of the specific materials listed herein, materials having similar functional properties to the materials described herein may also be used. FIG. 1 is a block diagram of the configuration of an image sensor 1100 according to some exemplary embodiments. Referring to FIG. 1, the image sensor 1100 may include a pixel array 1110, a controller 1130, a column driver 1120, and a pixel signal processing unit 1140. The image sensor 1100 may include at least one of the image sensors 1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 6, 1000, and / or 1000a described with reference to FIGS. 4 to 21, but is not limited thereto. The pixel array 1110 may include a plurality of unit pixels in a two-dimensional array form, and each of the unit pixels may include a photoelectric conversion layer. The photoelectric conversion layer may absorb light and generate charges, and may provide an electrical signal (output voltage) according to the generated charges to the pixel signal processing unit 1140 via a vertical signal line. The unit pixels included in the pixel array 1110 may provide one output voltage per column at a time, and thus, the unit pixels belonging to each column of the pixel array 1110 may be simultaneously enabled by a selection signal output from the column driver 1120. The unit pixels belonging to the selected column may provide an output voltage according to the absorbed light to the output line of the corresponding row. The controller 1130 may enable the pixel array 1110 to absorb light and accumulate charges and / or temporarily store the accumulated charges, and may control the column driver 1120 to output an electrical signal according to the stored charges to the outside of the pixel array 1110. In addition, the controller 1130 may control the pixel signal processing unit 1140 to measure the output voltage provided by the pixel array 1110. The controller 1130 may include processing circuitry, such as: hardware including logic circuits; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC). The pixel signal processing unit 1140 may include a correlated-double sampler (CDS) 1142, an analog-to-digital converter (ADC) 1144, and a buffer 1146. The CDS 1142 may sample and hold the output voltage provided from the pixel array 1110. The CDS 1142 may perform correlated double sampling on a specific noise level and voltage level based on the generated output voltage and output a voltage level corresponding to the difference. Additionally, the CDS 1142 may receive an input of a ramp signal generated by the ramp signal generator 1148, compare the received ramp signals with each other, and output a comparison result. The ADC 1144 may convert an analog signal corresponding to the voltage level received from the CDS 1142 into a digital signal. The buffer 1146 may latch the digital signal and may sequentially output the latched signal to the outside of the image sensor 1100 and transmit it to an image processor (not shown). FIG. 2 is a block diagram of the configuration of an image sensor 2000 according to some exemplary embodiments. Referring to FIG. 2, the image sensor 2000 may include a pixel unit 2200 and a peripheral circuit unit. The pixel unit 2200 may be formed on the substrate 2010 by regularly arranging the plurality of unit pixels 2100 including a photosensitive conversion layer in a two-dimensional array structure. The image sensor 2000 may include at least one of the image sensors 1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 6, 1000, and / or 1000a described with reference to FIGS. 4 to 21, but is not limited thereto. The peripheral circuit unit may be arranged around the pixel unit 2200 and may include a vertical drive circuit 2400, a row signal processing circuit 2500, a horizontal drive circuit 2600, an output circuit 2700, a control circuit 2800, and / or similar devices. The control circuit 2800 can control the vertical drive circuit 2400, the line signal processing circuit 2500, the horizontal drive circuit 2600, and / or similar devices. For example, the control circuit 2800 can generate a clock signal or a control signal based on a vertical synchronization signal, a horizontal synchronization signal, and / or a main clock, and the clock signal or the control signal is used as a reference for the operation of the vertical drive circuit 2400, the line signal processing circuit 2500, the horizontal drive circuit 2600, and / or similar devices. Additionally, the control circuit 2800 can input the clock signal or the control signal to the vertical drive circuit 2400, the line signal processing circuit 2500, and the horizontal drive circuit 2600. The control circuit 2800 can include a processing circuit system, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit system can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, or an application specific integrated circuit (ASIC). The vertical drive circuit 2400 can include, for example, a shift register, and can select pixel drive lines, supply pulses for driving unit pixels to the selected pixel drive lines, and drive unit pixels in units of columns. For example, the vertical drive circuit 2400 can sequentially and selectively scan pulses to each of the unit pixels of the pixel unit 2200 in the vertical direction in units of columns. Additionally, pixel signals according to the charges generated in the photosensitive conversion layers of each of the unit pixels 2100 can be supplied to the line signal processing circuit 2500 via the vertical signal lines 2320. The line signal processing circuit 2500 can be arranged in each row of the unit pixel 2100 and can perform signal processing (such as noise removal) for the signals output from the unit pixels 2100 in one column for each unit pixel row. For example, the line signal processing circuit 2500 can perform signal processing for removing noise inherent in the unit pixels 2100, such as CDS, signal amplification, and / or AD conversion. A horizontal selection switch (not shown) can be installed at the output terminal of the line signal processing circuit 2500. The horizontal drive circuit 2600 can include, for example, a shift register, and can sequentially output horizontal scan pulses to sequentially select each of the line signal processing circuits 2500 and output the pixel signals of each of the line signal processing circuits 2500 to the horizontal signal lines 2340. The output circuit 2700 can perform signal processing on the signals sequentially supplied by the self-signal processing circuit 2500 via the horizontal signal line 2340 and output the signals. For example, the output circuit 2700 can perform buffering, or can perform black level adjustment, thermal non-uniformity correction, various digital signal processing, and / or similar processing. At the same time, the input / output terminals can exchange signals with the outside. FIGS. 3A and 3B are circuit diagrams of the readout circuits of the image sensors 3000 and 3000a according to some exemplary embodiments. Referring to FIG. 3A, the image sensor 3000 may include a photosensitive element PD, a transfer transistor TT, a floating diffusion region FD, a reset transistor RST, a source follower transistor SF, and a selection transistor SEL. The photosensitive element PD and the transfer transistor TT may be included in a unit pixel. The image sensor 3000 may include at least one of the image sensors 1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 6, 1000, and / or 1000a described with reference to FIGS. 4 to 21, but is not limited thereto. The transfer transistor TT, the reset transistor RST, the source follower transistor SF, and the selection transistor SEL may have a transfer gate, a reset gate, a source follower gate, and / or a selection gate, respectively. In some embodiments, the transfer gate may be a vertical gate, and each of the reset gate, the source follower gate, and / or the selection gate may be a planar gate. The transfer gate may be disposed between the photosensitive element PD and the floating diffusion region FD and may transfer the charges generated in the photosensitive element PD to the floating diffusion region FD. The transfer transistor TT may include a transfer gate, a source region, and / or a drain region, and the source region and the drain region may be connected to the floating diffusion region FD and the photosensitive element PD, respectively. The reset transistor RST may include: a reset gate; a source region connected to the floating diffusion region FD; and / or a drain region connected to the power supply voltage VPIX. The source follower transistor SF may include: a source follower gate connected to the floating diffusion region FD; a source region connected to the source region of the selection transistor SEL; and / or a drain region connected to the power supply voltage VPIX. The selection transistor SEL may include: a selection gate; a source region connected to the source region of the source follower transistor SF; and a drain region connected to the output voltage VOUT. Referring to FIG. 3B, according to some exemplary embodiments, the image sensor 3000a may include a plurality of photosensitive elements PD, a plurality of transfer transistors TT, a floating diffusion region FD, a reset transistor RST, a source follower transistor SF, and / or a selection transistor SEL. The photosensitive element PD and the transfer transistor TT may be included in a unit pixel. The image sensor 3000a may include the image sensors 1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 6, 1000, and / or 1000a described with reference to FIGS. 4 to 21, but is not limited thereto. In FIG. 3B, four unit pixels each including four photosensitive elements PD can constitute a shared pixel in which one floating diffusion region FD, one reset transistor RST, one source follower transistor SF, and one select transistor SEL are shared by four transfer transistors TT. However, the concept of the present invention is not limited thereto. For example, in some exemplary embodiments, two unit pixels each including two photosensitive elements PD can constitute a shared pixel in which one floating diffusion region FD, one reset transistor RST, one source follower transistor SF, and one select transistor SEL are shared by two transfer transistors TT. FIG. 4 is a plan layout showing a unit pixel PX including a photosensitive element PD and a pixel isolation region DTI of an image sensor 1000 according to some exemplary embodiments. Referring to FIG. 4, the image sensor 1000 may include a substrate SUB, the plurality of unit pixels PX, and a pixel isolation region DTI, wherein the substrate SUB has a pixel isolation recess, and the pixel isolation region DTI fills the pixel isolation recess DTR. Each of the plurality of unit pixels PX may include a photosensitive element PD. The pixel isolation region DTI may be disposed between the plurality of photosensitive elements PD. In some exemplary embodiments, in a plan view, the pixel isolation region DTI may not completely surround each of the plurality of photosensitive elements PD, but may only include a part of each of the plurality of photosensitive elements PD. For example, when each of the plurality of photosensitive elements PD has an approximately quadrilateral shape in a plan view, in the plan view, the pixel isolation region DTI may surround all three edges of each of the plurality of photosensitive elements PD and two sides connecting the three edges to each other. The pixel isolation region DTI may also not surround one edge and a part of the other two sides connected to the edge, but may only surround the remaining part of the other two sides. In some exemplary embodiments, in a plan view, the pixel isolation region DTI may completely surround four of the plurality of photosensitive elements PD. The substrate SUB may have a connection substrate region CR between the four photosensitive elements PD that are completely surrounded by the pixel isolation region DTI in the plan view. For example, when each of the plurality of photosensitive elements PD has an approximately quadrilateral shape in a plan view, the connection substrate region CR may be connected to one edge of each of the four photosensitive elements PD that is not surrounded by the pixel isolation region DTI in the plan view and may be connected to a part of the other two sides. For example, each of the four photosensitive elements PD completely surrounded by the pixel separation region DTI in the plan view may correspond to one of red (R), blue (B), and green (G), but is not limited thereto. For example, each of the four photosensitive elements PD completely surrounded by the pixel separation region DTI in the plan view may correspond to one of cyan (C), yellow (Y), and magenta (M). Although described with reference to a specific color group, those of ordinary skill in the art should understand that each of the four photosensitive elements PD completely surrounded by the pixel separation region DTI in the plan view may correspond to a color different from the colors listed above and / or a combination different from the combinations listed above. The pixel separation region DTI may include: a narrow region DTIN having a relatively narrow first horizontal width W1; and a wide region DTIW having a relatively wide second horizontal width W2. The narrow region DTIN may be a portion of the pixel separation region DTI disposed between photosensitive elements PD adjacent to each other in the width direction of the photosensitive element PD, and the wide region DTIW may be a portion of the pixel separation region DTI disposed between photosensitive elements PD adjacent to each other in the diagonal direction of the photosensitive element PD. For example, the narrow region DTIN may be a portion of the pixel separation region DTI disposed between opposite sides, and the wide region DTIW may be a portion of the pixel separation region DTI disposed between facing edges of adjacent photosensitive elements PD. FIGS. 5A and 5B are vertical cross-sectional views of the image sensor 1 according to some exemplary embodiments, and FIGS. 6A and 6B are horizontal cross-sectional views of the image sensor 1. Specifically, FIG. 5A is a vertical cross-sectional view of a portion taken along line A-A' in FIG. 4, FIG. 5B is a vertical cross-sectional view of a portion taken along line B-B' in FIG. 4, FIG. 6A is a horizontal cross-sectional view taken along a first horizontal level LV1 in FIGS. 5A and 5B, and FIG. 6B is a horizontal cross-sectional view taken along a second horizontal level LV2 in FIGS. 5A and 5B. Referring together to FIGS. 5A, 5B, 6A, and 6B, the image sensor 1 may include: an optical element substrate WFO having a plurality of unit pixels PX including a plurality of photosensitive elements PD 210; a plurality of microlenses 550 disposed on the optical element substrate WFO; and a plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. The optical element substrate WFO may include: a first substrate 200 having a first surface 200F and a second surface 200B opposite to each other; and a first interconnection structure 280. The first substrate 200 may include a semiconductor substrate. For example, the first substrate 200 may comprise a Group-IV semiconductor material, a Group-III-V semiconductor material, or a Group-II-VI semiconductor material. For example, the Group-IV semiconductor material may include silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). For example, the Group-III-V semiconductor material may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), and / or indium gallium arsenide (InGaAs). For example, the Group-II-VI semiconductor material may include zinc telluride (ZnTe) and / or cadmium sulfide (CdS). In some exemplary embodiments, the first substrate 200 may include a P-type silicon substrate. In some exemplary embodiments, the first substrate 200 may include a P-type bulk substrate and a P-type epitaxial layer or an N-type epitaxial layer grown on the P-type bulk substrate. In some exemplary embodiments, the first substrate 200 may include an N-type bulk substrate and a P-type epitaxial layer or an N-type epitaxial layer grown on the N-type bulk substrate. The first substrate 200 may be the substrate SUB shown in FIG. 4. Within the optical element substrate WFO, the plurality of unit pixels PX may be arranged in a matrix form in a plan view. The plurality of unit pixels PX may include a plurality of photosensitive elements PD located on the first substrate 200. The first substrate 200 may be doped with impurities of a first conductivity type, and each of the plurality of photosensitive elements PD 210 may be doped with impurities of a second conductivity type different from the first conductivity type. In some embodiments, the first conductivity type may be p-type, and the second conductivity type may be n-type. For example, the first conductivity type impurities may include one or more of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), zinc (Zn), cadmium (Cd), and / or mercury (Hg), and the second conductivity type impurities may include one or more of nitride (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), tellurium (Te), and / or polonium (Po). An element isolation region STI and a pixel isolation region DTI may be disposed in the first substrate 200. A plurality of unit pixels PX may be defined in the first substrate 200 by the pixel isolation region DTI, and the pixel isolation region DTI may surround at least a portion of each of the plurality of photosensitive elements PD in a plan view. The pixel isolation region DTI may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTI is disposed between each of the plurality of photosensitive elements PD arranged in a matrix form in a plan view, and may have a grid shape or a mesh shape in a plan view. In the first substrate 200, the active region and the floating diffusion region can be defined by the device isolation STI. In some exemplary embodiments, the device isolation STI can include three layers (including a first layer 222, a second layer 224, and a third layer 226), and the three layers include a combination of at least three types of insulating films. For example, the first layer 222 can include an oxide, the second layer 224 can include a nitride, and the third layer 226 can include an oxide, but is not limited thereto. For example, in some exemplary embodiments, the device isolation STI can include a single layer of one type of insulating film, a bilayer of two types of insulating films, or a multilayer of four or more types of insulating films. The pixel isolation DTI can be formed in a pixel isolation recess DTR extending from the first surface 200F of the first substrate 200 to the second surface 200B. The device isolation STI can be formed in a device isolation recess STR extending from the first surface 200F of the first substrate 200 to the inside. In some exemplary embodiments, each of the pixel isolation DTI and the device isolation STI can have a tapered shape in which the horizontal width decreases from the first surface 200F toward the second surface 200B of the first substrate 200. In the vertical direction, the extension length of the pixel isolation recess DTR can be greater than the extension length of the device isolation recess STR. For example, the pixel isolation recess DTR can penetrate through the first substrate 200, and the device isolation recess STR may not penetrate through the first substrate 200. In some exemplary embodiments, the pixel isolation DTI can overlap a part of the device isolation STI in the vertical direction. For example, the pixel isolation recess DTR can penetrate through a part of the device isolation STI and the first substrate 200 together. In some exemplary embodiments, gate electrodes included in a plurality of transistors can be formed on the first surface 200F of the first substrate 200. For example, the plurality of transistors can include: a transfer transistor configured to transfer charges generated in the photosensitive element PD to the floating diffusion region; a reset transistor configured to periodically reset the charges stored in the floating diffusion region; a driving transistor serving as a source follower buffer amplifier and configured to buffer a signal according to the charges charged in the floating diffusion region; and a selection transistor for performing switching and addressing for selecting a unit pixel PX. However, the plurality of transistors is not limited thereto. Each of the gate electrodes included in the plurality of transistors may be a vertical gate or a planar gate. In FIG. 5A, as an example, the transfer gate 270 included in the transfer transistor among the gate electrodes included in the plurality of transistors is shown as a vertical gate. Although the transfer gate 270 included in the transfer transistor is shown as an example as a vertical gate formed in a recessed gate type extending from the first surface 200F of the first substrate 200 into the first substrate 200, the shape of the transfer gate 270 is not limited thereto. The first interconnection structure 280 may be disposed on the first surface 200F of the first substrate 200. The first interconnection structure 280 may include a plurality of first interconnection patterns 282 and a first inter-wiring insulating layer 284 surrounding the plurality of first interconnection patterns 282. The plurality of first interconnection patterns 282 may be electrically connected to the gate electrode or the active region of the first substrate 200. The plurality of first interconnection patterns 282 may include a stacked structure of a plurality of first interconnection lines and a plurality of first interconnection vias. For example, the plurality of first interconnection patterns 282 may include a conductive material such as tungsten, Al, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, and / or doped polysilicon, and the first inter-wiring insulating layer 284 may include an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The plurality of color filter layers 530 may be disposed on the second surface 200B of the first substrate 200. In some exemplary embodiments, the first passivation layer 510 may be located between the second surface 200B of the first substrate 200 and the plurality of color filter layers 530. The first passivation layer 510 may include an oxide, a nitride, a nitrogen oxide, or a combination thereof. For example, the first passivation layer 510 may include one of silicon nitride, hafnium oxide, aluminum oxide, and / or tantalum oxide, or may include a stacked structure thereof. A guiding pattern 520 may be formed on the first passivation layer 510. In a plan view, the guiding pattern 520 may have a grid shape or a mesh shape. The guiding pattern 520 may prevent light incident on one photosensitive element PD at an oblique angle from entering an adjacent photosensitive element PD. For example, the guiding pattern 520 may include at least one metal material among tungsten, Al, titanium, ruthenium, cobalt, nickel, copper, gold, silver, and platinum. On the first passivation layer 510 formed with the guiding pattern 520 thereon, the plurality of color filter layers 530 overlapping with the plurality of photosensitive elements PD and the plurality of microlenses 550 disposed on the plurality of color filter layers 530 may be provided. The plurality of color filter layers 530 may enable the light incident through the plurality of microlenses 550 to pass therethrough, and only enable the light of a desired wavelength to be incident on the plurality of photosensitive elements PD. In some exemplary embodiments, the plurality of color filter layers 530 may only enable the light having a wavelength within a range, where the range is between a lower wavelength value and a higher wavelength value. In some exemplary embodiments, the second passivation layer 540 may be located between the plurality of color filter layers 530 and the plurality of microlenses 550. The second passivation layer 540 may include an oxide, a nitride, a nitrogen oxide, or a combination thereof. For example, each of the plurality of color filter layers 530 may include one of a red (R) filter, a blue (B) filter, and a green (G) filter. In some exemplary embodiments, each of the plurality of color filter layers 530 may include one of a cyan (C) filter, a yellow (Y) filter, and a magenta (M) filter. The color filter layer 530 of one of the R filter, the B filter, and the G filter or the color filter layer 530 of one of the C filter, the Y filter, and the M filter may be formed on each of the photosensitive elements PD such that each of the unit pixels PX may detect a separated component of the incident light and identify a kind of light, such as light having a desired wavelength or having a wavelength within a range. The microlens 550 may focus the light incident on the image sensor 1 onto the photosensitive element PD of the unit pixel PX. In some exemplary embodiments, the microlens 550 may include: an organic material layer; and an inorganic material layer conformally covering the surface of the organic material layer. For example, the organic material layer may include a TMR-based resin (a product of Tokyo Ohka Kogyo Co., Ltd.) and / or an MFR-based resin (a product of Japan Synthetic Rubber Corporation). A logic board WFL may be disposed on the lower surface of the first inner connection structure 280. The logic board WFL may include: a second substrate 410; logic circuit elements 420 disposed in the second substrate 410; and a second inner connection structure 430. The second inner connection structure 430 may be in contact with the first inner connection structure 280. The second inner connection structure 430 may include: a plurality of second inner connection patterns 432; and a second inter-wiring insulating layer 434 surrounding the plurality of second inner connection patterns 432. In some exemplary embodiments, the first inter-wiring insulating layer 284 and the second inter-wiring insulating layer 434 may be in contact with each other. The plurality of second inner connection patterns 432 may be electrically connected to the plurality of first inner connection patterns 282 and / or the logic circuit elements 420. The plurality of second inner connection patterns 432 may include a stacked structure of a plurality of second inner connection lines and a plurality of second inner connection vias. For example, the plurality of second inner connection patterns 432 may include a conductive material such as tungsten, Al, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, and / or doped polysilicon. For example, the second inter-wiring insulating layer 434 may include an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The logic circuit elements 420 may include at least one of the column driver 1120, the controller 1130, and the pixel signal processing unit shown in FIG. 1, or may include at least one of the vertical driving circuit 2400, the row signal processing circuit 2500, the horizontal driving circuit 2600, the output circuit 2700, and the control circuit 2800 shown in FIG. 2. The plurality of first inner connection patterns of the optical element substrate WFO and the plurality of second inner connection patterns 432 of the logic board WFL may be electrically connected to each other by a plurality of bonding pads or a plurality of through electrodes. In some exemplary embodiments, the optical element substrate WFO and the logic substrate WFL may be stacked using a metal-oxide hybrid bonding method. The plurality of bonding pads may be formed by expanding a plurality of first pad units and a plurality of second pad units that correspond to each other and are in contact with each other by heating to form an integral body by diffusion of metal atoms contained therein. The first inter-wiring insulating layer 284 and the second inter-wiring insulating layer 434 may be bonded by forming a covalent bond. The pixel isolation region DTI may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and a second conductive layer 244. Each of the first insulating layer 232, the second insulating layer 234, and the third insulating layer 236 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, and / or metal oxide. For example, the metal oxide may be hafnium oxide, aluminum oxide, and / or tantalum oxide. Each of the first conductive layer 242 and the second conductive layer 244 may include at least one of silicon, metal, metal silicide, metal nitride, and / or metal-containing film. For example, each of the first conductive layer 242 and the second conductive layer 244 may include doped polycrystalline silicon. The first insulating layer 232 may cover the inner wall of the pixel isolation recess DTR. The first insulating layer 232 may conformally cover the inner wall of the pixel isolation recess DTR and may not fill all of the pixel isolation recesses DTR. In the pixel isolation recess DTR, the first insulating layer 232 may be arranged to be spaced apart from each other in a plan view and surround at least one photosensitive element PD. The first conductive layer 242 may cover a part of the side surface of the first insulating layer 232 in the pixel isolation recess DTR. For example, the first conductive layer 242 may extend from the second surface 200B of the first substrate 200 toward the first surface 200F, but may not extend to the first surface 200F. The first conductive layer 242 may conformally cover a part of the side surface of the first insulating layer 232 in the pixel isolation recess DTR and may not fill the entire space defined by the first insulating layer 232. In the pixel isolation recess DTR, the first conductive layer 242 may be arranged to be spaced apart from each other in a plan view and surround at least one photosensitive element PD, and the first conductive layer 242 may cover a part of the side surface of the first insulating layer 232 that is spaced apart from each other in a plan view and surrounds at least one photosensitive element PD. The second insulating layer 234 may cover a part of the side surface of the first conductive layer 242 in the internal space defined by the first conductive layer 242. The second insulating layer 234 may conformally cover a part of the inner surface of the internal space defined by the first conductive layer 242 and may not cover the entire internal space defined by the first conductive layer 242. The second conductive layer 244 may cover the second insulating layer 234. The second conductive layer 244 may fill the entire space in the internal space defined by the first conductive layer 242 that is not filled by the second insulating layer 234. The third insulating layer 236 may cover the first conductive layer 242, the second insulating layer 234, and the second conductive layer 244 and may fill the pixel isolation region DTI. The third insulating layer 236 may fill a part of the internal space defined by the first insulating layer 232 that is adjacent to the first surface 200F of the first substrate 200. The third insulating layer 236 may extend from the same vertical level where the first surface 200F of the first substrate 200 is located into the pixel isolation region DTI. In the narrow region DTIN of the pixel isolation region DTI, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, and the first conductive layer 242 can be arranged, but the second conductive layer 244 may not be arranged. In the wide region DTIW of the pixel isolation region DTI, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244 can be arranged. The second insulating layer 234 can fill all the internal spaces defined by the first conductive layer 242 in the narrow region DTIN of the pixel isolation region DTI, but may not fill all the internal spaces defined by the first conductive layer 242 in the wide region DTIW of the pixel isolation region DTI. In the wide region DTIW of the pixel isolation region DTI, all the internal spaces defined by the first conductive layer 242 can be filled by the second insulating layer 234 and the second conductive layer 244. The first vertical level LV1 can be relatively adjacent or close to the second surface 200B of the first substrate 200, and the second vertical level LV2 can be relatively adjacent or close to the first surface 200F of the first substrate 200. At the first vertical level LV1, a part of the first conductive layer 242 can be relatively adjacent or close to the second surface 200B of the first substrate 200, and at the second vertical level LV2, a part of the first conductive layer 242 can be relatively adjacent or close to the first surface 200F of the first substrate 200. The second conductive layer 244 can include a connection part 244C and a charging part 244S. The connection part 244C of the second conductive layer 244 can be the part of the second conductive layer 244 that is relatively adjacent or close to the first surface 200F of the first substrate, and the charging part 244S of the second conductive layer 244 can be the part that is relatively adjacent or close to the second surface 200B of the first substrate 200. The connection part 244C of the second conductive layer 244 can be located between the second insulating layer 234 and the third insulating layer 236 and can extend from the connection part 244C into the second insulating layer 234. The connection part 244C of the second conductive layer 244 can extend from the charging part 244S of the second conductive layer 244 toward the first surface 200F of the first substrate 200, and the charging part 244S can extend from the connection part 244C to the second surface 200B of the first substrate 200. The charging part 244S of the second conductive layer 244 can fill all the internal spaces defined by the second insulating layer 234. The second insulating layer 234 and the third insulating layer 236 can be in contact with each other in the narrow region DTIN of the pixel isolation region DTI, but may not be in contact with each other in the wide region DTIW of the pixel isolation region DTI. In the wide region DTIW of the pixel isolation region DTI, the second insulating layer 234 and the third insulating layer 236 can be spaced apart from each other by the connection part 244C of the second conductive layer 244 located between the second insulating layer 234 and the third insulating layer 236. The connection portion 244C of the second conductive layer 244 may be located between the second insulating layer 234 and the third insulating layer 236 and may be in contact with the first conductive layer 242. The charging portion 244S of the second conductive layer 244 may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the charging portion 244S of the second conductive layer 244 and the first conductive layer 242. The second conductive layer 244 may be in contact with and connected to the first conductive layer 242 in a portion adjacent to the first surface 200F of the first substrate 200, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 in a portion adjacent to the second surface 200B. The second conductive layer 244 may be in contact with and connected to the first conductive layer 242 in a portion adjacent to the edge of each of the plurality of photosensitive elements PD, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 in a portion adjacent to the side of each of the plurality of photosensitive elements PD. Accordingly, the first conductive layers 242 spaced apart from each other in the pixel isolation region DTI may be electrically connected to each other by the connection portion 244C of the second conductive layer 244. In the image sensor 1 according to some exemplary embodiments, since the pixel isolation region DTI includes the first conductive layer 242 adjacent to the photosensitive element PD, electrons that cause dark current at the interface between the pixel isolation region DTI and the photosensitive element PD are reduced, the dark level is lowered, and the performance can be improved. Additionally, in the pixel isolation region DTI included in the image sensor 1 according to some exemplary embodiments, the internal space defined by the first insulating layer 232 is filled together with a conductive material including the first conductive layer 242 and the second conductive layer 244 and an insulating material including the second insulating layer 234 and the third insulating layer 236, and thus, the volume ratio of the insulating material in the pixel isolation region DTI is relatively increased, and thus, the volume ratio of the conductive material can be relatively decreased. In the image sensor 1 according to some exemplary embodiments, the ratio of the conductive material having a relatively high light absorption rate is decreased, and the ratio of the insulating material having a relatively low light absorption rate is increased, and thus, the photosensitivity can be increased. FIG. 7 is a plan layout showing a unit pixel PX including a photosensitive element PD and a pixel isolation region DTI of an image sensor 1000a according to some exemplary embodiments. Referring to FIG. 7, the image sensor 1000a may include: a substrate SB having pixel separation recesses DTR; the plurality of unit pixels; and a pixel separation region DTI filling the pixel separation recesses DTR. Each of the plurality of unit pixels PX may include a photosensitive element PD. The pixel separation region DTI may be located between the plurality of photosensitive elements PD. In some exemplary embodiments, in a plan view, the pixel separation region DTI may completely surround each of the plurality of photosensitive elements PD. The pixel separation DTI may include: a narrow region DTIN having a relatively narrow first horizontal width W1; and a wide region DTIW having a relatively wide second horizontal width W2. The narrow region DTIN may be a portion of the pixel separation region DTI disposed between photosensitive elements PD adjacent to each other in the width direction of the photosensitive element PD, and the wide region DTIW may be a portion of the pixel separation region DTI disposed between photosensitive elements PD adjacent to each other in the diagonal direction of the photosensitive element PD. For example, the narrow region DTIN may be a portion of the pixel separation region DTI disposed between facing edges of each of the adjacent photosensitive elements PD, and the wide region DTIW may be a portion of the pixel separation region DTI disposed between facing sides of the adjacent photosensitive elements PD. A vertical cross-sectional view of a portion of FIG. 7 taken along line A-A' in FIG. 7 may be substantially the same as FIG. 5A, and a vertical cross-sectional view of a portion of FIG. 7 taken along line B-B' in FIG. 7 may be substantially the same as FIG. 5B, and thus will not be described in detail herein. FIGS. 8A and 8B are horizontal cross-sectional views of an image sensor 1a according to some exemplary embodiments. FIG. 8A is a horizontal cross-sectional view of a portion of FIGS. 5A and 5B taken along a first vertical level LV1 in FIGS. 5A and 5B, and FIG. 8B is a horizontal cross-sectional view of a portion of FIGS. 5A and 5B taken along a second vertical level LV2 in FIGS. 5A and 5B. Referring to FIGS. 8A and 8B and FIGS. 5A and 5B, the image sensor 1a may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the photosensitive substrate WFO and the plurality of microlenses 550. Element isolation regions STI and pixel isolation regions DTI may be disposed in the first substrate 200. The plurality of unit pixels PX may be defined by the pixel isolation regions DTI, and the pixel isolation regions DTI may surround each of the plurality of photosensitive elements PD in a plan view in the first substrate 200. The pixel isolation regions DTI may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and a second conductive layer 244. In the pixel isolation recess DTR, the plurality of first insulating layers 232 that surround each of the plurality of photosensitive elements PD and are spaced apart from each other may be disposed. In the pixel isolation recess DTR, the plurality of first conductive layers 242 that surround each of the plurality of photosensitive elements PD and are spaced apart from each other may be disposed, and each of the plurality of first conductive layers 242 may cover a part of the side surface of each of the plurality of first insulating layers 232. In the narrow region DTIN of the pixel isolation region DTI, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, and the first conductive layer 242 may be disposed, but the second conductive layer 244 may not be disposed. In the wide region of the pixel isolation region DTI, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244 may be disposed. The second conductive layer 244 may include a connection portion 244C and a charging portion 244S. The first conductive layers 242 spaced apart from each other in the pixel isolation region DTI may be electrically connected to each other by the connection portion 244C of the second conductive layer 244. FIGS. 9A to 9J are vertical cross-sectional views showing a method of manufacturing an image sensor according to some exemplary embodiments. Specifically, FIGS. 9A to 9J are enlarged vertical cross-sectional views of each of a part corresponding to the region X1 in FIG. 5A and a part corresponding to the region X2 in FIG. 5B. Referring to FIG. 9A, the element isolation recess STR is formed by the following method: a first pad layer 202 and a second pad layer 204 are formed on the first surface 200F of the first substrate 200; and then a part of each of the first pad layer 202, the second pad layer 204, and the first substrate 200 is removed. For example, the first pad layer 202 may include an oxide and the second pad layer 204 may include a nitride. The element isolation recess STR penetrates through the first pad layer 202 and the second pad layer 204, and may be formed to extend from the first surface 200F of the first substrate 200 into the first substrate 200. A preliminary first layer 222P, a preliminary second layer 224P, and a preliminary third layer 226P are sequentially formed on the first substrate 200, the first pad layer 202, and the second pad layer 204 in which the element isolation recess STR is formed. The preliminary first layer 222P may include an oxide, the preliminary second layer 224P may include a nitride, and the preliminary third layer 226P may include an oxide. Remove a part of each of the preliminary first layer 222P, the preliminary second layer 224P, the preliminary third layer 226P, and the first substrate 200 to form a pixel separation recess DTR. The pixel separation recess DTR penetrates the preliminary first layer 222P, the preliminary second layer 224P, and the preliminary third layer 226P, and can be formed to extend from the first surface 200F of the first substrate 200 into the first substrate 200. A part of the pixel separation recess DTR can be formed to have a relatively narrow first horizontal width W1, and other parts can be formed to have a relatively wide second horizontal width W2. Form a preliminary first insulating layer 232P on the preliminary first layer 222P, the preliminary second layer 224P, the preliminary third layer 226P, and the first substrate 200 in which the pixel separation recess DTR is formed. The preliminary first insulating layer 232P can be formed to conformally cover the inner wall and bottom surface of the pixel separation recess DTR and the preliminary third layer 226P. The preliminary first insulating layer 232P can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and / or metal oxide. Referring to FIG. 9B, form a preliminary first conductive layer 242P on the preliminary first insulating layer 232P. The preliminary first conductive layer 242P can be formed to conformally cover the preliminary first insulating layer 232P. The preliminary first conductive layer 242P can include at least one of silicon, metal, metal silicide, metal nitride, and / or a metal-containing film. For example, the preliminary first conductive layer 242P can include doped polycrystalline silicon. Referring to FIG. 9C, form a preliminary second insulating layer 234P on the preliminary first conductive layer 242P. The preliminary second insulating layer 234P can be formed to conformally cover the preliminary first conductive layer 242P. The preliminary second insulating layer 234P can include an insulating layer such as silicon oxide, silicon nitride, silicon oxynitride, and / or metal oxide. The preliminary second insulating layer 234P can fill the lower part of the internal space defined by the preliminary first conductive layer 242P in the part X1 of the pixel separation recess DTR corresponding to the narrow region DTIN in FIGS. 5A to 8B, and can fill only a part of the lower part of the internal space defined by the preliminary first conductive layer 242P in the part X2 of the pixel separation recess DTR corresponding to the wide region DTIW. Referring to FIGS. 9C and 9D together, a part of the preliminary second insulating layer 234P can be removed to form the second insulating layer 234. In order to fill the entire lower part of the internal space defined by the preliminary first conductive layer 242P in the portion X1 of the pixel separation recess DTR corresponding to the narrow region DTIN in FIGS. 5A to 8B without filling the upper part, and in order to fill only a part of the lower part of the internal space defined by the preliminary first conductive layer 242P in the portion X2 of the pixel separation recess DTR corresponding to the wide region DTIW without filling the upper part, the preliminary second insulating layer 234P can conformally cover the lower part. Referring to FIG. 9E, a preliminary second conductive layer 244P can be formed on the second insulating layer 234 and the preliminary first conductive layer 242P. The preliminary second conductive layer 244P can include at least one of silicon, metal, metal silicide, metal nitride, and / or metal-containing film. For example, the preliminary second conductive layer 244P can include doped polycrystalline silicon. The preliminary second conductive layer 244P can be formed to fill the internal space defined by the preliminary first conductive layer 242P and the second insulating layer 234. Referring to FIGS. 9E and 9F together, a part of the preliminary second conductive layer 244P and a part of the preliminary first conductive layer 242P can be removed to form the second conductive layer 244 and the first conductive layer 242. The second insulating layer 234 can be used to fill the internal space defined by the first conductive layer 242 in the portion X1 of the pixel separation recess DTR corresponding to the narrow region DTIN in FIGS. 5A to 8B, and the second insulating layer 234 and the second conductive layer 244 can be used together to fill the internal space defined by the first conductive layer 242 in the portion X2 of the pixel separation recess DTR corresponding to the wide region DTIW. In the portion X2 of the pixel separation recess DTR corresponding to the wide region DTIW, the second insulating layer 234 can conformally cover the lower part of the internal space defined by the first conductive layer 242 (except for a part of the upper part), and the second conductive layer 244 can fill a part of the upper side of the internal space defined by the first conductive layer 242 and fill the internal space defined by the second insulating layer 234. In the portion X2 of the pixel separation recess DTR corresponding to the wide region DTIW, the second conductive layer 244 can be connected to and in contact with the upper part of the first conductive layer 242. Referring to FIG. 9G, a preliminary third insulating layer 236P can be formed on the preliminary first insulating layer 232P, the second insulating layer 234, the first conductive layer 242, and the second conductive layer 244. The preliminary third insulating layer 236P can be formed to fill the internal space defined by the preliminary first insulating layer 232P. The preliminary third insulating layer 236P can include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and / or metal oxide. Referring to FIGS. 9G and 9H together, in order to expose the second contact pad layer 204, a part of each of the preliminary first layer 222P, the preliminary second layer 224P, and the preliminary third layer 226P may be removed to form an element isolation region STI including the first layer 222, the second layer 224, and the third layer 226, and a part of each of the preliminary first insulating layer 232P and the preliminary third insulating layer 236P may be removed to form a pixel isolation region DTI including the first insulating layer 232, the first conductive layer 242, the second insulating layer 234, the second conductive layer 244, and the third insulating layer 236. Referring to FIGS. 9H and 9I together, the second contact pad layer 204 may be removed. Referring to FIGS. 9I and 9J together, in a subsequent process, the first contact pad layer 202 may be removed, and a part of the upper portion of each of the element isolation region STI and the pixel isolation region DTI may be removed. In some exemplary embodiments, the first surface 200F of the first substrate 200, the upper surface of the element isolation region STI, and the upper surface of the pixel isolation region DTI may be located at the same vertical level, but is not limited thereto. FIGS. 10A and 10B are vertical cross-sectional views of the image sensor 2 according to some exemplary embodiments, and FIGS. 11A and 11B are horizontal cross-sectional views of the image sensor 2. Specifically, FIG. 10A is a vertical cross-sectional view of a part of FIG. 4 taken along line A-A' in FIG. 4, FIG. 10B is a vertical cross-sectional view of a part of FIG. 4 taken along line B-B' in FIG. 4, FIG. 11A is a horizontal cross-sectional view taken along the first vertical level LV1 in FIGS. 10A and 10B, and FIG. 11B is a horizontal cross-sectional view taken along the second vertical level LV2. Referring to FIGS. 10A, 10B, 11A, and 11B together, the image sensor 2 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. An element isolation region STI and a pixel isolation region DTIa may be disposed in the first substrate 200. The plurality of unit pixels PX may be defined by the pixel isolation region DTIa, and the pixel isolation region DTIa may surround at least a part of each of the plurality of photosensitive elements PD in the first substrate 200 in a plan view. The pixel isolation region DTIa may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTIa may be disposed between the plurality of photosensitive elements PD arranged in a matrix in a plan view, and may have a grid shape or a mesh shape in the plan view. The pixel isolation region DTIa can be formed within a pixel isolation recess DTR that extends from the first surface 200F to the second surface 200B of the first substrate 200. For example, the pixel isolation recess DTRa can penetrate the first substrate 200, and the component isolation recess STR may not penetrate the first substrate 200. In some embodiments, the pixel isolation region DTIa can overlap a portion of the component isolation region STI in the vertical direction. The pixel isolation region DTIa can include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and / or a second conductive layer 244a. In the narrow region DTIN of the pixel isolation region DTIa, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244a can be arranged. In the wide region DTIW of the pixel isolation region DTIa, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244a can be arranged. The second insulating layer 234 may not fill all the internal spaces defined by the first conductive layer 242 in each of the narrow region DTIN and the wide region DTIW of the pixel isolation region DTIa. The internal spaces defined by the first conductive layer 242 in the narrow region DTIN and the wide region DTIW of the pixel isolation region DTIa can be entirely filled by the second insulating layer 234 and the second conductive layer 244a. The second conductive layer 244a can include a connection portion 244C, a charging portion 244S, and a narrow charging portion 244SL. The internal spaces defined by the first conductive layer 242 in the narrow region DTIN of the pixel isolation region DTIa can be entirely filled by the second insulating layer 234, and the connection portion 244C and the narrow charging portion 244SL of the second conductive layer 244a. The internal spaces defined by the first conductive layer 242 in the wide region DTIW of the pixel isolation region DTIa can be entirely filled by the second insulating layer 234, the connection portion 244C, and the charging portion 244S of the second conductive layer 244a. The connection portion 244C of the second conductive layer 244a is the portion of the second conductive layer 244a that is relatively adjacent to or close to the first surface 200F of the first substrate 200, and the charging portion 244S and the narrow charging portion 244SL of the second conductive layer 244a are the portions of the second conductive layer 244a that are relatively adjacent to or close to the second surface 200B of the first substrate 200. The connection portion 244C of the second conductive layer 244a may be located between the second insulating layer 234 and the third insulating layer 236, and the charging portion 244S and the narrow charging portion 244SL may extend from the connection portion 244C into the second insulating layer 234. The connection portion 244C of the second conductive layer 244a may extend from the charging portion 244S of the second conductive layer 244a toward the first surface 200F of the first substrate 200, the charging portion 244S may extend from the connection portion 244C to the second surface 200B of the first substrate 200, and the narrow charging portion 244SL may extend from the connection portion 244C toward the second surface 200B of the first substrate 200. The extension length of the charging portion 244S in the vertical direction may be greater than the extension length of the narrow charging portion 244SL. The horizontal width of the charging portion 244S may be greater than the horizontal width of the narrow charging portion 244SL. The charging portion 244S and the narrow charging portion 244SL of the second conductive layer 244a may fill all the internal spaces defined by the second insulating layer 234. The second insulating layer 234 and the third insulating layer 236 do not contact each other in the narrow region DTIN of the pixel division region DTIa and do not contact each other in the wide region DTIW of the pixel division region DTIa. In the narrow region DTIN and the wide region DTIW of the pixel division region DTIa, the second insulating layer 234 and the third insulating layer 236 may be spaced apart from each other by the connection portion 244C of the second conductive layer 244a located between the second insulating layer 234 and the third insulating layer 236. The connection portion 244C of the second conductive layer 244a may be located between the second insulating layer 234 and the third insulating layer 236 and may be in contact with the first conductive layer 242. The charging portion 244S and the narrow charging portion 244SL of the second conductive layer 244a may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the charging portion 244S and the narrow charging portion 244SL of the second conductive layer 244a and the first conductive layer 242. The second conductive layer 244a may be connected to and in contact with the first conductive layer 242 in a portion adjacent to the first surface 200F of the first substrate 200, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the second conductive layer 244a and the first conductive layer 242 in a portion adjacent to the second surface 200B. The second conductive layer 244a may be connected to and in contact with the first conductive layer 242 in a portion adjacent to the edge of each of the plurality of photosensitive elements PD, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the second conductive layer 244a and the first conductive layer 242 in a portion adjacent to the side of each of the plurality of photosensitive elements PD. The first conductive layers 242 may be spaced apart from each other in the pixel division region DTIa and may be electrically connected to each other by the connection portion 244C of the second conductive layer 244a. FIGS. 12A and 12B are horizontal cross-sectional views of the image sensor 2a according to some exemplary embodiments. FIG. 12A is a horizontal cross-sectional view of a portion of FIGS. 10A and 10B taken along the first vertical level LV1 in FIGS. 10A and 10B, and FIG. 12B is a horizontal cross-sectional view of a portion of FIGS. 10A and 10B taken along the second vertical level LV2 in FIGS. 10A and 10B. Referring to FIGS. 12A and 12B and FIGS. 10A and 10B, the image sensor 2a may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. In the first substrate 200, an element isolation region STI and a pixel isolation region DTIa may be disposed. The plurality of unit pixels PX may be defined by the pixel isolation region DTIa, and the pixel isolation region DTIa may surround each of the plurality of photosensitive elements in the first substrate 200 in a plan view. The pixel isolation region DTIa may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and a second conductive layer 244a. In a narrow region DTIN of the pixel isolation region DTIa, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244a may be disposed. In a wide region DTIW of the pixel isolation region DTIa, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244a may be disposed. The second conductive layer 244a may include a connection portion 244C, a charging portion 244S, and a narrow charging portion 244SL. The first conductive layers 242 may be spaced apart from each other in the pixel isolation region DTIa and may be electrically connected to each other by the connection portion 244C of the second conductive layer 244a. FIGS. 13A and 13B are vertical cross-sectional views of an image sensor 3 according to some exemplary embodiments, and FIGS. 14A and 14B are horizontal cross-sectional views of the image sensor 3. Specifically, FIG. 13A is a vertical cross-sectional view of a portion of FIG. 4 taken along line A-A' in FIG. 4, FIG. 13B is a vertical cross-sectional view of a portion of FIG. 4 taken along line B-B' in FIG. 4, FIG. 14A is a horizontal cross-sectional view taken along a first vertical level LV1 in FIGS. 13A and 13B, and FIG. 14B is a horizontal cross-sectional view taken along a second vertical level LV2 in FIGS. 13A and 13B. Referring together to FIGS. 13A, 13B, 14A, and 14B, the image sensor 3 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. In the first substrate 200, an element isolation region STI and a pixel isolation region DTIb may be disposed. The plurality of unit pixels PX may be defined by the pixel isolation region DTIb, and the pixel isolation region DTIb may surround at least a portion of each of the plurality of photosensitive elements PD in the first substrate 200 in a plan view. The pixel isolation region DTIb may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTIb may be disposed between each of the plurality of photosensitive elements PD arranged in a matrix in a plan view and may have a grid shape or a mesh shape in the plan view. The pixel isolation region DTIb can be formed in a pixel isolation recess DTR extending from the first surface 200F to the second surface 200B of the first substrate 200. For example, the pixel isolation recess DTRb can penetrate the first substrate 200, and the element isolation recess STR may not penetrate the first substrate 200. In some exemplary embodiments, the pixel isolation region DTIb can overlap a part of the element isolation region STI in the vertical direction. The pixel isolation region DTIb can include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and a second conductive layer 244b. In the narrow region DTIN of the pixel isolation region DTIb, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244b can be arranged. In the wide region DTIW of the pixel isolation region DTIb, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244b can be arranged. The second insulating layer 234 may not fill all the internal spaces defined by the first conductive layer 242 in each of the narrow region DTIN and the wide region DTIW of the pixel isolation region DTIb. The internal spaces defined by the first conductive layer 242 in the narrow region DTIN and the wide region DTIW of the pixel isolation region DTIb can be completely filled with the second insulating layer 234 and the second conductive layer 244b. The second conductive layer 244b can include a connection portion 244C, a charging portion 244S, and a narrow charging portion 244SLa. The internal spaces defined by the first conductive layer 242 in the narrow region DTIN of the pixel isolation region DTIb can be completely filled with the second insulating layer 234, and the connection portion 244C and the narrow charging portion 244SLa of the second conductive layer 244b. The internal spaces defined by the first conductive layer 242 in the wide region DTIW of the pixel isolation region DTIb can be completely filled with the second insulating layer 234, the connection portion 244C, and the charging portion 244S of the second conductive layer 244b. The connection portion 244C of the second conductive layer 244b is a portion of the second conductive layer 244b that is relatively adjacent to or close to the first surface 200F of the first substrate 200, and the charging portion 244S and the narrow charging portion 244SLa of the second conductive layer 244b are portions of the second conductive layer 244b that are relatively adjacent to or close to the second surface 200B of the first substrate 200. The connection portion 244C of the second conductive layer 244b is located between the second insulating layer 234 and the third insulating layer 236, and the charging portion 244S and the narrow charging portion 244SLa can extend from the connection portion 244C into the second insulating layer 234. The connection portion 244C of the second conductive layer 244b can extend from the charging portion 244S of the second conductive layer 244b toward the first surface 200F of the first substrate 200, the charging portion 244S can extend from the connection portion 244C to the second surface 200B of the first substrate 200, and the narrow charging portion 244SLa can extend from the connection portion 244C toward the second surface 200B of the first substrate 200. The extension length of the charging portion 244S in the vertical direction can be substantially equal to the extension length of the narrow charging portion 244SLa. The horizontal width of the charging portion 244S can be greater than the horizontal width of the narrow charging portion 244SLa. The charging portion 244S and the narrow charging portion 244SLa of the second conductive layer 244b can fill all the internal spaces defined by the second insulating layer 234. The second insulating layer 234 and the third insulating layer 236 can be not in contact with each other in the narrow region DTIN of the pixel separation region DTIb and can be not in contact with each other in the wide region DTIW of the pixel separation region DTIb. In the narrow region DTIN and the wide region DTIW of the pixel separation region DTIb, the second insulating layer 234 and the third insulating layer 236 can be spaced apart from each other by the connection portion 244C of the second conductive layer 244b located between the second insulating layer 234 and the third insulating layer 236. The connection portion 244C of the second conductive layer 244b may be located between the second insulating layer 234 and the third insulating layer 236 and may be in contact with the first conductive layer 242. The charging portion 244S and the narrow charging portion 244SLa of the second conductive layer 244b may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the charging portion 244S and the narrow charging portion 244SLa of the second conductive layer 244b and the first conductive layer 242. The second conductive layer 244b may be in contact with and connected to the first conductive layer 242 in a portion adjacent to the first surface 200F of the first substrate 200, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the second conductive layer 244b and the first conductive layer 242 in a portion adjacent to the second surface 200B. The second conductive layer 244b may be in contact with and connected to the first conductive layer 242 in a portion adjacent to the edge of each of the plurality of photosensitive elements PD, and may be spaced apart from the first conductive layer 242 by the second insulating layer 234 located between the second conductive layer 244b and the first conductive layer 242 in a portion adjacent to the side of each of the plurality of photosensitive elements PD. The first conductive layers 242 may be spaced apart from each other in the pixel partition area DTIb and may be electrically connected to each other by the connection portion 244C of the second conductive layer 244b. FIGS. 15A and 15B are horizontal cross-sectional views of the image sensor 3a according to some exemplary embodiments. FIG. 15A is a horizontal cross-sectional view of a portion of FIGS. 13A and 13B taken along the first vertical level LV1 in FIGS. 10A and 10B, and FIG. 15B is a horizontal cross-sectional view of a portion of FIGS. 13A and 13B taken along the second vertical level LV2 in FIGS. 13A and 13B. Referring to FIGS. 15A and 15B and FIGS. 13A and 13B, the image sensor 3a may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. In the first substrate 200, an element isolation region STI and a pixel isolation region DTIb may be disposed. The plurality of unit pixels PX may be defined by the pixel isolation region DTIb, and the pixel isolation region DTIb may surround each of the plurality of photosensitive elements in the first substrate 200 in a plan view. The pixel isolation region DTIb may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, and a second conductive layer 244b. In a narrow region DTIN of the pixel isolation region DTIb, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244b may be disposed. In a wide region DTIW of the pixel isolation region DTIb, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244b may be disposed. The second conductive layer 244b may include a connection portion 244C, a charging portion 244S, and a narrow charging portion 244SLa. The first conductive layers 242 spaced apart from each other in the pixel isolation region DTIb may be electrically connected to each other by the connection portion 244C of the second conductive layer 244b. FIGS. 16A and 16B are vertical cross-sectional views of an image sensor 4 according to some exemplary embodiments, and FIGS. 17A and 17B are horizontal cross-sectional views of the image sensor 4. Specifically, FIG. 16A is a vertical cross-sectional view of a portion of FIG. 4 taken along line A-A' in FIG. 4, FIG. 16B is a vertical cross-sectional view of a portion of FIG. 4 taken along line B-B' in FIG. 4, FIG. 17A is a horizontal cross-sectional view taken along a first vertical level LV1 in FIGS. 16A and 16B, and FIG. 17B is a horizontal cross-sectional view taken along a second vertical level LV2 in FIGS. 16A and 16B. Referring together to FIGS. 16A, 16B, 17A, and 17B, the image sensor 4 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. In the first substrate 200, an element isolation region STI and a pixel isolation region DTIc may be disposed. The plurality of unit pixels PX may be defined by the pixel isolation region DTIc, and the pixel isolation region DTIc may surround at least a portion of each of the plurality of photosensitive elements PD in the first substrate 200 in a plan view. The pixel isolation region DTIc may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTIc may be disposed between each of the plurality of photosensitive elements PD arranged in a matrix in a plan view, and may have a grid shape or a mesh shape in the plan view. The pixel isolation region DTIc can be formed within a pixel isolation recess DTR that extends from the first surface 200F of the first substrate 200 to the second surface 200B. For example, the pixel isolation recess DTRc can penetrate through the first substrate 200, and the component isolation recess STR may not penetrate through the first substrate 200. In some exemplary embodiments, the pixel isolation region DTIc can overlap a portion of the component isolation region STI in the vertical direction. The pixel isolation region DTIc can include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, a second conductive layer 244c, and a third conductive layer 246. Each of the first insulating layer 232, the second insulating layer 234, and the third insulating layer 236 can include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, and / or metal oxide. Each of the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 can include at least one of silicon, metal, metal silicide, metal nitride, and / or metal-containing film. For example, each of the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 can include doped polycrystalline silicon. In the narrow region DTIN of the pixel isolation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, and the first conductive layer 242 are arranged, but the second conductive layer 244c and the third conductive layer 246 may not be arranged. In the wide region DTIW of the pixel isolation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 can be arranged. The first insulating layer 232 may cover the inner wall of the pixel separation recess DTR. The first conductive layer 242 may cover a part of the side surface of the first insulating layer 232 in the pixel separation recess DTR. For example, the first conductive layer 242 may extend from the second surface 200B of the first substrate 200 toward the first surface 200F, but may not extend to the first surface 200F. The first conductive layer 242 may conformally cover a part of the side surface of the first insulating layer 232 in the pixel separation recess DTR, and may not fill the entire space defined by the first insulating layer 232. In the internal space defined by the first conductive layer 242, the second insulating layer 234 may cover a part of the side surface of the first conductive layer 242, and the third conductive layer 246 may cover the remaining part of the side surface of the first conductive layer 242. The second insulating layer 234 and the third conductive layer 246 may not fill all of the internal space defined by the first conductive layer 242. The second conductive layer 244c may extend in a vertical direction from the third insulating layer 236. The second conductive layer 244c may fill all of the internal space defined by the second insulating layer 234 and the third conductive layer 246. The third insulating layer 236 may cover the first conductive layer 242, the second insulating layer 234, the second conductive layer 244c, and the third conductive layer 246, and fill the pixel separation region DTIc. The third insulating layer 236 may fill a part of the internal space defined by the first insulating layer 232 that is adjacent to the first surface 200F of the first substrate 200. In the narrow region DTIN of the pixel separation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, and the first conductive layer 242 may be disposed, but the second conductive layer 244c and the third conductive layer 246 may not be disposed. In the wide region DTIW of the pixel separation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 may be disposed. The second conductive layer 244c and the third conductive layer 246 may respectively correspond to the charging portion 244S and the connection portion 244C of the second conductive layer 244 shown in FIGS. 5A to 6B. The third conductive layer 246 may be located between the second insulating layer 234 and the third insulating layer 236 and may be in contact with the first conductive layer 242. The second conductive layer 244c may be spaced apart from the first conductive layer 242 by the third conductive layer 246 located between the second conductive layer 244c and the first conductive layer 242. The first conductive layers 242 spaced apart from each other in the pixel isolation region DTIc may be electrically connected to each other by the third conductive layer 246. The second conductive layer 244c and the third conductive layer 246 may be collectively referred to as the second conductive layer, and the portion of the second conductive layer 244c protruding from the third conductive layer 246 and the portion extending in the vertical direction may be referred to as the charging portion of the second conductive layer and the connection portion of the second conductive layer, respectively. For example, the charging portion 244S of the second conductive layer 244 shown in FIGS. 5A to 6B may be connected from the connection portion 244C to the second surface 200B of the first substrate 200, and the second conductive layer 244c may pass through the third conductive layer 246 and the second insulating layer 234 and extend from the upper surface of the third insulating layer 236 to the second surface 200B of the first substrate 200. The lower surfaces of the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 may be located at the same vertical level, and the upper surfaces of the first conductive layer 242 and the second conductive layer 244c may be located at the same vertical level. FIGS. 18A and 18B are horizontal cross-sectional views of the image sensor 4a according to some exemplary embodiments. FIG. 18A is a horizontal cross-sectional view of a portion of FIGS. 16A and 16B taken along the first vertical level LV1 in FIGS. 16A and 16B, and FIG. 18B is a horizontal cross-sectional view of a portion of FIGS. 16A and 16B taken along the second vertical level LV2 in FIGS. 16A and 16B. Referring to FIGS. 18A and 18B and FIGS. 16A and 16B, the image sensor 4a may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. In the first substrate 200, an element isolation region STI and a pixel isolation region DTIc may be disposed. The plurality of unit pixels PX may be defined by the pixel isolation region DTIc, and the pixel isolation region DTIc may surround each of the plurality of photosensitive elements in a plan view in the first substrate 200. The pixel isolation region DTIc may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, a second conductive layer 244c, and a third conductive layer 246. In a narrow region DTIN of the pixel isolation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, and the first conductive layer 242 may be disposed. In a wide region DTIW of the pixel isolation region DTIc, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246 may be disposed. The first conductive layers 242 spaced apart from each other in the pixel isolation region DTIc may be electrically connected to each other by the third conductive layer 246. FIGS. 19A to 19L are vertical cross-sectional views showing a method of manufacturing an image sensor according to an embodiment. Specifically, FIGS. 19A to 19J are enlarged vertical cross-sectional views of each of a part corresponding to region X3 in FIG. 16A and a part corresponding to region X4 in FIG. 16B. Referring to FIG. 19A, an element isolation recess STR is formed by the following method: a first pad layer 202 and a second pad layer 204 are formed on a first surface 200F of the first substrate 200; and then a part of each of the first pad layer 202, the second pad layer 204, and the first substrate 200 is removed. The element isolation recess STR penetrates through the first pad layer 202 and the second pad layer 204, and may be formed to extend from the first surface 200F of the first substrate 200 into the first substrate 200. A preliminary first layer 222P, a preliminary second layer 224P, and a preliminary third layer 226P are sequentially formed on the first substrate 200, the first pad layer 202, and the second pad layer 204 in which the element isolation recess STR is formed. A part of each of the preliminary first layer 222P, the preliminary second layer 224P, the preliminary third layer 226P, and the first substrate 200 is removed to form a pixel isolation recess DTR. The pixel isolation recess DTR penetrates through the preliminary first layer 222P, the preliminary second layer 224P, and the preliminary third layer 226P, and may be formed to extend from the first surface 200F of the first substrate 200 into the first substrate 200. A part of the pixel isolation recess DTR may be formed to have a relatively narrow first horizontal width W1, and other parts may be formed to have a relatively wide second horizontal width W2. A preliminary first insulating layer 232P can be formed on a preliminary first layer 222P, a preliminary second layer 224P, a preliminary third layer 226P, and a first substrate 200 in which pixel separation recesses DTR can be formed. Referring to FIG. 19B, a preliminary first conductive layer 242P can be formed on the preliminary first insulating layer 232P. Referring to FIG. 19C, a preliminary second insulating layer 234P can be formed on the preliminary first conductive layer 242P. Referring to FIG. 19D, a preliminary second conductive layer 244P can be formed on the preliminary second insulating layer 234P. The preliminary second conductive layer 244P can be formed to fill an internal space defined by the preliminary second insulating layer 234P. Referring together to FIGS. 19D and 19E, a part of the preliminary second conductive layer 244P can be removed to form a second conductive layer 244c. The part of the preliminary second conductive layer 244P that fills the internal space defined by the preliminary second insulating layer 234P in a part X3 corresponding to the narrow region DTIN in FIGS. 16A to 18B of the pixel separation recess DTRc can be entirely removed; the upper part of the preliminary second conductive layer 244P that fills the internal space defined by the preliminary second insulating layer 234P in a part X4 corresponding to the wide region DTIW of the pixel separation recess DTR can be removed, and the lower part of the preliminary second conductive layer 244P can be retained as the second conductive layer 244c. Referring together to FIGS. 19E and 19F, a part of the preliminary second insulating layer 234P can be removed to form a second insulating layer 234. The second insulating layer 234 can be formed, for example, by removing a part of the preliminary second insulating layer 234P such that the upper part of the second conductive layer 244c protrudes more upward than the upper surface of the second insulating layer 234. Referring to FIG. 19G, a preliminary third conductive layer 246P can be formed on the second insulating layer 234, the preliminary first conductive layer 242P, and the second conductive layer 244c. The preliminary third conductive layer 246P can include at least one of silicon, metal, metal silicide, metal nitride, and / or a metal-containing film. For example, the preliminary third conductive layer 246P can include doped polycrystalline silicon. The preliminary third conductive layer 246P can be formed to fill an internal space defined by the preliminary first conductive layer 242P, the second insulating layer 234, and the second conductive layer 244. Referring to FIGS. 19G and 19H together, a part of the preliminary third conductive layer 246P and a part of the preliminary first conductive layer 242P may be removed to form the third conductive layer 246 and the first conductive layer 242. The second insulating layer 234 may be used to fill all the internal spaces defined by the first conductive layer 242 in the portion X3 of the pixel separation recess DTR corresponding to the narrow region DTIN in FIGS. 16A to 18B, and the second insulating layer 234 and the third conductive layer 246 may be used together to fill all the internal spaces defined by the first conductive layer 242 in the portion X4 of the pixel separation recess DTR corresponding to the wide region DTIW. In the portion X4 of the pixel separation recess DTR corresponding to the wide region DTIW, the second insulating layer 234 may conformally cover the lower part of the internal space defined by the first conductive layer 242 (except for a part of the upper part), and the third conductive layer 246 may conformally cover a part of the upper side of the internal space defined by the first conductive layer 242 and fill the internal space defined by the second insulating layer 234. The second conductive layer 244c may fill all the internal spaces defined by the second insulating layer 234 and the third conductive layer 246. In the portion X4 of the pixel separation recess DTR corresponding to the wide region DTIW, the third conductive layer 246 may be connected to and in contact with the upper part of the first conductive layer 242. Referring to FIG. 19I, a preliminary third insulating layer 236P may be formed on the preliminary first insulating layer 232P, the second insulating layer 234, the first conductive layer 242, the second conductive layer 244c, and the third conductive layer 246. Referring to FIGS. 19I and 19J together, in order to expose the second pad layer 204, a part of each of the preliminary first layer 222P, the preliminary second layer 224P, and the preliminary third layer 226P may be removed to form the element isolation region STI including the first layer 222, the second layer 224, and the third layer 226, and a part of each of the preliminary first insulating layer 232P and the preliminary third insulating layer 236P may be removed to form the pixel separation region DTIc including the first insulating layer 232, the first conductive layer 242, the second insulating layer 234, the second conductive layer 244c, the third conductive layer 246, and the third insulating layer 236. Referring to FIGS. 19J and 19K together, the second pad layer 204 may be removed. Referring to FIGS. 19K and 19L, in a subsequent process, the first pad layer 202 may be removed, and a part of the upper part of each of the element isolation region STI and the pixel separation region DTIc may be removed. In some exemplary embodiments, the first surface 200F of the first substrate 200, the upper surface of the element isolation region STI, and the upper surface of the pixel separation region DTIc may be located at the same vertical level. FIGS. 20 to 22 are respectively vertical cross-sectional views of image sensors 5, 6, and 7 according to some exemplary embodiments. Referring to FIG. 20, the image sensor 5 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. An element isolation region STI and a pixel isolation region DTId may be disposed in the first substrate 200. The plurality of unit pixels PX may be defined by the pixel isolation region DTId, and the pixel isolation region DTId may surround at least a portion of each of the plurality of photosensitive elements PD in a plan view of the first substrate 200. The pixel isolation region DTId may be disposed between one of the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTId may be disposed between each of the plurality of photosensitive elements PD arranged in a matrix in a plan view and may have a grid shape or a mesh shape in the plan view. The pixel isolation region DTId may be formed in a pixel isolation recess DTR extending from a first surface 200F of the first substrate 200 to a second surface 200B. For example, the pixel isolation recess DTR may penetrate through the first substrate 200, and the element isolation recess STR may not penetrate through the first substrate 200. In some exemplary embodiments, the pixel isolation region DTId may overlap a portion of the element isolation region STI in a vertical direction. The pixel isolation region DTId may include a narrow region DTIN and a wide region (DTIW in FIG. 16B). The wide region DTIW of the pixel isolation region DTId included in the image sensor 5 may be substantially the same as the wide region DTIW of the pixel isolation region DTIc shown in FIGS. 17A and 17B, and redundant illustrations and descriptions are omitted. The pixel isolation region DTId may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, a second conductive layer 244d, and a third conductive layer (246 in FIG. 16B). The second conductive layer 244d and the third conductive layer 246 may be collectively referred to as the second conductive layer, and a portion of the second conductive layer 244d protruding from the third conductive layer 246 and a portion extending in a vertical direction may be respectively referred to as a charging portion of the second conductive layer and a connecting portion of the second conductive layer. In the narrow region DTIN of the pixel separation region DTId, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, and the second conductive layer 244d may be disposed, but the third conductive layer (246 in FIG. 16B) may not be disposed. The length of a part of the second conductive layer 244d extending vertically from the upper surface of the third insulating layer 236 in the narrow region DTIN of the pixel separation region DTId may be smaller than the length of a part of the second conductive layer 244d extending vertically from the upper surface of the third insulating layer 236 in the wide region (DTIW in FIG. 16B) of the pixel separation region DTId. Referring to FIG. 21, the image sensor 6 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. An element separation region STI and a pixel separation region DTIe may be disposed in the first substrate 200. The plurality of unit pixels PX may be defined by the pixel separation region DTIe, and the pixel separation region DTIe may surround at least a part of each of the plurality of photosensitive elements PD in the first substrate 200 in a plan view. The pixel separation region DTIe may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel separation region DTIe may be disposed between each of the plurality of photosensitive elements PD arranged in a matrix form in a plan view, and may have a grid shape or a mesh shape in the plan view. The pixel separation region DTIe may be formed in a pixel separation recess DTR extending from the first surface 200F of the first substrate 200 to the second surface 200B. For example, the pixel separation recess DTR may penetrate through the first substrate 200, and the element separation recess STR may not penetrate through the first substrate 200. In some exemplary embodiments, the pixel separation region DTIe may overlap a part of the element separation region STI in a vertical direction. The pixel separation region DTIe may include a narrow region DTIN and a wide region (DTIW in FIG. 16B). The wide region DTIW of the pixel separation region DTIe included in the image sensor 6 may be substantially the same as the wide region DTIW of the pixel separation region DTIc shown in FIGS. 17A and 17B, and redundant illustrations and descriptions are omitted. The pixel isolation region DTIe may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, a second conductive layer 244e, and a third conductive layer 246a. The second conductive layer 244e and the third conductive layer 246a may be collectively referred to as the second conductive layer, and the portion of the second conductive layer 244e protruding from the third conductive layer 246a and the portion extending in the vertical direction may be referred to as the charging portion of the second conductive layer and the connecting portion of the second conductive layer, respectively. In the narrow region DTIN of the pixel isolation region DTIe, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, the second conductive layer 244e, and the third conductive layer 246a may be disposed. The second conductive layer 244e may be substantially the same as the second conductive layer 244d shown in FIG. 20. The thickness of the third conductive layer 246a in the vertical direction from the upper surface of the third insulating layer 236 in the narrow region DTIN of the pixel isolation region DTIe may be less than the thickness of the third conductive layer 246a in the vertical direction from the upper surface of the third insulating layer 236 in the wide region (DTIW in FIG. 16B) of the pixel isolation region DTIe. Referring to FIG. 22, the image sensor 7 may include: an optical element substrate WFO having the plurality of unit pixels PX including the plurality of photosensitive elements PD; the plurality of microlenses 550 disposed on the optical element substrate WFO; and the plurality of color filter layers 530 located between the optical element substrate WFO and the plurality of microlenses 550. An element isolation region STI and a pixel isolation region DTIf may be disposed in the first substrate 200. The plurality of unit pixels PX may be defined by the pixel isolation region DTIf, and the pixel isolation region DTIf may surround at least a part of each of the plurality of photosensitive elements PD in the first substrate 200 in a plan view. The pixel isolation region DTIf may be disposed between one photosensitive element PD among the plurality of photosensitive elements PD and another photosensitive element PD adjacent to the one photosensitive element PD. The pixel isolation region DTIf may be disposed between each of the plurality of photosensitive elements PD arranged in a matrix in a plan view, and may have a grid shape or a mesh shape in the plan view. The pixel isolation region DTIf may be formed in a pixel isolation recess DTR extending from the first surface 200F of the first substrate 200 to the second surface 200B. For example, the pixel isolation recess DTR may penetrate through the first substrate 200, and the element isolation recess STR may not penetrate through the first substrate 200. In some exemplary embodiments, the pixel isolation region DTIf may overlap a part of the element isolation region STI in the vertical direction. The pixel separation region DTIf may include a narrow region DTIN and a wide region (DTIW in FIG. 16B). The wide region DTIW of the pixel separation region DTIf included in the image sensor 7 may be substantially the same as the wide region DTIW of the pixel separation region DTIc shown in FIGS. 17A and 17B, and redundant illustrations and descriptions are omitted. The pixel separation region DTIf may include a first insulating layer 232, a second insulating layer 234, a third insulating layer 236, a first conductive layer 242, a second conductive layer 244f, and a third conductive layer 246a. The second conductive layer 244f and the third conductive layer 246a may be collectively referred to as the second conductive layer, and the portion of the second conductive layer 244f protruding from the third conductive layer 246a and the portion extending in the vertical direction may be referred to as the charging portion and the connecting portion of the second conductive layer, respectively. In the narrow region DTIN of the pixel separation region DTIf, the first insulating layer 232, the second insulating layer 234, the third insulating layer 236, the first conductive layer 242, the second conductive layer 244f, and the third conductive layer 246a may be arranged. The length of the portion of the second conductive layer 244f extending vertically from the upper surface of the third insulating layer 236 in the narrow region DTIN of the pixel separation region DTIf may be substantially equal to the length of the portion of the second conductive layer 244f extending vertically from the upper surface of the third insulating layer 236 in the wide region (DTIW in FIG. 16B) of the pixel separation region DTIf. The horizontal width of the portion of the second conductive layer 244f located in the narrow region DTIN of the pixel separation region DTIf may be smaller than the horizontal width of the portion of the second conductive layer 244f located in the wide region (DTIW in FIG. 16B) of the pixel separation region DTIf. Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the following claims for patent. 1, 1a, 2, 2a, 3, 3a, 4, 4a, 5, 6, 7, 1000, 1000a, 1100, 2000, 3000, 3000a: Image sensor 200: First substrate 200B: Second surface 200F: First surface 202: First pad layer 204: Second pad layer 210, PD: Photosensitive element 222: First layer 222P: Preliminary first layer 224: Second layer 224P: Preliminary second layer 226: Third layer 226P: Preliminary third layer 232: First insulating layer 232P: Preliminary first insulating layer 234: Second insulating layer 234P: Preliminary second insulating layer 236: Third insulating layer 236P: Preliminary third insulating layer 242: First conductive layer 242P: Preliminary first conductive layer 244, 244a, 244b, 244c, 244d, 244e, 244f: Second conductive layer 244C: Connection part 244P: Preliminary second conductive layer 244S: Charging part 244SL, 244SLa: Narrow charging part 246, 246a: Third conductive layer 246P: Preliminary third conductive layer 270: Transfer gate 280: First internal connection structure 282: First internal connection pattern 284: First inter-wiring insulating layer 410: Second substrate 420: Logic circuit element 430: Second internal connection structure 432: Second internal connection pattern 434: Second inter-wiring insulating layer 510: First passivation layer 520: Guide pattern 530: Color filter layer 540: Second passivation layer 550: Microlens 1110: Pixel array 1120: Column driver 1130: Controller 1140: Pixel signal processing unit 1142: Correlated double sampler (CDS) 1144: Analog-to-digital converter (ADC) 1146: Buffer 1148: Ramp signal generator 2010, SUB: Substrate 2100, PX: Unit pixel 2200: Pixel unit 2320: Vertical signal line 2340: Horizontal signal line 2400: Vertical drive circuit 2500: Row signal processing circuit 2600: Horizontal drive circuit 2700: Output circuit 2800: Control circuit A-A', B-B': Line CR: Connection substrate area DTI, DTIa, DTIb, DTIc, DTId, DTIe, DTIf: Pixel partition DTIN: Narrow area DTIW: Wide area DTR: Pixel partition depression FD: Floating diffusion area LV1: First vertical level LV2: Second vertical level RST: Reset transistor SEL: Select transistor SF: Source follower transistor STI: Element separation area STR: Element separation depression TT: Transfer transistor VOUT: Output voltage VPIX: Power supply voltage W1: First horizontal width W2: Second horizontal width WFL: Logic board / logic substrateWFO: Optical element substrate X1, X2, X3, X4: Region / portion Referring to the following detailed description in conjunction with the accompanying drawings, some exemplary embodiments according to the concepts of the present invention will be more clearly understood. In the drawings: FIG. 1 is a block diagram of the configuration of an image sensor according to some exemplary embodiments. FIG. 2 is a block diagram showing the configuration of an image sensor according to some exemplary embodiments. FIGS. 3A and 3B are readout circuit diagrams of an image sensor according to some exemplary embodiments. FIG. 4 is a planar layout showing a unit pixel including a photosensitive element and a pixel partition region of an image sensor according to some exemplary embodiments. FIGS. 5A and 5B are vertical cross-sectional views of an image sensor according to some exemplary embodiments, and FIGS. 6A and 6B are horizontal cross-sectional views of the image sensor. FIG. 7 is a planar layout showing a unit pixel including a photosensitive element and a pixel partition region of an image sensor according to some exemplary embodiments. FIGS. 8A and 8B are horizontal cross-sectional views of an image sensor according to some exemplary embodiments. FIGS. 9A to 9J are vertical cross-sectional views showing a method of manufacturing an image sensor according to some exemplary embodiments. FIGS. 10A and 10B are vertical cross-sectional views of an image sensor according to some exemplary embodiments, and FIGS. 11A and 11B are horizontal cross-sectional views of the image sensor. FIGS. 12A and 12B are horizontal cross-sectional views of an image sensor according to some exemplary embodiments. FIGS. 13A and 13B are vertical cross-sectional views of an image sensor according to some exemplary embodiments, and FIGS. 14A and 14B are horizontal cross-sectional views. FIGS. 15A and 15B are horizontal cross-sectional views of an image sensor according to some exemplary embodiments. FIGS. 16A and 16B are vertical cross-sectional views of an image sensor according to some exemplary embodiments, and FIGS. 17A and 17B are horizontal cross-sectional views of the image sensor. FIGS. 18A and 18B are horizontal cross-sectional views of an image sensor according to some exemplary embodiments. FIGS. 19A to 19L are vertical cross-sectional views showing a method of manufacturing an image sensor according to some exemplary embodiments. FIGS. 20 to 22 are each vertical cross-sectional views of an image sensor according to some exemplary embodiments. 1: Image sensor 200: First substrate 200B: Second surface 200F: First surface 210, PD: Photosensitive element 222: First layer 224: Second layer 226: Third layer 232: First insulating layer 234: Second insulating layer 236: Third insulating layer 242: First conductive layer 270: Transmission gate 280: First internal connection structure 282: First internal connection pattern 284: First inter-wiring insulating layer 410: Second substrate 420: Logic circuit element 430: Second internal connection structure 432: Second internal connection pattern 434: Second inter-wiring insulating layer 510: First passivation layer 520: Guide pattern 530: Color filter layer 540: Second passivation layer 550: Microlens A-A': Line DTI: Pixel partition area DTIN: Narrow area DTR: Pixel partition recess LV1: First vertical level LV2: Second vertical level PX: Unit pixel STI: Component partition area STR: Component partition recess WFL: Logic board / logic substrate WFO: Optical component substrate X1: Area / portion

Claims

1. An image sensor, comprising: The substrate has a first surface and a second surface that are opposite to each other, and has a pixel-separating recess extending from the first surface to the second surface; A plurality of photosensitive elements are located in the substrate; and a pixel separation region fills the pixel separation recess and surrounds at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow area between the sides of adjacent photosensitive elements facing each other and a wide area between the edges of the adjacent photosensitive elements facing each other, and the pixel separation region comprising: a first insulating layer covering the inner wall of the pixel separation recess; a first conductive layer covering at least a portion of the side surface of the first insulating layer within the pixel separation recess; a second insulating layer covering a portion of the side surface of the first conductive layer within an internal space defined by the first conductive layer; and a second conductive layer filling all spaces within the internal space defined by the first conductive layer that are not filled by the second insulating layer such that the second conductive layer is connected to and in contact with the first conductive layer.

2. The image sensor of claim 1, wherein the second conductive layer is spaced apart from the first conductive layer at a first vertical level adjacent to the second surface of the substrate by a second insulating layer located between the second conductive layer and the first conductive layer, and the second conductive layer is connected to and in contact with the first conductive layer at a second vertical level adjacent to the first surface of the substrate.

3. The image sensor as claimed in claim 1, wherein the second conductive layer is located in the wide region of the pixel separation region, but not in the narrow region of the pixel separation region.

4. The image sensor of claim 1, wherein the portion of the second conductive layer located in the wide region of the pixel separation region extends in the vertical direction longer than the portion of the second conductive layer located in the narrow region of the pixel separation region extends in the vertical direction.

5. The image sensor of claim 1, wherein the vertical extension length of the portion of the second conductive layer located in the wide region of the pixel separation region is equal to the vertical extension length of the portion of the second conductive layer located in the narrow region of the pixel separation region, and the horizontal width of the portion of the second conductive layer located in the wide region of the pixel separation region is greater than the horizontal width of the portion of the second conductive layer located in the narrow region of the pixel separation region.

6. The image sensor of claim 1, wherein the first insulating layer is located among a plurality of first insulating layers included in the pixel separation region, and the first conductive layer is located among a plurality of first conductive layers included in the pixel separation region and surrounds at least one of the plurality of photosensitive elements, and at least two of the plurality of first conductive layers spaced apart from each other are electrically connected to each other via the second conductive layer.

7. The image sensor of claim 6, wherein each of the plurality of first insulating layers is spaced apart from and surrounds each of the plurality of first conductive layers.

8. The image sensor of claim 6, wherein at least two of the plurality of first conductive layers, which are spaced apart from each other, are connected to and in contact with a portion of the second conductive layer located in the wide area of ​​the pixel separation region, and are electrically connected to each other.

9. The image sensor as claimed in claim 1, further comprising: A third insulating layer fills the portion of another internal space defined by the first insulating layer that is adjacent to the first surface of the substrate.

10. The image sensor of claim 9, wherein the second conductive layer extends from the upper surface of the third insulating layer to the second surface of the substrate.

11. An image sensor, comprising: The substrate has a first surface and a second surface that are opposite to each other, and has a pixel-separating recess extending from the first surface to the second surface; A plurality of photosensitive elements are located in the substrate; and a pixel separation region fills the pixel separation recess and surrounds at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow area between the sides of adjacent photosensitive elements facing each other and a wide area between the edges of the adjacent photosensitive elements facing each other, and the pixel separation region comprising: a plurality of first insulating layers covering the inner wall of the pixel separation recess and spaced apart from each other and surrounding at least one of the plurality of photosensitive elements; a plurality of first conductive layers spaced apart from each other and covering at least a portion of the side surface of each of the plurality of first insulating layers within the pixel separation recess; a second insulating layer covering a portion of the side surface of the plurality of first conductive layers within the pixel separation recess within an internal space defined by the plurality of first conductive layers; and a second conductive layer covering the plurality of first conductive layers and the second insulating layer within the pixel separation recess within the internal space defined by the plurality of first conductive layers, and the second conductive layer comprising: The connection portion is adjacent to the first surface of the substrate and electrically connects at least some of the plurality of first conductive layers that are spaced apart from each other, and the extension portion extends in a vertical direction from the connection portion toward the second surface of the substrate and is spaced apart from the plurality of first conductive layers by a second insulating layer located between the extension portion and the plurality of first conductive layers.

12. The image sensor of claim 11, wherein the connecting portion and the extension portion of the second conductive layer are located in the wide region of the pixel separation region, and the connecting portion and the extension portion of the second conductive layer are not located in the narrow region of the pixel separation region.

13. The image sensor of claim 11, wherein the connection portion of the second conductive layer is located in the wide region of the pixel separation region, and the connection portion of the second conductive layer is not located in the narrow region, and the extension portion of the second conductive layer is located in both the wide region and the narrow region of the pixel separation region.

14. The image sensor of claim 13, wherein the extension of the second conductive layer in the wide region of the pixel separation region has a greater vertical extension than the extension of the second conductive layer in the narrow region of the pixel separation region.

15. The image sensor of claim 11, wherein the connection portion and the extension portion of the second conductive layer are respectively located in the wide region and the narrow region of the pixel separation region.

16. The image sensor of claim 15, wherein the extension of the second conductive layer in the wide region of the pixel separation region has an extension length in the vertical direction greater than the extension length in the vertical direction of the narrow region of the extension of the second conductive layer in the pixel separation region.

17. The image sensor of claim 15, wherein the extension length of a portion of the extension of the second conductive layer located in the wide region of the pixel separation region in the vertical direction is equal to the extension length of a portion of the extension of the second conductive layer located in the narrow region of the pixel separation region in the vertical direction.

18. The image sensor of claim 15, wherein a portion of the connection portion of the second conductive layer located in the wide region of the pixel separation region has a thickness in the vertical direction greater than the thickness in the vertical direction of a portion of the connection portion of the second conductive layer located in the narrow region of the pixel separation region.

19. An image sensor, comprising: The substrate has a first surface and a second surface that are opposite to each other, and has a pixel-separating recess extending from the first surface to the second surface; A plurality of photosensitive elements are located in the substrate; and a pixel separation region fills the pixel separation recess and surrounds at least a portion of each of the plurality of photosensitive elements, the pixel separation region having a narrow region between the sides of adjacent photosensitive elements facing each other and a wide region between the edges of the adjacent photosensitive elements facing each other, and the pixel separation region comprising: a plurality of first insulating layers covering the inner wall of the pixel separation recess and spaced apart from each other and surrounding at least one of the plurality of photosensitive elements; and a plurality of first conductive layers spaced apart from each other and covering at least a portion of the side surface of each of the plurality of first insulating layers within the pixel separation recess. A second insulating layer covers the side surfaces of the plurality of first conductive layers within the internal space defined by the plurality of first conductive layers in the pixel separation recess, and a second conductive layer covers the plurality of first conductive layers and the second insulating layer within the internal space defined by the plurality of first conductive layers in the pixel separation recess. The second conductive layer is located in the wide area of ​​the pixel separation region but not in the narrow area of ​​the pixel separation region. The second conductive layer includes a connecting portion adjacent to the first surface of the substrate and electrically connecting at least some of the plurality of first conductive layers that are spaced apart from each other, and an extension portion extending vertically from the connecting portion to the second surface of the substrate and spaced apart from the plurality of first conductive layers by the second insulating layer located between the extension portion and the plurality of first conductive layers.

20. The image sensor of claim 19, wherein each of the plurality of first conductive layers and the second conductive layer comprises doped polycrystalline silicon.

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