Substrate structure and manufacturing method thereof

Abstract

A substrate structure includes a substrate and a vertical conductive connector. The substrate comprises a material with a heat resistance temperature of 300°C or higher. The vertical conductive connector penetrates the substrate. The vertical conductive connector has a bonding structure extending in the direction of the substrate. A method for manufacturing the substrate structure is also provided.

Description

Technical Field

[0001] The invention relates to a substrate structure and a manufacturing method thereof. Prior Art

[0002] In substrate technology, vertical conductive connectors (such as plated through holes (PTHs)) are often formed to allow circuits to be interconnected in the thickness direction. However, due to the difference in material properties between the vertical conductive connectors and other components, problems such as low adhesion strength may occur. Therefore, it is a challenge to improve the adhesion strength of the vertical conductive connectors in the substrate to enhance product reliability. Summary of the invention

[0003] The present invention provides a substrate structure and a manufacturing method thereof, which can effectively improve product reliability.

[0004] A substrate structure of the present invention comprises a substrate and a vertical conductive connector. The substrate comprises a material with a heat-resistant temperature of 300° C. or higher. The vertical conductive connector penetrates the substrate. The vertical conductive connector has a bonding structure extending toward the substrate.

[0005] A method for manufacturing a substrate structure of the present invention comprises at least the following steps: providing a substrate having a plurality of through holes and a conductive layer; bonding the substrate to the conductive layer; performing an electroplating process to form vertical conductive connectors in the plurality of through holes; and performing an annealing process to diffuse a plurality of first atoms in the vertical conductive connectors toward the substrate to form a bonding structure.

[0006] Based on the above, the present invention introduces an annealing process to diffuse the atoms in the vertical conductive connector to form a bonding structure extending toward the substrate, thereby enhancing the adhesion strength between the vertical conductive connector and the adjacent components, thereby effectively improving product reliability.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. Simple diagram description

[0008] 1A to 1L are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to an embodiment of the present invention. 2A to 2L are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. 3A to 3E are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to yet another embodiment of the present invention. 4A to 4E are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to yet another embodiment of the present invention. Implementation

[0009] In the following detailed description, for purposes of illustration and not limitation, exemplary embodiments disclosing specific details are described to provide a thorough understanding of the various principles of the present invention. However, it will be apparent to one of ordinary skill in the art that, with the benefit of this disclosure, the present invention may be practiced in other embodiments that depart from the specific details disclosed herein. In addition, descriptions of well-known devices, methods, and materials may be omitted to avoid obscuring the description of the various principles of the present invention.

[0010] The present invention is more fully described with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or dimensions of the layers or regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0011] The above-mentioned other technical contents, features and effects of the present invention will be clearly presented in the detailed description of each embodiment with reference to the drawings below. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used for explanation, not for limiting the present invention.

[0012] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0013] 1A to 1L are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to an embodiment of the present invention.

[0014] Referring to FIG. 1A , a substrate 110 is provided, wherein the substrate 110 includes a material with a heat-resistant temperature of 300° C. or higher, so as to reduce the probability of problems such as cracking when the substrate is subsequently subjected to an annealing process, thereby ensuring that the annealing process does not have a significant adverse effect on the substrate 110. Here, the heat-resistant temperature may be 1500° C., and the substrate 110 may be used as a core layer of the substrate structure 100, wherein the heat-resistant temperature is a technical term known to those with ordinary knowledge in the relevant technical field, and will not be described in detail herein.

[0015] For example, the material of the substrate 110 includes glass, ceramic, liquid crystal polymer (LPC) or a combination thereof, but the present invention is not limited thereto, and the material of the substrate 110 may also be other suitable inorganic compounds and / or organic compounds that are more heat-resistant.

[0016] In some embodiments, the thickness 110T of the substrate 110 is between 0.05 mm and 10 mm, but the present invention is not limited thereto, and the thickness 110T of the substrate 110 can be selected according to actual design requirements.

[0017] In FIG. 1A , the substrate 110 may be formed with a plurality of through holes 111, wherein the through holes 111 penetrate the substrate 110, for example, from the upper surface 110a of the substrate 110 to the lower surface 110b of the substrate 110 in the direction of the thickness 110T. Further, the through holes 111 are formed by a drilling process or a similar process.

[0018] In some embodiments, the aperture 111D of the through hole 111 is between 0.05 mm and 0.5 mm, but the present invention is not limited thereto, and the aperture 111D of the through hole 111 can be determined according to actual design requirements.

[0019] In the present embodiment, the through hole 111, the upper surface 110a of the substrate 110 and the lower surface 110b of the substrate 110 are not formed with a seed layer made of a metal material such as titanium, copper, palladium or the like.

[0020] In some embodiments, when the material of the substrate 110 is glass, since the surface roughness of the glass is relatively low (for example, Ra<1 nanometer (nm)), it is difficult for the seed layer to be deposited thereon (whether it is formed by sputtering titanium / copper using a dry process or nano-palladium formed by a wet process, etc.), thereby causing the deposition amount of the seed layer to be uneven. As a result, the tensile force of the seed layer is reduced (for example, the tensile force of sputtering titanium / copper is <0.3 (kg / cm)), so it cannot effectively improve the subsequent adhesion strength between the vertical conductive connector and its adjacent components. Based on this, the present embodiment can omit the formation of such a film layer, and in the case of omitting such a film layer, the technical effect of improving the adhesion strength between the vertical conductive connector and its adjacent components can still be achieved, but the present invention is not limited to this.

[0021] 1B , the substrate 110 is bonded to the conductive layer 121 . For example, the conductive layer 121 may be attached to the substrate 110 via the adhesive layer 130 . Thus, the adhesive layer 130 is located between the conductive layer 121 and the substrate 110 , and the through hole 111 may expose a portion of the adhesive layer 130 .

[0022] In some embodiments, the thickness 121T of the conductive layer 121 is between 2 micrometers and 100 micrometers (e.g., 3 micrometers), so it can be regarded as a thin metal layer. At this thinness, it is easier to produce defects (e.g., holes) during use, so the conductive layer 121 can be further bonded to the carrier layer 122, wherein the thickness 122T of the carrier layer 122 is between 1 micrometer and 25 micrometers (e.g., 18 micrometers), so the probability of the conductive layer 121 producing defects during the manufacturing process can be reduced by the carrier layer 122, but the present invention is not limited thereto. Here, the conductive layer 121 and the carrier layer 122 can be bonded together through a release layer (not shown) to reduce the difficulty of subsequently removing the carrier layer 122.

[0023] In some embodiments, the material of the conductive layer 121 includes copper or the like, the material of the carrier layer 122 includes copper or the like, and the adhesive layer 130 includes polyimide or the like, but the present invention is not limited thereto.

[0024] In some embodiments, in order to improve the adhesion between the adhesive layer 130, the conductive layer 121 and the carrier layer 122, a lamination process may be further used.

[0025] In some embodiments, the thickness 130T of the adhesive layer 130 is between 1 nm and 50 μm, but the present invention is not limited thereto, and the thickness 130T of the adhesive layer 130 can be determined according to actual design requirements.

[0026] 1C , the adhesive layer 130 at the bottom of the through hole 111 is removed to expose the conductive layer 121 underneath, wherein the removal method includes a dry process such as laser, plasma, or a wet process such as de-smear, and the present invention is not limited thereto.

[0027] Referring to FIG. 1D , an electroplating process is performed to form vertical conductive connectors 140 in the plurality of through holes 111. The electroplating process may be performed by connecting electricity through the conductive layer 121, so that the conductive material (such as copper) is formed from the bottom of the through hole 111 upward until it fills the through hole 111 and is higher than the top surface (such as the upper surface 110a) of the substrate 110. That is, the top surface 140a of the formed vertical conductive connector 140 is higher than the top surface (such as the upper surface 110a) of the substrate 110. In this way, in addition to ensuring that the conductive material completely fills the internal space of the through hole 111, it can also ensure that the circuits subsequently formed on the substrate 110 will not be recessed into the substrate 110, thereby enabling the product to have better electrical performance, but the present invention is not limited thereto. Here, the conductive material includes copper or the like.

[0028] In this embodiment, since no seed layer is formed in the through hole 111 , the vertical conductive connection 140 is physically connected to the substrate 110 . In other words, the vertical conductive connection 140 can directly contact the substrate 110 .

[0029] In some embodiments, when forming a vertical conductive connector through a seed layer, a larger thickness (e.g., a thickness greater than 60 microns (µm)) is required to fully plate the metal in the through hole. In this case, it is difficult for the substrate wiring to achieve a line width / line spacing (L / S) such as a fine line less than 16 / 16 microns. However, the method of this embodiment can overcome the aforementioned problem and make it easier to meet the requirements of fine lines.

[0030] 1E , after the electroplating process is performed, the carrier layer 122 is removed from the conductive layer 121 , for example, through the release layer to expose the bottom surface of the conductive layer 121 , but the present invention is not limited thereto, and the carrier layer 122 may also be removed by other suitable methods.

[0031] 1F , the conductive layer 121 is removed by stripping or reduction using a suitable etching solution to expose the bottom surface 140 b of the vertical conductive connection 140 , wherein the bottom surface 140 b of the vertical conductive connection 140 may be coplanar with the bottom surface 130 b of the adhesive layer 130 .

[0032] 1G , the adhesive layer 130 is dipped in a suitable alkaline solution to remove the adhesive layer 130 , so that the vertical conductive connection member 140 is protruded from the lower surface 110 b of the substrate 110 , but the present invention is not limited thereto, and the adhesive layer 130 may also be removed by other suitable methods.

[0033] Please refer to FIG. 1H , and perform an annealing process so that a plurality of first atoms (not shown) in the vertical conductive connection 140 diffuse toward the substrate 110 to form a bonding structure 141. Further, in this embodiment, by introducing an annealing process, the first atoms of the vertical conductive connection 140 undergo an atomic diffusion phenomenon toward the substrate 110, that is, as shown in the enlarged portion of FIG. 1H , the first atoms move from the interface between the vertical conductive connection 140 and the substrate 110 to the gap inside the substrate 110, and the first atoms are arranged between the gaps to form a bonding structure 141 extending into the substrate 110. Under this mechanism, the bonding structure 141 may have an irregular boundary, and a plurality of first atoms are embedded in the gaps of the material of the substrate 110 to enhance the adhesion strength between the vertical conductive connection 140 and the adjacent substrate 110, thereby effectively improving product reliability. Here, the first atoms include copper atoms or other metal atoms.

[0034] In some embodiments, the maximum extension distance of the bonding structure 141 is between 0.1 nm and 100 nm, but the present invention is not limited thereto. The extension distance of the bonding structure 141 depends on the process temperature and execution time of the annealing process.

[0035] In some embodiments, the annealing process is performed in nitrogen (N2) or other suitable ovens, and the execution time is more than 30 minutes (for example, between 30 minutes and 90 minutes), and the process temperature is more than 300°C (for example, between 300°C minutes and 600°C minutes) to ensure that the first atoms diffuse out, but the present invention is not limited to this, and the parameter setting of the annealing process can be determined according to actual design requirements.

[0036] 1I, a planarization process such as chemical mechanical polishing (CMP) or the like is performed to remove the redundant vertical conductive connections 140 on the upper surface 110a and the lower surface 110b of the substrate 110. It should be noted that in an embodiment not shown, the planarization process may also be performed before the annealing process.

[0037] 1J , a seed layer 150 is formed on the substrate 110. For example, the seed layer 150 can completely cover and directly contact the upper surface 110a and the lower surface 110b of the substrate 110 and the top surface 140a and the bottom surface 140b of the vertical conductive connection 140, wherein the seed layer 150 includes a sputtered titanium / copper layer or a copper layer formed by an electro-less plating process, but the present invention is not limited thereto.

[0038] 1K, a circuit layer 160 is formed on the seed layer 150, wherein the circuit layer 160 can be formed by a lithography process, such as a semi-additive process (SAP) or a patterned electroplating method, to form a circuit pattern having a plurality of openings, and the plurality of openings expose the seed layer 150. For example, the circuit layer 160 is located on the seed layer 150 on both sides of the substrate 110. Here, the material of the circuit layer 160 includes copper or the like.

[0039] 1L , the portion of the seed layer 150 exposed by the plurality of openings of the circuit layer 160 is removed by a stripping process (eg, using an appropriate etching solution) to complete circuit fabrication.

[0040] After the above process, the substrate structure 100 of the present embodiment can be substantially completed. In the present embodiment, the substrate structure 100 includes a base 110 and a vertical conductive connection member 140 penetrating the base 110, wherein the vertical conductive connection member 140 has a bonding structure 141 (formed by an annealing process) extending toward the base 110, so that the adhesion strength between the vertical conductive connection member 140 and the adjacent base 110 can be enhanced, thereby effectively improving the product reliability.

[0041] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above embodiments, and the following embodiments will not be repeated.

[0042] 2A to 2L are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to another embodiment of the present invention.

[0043] Please refer to FIG. 2A , which is similar to FIG. 1A , except that after forming the through hole 111, a buffer layer 270 is further formed on the substrate 110, wherein the buffer layer 270 is formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0044] In some embodiments, the material of the buffer layer 270 includes metal oxide (such as titanium oxide, zinc oxide, aluminum oxide, silicon oxide or the like), metal (such as titanium) or a combination thereof, but the present invention is not limited thereto.

[0045] In some embodiments, the buffer layer 270 may surround the outer surface of the substrate 110 so that no surface of the substrate 110 is exposed, but the present invention is not limited thereto.

[0046] In an embodiment not shown, the buffer layer may be a multi-layer structure, for example, a titanium oxide layer may be formed first and then a titanium layer may be formed, but the present invention is not limited thereto.

[0047] Please refer to Figures 2B and 2C. Similar to Figures 1B and 1C, the substrate 110 is bonded to the conductive layer 121 through the adhesive layer 130, and the adhesive layer 130 at the bottom of the through hole 111 is removed to expose the conductive layer 121 underneath. In this embodiment, the buffer layer 270 is in direct contact with the adhesive layer 130 to separate the substrate 110 from the adhesive layer 130.

[0048] Please refer to Figure 2D. Similar to Figure 1D, an electroplating process is performed to form vertical conductive connectors 140 in multiple through holes 111, respectively, wherein a buffer layer 270 is arranged between the substrate 110 and the vertical conductive connector 140 (such as in a direction perpendicular to the thickness), and the buffer layer 270 is in direct contact with the vertical conductive connector 140, so that the vertical conductive connector 140 is not physically connected to the substrate 110.

[0049] Please refer to Figures 2E, 2F and 2G. Similar to Figures 1E, 1F and 1G, after the electroplating process is performed, the carrier layer 122, the conductive layer 121 and the adhesive layer 130 are removed in sequence. After the adhesive layer 130 is removed, the vertical conductive connecting member 140 will protrude from the bottom surface of the buffer layer 270.

[0050] Referring to FIG. 2H , similar to FIG. 1H , an annealing process is performed to allow a plurality of first atoms in the vertical conductive connection member 140 to diffuse toward the substrate 110 to form a bonding structure 141. Further, the difference between this embodiment and the embodiment of FIG. 1H is that since the buffer layer 270 is located between the vertical conductive connection member 140 and the substrate 110, after the annealing process is performed, the bonding structure 141 extends into the buffer layer 270 instead of the substrate 110, so that the plurality of first atoms are inserted into the gaps of the material of the buffer layer 270. In addition, after the annealing process is performed, a plurality of second atoms (not shown) in the buffer layer 270 diffuse toward the substrate 110 to form another bonding structure 271, so that the plurality of second atoms are inserted into the gaps of the material of the substrate 110. In this way, the adhesion strength between the corresponding components can be further enhanced through the plurality of bonding structures 141 and 271. Here, the second atoms include titanium or aluminum, but the present invention is not limited thereto.

[0051] For example, in this embodiment, by introducing an annealing process, the first atoms in the vertical conductive connector 140 and the second atoms in the buffer layer 270 both undergo atomic diffusion toward the substrate 110. That is, as shown in the enlarged portion of FIG. 2H , the first atoms move from the interface between the vertical conductive connector 140 and the buffer layer 270 to the gap inside the buffer layer 270, and the second atoms move from the interface between the buffer layer 270 and the substrate 110 to the gap inside the substrate 110. Therefore, both the bonding structures 141 and 271 have irregular boundaries.

[0052] In some embodiments, the annealing process is performed in a nitrogen or other suitable oven, the execution time is more than 30 minutes (for example, between 30 minutes and 90 minutes), and the process temperature is more than 300° C. (for example, between 300° C. minutes and 600° C. minutes) to ensure that the first atoms and the second atoms diffuse out.

[0053] In some embodiments, the maximum extension distance of the bonding structure 271 is between 0.1 nm and 100 nm, but the present invention is not limited thereto. The extension distance of the bonding structure 271 depends on the process temperature and execution time of the annealing process.

[0054] 2I , similar to FIG. 1I , a planarization process is performed to remove excess vertical conductive connections 140 on the buffer layer 270 so that a top surface 270 a of the buffer layer 270 is coplanar with a top surface 140 a of the vertical conductive connection 140 , and a bottom surface 270 b of the buffer layer 270 is coplanar with a bottom surface 140 b of the vertical conductive connection 140 .

[0055] Referring to FIG. 2J, FIG. 2K and FIG. 2L, similar to FIG. 1J, FIG. 1K and FIG. 1L, a seed layer 150 and a circuit layer 160 are sequentially stacked on the substrate 110, and the portion of the seed layer 150 exposed by the plurality of openings of the circuit layer 160 is removed by a stripping process (such as using an appropriate etching solution) to complete the circuit manufacturing. After the above process, the manufacturing of the substrate structure 200 of this embodiment can be substantially completed.

[0056] 3A to 3E are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. Specifically, FIG3A to FIG3E illustrate the structure manufacturing following the steps of FIG1I.

[0057] 3A , after the annealing process is performed, an insulating layer 380 is further formed on the substrate 110, wherein the insulating layer 380 may be formed by a lamination process using an ABF (Ajinomoto Build-up Film) material or a slit coating process using a photo imageable dielectric (PID) material, but the present invention is not limited thereto.

[0058] For example, the insulating layer 380 may completely cover and directly contact the upper surface 110a and the lower surface 110b of the substrate 110 and the top surface 140a and the bottom surface 140b of the vertical conductive connection member 140, but the present invention is not limited thereto.

[0059] Referring to FIG. 3B to FIG. 3E, first, as shown in FIG. 3B, multiple openings 380a are formed in the insulating layer 380 on both sides of the substrate 110 to expose the vertical conductive connection 140. Then, as shown in FIG. 3C to FIG. 3E, similar to FIG. 1J to FIG. 1L, a seed layer 150 and a circuit layer 160 are stacked in sequence on the substrate 110, and the portion of the seed layer 150 exposed by the multiple openings of the circuit layer 160 is removed by stripping to complete the circuit manufacturing. After the above process, the manufacturing of the substrate structure 300 of this embodiment can be substantially completed.

[0060] In some embodiments, the bottom of the opening of the insulating layer 380 may be further cleaned, such as by a desmear process or a plasma process, so that the vertical conductive connection 140 is more surely exposed, but the present invention is not limited thereto.

[0061] In this embodiment, the circuit layer 160 formed on the insulating layer 380 can penetrate the insulating layer 380 and directly contact and electrically connect the vertical conductive connecting member 140, that is, the insulating layer 380 is located between the circuit layer 160 and the substrate 110, and the circuit layer 160 is only in direct contact with the vertical conductive connecting member 140, so that the circuit layer 160 is not in direct contact with the substrate 110.

[0062] 4A to 4E are partial cross-sectional schematic diagrams of a partial manufacturing method of a substrate structure according to another embodiment of the present invention. Specifically, FIG. 4A to FIG. 4E illustrate the structure manufacturing following the steps of FIG. 2I.

[0063] 4A and 4B , similar to FIG. 3A and FIG. 3B , after performing the annealing process, an insulating layer 380 is formed on the substrate 110 , and then, a plurality of openings 380 a are formed in the insulating layer 380 to expose the vertical conductive connectors 140 , wherein the insulating layer 380 can be in direct contact with the buffer layer 270 .

[0064] Referring to FIG. 4C to FIG. 4E , similar to FIG. 3C to FIG. 3E , a seed layer 150 and a circuit layer 160 are sequentially stacked on the substrate 110, and the portion of the seed layer 150 exposed by the plurality of openings of the circuit layer 160 is removed by a stripping process (such as using an appropriate etching solution) to complete the circuit manufacturing. After the above process, the manufacturing of the substrate structure 400 of this embodiment can be substantially completed.

[0065] In summary, the present invention introduces an annealing process to diffuse the atoms in the vertical conductive connector to form a bonding structure extending toward the substrate, thereby enhancing the adhesion strength between the vertical conductive connector and the adjacent components, thereby effectively improving product reliability.

[0066] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the definition of the attached patent application scope.

[0067] 100, 200, 300, 400: substrate structure 110: Base 110a: upper surface 110b: Lower surface 110T, 121T, 122T, 130T: thickness 111:Through hole 111D: Aperture 121: Conductive layer 122: carrier layer 130: Adhesive layer 140a, 270a: top surface 130b, 140b, 270b: bottom surface 140: Vertical conductive connector 141, 271: Bond structure 150: Seed layer 160: Circuit layer 270: Buffer layer 380: Insulation layer 380a: Opening

Claims

1. A method for manufacturing a substrate structure, comprising: A substrate having multiple vias, a conductive layer, and a carrier layer are provided, wherein the thickness of the conductive layer is between 2 micrometers and 100 micrometers, and the thickness of the carrier layer is between 1 micrometer and 25 micrometers; the conductive layer is bonded to the carrier layer, wherein the material of the carrier layer includes copper; the substrate is bonded to the conductive layer; an electroplating process is performed to form vertical conductive connectors in the multiple vias; and an annealing process is performed to cause multiple first atoms in the vertical conductive connectors to diffuse toward the substrate to form a bonding structure, wherein the bonding structure extends into the substrate.

2. The method for manufacturing a substrate structure as described in claim 1, wherein the annealing process takes 30 minutes or more to complete.

3. The method for manufacturing the substrate structure as claimed in claim 1, wherein the process temperature of the annealing process is 300°C or higher.

4. The method for manufacturing a substrate structure as claimed in claim 1, wherein the step of forming a seed layer is not included before forming the vertical conductive connector.

5. A method for manufacturing a substrate structure as claimed in claim 4, wherein the plurality of first atoms are inserted into gaps in the material of the substrate.

6. The method for manufacturing a substrate structure as claimed in claim 1, wherein after performing the annealing process, it further includes: An insulating layer is formed on the substrate; A circuit layer is formed on the insulating layer, wherein the circuit layer penetrates the insulating layer and is in direct contact with and electrically connected to the vertical conductive connector.

Images