Methods for manufacturing semiconductor wafers and semiconductor wafers

Abstract

The present invention relates to a method for manufacturing a semiconductor wafer, wherein a coated wafer (1) is placed on and secured to a carrier wafer (2), the initial thickness of the coated wafer (1) is reduced to a first processing thickness by a first mechanical removal process, the thickness of the coated wafer (1) on the entire bottom surface of its contact with the carrier wafer (2) after the first removal process is obtained in the form of a thickness map, and the thickness of the coated wafer (1) is further reduced by means of an ion beam and / or a laser beam in a second removal process, wherein the area to be removed and the proportion to be removed of the thickness of the coated wafer (1) are selected according to the created thickness map.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor wafer and a semiconductor wafer. Prior Art

[0002] US 2023 / 0039295 A1 discloses a method for manufacturing an image sensor, in which an acceptor substrate and a donor substrate are connected to each other. The donor substrate is partially separated to transfer a semiconductor layer from the donor substrate to the acceptor substrate. Subsequently, the transferred single-crystalline semiconductor layer is subjected to finishing, wherein the finishing includes thinning the transferred single-crystalline semiconductor layer by sacrificial oxidation followed by chemical etching, and planarizing the transferred single-crystalline semiconductor layer by at least one rapid annealing step.

[0003] A method for processing and manufacturing semiconductor components is known from CN 115697016 A. In this method, lithium niobate is bonded to a silicon substrate at low temperatures and subsequently subjected to a thinning and polishing process.

[0004] Furthermore, a semiconductor substrate is known from US 2014 / 0367691 A1. Summary of the Invention

[0005] The object of the present invention is to provide a solution by means of which the generation of damaged or uneven single-crystalline thin layers on amorphous material during the production of semiconductor wafers can be avoided.

[0006] According to the present invention, this object is achieved by the subject matter of the independent claims. Other possible embodiments of the present invention are given in the dependent claims, the description, and the drawings. Within the scope of the description, the features, advantages, and possible embodiments stated for one of the subject matter of the independent claims may be regarded as at least analogously the features, advantages, and possible embodiments of the corresponding subject matter of the other independent claims, as well as any possible combination of the subject matter of the independent claim (if necessary in combination with one or more dependent claims).

[0007] The present invention relates to a method for producing semiconductor wafers. In microelectronics, photovoltaics, and microsystems technology, round or square disks are called wafers. Wafers are made from single-crystalline or polycrystalline semiconductor blanks (so-called ingots) and are generally used as substrates and, therefore, as bases for electronic components (especially integrated circuits and wafers containing them), micromechanical components, or optoelectronic coatings.

[0008] The method for manufacturing semiconductor wafers includes the following sequentially performed method steps a) to d). In the method, in the first method step a), a coated wafer is placed on a carrier wafer and fastened to the carrier wafer. In the second method step b), the initial thickness of the coated wafer is reduced to a first working thickness by a mechanical first removal process. A mechanical method is used for material removal during the first mechanical removal process. Within the scope of this first mechanical removal process, the thickness of the coated wafer can be reduced by grinding and / or polishing. In the third method step c), the thickness of the coated wafer obtained after the first removal process is recorded in the form of a thickness map over its entire bottom surface resting against the carrier wafer. The thickness of the coated wafer is thus examined over the entire bottom surface. The thickness map thus stores the thickness of the bottom surface of the coated wafer at a specific point. In particular, the thickness is perpendicular to the bottom surface.

[0009] The method further provides that, in a fourth method step d), the thickness of the coated wafer is further reduced in a second removal process using an ion beam and / or a laser beam, wherein the areas and proportions of the coated wafer thickness to be removed are selected based on a generated thickness map. This means that within the scope of the second removal process, the proportions of the coated wafer thickness to be reduced are selected based on the generated thickness map and, therefore, the thickness distribution of the coated wafer on its bottom surface. This allows for a targeted and locally defined reduction in the thickness of the coated wafer within the scope of the second removal process, thereby achieving particularly good uniformity of the thickness of the coated wafer across its bottom surface. Thus, in the method, the thickness of the coated wafer is roughly reduced using a first mechanical removal process, and then the thickness is finely adjusted across the entire bottom surface of the coated wafer in a second removal process. This ensures that the risk of damage to the coated wafer, in particular to thin, single-crystalline layers, is kept particularly low.

[0010] In other words, the method provides two wafers (here, a coating wafer and a carrier wafer, particularly of identical size). The coating wafer contains only the material that is to produce a crystalline thin film in the semiconductor wafer. The carrier wafer serves as a carrier for the coating wafer and may have an amorphous dielectric (e.g., silicon dioxide) as a top layer. Alternatively, the coating wafer may be coated with an amorphous dielectric and applied to the carrier wafer using this coating. In this method, the coating wafer and the carrier wafer are connected. Within the scope of a first removal process, the coating wafer is thinned using mechanical thinning techniques to a thickness greater than the final desired thin layer across its entire bottom surface. The thickness of the remaining coating wafer material is plotted across the entire coating wafer. Within the scope of a second removal process, the carrier wafer, which has the remaining coating wafer material on its top side, is selectively etched. This method allows the thickness of the coating wafer on the carrier wafer to be precisely set with minimal damage to the thin layer to be produced. The thickness of the coating wafer can be removed particularly precisely using an ion beam or a laser beam.

[0011] In one possible refinement of the present invention, after the second removal process, the thickness of the coated wafer on the bottom surface is determined in the form of an additional thickness map, and the coated wafer is subjected to or not subjected to the additional second removal process based on this additional thickness map. In other words, during the second removal process, the creation of the thickness map and the reduction of the coated wafer thickness are repeated alternately until the thickness of the coated wafer across its entire bottom surface is within predetermined tolerance limits for the thickness of the coated wafer. Thus, during the second removal process, the thickness of the coated wafer is repeatedly checked and reduced. This allows the thickness of the coated wafer on the carrier wafer to be set particularly accurately and reproducibly. This allows the risk of damage to be kept particularly low when setting the thickness of the coated wafer. Furthermore, the actual thickness of the coated wafer across its entire bottom surface can be adjusted to be particularly close to the predetermined target thickness of the coated wafer.

[0012] Another possible embodiment of the present invention provides for polishing the outer surface of the coated wafer, opposite the bottom surface, after the final second removal process. Polishing the coated wafer reduces thickness variations on the bottom surface. This means that the surface of the coated wafer is flattened. Consequently, thickness variations between different areas of the coated wafer are reduced. This subsequent polishing process helps smooth and thus even out the topmost layer of the coated wafer, which has been eroded by the second removal process (e.g., using an ion beam or laser beam). This also removes very fine debris in the top interface layer generated by the ion beam and / or laser beam process.

[0013] Another possible embodiment of the present invention provides for polishing the outer surface of the coated wafer, opposite the bottom surface, after the first removal process and before the second removal process. In other words, the polishing process can be performed already after the first removal process. This allows the surface of the coated wafer to be flattened after the first removal process, which can in particular be performed as a mechanical removal process (e.g., grinding or polishing).

[0014] In this regard, it is particularly useful to polish the outer surface using chemical mechanical polishing. Chemical mechanical polishing (also known as chemical mechanical planarization) is a polishing process performed during wafer processing to uniformly ablate thin layers. To produce microelectronic circuits, thin layers are applied to very flat and smooth wafers and structured in multiple steps. After just a few layers, significant inhomogeneities can occur, which can lead to tearing of higher layers and thus make multilayer systems difficult to implement. This problem becomes more severe with increasingly complex circuits, as multiple metallization planes are required for wiring components. Chemical mechanical polishing compensates for these inhomogeneities in the coated wafer. This allows for particularly precise application of additional layers to the coated wafer, minimizing the risk of tearing of higher layers.

[0015] Another advantage of chemical mechanical polishing is that the waveguides subsequently introduced into the coated wafer have a very smooth top surface. The top surface refers to the surface facing away from the carrier wafer. The smoothest possible top or side surface reduces the losses incurred during light guidance in the waveguide, thus positively impacting waveguide efficiency.

[0016] In another embodiment of the invention, it is provided that the thickness map is acquired with the aid of ellipsometry or reflection spectroscopy. Spectroscopic ellipsometry is an optical research method for measuring the thickness of thin layers. In ellipsometry, the change in the polarization state of light during reflection or transmission at a sample is determined. Reflection spectroscopy is understood to be the study of the spectral composition of radiation reflected from a surface in relation to its angle-dependent intensity and the composition of the incident primary radiation. Producing a thickness map with the aid of ellipsometry or reflection spectroscopy allows for particularly precise determination of the thickness of a coated wafer over the entire area of ​​its bottom surface.

[0017] In another possible embodiment of the present invention, the average thickness of the coated wafer on its bottom surface is set to a maximum of 3000 nanometers, preferably a maximum of 1200 nanometers, and particularly a maximum of 600 nanometers by the second removal process. This means that the average thickness of the coated wafer is reduced in the second removal process such that the average thickness of the coated wafer in the semiconductor wafer is a maximum of 3000 nanometers, preferably a maximum of 1200 nanometers, and particularly preferably a maximum of 600 nanometers. Thus, the coated wafer can be used to form relatively thick layers and particularly thin layers on the carrier wafer.

[0018] Another possible embodiment of the present invention provides for applying a lithium niobate wafer as a coating wafer to the silicon dioxide layer of a silicon carrier wafer serving as a carrier wafer. The lithium niobate of the lithium niobate wafer thus forms a crystalline thin film on the carrier wafer. A silicon carrier wafer with a silicon dioxide layer is used as the carrier wafer. Lithium niobate has a wide transparency range, high electro-optical coefficients and nonlinear optical coefficients, a very high electromechanical coupling coefficient, and high chemical and mechanical stability.

[0019] Another possible design of the present invention provides for reducing the thickness of the coated wafer in the second removal process by means of ion beam etching using a focused ion beam (also known as ion thinning or focused ion beam electric etching (FIBE)), grayscale lithography combined with ion beam etching (also known as grayscale lithography combined with ion beam etching (IBE)), or laser ablation. In unfocused ion beam etching (also known as ion beam etching (IBE)), a broad beam of positively charged ions is directed toward the substrate, and material is removed from the substrate surface by ion bombardment. Laser ablation (also known as laser evaporation) is ablation performed using pulsed laser radiation. The high power density of the laser radiation used here causes rapid heating and plasma formation on the surface. This exceeding of the plasma threshold is used to distinguish it from laser desorption, which does not generate plasma. Grayscale lithography is developed to achieve the desired thickness topography. The concept of lithography can be employed here, which involves the creation of binary structures consisting of removed and unchanged areas. The surface topography is controlled by varying the dose of ionizing radiation. Variable-dose ion irradiation can be achieved using multiple irradiation steps or grayscale masks. In multiple irradiation steps, the mask is shifted stepwise depending on the desired structure, or multiple binary masks with different shades are used. Each irradiation step can have a different irradiation dose. Grayscale masks have regions of varying transmittance. These transmittances are achieved using a layer of partially absorbing material whose thickness varies between complete absorption and transmission of the ionizing radiation.

[0020] In a specific embodiment, photoresist is applied to the top of a wafer and exposed to varying degrees in different areas. After development, the remaining photoresist thickness varies depending on the exposure. The wafer is then subjected to an IBE process, which removes the photoresist layer. Thinner portions of the photoresist act as a protective layer for a shorter period of time than thicker photoresist layers. This means that wafer layers beneath thinner photoresist are more susceptible to the ion beam than wafer layers beneath thicker photoresist. If the wafer is processed in the IBE process for a period of time until all the photoresist is removed from the wafer, the photoresist thickness profile is transferred to the thickness of the wafer layers beneath the photoresist.

[0021] The described method allows for a particularly precise separation of the respective regions of reduced thickness of the coated wafer within the scope of the second removal process and a particularly precise reduction of the thickness in the respective separated regions.

[0022] In another possible embodiment of the present invention, the coated wafer is fastened to the carrier wafer using metal bonding, Van der Waals bonding, polymer bonding, or anodic bonding. The bonding techniques described above allow the coated wafer to be held particularly securely on the carrier wafer.

[0023] The invention also relates to a semiconductor wafer produced in a method as has been described in conjunction with the method according to the invention for producing a semiconductor wafer.

[0024] Further features of the invention can be derived from the following description of the drawings and with the aid of the accompanying drawings. The features and feature combinations mentioned above in the description and the features and feature combinations shown individually below in the description of the drawings and / or in the accompanying drawings can be used not only in the respectively indicated combination but also in other combinations or alone without departing from the scope of the invention. Simple diagram description

[0025] In the accompanying drawings (not to scale):

[0026] FIG1 shows a simplified diagram of a method for manufacturing a semiconductor wafer; and

[0027] 2a-2b show schematic side views of a semiconductor wafer at different stages of the manufacturing process. Implementation Method

[0028] FIG1 shows a simplified diagram of a method for producing semiconductor wafers. The method comprises a plurality of sequentially performed method steps a) to e). In the first method step a), a coated wafer 1, in this case a lithium niobate wafer (LiNbO3), is placed on a carrier wafer 2 and fastened to the carrier wafer 2. Carrier wafer 2 is in this case a silicon carrier wafer 4 (Si) coated with a silicon dioxide layer 3 (SiO2). The lithium niobate wafer is applied to the silicon dioxide layer 3 of the silicon carrier wafer 4. The lithium niobate wafer is fastened to the carrier wafer 2 using metallic bonding, Van der Waals bonding, polymer bonding, or anodic bonding.

[0029] In the second method step b), the initial thickness of the lithium niobate wafer is reduced to a first processing thickness by a mechanical first removal process. The thickness of the lithium niobate wafer can be reduced by a conventional first removal process (including grinding and / or polishing).

[0030] In the third method step c) of the method, the thickness of the lithium niobate wafer, obtained after the first removal process, is determined over its entire bottom surface resting against the carrier wafer 2 in the form of a thickness map. The thickness map is determined using ellipsometry or reflectance spectroscopy. After the thickness map has been determined, in the fourth method step d) of the method, the thickness of the lithium niobate wafer is further reduced in a second removal process using an ion beam and / or a laser beam. The areas and proportions of the lithium niobate wafer thickness to be removed are selected based on the thickness map generated. Within the scope of the second removal process, the thickness of the lithium niobate wafer is reduced using ion beam etching using a focused ion beam and / or grayscale lithography or laser ablation in combination with ion beam etching.

[0031] After the second removal process, the thickness of the coated wafer 1 on the bottom surface can be checked by creating a further thickness map. This thickness map can also be obtained using ellipsometry or reflectance spectroscopy. Therefore, if necessary, the third method step c) is repeated, in which the thickness of the lithium niobate wafer is determined in the form of a further thickness map. If the obtained further thickness map determines that the thickness of the lithium niobate wafer across the entire bottom surface is within predetermined tolerance limits, no further second removal process is performed. However, if it is determined that the thickness of the lithium niobate wafer in at least a certain region of the bottom surface exceeds predetermined tolerance limits, the lithium niobate wafer is subjected to a further second removal process. After the further second removal process, the thickness of the lithium niobate wafer can be checked by creating a further thickness map. This thickness check and the execution of the corresponding second removal process can be repeated, in particular, until it is determined that the thickness of the lithium niobate wafer across its entire bottom surface is within predetermined tolerance limits. After the final second removal process, the fifth method step e) can be performed, in which the outer surface opposite the bottom surface of the lithium niobate wafer is polished. Here, the outer surface of the lithium niobate wafer is flattened by means of chemical mechanical polishing.

[0032] In particular, it is proposed within the scope of the method that the average thickness of the lithium niobate wafer over its entire bottom surface is set by means of the at least one second removal process to a maximum of 3000 nm, preferably a maximum of 1200 nm, in particular a maximum of 600 nm.

[0033] Figure 2a shows a semiconductor wafer in its unprocessed state as a coated wafer 1. Here, the coated wafer 1 is merely fastened to the carrier wafer 2, and its thickness has not been reduced. Figure 2b shows a finished semiconductor wafer. Here, a waveguide 5 is shown, arranged on the coated wafer 1. This waveguide is created on the surface of the semiconductor wafer by subsequent etching, machining, or mechanical removal of the surrounding surface. The waveguide 5 is an inhomogeneous medium that, due to its physical properties, bundles waves so that they are guided as traveling waves in the waveguide. The waveguide 5 has a top surface 6 and laterally inclined side surfaces 7 extending from the top surface 6. The top surface 6 and side surfaces 7 are designed to be as smooth as possible, thereby reducing losses incurred during light guidance in the waveguide 5 and thus positively impacting waveguide efficiency.

[0034] By means of correspondingly measured and spatially selective etching of lithium niobate wafers, the thickness of thin semiconductor wafer layers can be reduced with nanometer precision without damaging the thin film (here, lithium niobate).

[0035] The method produces a semiconductor wafer having a 400-nanometer-thick lithium niobate layer on a five-micrometer-thick silicon dioxide layer on a 500-micrometer-thick silicon carrier wafer 4. The lithium niobate wafer is fastened to the carrier wafer 2 by melt bonding, whereby it is held there by van der Waals forces. The bond between the lithium niobate wafer and the carrier wafer 2 can be annealed at elevated temperatures to increase the strength of the bond. Subsequently, the thickness of the topmost layer of the semiconductor wafer, and therefore the lithium niobate wafer, is reduced by mechanical grinding. The roughness produced by mechanical grinding can be smoothed by final polishing using chemical mechanical polishing. This method can reduce the remaining lithium niobate layer on the lithium niobate wafer to 3000 nanometers, preferably to a maximum of 1200 nanometers, and in particular to a maximum of 600 nanometers, across the entire bottom surface. The thickness variation across the entire bottom surface of the lithium niobate wafer can be between five and ten micrometers, and thus, for a lithium niobate wafer thickness of 600 nanometers, the thickness variation can be between 5.6 micrometers and 10.6 micrometers. The resulting thickness topography of the lithium niobate wafer is detected by reflectance spectroscopy with a spatial resolution in the millimeter range, with the resolution of the layer thickness measurement being in the nanometer range. Based on this thickness map, the thickness of the lithium niobate layer on the carrier wafer 2 is planarized and homogenized by placing the held wafers in an apparatus for ion beam etching using a focused ion beam and reducing the thickness of the lithium niobate wafer using the focused ion beam. After the second removal process, the thickness of the lithium niobate wafer can be re-determined, and based on the results of the thickness measurement, a second iteration of ion beam etching using the focused ion beam is performed. The iterations of measuring the thickness of the lithium niobate wafer and ion beam etching are repeated until the predetermined specifications of the lithium niobate thin film on the semiconductor wafer and the carrier wafer 2 are achieved. As an alternative to a mechanical first removal process, the initial thickness of the lithium niobate wafer can be reduced by means of a so-called crystal ion slicing process.

[0036] The advantage of the described method is that the thin crystalline layer of lithium niobate is of particularly high quality because it is impermeable to ions. Furthermore, within the scope of the method, the thickness of the thin layer formed from lithium niobate can be controlled in the nanometer range. Furthermore, the lithium niobate layer can be designed to be particularly uniform in thickness. Compared to the described method, conventional methods for reducing the thickness of coated wafers 1 to a predetermined target thickness without further post-processing, such as crystalline ion slicing, are technically inferior methods based on implanted ions, the material itself, voltage increases, and temperature.

[0037] In general, the present invention demonstrates a method by which thin layers can be produced on insulators by selective etching. 1: Coated wafer 2: Carrier wafer 3: Silicon dioxide layer 4: Silicon carrier wafer 5: Waveguide 6: Top surface 7: Side surface a) to d): Method steps

Claims

1. A method for manufacturing semiconductor wafers, wherein: a) Placing the coated wafer (1) onto the carrier wafer (2) and securing it thereto; b) Reducing the initial thickness of the coated wafer (1) to a first processing thickness by a first mechanical removal process; c) Obtaining, in the form of a thickness map, the thickness of the coated wafer (1) on its entire bottom surface abutting the carrier wafer (2) after the first removal process; and d) Further reducing the thickness of the coated wafer (1) by means of an ion beam and / or a laser beam in a second removal process, wherein the area to be removed and the proportion to be removed of the thickness of the coated wafer (1) are selected according to the created thickness map; wherein, after the second removal process, the thickness of the coated wafer (1) on the bottom surface is obtained in the form of a further thickness map, and the coated wafer (1) is subjected to or not subjected to a further second removal process according to the further thickness map.

2. The method as described in claim 1, characterized in that, e) after performing the final second removal process, the outer surface of the coated wafer (1) opposite to the bottom surface is polished.

3. The method as claimed in claim 1, characterized in that, after performing the first removal process and before performing the second removal process, the outer surface of the coated wafer (1) opposite to the bottom surface is polished.

4. The method as described in claim 2 or 3, characterized in that the outer surface is polished by means of chemical mechanical polishing.

5. The method as described in claim 1, characterized in that the thickness map is obtained by means of ellipsometry or reflectance spectroscopy.

6. The method as claimed in claim 1, characterized in that the average thickness of the coated wafer (1) on its bottom surface is set to a maximum of 3000 nm, more preferably a maximum of 1200 nm, and particularly a maximum of 600 nm by means of the second removal process.

7. The method as claimed in claim 1, characterized in that a lithium niobate wafer is applied as a coating wafer (1) onto a silicon dioxide layer (3) of a silicon carrier wafer (4) which is a carrier wafer (2).

8. The method as claimed in claim 1, characterized in that, in the second removal process, the thickness of the coated wafer (1) is reduced by means of ion beam etching, grayscale lithography combined with ion beam etching, or laser ablation.

9. The method as claimed in claim 1, characterized in that the coated wafer (1) is fastened to the carrier wafer (2) by means of metal bonding technology or van der Waals bonding technology or polymer layer or anodic bonding technology.

10. A semiconductor wafer manufactured in the method described in any one of claims 1 to 9.

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