Integrated circuit device structures and double-sided fabrication techniques

Abstract

Integrated circuit cell architectures comprise both front-side and back-side structures. One or more back-side placements, semiconductor depositions, dielectric depositions, metallizations, film patternings, and wafer-level layer transfer systems are integrated with the front-side processing. This dual-side processing may require exposing the back side of structures fabricated from the front side of the substrate. Main donor substrate assemblies can be built during back-side processing to support and protect the front-side structures. Front-side devices, such as FETs, can be modified and / or interconnected during back-side processing. Back-side devices, such as FETs, can be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Description

Integrated Circuit Device Structures and Double-Sided Fabrication Techniques The present invention relates to integrated circuit device structures and double-sided fabrication techniques. Priority of the patent application scope This application claims priority to U.S. Provisional Application No. 62 / 380,316, filed on August 26, 2016, entitled "Integrated Circuit Device Structures and Fabrication Techniques with a Back-side Reveal of Front-Side Structures". Related applications This application relates to International Patent Applications: US2015 / 052033, filed on October 1, 2015, entitled "Methods of Forming Backside Self-Aligned Vias and Structures Formed Thereby"; US2015 / 052440, filed on September 25, 2015, entitled "Backside Contact Structures and Fabrication For Metal on Both Sides of Devices"; and US2015 / 052288, filed on September 25, 2015, entitled "Backside Fin Recess Control With Multi-H Si Option"; US2016 / 025576, filed on April 1, 2016, entitled "Layer Transferred Ferroelectric Memory Devices"; US2016 / 025579, filed on April 1, 2016, entitled "Semiconductor Diodes Employing Back-Side Semiconductor or Metal"; US2016 / 025593, filed on April 1, 2016, entitled "Transistor structures Including a Deep Via Lined With A Dielectric Material"; The device density in integrated circuits (ICs) has increased in accordance with Moore's law for decades. However, as the lateral dimensions of device structures shrink with each generation of technology, it becomes difficult to further reduce the structure size. Three-dimensional (3D) scaling is currently receiving high attention because the reduction of the z-height (device thickness) provides another way to increase the overall device density and IC performance. 3D scaling can be in the form of, for example, wafer stacking or packaged IC stacking. Known 3D integration technologies are expensive and can only provide incremental improvements in z-height and device density. For example, most of the thickness of a wafer can be inactive substrate material. Stacking of such wafers can employ through-substrate via (TSV) technology as a means to vertically interconnect the wafer stacks. TSVs typically extend through 20 - 50 microns or more of substrate material and thus are typically limited to via diameters in the micron range. Therefore, the TSV density is limited to far lower than the density of most device (e.g., transistor, memory) cells. In addition, the final z-height of a wafer stack employing TSV technology can be hundreds of microns thicker than the actual device layers employed by the stacked devices. 3D scaling can also be in the form of vertically oriented devices, such as where the transistor channel length is substantially perpendicular to the surface of the wafer, rather than parallel to that surface as in the more common horizontally oriented transistors. One problem faced by many vertically oriented device structures is how to fabricate terminals on opposite ends of the device, which can more easily be achieved for horizontally oriented devices. And One or more embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will understand that other configurations and arrangements are possible without departing from the spirit and scope of this description. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein can be employed in a variety of other systems and applications beyond those detailed herein. Reference is made in the following detailed description to the accompanying drawings, which form a part of the present invention and show exemplary embodiments. In addition, it is understood that other embodiments can be utilized and structural and / or logical changes can occur without departing from the scope of the claimed subject matter. It should also be noted that, for example, directions and references such as up, down, top, bottom, etc. can be used only to assist in describing features in the drawings. Therefore, the following detailed description should not be considered limiting, and the scope of the claimed subject matter is defined only by the appended claims and their equivalents. In the following description, many details are set forth. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the embodiments. Reference throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the phrase "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "coupled" and "connected" are used herein to describe a functional or structural relationship between components. However, it should be understood that these terms are not used as synonyms for each other. Rather, in a particular embodiment, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may mean that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact, and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship). As used herein, the terms "above", "below", "between", and "on" mean a relative position of one component or material with respect to other components or materials, where such physical relationships are significant. For example, in the context of materials, a material or a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Additionally, a material or materials disposed between two materials may be in direct contact with both layers or may have one or more intervening layers. In contrast, a first material or material "on" a second material or material is in direct contact with the second material / material. Similar distinctions are made in the context of the assembly of components. As used throughout this specification and the claims, the phrase "at least one of" or "one or more of" joined to a list of terms may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; A, B, and C. This document describes IC device structures and manufacturing techniques for double-sided processing using device structures. In addition to the front-side processing commonly used to manufacture IC device structures, double-sided processing also includes back-side processing of the IC device structures. Double-sided processing may also require non-typical front-side processing to facilitate back-side processing. In some exemplary embodiments, double-sided processing includes the exposure of the back side of the front-side device structure. In some exemplary embodiments, the exposure of the back side of the device structure (also referred to herein as "back-side exposure" or "BSR") requires wafer-level back-side processing, which is used to remove a bulk of the substrate material integrally or locally within a portion of the wafer area, such as a wafer area restricted by an etching mask. Compared to the traditional TSV-type technology that only provides electrical wiring through the thickness of the substrate material, the back-side exposure as described herein is to facilitate the further manufacturing of device structures within the device layer of the IC. This back-side device layer manufacturing can be performed at the density of individual devices (e.g., transistors), even within a sub-region of a single device (e.g., the terminals of a single transistor). In addition, this back-side exposure can be performed to remove only a portion or substantially all of the donor substrate on which the device layer is disposed during front-side device processing. Thus, when the thickness of the semiconductor material of the device structure accessed from the back side can be only a few tens or hundreds of nanometers, micron-depth TSVs can become unnecessary. It is worth noting that although micron-depth conductive TSVs can become unnecessary in the case of more in-depth back-side processing according to the embodiments herein, for example, TSV-type technology can still be used as a means to expose the back side of the device layer. As some exemplary embodiments further described below, the processing of the exposed back side of the device structure may require one or more of the following: removal of sacrificial device structures and / or products of front-side processing; deposition of contact metals, e.g., to increase device wiring density, and / or to allow back-side electron probing and / or to increase device terminal contact areas; deposition of dielectrics, e.g., to increase device isolation, increase gate electrode coupling, and / or reduce parasitic capacitance; deposition of semiconductors, e.g., to reduce parasitic resistance and / or improve crystal quality, bandgap engineering, impart strain in the device semiconductor region, and / or form vertically oriented devices; and / or manufacturing stacked devices that are coupled or in close contact with each other. The back-side exposure techniques described herein result in a mode shift from "bottom-up" device manufacturing to "center-outward" manufacturing, where the "center" is any layer used in front-side manufacturing, exposed from the back side, and reused in back-side manufacturing. As should become clear from the discussion below, the front-side and exposed back-side processing of the device structure can address many of the challenges associated with manufacturing 3D ICs by front-side processing alone. The techniques described herein can be performed with sufficient precision to expose the backside of a device layer at the transistor level (e.g., on the order of 5-10 nanometers). Thus, almost all materials not employed by the integrated device can be discarded from the device. This precision is made possible in part by advancements in the control of the uniformity of the substrate (e.g., wafer) material and the handling of material quality. To date, TSV-style backside electrical connection techniques have not enabled interconnections at specific locations down to the size of the device (e.g., transistor) level because TSV techniques typically involve grinding down the backside of the substrate to a remaining substrate material of at least 20-50 microns to the extent that relatively large (e.g., 2-5 microns) diameter through-holes can be formed through which only conductive vias can be formed. Through the removal of a substantial amount of substrate material, electrical connection at the nanoscale becomes possible. As further described in some of the following exemplary embodiments, permanent bonding (''processing'') of carriers can be employed, where techniques similar to those for penetrating substrate vias utilize relatively more compliant temporary bonds and are not rigid enough to achieve sufficient thickness uniformity control. For example, permanent bonding (such as oxide fusion bonding) can achieve a mechanical stiffness that is advantageous for fabricating the structures further described herein. Oxides can be very hard, have high mechanical strength, and be non-compressible. As further described in some of the following exemplary embodiments, a CMP process that is highly selective for oxide materials can advantageously utilize thickness control sufficient to remove even micron-level material thicknesses in a planar fashion with a reduced material thickness and widely stop at a target thickness within 10 nanometers over the surface area of the substrate. By virtue of this flatness, processing that is typically limited to the front side of the substrate (such as high-resolution lithography) can also be employed on the backside of the substrate, for example, to make electrical contacts having dimensions on the same order as those of those typical front-side metals (e.g., device contacts). This planar processing can be used alone or in conjunction with other substrate removal techniques, including but not limited to nanoscale TSV-type substrate processing, for example, to facilitate the formation of openings of a small enough lateral dimension such that individual devices and / or individual terminals of individual devices can be exposed. FIG. 1 is a flowchart showing a dual-sided device processing method 101 according to some embodiments. The method 101 can be implemented at the wafer level. In some exemplary embodiments, large format substrate (e.g., 300 or 450 mm in diameter) wafers can be processed by the method 101. The method 101 begins with an operation 105 of having a donor substrate that includes a device layer. In certain embodiments, the device layer can include active devices or passive devices. In some embodiments, the device layer is a semiconductor material employed by IC devices. In a specific embodiment, the device layer is a single crystal semiconductor material, which often provides advantages in device performance over thin film semiconductor materials that are polycrystalline or amorphous. For example, in a transistor device such as a field effect transistor (FET), the transistor channel is formed from the semiconductor device layer. As another example, for an optical device such as a photodiode, the drift and / or gain semiconductor is formed from the device layer. The device layer can also be employed in passive structures having IC devices. For example, a positive optical waveguide can employ semiconductor patterned from the device layer. In some embodiments, the donor substrate includes a stack of material layers. Such a material stack can facilitate the subsequent formation of the IC device layer. As used herein, the term “device layer” refers to at least the device layer and lacks other layers of the donor substrate that are not required for IC device functionality and thus are only non-functional “open pins”. For example, the “device layer” can include only one device layer, multiple device layers, or a device layer having one or more intervening layers. In certain embodiments, the “device layer” can also include one or more other non-native material layers, as further explained below, that have been deposited above or below the device layer. In the exemplary embodiment shown in FIG. 1, the method 101 provides a donor substrate that includes a carrier layer separated from the device layer by one or more intermediate material layers. The carrier layer can provide mechanical support during the front side processing of the device layer. The carrier can also provide a foundation for the crystals in the semiconductor device layer. Although intervening layers are not necessary, including one or more such material layers can facilitate the removal of the carrier layer from the device layer or promote the exposure of the back side of the device layer. Method 101 continues at operation 110, where a front-side manufacturing operation is performed on the donor substrate to form a device structure including one or more regions in the device layer. Any suitable front-side processing techniques may be employed at operation 110 to form any suitable IC device and the exemplary embodiments further described elsewhere herein. Such an IC device may include a device (e.g., a transistor) employing the device layer material and one or more layers of interconnect metal formed on the front side of the device layer. At operation 115, the front side of the donor substrate may be bonded to the host substrate to form a device-host assembly. The host substrate may be used to provide front-side mechanical support during back-side processing of the device layer. The host substrate may also include integrated circuits to which the IC devices fabricated on the donor substrate may be interconnected. For such embodiments, the bonding of the host and donor substrates may further mean forming a 3D interconnect structure by hybrid (dielectric / metal) bonding. Any suitable host substrate and wafer-level bonding techniques may be employed at operation 115, and some exemplary embodiments are further described elsewhere herein. Method 101 continues at operation 120 where the back side of the device layer is exposed by removing at least a portion of the carrier layer. In some further embodiments, portions of any intervening layer below the device layer may also be removed during the exposing operation 120. In some other embodiments, front-side materials deposited on the front side of the device layer may also be removed during the exposing operation 120. As described elsewhere herein, in the context of some exemplary embodiments, an intervening layer may contribute to a highly uniform exposure of the back side of the device layer, such as one or more of an etch marker or etch stop employed in a wafer-level back-side exposing process. At operation 125, the surface of the device layer exposed from the back side is processed to form a double-sided device layer. In certain embodiments, the native material of any of the donor substrates, such as regions contacting the device layer, may be replaced with one or more non-native materials at operation 125. For example, a portion of the semiconductor device layer or intervening layer may be replaced with one or more other semiconductor, metal, or dielectric materials. In some other embodiments, non-native materials may be deposited on at least a portion of the back side of the device layer. In some further embodiments, portions of the front-side materials removed during the exposing operation 120 may also be replaced at operation 125. For example, a portion of a semiconductor body, dielectric spacer, gate stack, or contact metal formed during front-side device fabrication may be replaced with one or more other semiconductor, metal, or dielectric materials during back-side stripping / reprocessing of the front-side device. In still other embodiments, a second device layer or metal interposer is bonded to the exposed back side. Method 101 completes the output of the device layer - main substrate assembly at operation 130. The device layer - main substrate assembly can then be further processed. For example, any suitable technique can be used to singulate and package the device layer - main substrate assembly. When the main substrate is fully sacrificial, the packaging of the device layer - main substrate may mean separating the main substrate from the device layer. When the main substrate is not fully sacrificial (e.g., when the main substrate also contains the device layer), the device layer - main substrate assembly output at operation 130 may be fed back as the main substrate input to operation 115 during subsequent iterations of method 101 (dashed lines in FIG. 1). As the main substrate, the device layer - main assembly can be connected to another donor substrate, and method 101 is iterated. Iterations of method 101 can thereby form wafer - level assemblies of any number of double - sided device layers, e.g., each having a thickness of only a few tens or hundreds of nanometers. In some embodiments, and as further described elsewhere herein, one or more devices (e.g., transistors) or device cells (e.g., 1T - 1R memory cells) within the device layer are electrically tested at operation 130, e.g., as a yield control point in the manufacture of wafer - level assemblies of double - sided device layers. In some embodiments further described below, the electrical testing means back - side device probing. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, and 2G are plan views of substrates processed using a double - sided device processing method such as method 101 according to some embodiments. FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are corresponding cross - sectional views of substrates processed using a double - sided device processing method according to some embodiments. As shown in FIGS. 2A and 3A, donor substrate 201 contains a plurality of IC die 211 in any spatial layout on the front - side wafer surface. Front - side processing of IC die 211 can be performed after any technique used to form any device structure. In an exemplary embodiment, die 211 contain one or more semiconductor regions within device layer 215. Die 211 also contain one or more front - side interconnect metal layers (not shown) on the front - side of device layer 215. Intermediate layer 210 separates the back - side of device layer 215 from carrier layer 205. In an exemplary embodiment, intermediate layer 210 is in direct contact with both carrier layer 205 and device layer 215. Alternatively, one or more spacer layers can be provided between intermediate layer 210 and device layer 215 and / or carrier layer 205. Donor substrate 201 can also contain other layers, e.g., above device layer 215 and / or below carrier layer 205. The device layer 215 may include one or more layers of any device material composition known to be suitable for specific IC devices such as, but not limited to, transistors, diodes, and resistors. In some exemplary embodiments, the device layer 215 includes one or more Group-IV (i.e., IUPAC Group 14) semiconductor material layers (e.g., Si, Ge, SiGe), Group-III-V semiconductor material layers (e.g., GaAs, InGaAs, InAs, InP), or Group-III-N semiconductor material layers (e.g., GaN, AlGaN, InGaN). The device layer 215 may also include one or more Group-II-VI semiconductor material layers, or semiconductor transition metal dichalcogenide (TMD or TMDC) layers. In other embodiments, the device layer 215 includes one or more graphene layers, or graphene material layers having semiconductor properties. In still other embodiments, the device layer 215 includes one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of transition metals (e.g., IUPAC Groups 4-10) or post-transition metals (e.g., IUPAC Groups 11-14). In advantageous embodiments, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxide may be a suboxide (A 2 O), monoxide (AO), dioxide (AO 2 ), trioxide (ABO 3 ), and mixtures thereof. In other embodiments, the device layer 215 includes one or more magnetic, ferromagnetic, ferroelectric material layers. For example, the device layer 215 may include one or more layers of any material known to be suitable for tunneling junction devices such as, but not limited to, magnetic tunneling junction (MTJ) devices. In some embodiments, device layer 215 is substantially single crystal. Although single crystal, there may still be a significant number of crystal defects. In other embodiments, device layer 215 is amorphous or polycrystalline (e.g., micro or nanocrystalline). Device layer 215 can be of any thickness (e.g., the z-dimension in FIG. 3A). In some exemplary embodiments, device layer 215 has a thickness greater than the z-thickness of at least some of the semiconductor regions that are used as the functional semiconductor regions of grains 211. The functional regions built on and / or embedded within device layer 215 do not need to extend through the entire thickness of device layer 215. In some embodiments, the semiconductor regions of grains 211 are only disposed within the top-side thickness of device layer 215 defined by dashed line 212 in FIG. 3A. For example, the semiconductor regions of grains 211 may have a z-thickness of less than 200 - 300 nanometers, while the device layer may have a z-thickness of greater than 700 - 1000 nanometers. Thus, a device layer thickness of approximately 600 nanometers can separate the semiconductor regions of grains 211 from the intermediate layer 210. Greater device layer thicknesses are also possible, such as in the range from 1000 nanometers to 10 microns. Carrier layer 205 can have the same material composition as device layer 215, or can have a different material composition from device layer 215. For embodiments where carrier layer 205 and device layer 215 have the same composition, the two layers can be identified by their positions relative to intermediate layer 210. In some embodiments, device layer 215 is a crystalline Group-IV, III-V, or III-N semiconductor, and carrier layer 205 is the same crystalline Group-IV, III-V, or III-N semiconductor as device layer 215. In alternative embodiments, device layer 215 is a crystalline Group-IV, III-V, or III-N semiconductor, and carrier layer 205 is a different crystalline Group-IV, III-V, or III-N semiconductor from device layer 215. In still other embodiments, carrier layer 205 can comprise (or be) the material onto which device layer 215 is transferred or grown. For example, carrier layer 205 can comprise one or more amorphous oxide layers (e.g., glass) or crystalline oxide layers (e.g., sapphire), polymer sheets, or any material that is built or laminated into a structural support known to be suitable as a carrier during IC device processing. Carrier layer 205 can be of any thickness (e.g., the z-dimension in FIG. 3A) as a function of the carrier material properties and the substrate diameter. For example, when carrier layer 205 is a large-format (e.g., 300 - 450 millimeter) semiconductor substrate, the carrier layer thickness can be greater than 700 - 1000 microns. In some embodiments, one or more intermediate layers 210 are disposed between the carrier layer 205 and the device layer 215. In some exemplary embodiments, the intermediate layer 210 is compositionally different from the carrier layer 205 such that it can serve as a marker for detection during subsequent removal of the carrier layer 205. In some such embodiments, the intermediate layer 210 has a composition that etches at a significantly slower rate compared to the carrier layer 205 when exposed to the etchant of the carrier layer 205 (i.e., the intermediate layer 210 serves as an etch stop for the carrier layer etch process). In further embodiments, the intermediate layer 210 has a composition different from the device layer 215. For example, the intermediate layer 210 can be a metal, semiconductor, or dielectric material. In some exemplary embodiments, at least one of the carrier layer 205 and the device layer 215 is a crystalline semiconductor, and the intermediate layer 210 is also a crystalline semiconductor layer. The intermediate layer 210 can further have the same crystallinity and crystal orientation as the carrier layer 205 and / or the device layer 215. Such embodiments can have the advantage of reducing the cost of the donor substrate relative to alternative embodiments where the intermediate layer 210 is formed as an amorphous insulator or the intermediate layer 210 is bonded (e.g., thermocompression bonded) to the device layer 215 and / or the carrier layer 205. For embodiments where the intermediate layer 210 is a semiconductor, one or more of the major semiconductor lattice elements, alloy components, or impurity concentrations can vary at least between the carrier layer 205 and the intermediate layer 210. In some embodiments where at least the carrier layer 205 is a Group-IV semiconductor, the intermediate layer 210 can also be a Group-IV semiconductor but with a different Group-IV element or alloy and / or an impurity concentration doped with an impurity substance different from the impurity substance of the carrier layer 205. For example, the intermediate layer 210 can be a SiGe alloy epitaxially grown on a Si carrier. For such embodiments, a pseudomorphic intermediate layer can be heteroepitaxially grown to any thickness below the critical thickness at which the intermediate layer becomes strained. Alternatively, the intermediate layer 210 can be a relaxed buffer layer having a thickness greater than the critical thickness. In other embodiments, where at least the carrier layer 205 is a Group-III-V semiconductor, the intermediate layer 210 can also be a Group-III-V semiconductor but with a different Group-III-V alloy and / or an impurity concentration doped with an impurity substance different from the impurity substance of the carrier layer 205. For example, the intermediate layer 210 can be an AlGaAs alloy epitaxially grown on a GaAs carrier. In some other embodiments where both the carrier layer 205 and the device layer 215 are crystalline semiconductors, the intermediate layer 210 is also a crystalline semiconductor layer, which can further have the same crystallinity and crystal orientation as the carrier layer 205 and / or the device layer 215. In embodiments where the carrier layer 205 and the intermediate layer 210 are both the same or different primary semiconductor lattice elements, impurity dopants can distinguish the carrier and intermediate layers. For example, both the intermediate layer 210 and the carrier layer 205 can be silicon crystals, where the intermediate layer 210 lacks impurities present in the carrier layer 205, or is doped with impurities lacking in the carrier layer 205, or is doped to a different degree than the impurities present in the carrier layer 205. The impurity differentiation can impart an etch selectivity between the carrier and intermediate layers, or merely introduce a detectable species that can be used as a marker by which backside processing can be predicted. The intermediate layer 210 can be doped with electroactive impurities (i.e., render the intermediate layer 210 an n-type or p-type semiconductor), or not, when the impurities can provide a basis for detecting the intermediate layer 210 during subsequent carrier layer removal as described, for example, in operation 120. Exemplary electroactive impurities for some semiconductor materials include group III elements (e.g., B), group IV elements (e.g., P). Any other element can also be employed as a non-electroactive species. The impurity doping concentration within the intermediate layer 210 need only vary from the impurity doping concentration of the carrier layer 205 by an amount sufficient for detection, which can be predetermined as a function of the detection technique and detector sensitivity. As further described elsewhere herein, the intermediate layer 210 can have a different composition than the device layer 215. In some such embodiments, the intermediate layer 210 can have a different bandgap than the device layer 215. For example, the intermediate layer 210 can have a wider bandgap than the device layer 215. In embodiments where the intermediate layer 210 comprises a dielectric material, the dielectric material can be an inorganic material (e.g., SiO, SiN, SiON, SiOC, hydrogen silsesquioxane, A-based silsesquioxane) or an organic material (polyimide, polynorbornene, benzocyclobutene). For some dielectric embodiments, the intermediate layer 210 can be formed as an embedded layer (e.g., by implanting oxygen into the silicon device and / or carrier layer to SiOx). Other embodiments of the dielectric intermediate layer may require bonding (e.g., thermocompression bonding) of the carrier layer 205 to the device layer 215. For example, when the donor substrate 201 is a semiconductor-on-insulator (SOI) substrate, either or both of the carrier layer 205 and the device layer 215 can be oxidized and bonded together to form the SiO intermediate layer 210. Similar bonding techniques can be used for other inorganic or organic dielectric materials. In some other embodiments, the intermediate layer 210 includes two or more materials spaced apart laterally within the layer (i.e., in the X direction in FIG. 3A). The two or more materials can include a dielectric and a semiconductor, a dielectric and a metal, a semiconductor and a metal, a dielectric and a semiconductor, two different dielectrics, two different semiconductors, or two different metals. Within such an intermediate layer, a first material can surround islands of a second material extending through the thickness of the intermediate layer. For example, the intermediate layer can include a field isolation dielectric surrounding islands of a semiconductor extending through the thickness of the intermediate layer. The semiconductor can be epitaxially grown within openings of a patterned dielectric, or a dielectric material can be deposited within openings of a patterned semiconductor. In some exemplary embodiments, features of a semiconductor, such as fins or pedestals, are etched into a front surface of a semiconductor device layer. Trenches surrounding these features can subsequently be backfilled with an isolation dielectric, for example, after any known shallow trench isolation (STI) process. One or more of the semiconductor features or the isolation dielectric can be used to terminate a backside carrier layer removal process, for example, as a backside exposure etch stop. In some embodiments, exposure of the trench isolation dielectric can halt, significantly slow, or trigger a detectable signal for terminating backside carrier polishing. For example, chemical mechanical polishing (CMP) of a carrier semiconductor using a slurry having a high selectivity for removing an isolation dielectric (e.g., SiO) over removing a carrier semiconductor (e.g., Si) can significantly slow when the (bottom) surface surrounding the trench isolation dielectric encompassing semiconductor features of the device layer is exposed. Since the device layer is disposed on the front side of the intermediate layer, the device layer does not need to be directly exposed to the backside exposure process. As another example, islands of semiconductor can be grown from the crystal carrier surface within a pinhole extending through the thickness of a dielectric layer disposed on a carrier layer. For such an embodiment, the intermediate layer is a composite of semiconductor islands embedded within the dielectric layer. Fabrication of the donor substrate can continue with a crystal carrier layer such as silicon, another Group-IV semiconductor, or others. A dielectric layer (e.g., SiO) can be deposited on the carrier layer, masked, and etched to form a high-density array of openings through the dielectric layer. Such openings can be trenches or pinholes. The critical dimension (CD) of such openings can be on the order of tens of nanometers to several microns. In some embodiments, the aspect ratio of the openings is sufficient (e.g., greater than 4:1) to effect aspect ratio trapping (ART) of crystal defects within the semiconductor grown within the openings. The crystal surface of the carrier layer is exposed within each opening. The openings of the array are backfilled with a crystalline semiconductor grown from heteroepitaxy or homoepitaxy exposing the carrier surface. In some embodiments, for example, silicon is grown within an ART pattern on a non-silicon seed surface. In some other embodiments, III-V materials are grown within an ART pattern on a III-V or Group-IV seed surface. In some other embodiments, III-N materials are grown within an ART pattern on an elemental or alloyed Group-IV seed surface. In some further embodiments, lateral epitaxial overgrowth (LEO) of the crystalline semiconductor is then performed using any known technique to bridge the islands of crystalline semiconductor and form a continuous device layer 215 extending over the pinhole intermediate layer 210. Figures 4A, 4B, and 4C are perspective views of some exemplary embodiments further showing the growth of the III-N semiconductor as part of the intermediate layer 210 and the device layer 215. In some such heteroepitaxial embodiments, the intermediate layer semiconductor can be a III-N material (e.g., GaN) grown on a Group-IV (e.g., silicon) carrier layer. Each III-N epitaxial island can be relaxed using a hexagonal / wurtzite c-axis that is substantially orthogonal to the carrier growth surface. As shown in FIG. 4A, the donor substrate 201 includes a field isolation dielectric layer 480 (e.g., SiO) deposited on the carrier layer 205 (e.g., crystalline silicon). The semiconductor 410 is a III-N material (e.g., GaN) that is heteroepitaxially grown from the surface of the carrier layer 205 and backfills the opening at the field isolation dielectric layer 480. The LEO of the III-N semiconductor is further depicted in FIG. 4B. For additional descriptions of the epitaxial growth parameters that can be used in the growth process shown in FIGS. 4A-4C, interested readers may refer to International Application PCT / US2014 / 56299 (US Application 15504634) (filed on September 19, 2014 and under common ownership or assignment). As shown in FIG. 4B, for a hexagonal crystal with the depicted orientation, when the device layer 215 grows over the field isolation dielectric layer 480, the crystal defects 440 will laterally glide during the lateral overgrowth and become more parallel to the c-plane of the III-N semiconductor. As shown in FIG. 4C, when the III-N semiconductor islands are merged, a continuous III-N semiconductor device layer 215 is formed. Additional material layers (such as a polarization layer (not shown)) can be grown as another component of the device layer 215. The polarization layer can facilitate a two-dimensional electron gas (2DEG) at the material interface within the device layer 215. Advantageously, the donor substrate 201 shown in FIG. 4C can be fabricated without any bonding of a separate substrate and / or transfer of the device layer 215. The donor substrate 201 can be further processed after any of the methods described elsewhere herein. In some embodiments of the III-N device layer, a high electron mobility transistor (HEMT) is fabricated in the III-N device layer 215. The carrier layer 205 and / or the intermediate layer 210 can be removed from the device layer 215, for example, as described elsewhere herein. Advantageously, the pinhole field isolation dielectric layer 480 can also provide excellent etch stop during subsequent removal of the carrier layer 205. After the etch stop, a backside exposure process can further remove the intermediate layer 210 and expose the backside of the device layer 215. The semiconductor material within the intermediate layer that includes both a semiconductor and a dielectric can also be a heteroepitaxially grown III-V material. As used herein, heteroepitaxial growth refers to the growth of a crystal of one material composition from the surface of another crystal of a different material composition. For example, a III-V epitaxial device layer (e.g., InAlAs, InGaAs, etc.) can be grown by depositing a pinhole dielectric on a Group IV crystal (e.g., Si, Ge, SiGe) or a III-V crystal (e.g., GaAs) carrier layer. For some such embodiments, the donor substrate 201 may be substantially as shown in FIG. 4D, where the intermediate layer 210 includes a pinhole or trench field isolation dielectric layer 480, and the semiconductor 410 is a III-V compound (e.g., InAlAs) grown within the base pinholes and / or trenches. The device layer 215 is further grown on the semiconductor 410 within the top portion of the pinholes and / or trenches. In some exemplary embodiments, the device layer 215 is a second III-V material (e.g., InGaAs) that is an alloy composition different from the alloy composition grown as part of the intermediate layer 210. Subsequent processing can then form devices (e.g., transistors) within the device layer 215. For example, as described elsewhere herein, the device layer 215 can be fabricated into fins or other non-planar structures. It is noted that for embodiments where the intermediate layer includes both a semiconductor and a dielectric, the thickness of the intermediate layer can be significantly greater than the critical thickness, where relaxation occurs due to the lattice mismatch between the intermediate layer and the carrier. While an intermediate layer below the critical thickness may be insufficient in thickness to accommodate the non-uniformities of a wafer-level backside exposure process, embodiments with a greater thickness can advantageously increase the window for the backside exposure process. Embodiments with a pinhole dielectric can also facilitate the subsequent separation of the carrier layer from the device layer, as well as improve the crystal quality within the device layer (e.g., within the device layer 215). The semiconductor material within the intermediate layer that includes both a semiconductor and a dielectric can also be homoepitaxially grown. As used herein, homoepitaxial growth refers to the growth of a crystal of one material composition from the surface of another crystal of the same material composition. In some exemplary embodiments, a silicon epitaxial device layer is grown through a pinhole dielectric disposed on a silicon carrier layer. For such embodiments, the donor substrate structure can also be substantially as shown in FIG. 4D, where the pinhole dielectric can facilitate the subsequent separation of the carrier layer and the device layer. The intermediate layer, which includes both semiconductor and dielectric, may also include semiconductor features etched into the front side of the carrier layer, such as but not limited to a silicon layer. These features may have substantially the same structure as a homoepitaxial structure grown into a pinhole dielectric when surrounded by a dielectric material (e.g., STI). For such an embodiment, the donor substrate structure may again be similar to the device layer 215 shown in FIG. 4D, and the semiconductor within the intermediate layer 210 is the same material as the carrier layer 205. In such an embodiment, the dielectric material 480 may again facilitate the subsequent separation of the carrier layer and the device layer. Continuing with FIGS. 2A and 3A, the intermediate layer 210 may also be a metal. For such an embodiment, the metal may be any composition known to be suitable for bonding to the carrier layer 205 or the device layer 215. For example, either or both of the carrier layer 205 and the device layer 215 may be finished with a metal, such as but not limited to Au or Pt, and subsequently bonded together, e.g., to form an Au or Pt intermediate layer 210. Such a metal may also be part of an intermediate layer that further includes a patterned dielectric surrounding the metal features. The intermediate layer 210 may be any thickness (e.g., the z-height in FIG. 3A). The intermediate layer 210 should be thick enough to ensure that the carrier removal operation can be reliably terminated before the device area and / or the device layer 215 is exposed. Exemplary thicknesses of the intermediate layer 210 range from a few hundred nanometers to a few micrometers. For example, the thickness may vary as a function of the amount of carrier material to be removed, the uniformity of the carrier removal process, and the selectivity of the carrier removal process. For embodiments where the intermediate layer 210 has the same crystallinity and crystal orientation as the carrier layer 205, the thickness of the carrier layer may be reduced by the thickness of the intermediate layer 210. In other words, the intermediate layer 210 may be the top of a 700 - 1000 micron thick Group IV crystalline semiconductor substrate that also serves as the carrier layer 205. In embodiments of pseudomorphic heteroepitaxy, the thickness of the intermediate layer may be limited by the critical thickness. For embodiments of heteroepitaxial intermediate layers employing ART or another fully relaxed buffer architecture, the intermediate layer 210 may have any thickness. As further shown in FIGS. 2B and 3B, for embodiments in which the backside processing is used to remove carrier substrate material over a substantial portion of the wafer area (e.g., over the entirety of the wafer), the donor substrate 201 may first be bonded to the host substrate 202 to form a donor-host substrate assembly 203. In alternative embodiments where the backside processing that descends to sub-micron thicknesses is restricted to a small enough area (e.g., that coincides with a subset of the transistors in the IC), such host substrate bonding can be avoided. In the illustrated embodiment, however, the front side surface of the donor substrate 201 is bonded to the surface of the host substrate 202 such that the device layer 215 is close to the host substrate 202 and the carrier layer 205 is remote from the host substrate 202. The host substrate 202 may be any substrate known to be suitable for bonding to the device layer 215 and / or a front side stack fabricated on the device layer 215. In some embodiments, the host substrate 202 includes one or more additional device layers. For example, the host substrate 202 may further include one or more device layers (not depicted). The host substrate 202 may include an integrated circuit with IC device interconnects fabricated in the device layer of the host substrate 202, where in the case where the device layer 215 is bonded to the host substrate 202, a 3D interconnect structure may further be formed by wafer-level bonding. Although FIG. 3B does not depict details, any number of front-side layers (such as interconnect metallization layers and interlayer dielectric (ILD) layers) may be present between the device layer 215 and the main substrate 202. The thicknesses of the main substrate 202 and the donor substrate 201 may vary substantially from the same thickness to significantly thicker than the other (e.g., 5 to 10 times). For some embodiments, the thickness of the main substrate 202 is a few micrometers (e.g., 20 - 50 micrometers) and also contains integrated circuits. In some embodiments, the donor and main substrates may be face-to-back bonded (e.g., the back side of the main substrate 202 is bonded to the front side of the donor substrate 201). For such embodiments, the circuitry on the main substrate 201 may include TSVs that extend through the thickness of the main substrate by a few micrometers. These TSVs may be bonded to features on the donor substrate 201 according to any known technique. Thus, the main substrate 202 that is tens of micrometers thick can be used as a permanent feature of the IC, having a greater thickness that guides subsequent backside processing of the donor substrate 201 without restriction through the mechanical support provided by the main substrate 202. Alternatively, the donor and main substrates may be face-to-face bonded. For such embodiments, the circuitry on the main substrate 201 does not need to include TSVs that extend through the thickness of the main substrate by a few micrometers. Instead, features on the front side of the donor substrate 201 may be bonded to features on the front side of the main substrate 202 according to any known technique. Because of the mechanical support provided by the main substrate 202, the main substrate 202 that is tens of micrometers thick can again be used to guide subsequent backside processing of the donor substrate 201 having a thickness that is free from minimum thickness constraints. By exposing the back side of the main substrate 202, the main substrate 202 may eventually be thinned, for example, at the end of the manufacturing process after the rigidity provided by the main substrate thickness is no longer advantageous. Any technique may be employed to bond the main substrate 202 and the donor substrate 201. In some exemplary embodiments further described elsewhere herein, the bonding of the donor substrate 201 to the main substrate 202 is by metal-metal, oxide-oxide, or hybrid (metal / oxide-metal / oxide) thermocompression bonding. Such permanent bonding techniques may advantageously provide high rigidity. Using the host substrate 202 facing the device layer 215 on the opposite side of the carrier layer 205, at least a portion of the carrier layer 205 can be removed as further shown in FIGS. 2C and 3C. Where the entire carrier layer 205 is removed, the donor-host substrate assembly 203 remains with a highly uniform thickness having planar back and front surfaces. Alternatively, the carrier layer 205 and the intermediate layer 210 can be selectively removed (e.g., the carrier layer 205 is masked and the intermediate layer 210 is only exposed or removed in the unmasked sub-regions) to form a non-planar back surface. In the exemplary embodiments shown in FIGS. 2C, 3C, the carrier layer 205 is removed from the entire back surface of the donor-host substrate assembly 203. The carrier layer 205 can be removed, for example, by cutting, grinding, and / or polishing (e.g., chemical mechanical polishing) and / or wet chemical etching, and / or plasma etching through the thickness of the carrier layer to expose the intermediate layer 210. One or more operations can be used to remove the carrier layer 205. Advantageously, the removal operation can be terminated based on a duration or an endpoint signal sensitive to the exposure of the intermediate layer 210. In a further embodiment, for example, as shown in FIGS. 2D and 3D, the intermediate layer 210 is also at least partially etched to expose the back side of the device layer 215. After the intermediate layer 210 is used as an etch stop for the carrier layer and / or an etch endpoint trigger for the carrier layer, at least a portion of the intermediate layer 210 can be removed. Where the entire intermediate layer 210 is removed (e.g., using highly selective CMP), the donor-host substrate assembly 203 maintains a highly uniform device layer thickness having planar back and front surfaces because the intermediate layer is much thinner than the carrier layer. Alternatively, the intermediate layer 210 can be masked and the device layer 215 is only exposed in the unmasked sub-regions, thereby forming a non-planar back side. In the exemplary embodiments shown in FIGS. 2D, 3D, the intermediate layer 210 is removed from the entire back surface of the donor-host substrate assembly 203. The intermediate layer 210 can be removed in this way, for example, by polishing (e.g., chemical mechanical polishing) and / or blanket wet chemical etching, and / or blanket plasma etching through the thickness of the intermediate layer to expose the device layer 215. One or more operations can be used to remove the intermediate layer 210. Advantageously, the removal operation can be terminated based on a duration or an endpoint signal sensitive to the exposure of the device layer 215. In some further embodiments, for example, as shown in FIGS. 2E and 3E, the device layer 215 is partially etched to expose the backside of the device structures formed previously during front-side processing. After the device layer 215 is fabricated in one or more of the device semiconductor regions and / or the device layer 215 serves as an etch stop or endpoint trigger for an intermediate layer, at least a portion of the device layer 215 can be removed. Where the device layer 215 is thinned over the entire substrate area, the donor-host substrate assembly 203 maintains a thickness that is uniformly reduced with a planar back surface and a front surface. Alternatively, the device layer 215 can be masked, and the device structures (e.g., device semiconductor regions) are selectively exposed only in the unmasked sub-regions, thereby forming a non-planar backside surface. Some such embodiments are described further below. In the exemplary embodiments shown in FIGS. 2E and 3E, however, the device layer 215 is thinned over the entire backside surface of the donor-host substrate assembly 203. The device layer 215 can be thinned, for example, by grinding (e.g., chemical mechanical polishing) and / or wet chemical etching, and / or plasma etching through the thickness of the device layer to expose one or more device semiconductor regions formed previously during front-side processing of the device layer 215, and / or one or more other device structures (e.g., front-side device terminal contact metals, gate electrode spacer dielectrics, etc.). One or more operations can be used to thin the device layer 215. Advantageously, the device layer thinning can be terminated based on a duration or an endpoint signal sensitive to the exposure of patterned features within the device layer 215. For example, where front-side processing forms device isolation features (e.g., shallow trench isolation), the backside thinning of the device layer 215 can be terminated upon exposure of the isolation dielectric material. The non-native material layer can be deposited on the backside surface of the intermediate layer, the device layer, and / or specific device regions within the device layer 215, and / or one or more other device structures (e.g., front-side device terminal contact metals, spacer dielectrics, etc.). One or more materials exposed from the backside can be covered with or replaced by the non-native material layer. In some embodiments, as shown in FIGS. 2F and 3F, the non-native material layer 220 is deposited on the device layer 215. The non-native material layer 220 can be any material having a different composition and / or microstructure from the material removed to expose the backside of the device layer. For example, where the intermediate layer 210 is removed to expose the device layer 215, the non-native material layer 220 can be another semiconductor having a different composition and / or microstructure from the intermediate layer 210. In some such embodiments where the device layer 215 is a III-N semiconductor, the non-native material layer 220 can also be a III-N semiconductor having the same or different composition as that regrown on the exposed backside surface of the III-N device region. Such material can be epitaxially regrown from the exposed III-N device region, e.g., to have better crystal quality compared to the removed material, and / or induce strain within the device layer and / or in device regions within the device layer, and / or form a vertical (e.g., z-dimension) stack of device regions suitable for fabricating stacked (multilayer) devices. In some other embodiments where the device layer 215 is a III-V semiconductor, the non-native material layer 220 can also be a III-V semiconductor having the same or different composition as that regrown on the exposed backside surface of the III-V device region. Such material can be epitaxially regrown from the exposed III-V device region, e.g., to have better crystal quality compared to the removed material, and / or induce strain within the device layer and / or in specific device regions within the device layer, and / or form a vertical stack of device semiconductor regions suitable for stacked (multilayer) devices. In some other embodiments where the device layer 215 is a Group-IV semiconductor, the non-native material layer 220 can also be a Group-IV semiconductor having the same or different composition as that regrown on the exposed backside surface of the Group-IV device region. Such material can be epitaxially regrown from the exposed Group-IV device region, e.g., to have better crystal quality compared to the removed material, and / or induce strain within the device layer and / or in specific device regions within the device layer, and / or form a vertical stack of device semiconductor regions suitable for stacked (multilayer) devices. In some other embodiments, the non-native material layer 220 is a dielectric material such as, but not limited to, SiO, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, benzocyclobutene, or the like. The deposition of such a dielectric can be used to electrically isolate various device structures (such as regions of a semiconductor device) that may have been pre-formed during the front-side processing of the donor substrate 201. Such a dielectric material layer may further comprise the first layer of a back-side material stack of an interconnect metal layer or hierarchy. In some other embodiments, the non-native material layer 220 is a conductive material such as any elemental metal or metal alloy known to be suitable for contacting one or more surfaces of a device region exposed from the back side. In some embodiments, the non-native material layer 220 is a metal suitable for contacting a device region (such as a source / drain (i.e., source or drain) region of a transistor) exposed from the back side. In some embodiments, the non-native material layer 220 is a stack of materials, such as an FET gate stack comprising both a gate dielectric layer and a gate electrode layer. For example, the non-native material layer 220 can be a gate stack suitable for contacting a semiconductor device region (such as a transistor channel region) exposed from the back side. Any other materials described as options for the device layer 215 can also be deposited on the back side of the device layer 215. For example, the non-native material layer 220 can be any of the oxide semiconductors, TMDCs, or tunneling materials described above, which can be deposited on the back side, for example, to incrementally fabricate vertically stacked device layers. Back-side wafer-level processing can continue in any manner known to be suitable for front-side processing. For example, the non-native material layer 220 can be patterned into active device regions, device isolation regions, device contact metals, or device interconnects using any known lithography and etching techniques. Back-side wafer-level processing can further fabricate one or more interconnect metallization hierarchies that couple the terminals of different devices to the IC. In some embodiments further described elsewhere herein, back-side processing can be used to interconnect power buses to various device terminals within the IC. In some embodiments, back-side processing includes bonding to a secondary host substrate. Such bonding can employ any layer transfer procedure to bond the back-side (e.g., non-native) material layer to another substrate. After such bonding, the previous host substrate can be removed as a sacrificial donor to re-expose the front-side stack and / or front side of the device layer. Such embodiments can enable side-to-side lamination iterations of the device layer with the first device layer as the core of the component. In some embodiments shown in FIGS. 2G and 3G, the secondary host substrate 240 bonded to the non-native material layer 220 provides at least mechanical support when the host substrate 202 is removed. Any bonding, such as but not limited to thermocompression bonding or similar sintering processes, can be used to bond the secondary main substrate 240 to the non-native material layer 220. In some embodiments, the surface layers of the secondary main substrate 240 and the non-native material layer 220 are both thermocompression-bonded continuous dielectric layers (e.g., SiO). In some other embodiments, the surface layers of the secondary main substrate 240 and the non-native material layer 220 both include thermocompression-bonded metal layers (e.g., Au, Pt, etc.). In other embodiments, at least one of the surface layers of the secondary main substrate 240 and the non-native material layer 220 is patterned and includes both a patterned metal surface (i.e., traces) and a surrounding dielectric (e.g., isolation), which are thermocompression-bonded to form a hybrid (e.g., metal / oxide) bond. For such embodiments, the structural features at the secondary main substrate 240 and the patterned non-native material layer 220 can be aligned (e.g., optically) during the bonding process. In some embodiments, the non-native material layer 220 includes one or more conductive backside traces coupled to the terminals of transistors fabricated in the device layer 215. The conductive backside traces can be bonded, for example, to metal on the secondary main substrate 240. In an alternative embodiment, a secondary donor substrate is bonded to the non-native material layer 220. The assembly shown in FIG. 3G is also applicable to this embodiment, however for an example in a manner substantially the same as described above for the donor substrate 201, the main substrate 202 is not removed until at least the backside processing of the secondary donor substrate is completed. Thus, any number of donor substrates can be stacked and thinned relying on the support provided by the main substrate 202. After this support is no longer needed, the main substrate 202 can be thinned (e.g., the main substrate 202 is bonded face-to-face with the donor substrate 201). The bonding of the device layer to the main (or secondary donor) substrate can be performed from the front side and / or the back side of the device layer before or after the front side processing of the device layer has been completed. The bonding process can be performed after the front side fabrication of the devices (e.g., transistors) on the donor substrate is substantially completed. Alternatively, the bonding of the main (or secondary donor) substrate can be performed before the front side fabrication of the devices (e.g., transistors) on the donor substrate is completed, in which case the front side of the device layer on the donor substrate can receive additional processing after being bonded to the main (or secondary donor) substrate on the back side. As further shown in FIGS. 2H and 3H, for example, the front side processing includes removing the main substrate 202 to re-expose the front side of the device layer 215. At this time, the donor-main substrate assembly 203 includes the secondary main substrate 240 bonded to the device layer 215 through the non-native material layer 220. Figure 3I shows an enlarged view of device layer 215 showing the front and backside metals according to some embodiments. In Figure 3I, the main substrate is not shown, for example, having been removed during the device packaging process. Device layer 215 includes a plurality of semiconductor bodies 310 surrounded by isolation dielectric 480. For example, each of the semiconductor bodies 310 can be a component of one or more finFETs. Front-side interconnect metal 333 includes a plurality of interconnect metal levels 320 embedded within an interlayer dielectric (ILD). Back-side interconnect metal 334 includes a plurality of interconnect metal levels 321 embedded within an interlayer dielectric (ILD). As further described below, for example, front-side interconnect metal 333 and back-side interconnect metal 334 can have different material compositions and / or dimensions. Each of the interconnect metals 333 and 334 can have any number of levels of higher levels that typically have dimensions released from those lower levels. When fully interconnected with both front-side interconnect metal 333 and back-side interconnect metal 334, device layer 215 is an IC layer 350. The IC layer can include only one or both of the front-side interconnect metal and the back-side interconnect metal. A single IC layer can be packaged according to any suitable technique. Alternatively, as described above, the IC layer can be bonded to a secondary host or donor substrate that includes another device layer. Figure 3J also shows a plurality of IC layers 350 bonded to form a 3D IC 360 according to some embodiments. Each IC layer 350 includes device layer 215, for example, having any of the characteristics described elsewhere herein. As shown, 3D IC 360 does not have any additional lead-out pins with a thickness related to the body crystal substrate material. Without such material, 3D IC 360 does not have a micron-thick TSV structure. Instead, the IC layers 350 are interfaced with each other by bonds 390 that can be any suitable bonding technique, such as, but not limited to, thermocompression bonding or adhesive bonding. Bond 390 is a geometry with sufficient alignment between the interconnect metal features of the IC layers that is sufficient to effect separation between two interconnect metal layers. Any number of IC layers 350 can be bonded, for example, according to one or more of the techniques described herein. In some embodiments, pairs of IC layers are bonded face-to-face (front-side to front-side). In some embodiments, pairs of IC layers are bonded back-to-back (back-side to back-side). In some embodiments, pairs of IC layers are bonded face-to-back (front-side to back-side), the distinction between the front side and the back side depending on the implementation. In some embodiments having at least four IC layers, a first (inner) pair of IC layers is bonded face-to-face, while each respective one of the first pair is bonded back-to-back with each respective one of a second (outer) pair of IC layers. FIG. 5 is a flowchart showing a backside exposure method 501 according to some embodiments. The method 501 can be used to remove at least a portion of the carrier layer and the intermediate layer of the donor-host substrate assembly, for example, as part of operation 120 (FIG. 1), and as shown in FIGS. 2C-2E and 3C-3E. At operation 505, the method 501 begins with the input of the donor-host substrate assembly. In some embodiments, the donor-host substrate assembly received at operation 505 is the donor-host substrate assembly 203 as shown in FIG. 3B. At operation 510, the thickness of the carrier layer in the donor substrate is ground away (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any polishing, grinding, and / or masked or unmasked wet / dry etching process known to be suitable for the composition of the carrier layer can be employed at operation 510. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be employed at operation 510. As another example, any wet etchant or plasma etching process known to be suitable for etching features into a Group IV semiconductor can also be employed at operation 510. In some embodiments, prior to operation 510, the carrier layer is cut along a fracture plane that is substantially parallel to the intermediate layer. The cutting or fracturing process can be used to remove a substantial portion of the carrier layer as an entity, reducing the grinding or etching time required to remove the carrier layer. For example, in the case where the carrier layer thickness is 400-900 microns, 100-700 microns may be excised. Any known blanket implant used to facilitate wafer-level fracture can be employed at operation 510. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth within the carrier layer at the desired fracture plane. After such a cutting process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be ground or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, the grinding, grinding, and / or etching operation 510 can be applied to remove a greater thickness of the carrier layer. At operation 515, the exposure of the intermediate layer is detected. Detection operation 515 is used to identify when the back surface of the donor substrate has progressed to the intermediate layer before exposing the device layer. Any known endpoint detection technique suitable for detecting the transition between the carrier layer and the intermediate layer material can be practiced at operation 515. In some embodiments, one or more endpoint criteria are based on changes in the optical absorption or emission of the back surface of the donor substrate during grinding and / or etching at operation 510. In some other embodiments, the endpoint criteria are related to changes in the optical absorption or emission of by-products during grinding or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etch by-products can be a function of the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are related to changes in the mass of species in the by-products of grinding or etching the back surface of the donor substrate. For example, the by-products of operation 510 can be sampled by a quadrupole mass analyzer, and the changes in the mass of species can be correlated to the different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are related to changes in the friction between the back surface of the donor substrate and the grinding surface in contact with the back surface of the donor substrate. The detection of the intermediate layer can be enhanced where the removal process is selective for the carrier layer relative to the intermediate layer, since non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intermediate layer. If the polishing, grinding, and / or etching operation 510 removes the intermediate layer at a rate sufficiently lower than the rate at which the carrier layer is removed, the detection operation 515 can even be omitted. If endpoint criteria are not employed at operation 515, then the polishing, grinding, and / or etching operation 510 of a predetermined fixed duration can be stopped at the intermediate layer material if the thickness of the intermediate layer is sufficient for etch selectivity. In some examples where the carrier is a semiconductor and the intermediate layer is a dielectric, the carrier etch rate:intermediate layer etch rate can be 3:1 to 10:1 or more. The CMP process employed at operation 510 can, for example, employ a slurry that provides a very high selectivity (e.g., 100:1 to 300:1 or more) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) that surrounds the device layer and is embedded within the intermediate layer (e.g., as electrical isolation between adjacent device regions). Once the intermediate layer is exposed, at operation 520, at least a portion of the intermediate layer can be removed. For example, one or more component layers in the intermediate layer can be removed. However, operation 520 is optional. The thickness of the intermediate layer can be uniformly removed, for example, by polishing. Alternatively, the thickness of the intermediate layer can be removed using a masking or blanket etching process. Operation 520 can employ the same polishing or etching process used to thin the carrier at operation 515, or can be a different process with different process parameters. For example, in the case where the intermediate layer provides an etch stop for the carrier removal process, operation 520 can employ a different polishing or etching process that preferentially removes the intermediate layer compared to removing the device layer. In the case where an intermediate layer thickness less than a few hundred nanometers is to be removed, the removal process may be relatively slow, optimized for across-wafer uniformity, and more precisely controlled compared to that used for removing the carrier layer. The CMP process employed at operation 520 uses a slurry that provides very high selectivity (e.g., 100:1 to 300:1 or more) between, for example, a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) that surrounds the device layer and is embedded within the intermediate layer (e.g., as an electrical isolation between adjacent device regions). For embodiments where the device layer is exposed by complete removal of the intermediate layer, backside processing can begin at the exposed backside of the device layer or a specific device region within the device layer. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and device regions (such as source / drain regions) previously fabricated in the device layer. In some embodiments where the carrier layer, intermediate layer, or backside of the device layer is recessed using wet and / or plasma etching, such etching can be a patterned etch or a material-selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described elsewhere herein, the patterning can be within a single device structure (i.e., "intra-cell" patterning), or can be across multiple (e.g., all) device cells (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a partial thickness of the intermediate layer is used as a hard mask for backside device layer patterning. Thus, the masking etch at operation 520 can be before the corresponding masked device layer etch. The output of method 501 is a donor-host substrate assembly that includes a backside having an intermediate layer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer, and / or an IC device having frontside metal that has been deposited onto / through the topography of the exposed device layer. Additional backside processing of any of these exposed regions can then be performed downstream of method 501. In some exemplary embodiments, downstream of the backside processing performed by method 501 includes deposition of non-native materials onto the exposed regions, as further described elsewhere herein. FIG. 6 is a plan view of a donor substrate 201 having an enlarged view of an IC die 211 and a further enlarged view of a logic transistor structure 604 disposed within the IC die 211, in accordance with some embodiments. As described above, the donor substrate 201 may be, for example, an input of method 101 (FIG. 1). Further referring to FIG. 6, a plurality of logic transistor structures 604 are arranged on a region of a device layer within the IC die 211. The additional device units 602 may be, for example, any one of a memory unit, a power transistor structure, an RF transistor structure, an optical device unit, or the like. According to some illustrative embodiments, the transistor structure 604 includes a field effect FET having a source terminal, a drain terminal, and a gate terminal. In some embodiments, the source and drain terminals include semiconductors having the same conductivity type. In other embodiments, the source and drain terminals include semiconductors having complementary conductivity types (i.e., a tunneling FET or TFET). The FET may also include a heterojunction (i.e., an HFET) and may also qualify as a high electron mobility transistor (HEMT) when the channel includes III-V or III-N materials. In FIG. 6, solid lines within the transistor structure 604 represent protruding materials that cover other materials or are formed over structural features shown by dashed lines within the transistor structure layer. The thick dashed lines in FIG. 6 represent planes A-A', B-B', and C-C' along which cross-sectional views are further provided in FIGS. 8A, 8B, 8C, 9A, 9B, 9C, and 11A, 11B, 11C, where the letters in the figure numbers correspond to cross-sections designated by the same letters. As further shown in FIG. 6, the transistor structure 604 is supported by a backside substrate 605 having a semiconductor body 610 embedded within a front-side field isolation dielectric material 680. In some embodiments, the backside substrate 605 includes a carrier layer (e.g., the carrier layer 205 of FIG. 3A). In some embodiments, an intermediate layer (not depicted) separates the backside substrate 505 from the transistor structure 604. In some other embodiments, the backside substrate 605 includes both a carrier layer (e.g., the carrier layer 205 of FIG. 3A) and an intermediate layer (e.g., the intermediate layer 210 of FIG. 3A). In one example, the transistor structure 604 is fabricated on a donor substrate 201 (FIG. 3A). In certain embodiments, the transistor cell 604 includes a non-planar FET such as a FinFET, a triple-gate, an ω-gate, etc. Further referring to FIG. 6, the transistor structure 604 includes a gate electrode 673 passing through the channel regions of each of the first and second semiconductor bodies 610. Although two semiconductor bodies 610 are shown in FIG. 6, the non-planar FET may include one or more such semiconductor bodies. In some exemplary embodiments, the semiconductor body 610 includes at least one semiconductor region from a device layer of the donor substrate 201. For example, the transistor channel regions within the semiconductor body 610 may be derived from the semiconductor device layer 215 of FIG. 3A. Thus, the semiconductor body 610 may include one or more semiconductor regions having any of the above-described components of a donor substrate device layer suitable for a field-effect transistor (e.g., the device layer 215 as shown in FIG. 3A). Exemplary materials include but are not limited to group-IV semiconductors (e.g., Si, Ge, SiGe), group-III-V semiconductors (e.g., GaAs, InGaAs, InAs, InP), group-III-N semiconductors (e.g., GaN, AlGaN, InGaN), oxide semiconductors, TMDC, graphene, etc. In some advantageous embodiments, the semiconductor body 610 is single-crystalline. As further shown in FIG. 6, the source / drain metal 650 is disposed adjacent to the gate electrode 673 and also extends across the semiconductor body 610. In the illustrated embodiment, the source / drain metal 650 is disposed on the regrown or raised source / drain semiconductor 640, which is further disposed in contact with the semiconductor body 610. The source / drain semiconductor 640 may be doped with electroactive impurities that impart n-type or p-type conductivity. For some exemplary embodiments, both the source and drain semiconductors 640 are doped to the same conductivity type (e.g., n-type for NMOS and p-type for PMOS). In alternative embodiments (e.g., for tunneling FETs), the source and drain semiconductors 640 are doped to have complementary conductivity (e.g., n-type source and p-type drain). The source / drain semiconductor 640 may be any semiconductor material compatible with the semiconductor body 610, such as, but not limited to, group-IV semiconductors (e.g., Si, Ge, SiGe), and / or group-III-V semiconductors (e.g., InGaAs, InAs), and / or group-III-N semiconductors (e.g., InGaN), and / or (metal) oxide semiconductors. The electrically insulating spacer dielectric 671 laterally separates the gate electrode 673 from the source / drain metal 650 and / or the source / drain semiconductor 640. The source / drain metal 650 may comprise one or more metals (e.g., Ti, W, Pt, their alloys, and nitrides) that form an ohmic or tunneling junction with the doped source / drain semiconductor 640. The spacer dielectric 671 may be or any dielectric, such as, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, or any known low-k material having a relative dielectric constant below 4.0. Although only one gate electrode 673 is shown as part of a single logic transistor structure in solid lines, an exemplary second gate electrode 673 is depicted in dashed lines as being associated with an adjacent transistor structure. The second gate electrode is also laterally separated from the metal 650 and / or the source / drain semiconductor 640 by the spacer dielectric 671. FIG. 7 is a flowchart showing a method 701 for backside isolation of a transistor according to some embodiments. Method 701 further illustrates the formation of a transistor structure layer that can be a thickness of no greater than a few hundred nanometers. Method 701 further illustrates how the techniques introduced above in the context of FIGS. 1-5 can be applied to provide a backside isolation structure to a device layer. As described elsewhere herein, such a layer is suitable for vertically stacking into 3D ICs (e.g., high number of layers / micron thickness) potentially having a very high vertical unit density. Method 701 also improves the electrical isolation of the transistor, e.g., by reducing substrate leakage through between adjacent devices. Method 701 begins at input 705 with a donor substrate of a transistor structure of a device layer that employs a donor substrate. As shown in FIG. 6, the transistor structure can operate exactly as manufactured from the front side, e.g., including three terminals. Alternatively, one or more terminals may be absent such that the transistor structure will not be operative until backside processing is complete. The donor substrate can have one or more of the above characteristics, such as but not limited to an intermediate layer and a carrier layer. However, it is noted that the carrier layer and / or the intermediate layer are not required to perform method 701. At operation 710, a donor-host substrate assembly is formed, e.g., as described elsewhere herein (e.g., after method 101). At operation 715, the backside of the transistor structure is exposed by removing at least a portion of the donor substrate to form a transistor layer-host substrate assembly. An isolation dielectric can then be deposited on the exposed backside surface, which in an exemplary embodiment is a surface of a semiconductor or a metal. At operation 720, the backside isolated transistor layer-host substrate assembly is the output from method 701 and is ready for further processing, e.g., after a subsequent iteration of method 101 (FIG. 1). FIGS. 8A, 9A, 10A, and 11A show cross-sectional views of a transistor structure 604 along the A-A' plane labeled in FIG. 6 as performed in the operations of method 701 according to some embodiments. FIGS. 8B, 9B, 10B, and 11B show cross-sectional views of the transistor structure 604 along the B-B' plane labeled in FIG. 6 as performed in the operations of method 701 according to some embodiments. FIGS. 8C, 9C, 10C, and 11C show cross-sectional views of the transistor structure 604 along the C-C' plane labeled in FIG. 6 as performed in the operations of method 701 according to some embodiments. It is noted that although the transistor structure 604 is shown as a non-planar transistor structure having gate electrodes coupled to multiple surfaces of a semiconductor body, method 701 can also be applied to planar transistor structures in a similar manner. FIGS. 8A-8C show the structures present in an exemplary transistor structure after front side processing of the donor substrate. The semiconductor body 610 extends vertically (e.g., in the z-dimension) a fin height H fThe fin structure. The semiconductor body 610 includes a channel portion having a channel height H c . In some exemplary embodiments, the channel height H c includes the device layer 215. In the embodiment shown in FIGS. 8A - 8C, the semiconductor body 610 further includes a sub - fin portion having a sub - fin height H sf that also includes the device layer 215. The transistor semiconductor body 610 may have been formed, for example, using a patterned front - side recess etch of the device layer 215. As further described elsewhere herein, the semiconductor fin body may include a sub - fin semiconductor of a different composition than the channel portion. In this case, the device layer 215 may be only the channel portion, while the sub - fin semiconductor may be a component of the intermediate layer 210 (FIG. 3A). Alternatively, the sub - fin semiconductor may be considered a spacer between the device layer 215 and the back - side substrate 605, which may also include an intermediate layer between the sub - fin semiconductor and the carrier layer. Surrounding one or more sidewalls of the semiconductor body 610 is a field - isolation dielectric 680. The field - isolation dielectric 680 may be one or more materials suitable for providing electrical isolation between adjacent transistors in the lateral (e.g., x or y dimension). In some exemplary embodiments, the field - isolation dielectric 680 includes silicon dioxide. Other materials, such as but not limited to SiN, SiON, SiOC, polyimide, HSQ, or MSQ are also possible. In some embodiments, the field - isolation dielectric 680 and the sub - fin portion of the semiconductor body 610 constitute an intermediate layer that stops a carrier removal process thereon. A gate stack including a gate electrode 673 disposed on a gate dielectric 845 intersecting the channel portion of the transistor semiconductor body 610 is further shown in FIGS. 8A and 8B. The intersection of the source / drain metal of the source / drain semiconductor 640 is further shown in FIG. 8C. The semiconductor body channel portion is coupled to the gate stack and has a sidewall height H c , which is lower than the sub - fin z - height H sf that the sub - fin has. Although any known gate stack materials suitable for the semiconductor body 610 may be used, in some exemplary embodiments, the gate stack includes a high - k dielectric material (having a bulk relative dielectric constant greater than 9), and a metal gate electrode having a work function suitable for the semiconductor body 610. Exemplary high - k materials include metal oxides such as but not limited to Al 2 O 3 , HfO 2 , HfAlO x . Silicates such as, but not limited to, HfSiO x or TaSiO x can also be applied to some semiconductor body components (e.g., Si, Ge, SiGe, III-V). The gate electrode 673 can advantageously have a work function of less than 5 electron volts and can include an elemental metal layer, a metal alloy layer, or a laminated structure of one or both of them. In some embodiments, the gate electrode is a metal nitride such as TiN (e.g., 4.0 to 4.7 electron volts). The gate electrode can also include Al (e.g., TiAlN). Other alloying components can also be used in the gate electrode 673 such as, but not limited to, C, Ta, W, Pt, and Sn. Figures 8A - 8C further show a front stack 690 disposed on the front surface. The front stack 690 is shown in dashed lines as part of the transistor structure layer, which can vary without limitation and can include, for example, any number of backend interconnect metal levels. Such levels can separate the semiconductor body 610 and / or each other by one or more interlayer dielectric (ILD) layers. A backside substrate 605, which may also include an intermediate layer and / or a carrier layer, is disposed on the backside surface. Figures 9A - 9C depict the transistor structure 604 after bonding of the donor substrate to the main substrate 202. The main substrate 202 can have any of the properties described elsewhere herein. As shown, the main substrate 202 is bonded to the front surface of the front stack 690, for example, by thermocompression bonding. As further shown in Figures 9A - 9C, the backside substrate 605 has been removed, exposing the backside surface 911 of the intermediate layer 210. The backside substrate 605 can be removed by any technique such as, but not limited to, method 501 (Figure 5). For example, a marker or etch stop may have been present within the intermediate layer 210 that terminates the carrier removal operation before the backside of the field isolation dielectric 680 is exposed. Figures 10A - 10C depict the transistor structure 604 after the backside 1012 of the semiconductor body 610 is exposed. To expose the backside of the transistor semiconductor body 610, portions of the fixed bulk semiconductor can be ground back and / or recess etched using wet and / or dry etch procedures, for example, as described above for operation 520 (Figure 5). In comparison to using a dielectric (e.g., SiO 2)In some exemplary embodiments of a highly selective (e.g., 200 to 300:1) CMP slurry having a higher etch rate for the device layer semiconductor (e.g., Si), the backside polishing of the intermediate layer 210 can be stopped when the field isolation dielectric 680 is exposed. Any amount of over-etch (over-polish) can be performed to reduce the finlet height by further thinning the intermediate layer that includes the semiconductor body 610 and the adjacent field isolation dielectric 680. H sf In some embodiments, the entire finlet of one or more semiconductor bodies within the transistor structure can be removed during the backside exposure operation. Figures 11A - 11C depict the transistor structure 604 after depositing the backside isolation dielectric 1120 on the exposed backside of the transistor semiconductor body 610. The backside isolation dielectric 1120 is an example of a non-native material that replaces a portion of the intermediate layer that was removed to expose the transistor semiconductor region. The backside isolation dielectric 1120 can be any dielectric material suitable for electrical isolation of the transistor. In some exemplary embodiments, the backside isolation dielectric 1120 is silicon dioxide. However, it is noted that since the backside isolation dielectric 1120 is deposited after the backside exposure rather than being pre-incorporated into the donor substrate, a wider selection of materials is possible, for example, compared to the case in an SOI substrate where the insulating layer is an embedded layer upstream as the substrate. Thus, in some advantageous embodiments, the backside isolation dielectric 1120 has a low relative dielectric constant (e.g., as measured for the material in bulk state). Such materials typically cannot withstand the high-temperature processes associated with many frontside manufacturing procedures (e.g., source / drain formation). The backside isolation dielectric can be a low-k dielectric material, such as any of those known to be suitable as the frontside ILD in the backend interconnect stack. In some embodiments, the backside isolation dielectric 1120 has a relative dielectric constant that is not greater than, and more preferably lower than, the relative dielectric constant of the field isolation dielectric 680. In some embodiments, the backside isolation dielectric 1120 has a relative dielectric constant less than 3.9, and more preferably less than 3.5. In some embodiments, the backside isolation dielectric 1120 has the same composition as one or more ILD layers in the frontside stack 690. Exemplary backside isolation dielectric materials include SiOC, SiOCH, HSQ, or MSQ. Other low-k dielectrics are also possible. Similarly, other dielectric materials having a relative dielectric constant higher than 3.9 (e.g., SiN, SiON) are also possible. Figures 11D - 11F depict the transistor structure 604 after replacing at least a portion of the semiconductor body 610 with the backside isolation dielectric 1120. FIG. 11D provides a view of the transistor structure 604 along the A - A' plane labeled in FIG. 6 according to some embodiments. FIG. 11E shows a cross - sectional view of the transistor structure 604 along the B - B' plane labeled in FIG. 6, and FIG. 11F shows a cross - sectional view of the transistor structure 604 along the B - B' plane labeled in FIG. 6. In some illustrative embodiments, the sub - fins of the semiconductor body 610 are etched from the backside, for example, using any etching process selective to the sub - fin semiconductor over the field isolation 680. The backside sub - fin recess may or may not expose the backside of the device layer 215 (e.g., including the channel semiconductor). The backside isolation dielectric 1120 is then back - filled into the resulting groove. In an alternative embodiment, a portion of the intermediate layer under the device layer is converted into an isolation dielectric. For example, the sub - fins of the semiconductor body 610 may be converted into the backside isolation dielectric 1120. In some advantageous embodiments, at least a portion of the thickness of the semiconductor body 610 (e.g., silicon) under the device layer 215 is converted into SiO 2 , to form the backside isolation dielectric 1120. FIG. 12 is a flowchart showing a method 1201 for forming a backside transistor source / drain contact metal according to some embodiments. Method 1201 further illustrates the formation of a transistor structure layer whose thickness can be no greater than a few hundred nanometers. Method 1201 begins with an input 1205 of a donor - host substrate assembly comprising a transistor structure. The donor substrate may have one or more of the features described above, such as but not limited to an intermediate layer and a carrier layer. However, it is noted that the carrier layer and / or the intermediate layer are not required to perform method 1201. The transistor structure at the input of method 1201 may be fully operational, for example, including three terminals as shown in FIG. 6. Alternatively, one or more terminals may be absent such that the transistor structure will be non - operational until the backside processing is complete. FIG. 13 is a plan view of a transistor structure 1304 lacking a source / drain metal 650. The thick dotted line indicates the plane along the cross-sectional views further provided in FIGS. 14A-14C, 15A-15C, and 16A-16C. When the source or drain metal 650 is absent, the pitch and / or critical dimension constraints of the source / drain metal 650 and / or other front-side metal layers (e.g., gate electrode 673 or higher metal layers) can be advantageously relaxed. The absence of the source or drain metal 650 renders the transistor structure 1304 inoperable until the third terminal connection is fabricated, e.g., using the back-side transistor source / drain contact metallization method 1201 (FIG. 12). Such back-side transistor source / drain contact metal can couple a power rail (e.g., V CC ) to the transistor structure, advantageously configuring power and signals (gate electrode voltage) routed on opposite sides of the transistor structure layer. Similar advantages may exist for memory cells such as SRAM or other memory cells. For example, bit lines, source lines, and / or word line metals may be on opposite sides of a memory cell layer. It is noted that the back-side transistor source / drain contact metallization method 1201 can also be practiced on a fully functional (e.g., including all device terminals) transistor structure fabricated from the front side. For such embodiments, the back-side transistor source / drain contact metallization method 1201 can be practiced to incorporate the source / drain transistor terminals into interconnect traces disposed on both sides of the transistor layer, which can advantageously reduce source / drain contact resistance and / or cause the transistor source / drain semiconductor region to become a circuit node that is directly fanned out to at least two other circuit nodes. At operation 1210, the back side of the source / drain region of at least one transistor is exposed. In some embodiments, a patterned back-side recess etch is performed at operation 1210 to selectively expose the source / drain region relative to other regions of the transistor structure. Alternatively, when the source / drain semiconductor (or any sacrificial material) at the source / drain location extends from the front side to a depth deeper than other transistor regions, operation 1210 may require an unpatterned back-side recess etch or polish that pauses upon exposure of the source / drain semiconductor (or other sacrificial material) prior to exposure of other device regions such as the channel semiconductor. Once exposed, method 1201 is completed at operation 1215, where the source / drain semiconductor and / or contact metal system is deposited on the back side of the source / drain semiconductor. Further examples of non-native materials on which the source / drain semiconductor and / or contact metal system can be deposited are, for example, as described above in the context of operation 125 of FIG. 1. Figures 14A, 15A, and 16A show cross-sectional views of the transistor structure 1304 along the A-A' plane shown in FIG. 13 according to some embodiments (such as operations performed in method 1201). Figures 14B, 15B, and 16B show cross-sectional views of the transistor structure 1304 along the B-B' plane shown in FIG. 13 according to some embodiments (such as operations performed in method 1201). Figures 14C, 15C, and 16C show cross-sectional views of the transistor structure 1304 along the C-C' plane shown in FIG. 13 according to some embodiments (such as operations performed in method 1201). Figures 14A-14C show structures present in an exemplary transistor structure after front-side processing of the donor substrate and bonding to the host substrate 202. As further shown in FIGS. 14A-14C, the back-side substrate has been removed by any technique, such as but not limited to method 501 (FIG. 5). For the structural features shown in FIGS. 14A-14C, the same reference symbols may have any of the characteristics described above (e.g., FIGS. 8A-8C and 9A-9C). The etch mask 1410 is aligned to the front-side transistor features as the back-side substrate is removed. Alignment relative to the source / drain semiconductor 640 need not be precise and minimizes or avoids overlap with the gate electrode 673. The etch mask 1410 protects only a portion of the intermediate layer 210. The etch mask 1410 can be, for example, another intermediate layer of the back-side substrate. Alternatively, the etch mask 1410 can be a dielectric (e.g., SiO, SiN, etc.) deposited after exposure of the intermediate layer 210 during carrier layer removal. In yet other embodiments, the etch mask 1410 is a soft mask (e.g., a photosensitive resist) applied to the back-side surface of the device layer 215. The unprotected device semiconductor regions 1411 are then recess etched using any known wet and / or plasma etch process known to be suitable for the material composition. For example, dry etching and / or wet etching selective to silicon on the etch mask can be used to selectively remove a portion of the silicon semiconductor fin and expose the transistor source / drain. Figures 14D - 14F show structures in an exemplary transistor structure that exist after front - side processing on a donor substrate and bonding to a host substrate 202. As further shown in Figures 14D - 14F, the back - side substrate has been removed by any technique, such as but not limited to method 501 (Figure 5). For the structural features shown in Figures 14D - 14F, the same reference symbols can have any of the characteristics described above (e.g., Figures 8A - 8C and 9A - 9C). For this embodiment, no etching mask is used to selectively expose one of the source or drain semiconductors 640. Instead, the front - side processing has distinguished the z - depth between two regions of the source and drain semiconductors 640 on opposite sides of the channel. In an illustrative embodiment, the source semiconductor 640 has a depth that is substantially equal to the height of the semiconductor body 610, although it can have a smaller or larger depth than shown. Figures 15A - 15C are a continuation of the structure shown in Figures 14A - 14C. As shown in Figures 15A - 15C, a major portion of the transistor semiconductor body 610 is removed within a selectively exposed recess 1540, while the sub - fin height H sf is maintained in the transistor - structure region protected by the etching mask 1410. The selectively exposed recess 1540 can be of any depth and lateral dimension. For example, the selectively exposed recess 1540 can completely remove the sub - fin portion of the semiconductor body 610 (i.e., the semiconductor portion of the intermediate layer 210) and expose the source / drain semiconductors 640. In other embodiments, the selectively exposed recess 1504 can be used as a back - side fin cut to fork a fin into two separate fins, for example, such that the first of the fins implements a PMOS FET and the second of the fins implements an NMOS FET. While fin forking is typically early in the process during fin patterning when limited to front - side processing, with back - side fin forking, the ends of the fins do not need to be defined at all. Thus, front - side fin processing can better match a one - dimensional grating pattern to NMOS and PMOS FETs even fabricated together in a single fin - die. When back - side exposure occurs, individual transistors can be delineated by a back - side fin cut. Figures 15D - 15F are a continuation of the structure shown in Figures 14D - 14F. The intermediate layer 210 has been removed, for example, using a blanket polish or an etching process to selectively expose deep transistor source / drains for shallow source / drains. As shown in Figures 15D - 15F, the deep source / drain semiconductors 640 are exposed while maintaining the sub - fin height H sf . Figures 16A - 16C are a continuation of the structures shown in Figures 15A - 15C. Figures 16A - 16C show the transistor structure 1304 after epitaxial growth or deposition of a p - type or n - type impurity - doped back - side source / drain semiconductor 1640, and the subsequent deposition of a back - side source / drain metal 1650. Any epitaxial growth or deposition process can be used to form the back - side source / drain semiconductor 1640. For example, the same epitaxial or deposition process used to form the source / drain semiconductor 640 can be used to form the back - side source / drain semiconductor 1640. Similarly, any metal deposition process can be used to form the back - side source / drain metal 1650. For example, the same deposition process used to form the source / drain metal 650 can be used to form the back - side source / drain metal 1650. The back - side source / drain semiconductor 1640 has a longitudinal length L f that is less than the longitudinal length of the semiconductor body 610 L 1 and a transverse length that is substantially equal to the transverse length of the semiconductor body 610 L 2 . Thus, in this illustrative embodiment, the source / drain semiconductor 640 has a greater transverse length L 3 than the back - side source / drain semiconductor 1640. Similarly, the longitudinal lengths of the front - side and back - side source / drain semiconductors can be different. For example, in some embodiments where the back - side source / drain semiconductor 1640 operates as the source of a transistor, a tip region (e.g., a lightly - doped source semiconductor) that can be included does not exist in the source / drain semiconductor 640 that operates as the drain of the transistor. Such a selective source tip region can be formed, for example, during the epitaxial growth of the impurity - doped back - side source / drain semiconductor 1640. A transistor drain without a tip can exhibit less drain - induced barrier lowering (DIBL), e.g., when the lowest source resistance can depend on the tip - doped source semiconductor. However, it is generally difficult to cause asymmetry in the FET source / drain structure solely through front - side processing. Thus, decoupling the fabrication of the drain semiconductor from the source semiconductor into separate front - side / back - side processes can be beneficial for forming an asymmetric source / drain architecture. In some further embodiments represented by FIGS. 16A - 16C, the backside metal overburden is removed by polishing (e.g., CMP), the etch mask 1410 and / or the intermediate layer 210 with source / drain contact metal are re-exposed, and then the recess 1540 is selectively backfilled. Subsequent backside processing may also include the fabrication of one or more backside interconnect metal levels (not shown) that are at least electrically coupled to the source / drain metal 1650. In some such embodiments, such backside interconnect metals have a different composition from the frontside interconnect metal hierarchy. For example, the frontside interconnect metal is mainly copper (e.g., a Cu-rich alloy), while the backside metal is copper-poor (e.g., an Al-rich alloy). In another example where the frontside interconnect metal is copper-poor (e.g., an Al-rich alloy), the backside metal is mainly copper (e.g., a Cu-rich alloy). The backside interconnect metals may also differ in size (e.g., be larger) from the corresponding levels of the frontside interconnect metals. For example, in some embodiments where the backside interconnect metals supply power to the transistor structure, the backside metals include lines with a larger lateral width and / or vertical height (e.g., the z-dimension). Backside metals with larger sizes can be beneficial for structures where power rails are confined to the backside metals and signal lines are confined to the frontside metals. Backside metals with larger sizes can also be beneficial for structures along long bus bars or clock distribution lines disposed on the backside of the device layer. FIGS. 16D - 16F are a continuation of the structure shown in FIGS. 15D - 15F. In FIGS. 16D - 16F, the transistor structure 1304 is shown after the deposition of the backside source / drain metal 1650 in contact with the deep source / drain semiconductor 1650. Any metal deposition process can be used to form the backside source / drain metal 1650. For example, the same deposition process used to form the source / drain metal 650 can be used to form the backside source / drain metal 1650. The formation of the backside source / drain metal 1650 may further imply the formation of the backside dielectric 1410, e.g., following any known damascene interconnect metal technique. Although the above discussion provides some illustrative examples of backside metal structures, other structures can be fabricated using substantially the same techniques. Generally, any terminal of a device fabricated in the device layer can include a backside metal structure. For example, other terminals of a transistor can be backside metal interconnected compared to (or in addition to) the backside source and / or drain contact metals shown above. For example, in a three-terminal device, the third terminal (e.g., the gate electrode in a FET or the substrate in a bipolar junction transistor) can include a backside metal structure. Similarly, in a four-terminal device, the fourth terminal (e.g., a floating body head or a field plate) can include a backside metal structure. Accordingly, the backside exposure of the transistor structure may also include exposing the transistor gate electrode and / or the channel semiconductor. In some embodiments, the backside gate electrode process is used to completely surround the transistor channel having the gate electrode, thereby forming a nanowire transistor having a wraparound gate electrode. Additionally, or in the alternative, the exposed gate electrode may be coupled to a backside interconnect further fabricated on the backside of the tier containing the transistor structure. In some other embodiments, the backside gate electrode process replaces a sacrificial gate mandrel or fixture fabricated during the frontside process. FIG. 17 is a flowchart showing a method 1701 for forming a backside transistor gate electrode according to some embodiments. Method 1701 further illustrates the backside processing of a transistor structure layer that can be no greater than a few hundred nanometers in thickness. Method 1701 begins with a donor-host substrate assembly containing a transistor structure as input 1705. The donor substrate may have one or more of the characteristics described above, such as but not limited to an interlayer and a carrier layer. It is noted, however, that the carrier layer and / or the interlayer are not necessary for performing method 1701. When received at input 1705, the transistor structure may be fully operational, e.g., including three terminals as shown in FIG. 6. Alternatively, one or more terminals (e.g., the gate electrode) may be absent such that the transistor structure will not be operational until the backside processing is complete. At operation 1710, the backside of the transistor gate electrode, the sacrificial gate mandrel, and / or the transistor channel semiconductor are exposed during a backside exposure procedure. In some embodiments, the backside exposure procedure performed at operation 1710 includes one or more of the operations of method 501 (FIG. 5). The backside exposure procedure may expose the semiconductor channel region, for example, by at least removing a portion of the donor substrate (e.g., the carrier layer). At operation 1715, a gate stack is formed from the backside of the device layer. The gate stack may be formed on the backside of the semiconductor channel and may also be formed on the frontside of the semiconductor channel, depending on how much of the channel semiconductor is exposed at operation 1710. Method 1701 ends with an output of a transistor structure layer including gate electrode material disposed on the backside of the transistor channel semiconductor. In some embodiments, method 1701 is facilitated by one or more front-side processing operations. For example, during front-side processing, the depth (e.g., z-dimension position) of a transistor gate electrode or the gate spindle is made greater than the depth of one or more transistor source / drain regions to facilitate exposing the gate electrode or gate spindle from the back side without exposing one or more source / drain regions. To illustrate the synergy between front-side and back-side processing, FIGS. 18A-26A provide cross-sectional views along the A-A' plane represented by the thick dotted line in the plan view of an exemplary transistor structure 604 (FIG. 6) according to some exemplary embodiments. FIGS. 18B-26B show cross-sectional views along the B-B' plane represented by the thick dotted line in the plan view of an exemplary transistor structure 604 when performing front-side transistor processing according to some exemplary embodiments. The front-side transistor processing shown can be performed, for example, upstream of the back-side processing embodiments described elsewhere herein. In the illustrated example, the semiconductor device layer is a transistor fin formed using an additional process. Alternatively, the semiconductor layer can be a transistor fin formed by any subtractive process (e.g., patterning of a continuous semiconductor device layer). In the embodiments shown in FIGS. 18A and 18B, trench 1809 is anisotropically etched into field isolation dielectric 680, exposing a portion of back-side substrate 605 at the bottom of trench 1809. In some embodiments, the exposed portion of back-side substrate 605 is recess-etched as shown. In some embodiments, trench 1809 has a CD between 10 and 200 nanometers. However, when needed, the z-thickness and CD of the trench material can be scaled to maintain a viable aspect ratio for a predetermined fin height selected for a desired transistor current-carrying width. As further shown in FIGS. 19A and 19B, sub-fin semiconductor 1810 is selectively epitaxially grown onto the substrate seed surface to partially backfill trench 1809. In some exemplary embodiments, sub-fin semiconductor 1810 is further used as an intermediate layer (e.g., 210 in FIG. 3A) employed in the subsequent removal of back-side substrate 605. Semiconductor device layer 215 is further epitaxially grown from the sub-fin seed surface as semiconductor body 610 extending from the sub-fin surface still contained within the trench. Device layer 215 and sub-fin semiconductor 1810 can be the same or different compositions. For example, both device layer 215 and sub-fin semiconductor 1810 can be silicon. Alternatively, device layer 215 can be a first semiconductor alloy and sub-fin semiconductor 1810 can be a second semiconductor alloy. After epitaxial fin growth, the surrounding field isolation dielectric 680 can be selectively recessed to a desired level below device layer 215, as further depicted in FIG. 20A. In an illustrative embodiment, field isolation dielectric 680 is recessed sufficiently to fully expose device layer 215 to prepare for the regrowth of raised source / drains. At this point, in the front-side processing, the sub-fin height H sf 、 1 The sub-fin semiconductor 1810 of H is embedded in the field isolation dielectric 680. It is worth noting that the subtractive patterning process in which the fin pattern is etched into the dorsal substrate 605 can substantially complete the same fin structure shown in FIG. 20A. For such an embodiment, the device layer 215 and the sub-fin semiconductor 1810 can be the same semiconductor material (e.g., both silicon), or different semiconductor materials. As shown in FIGS. 21A and 21B, a gate stack mandrel including a sacrificial gate material 2173 (e.g., polysilicon) is formed over the device layer 215 using any conventional technique. The sacrificial gate material 2173 can be formed on at least two sidewalls of the device layer 215 and land on the field isolation dielectric 680. The spacer dielectric 671 can also be formed using any conventional technique. For the embodiment depicted in FIG. 21A, the sacrificial gate material 2173 does not include any portion of the sidewalls of the sub-fin material 110, but it can function as an isolation dielectric recess. After forming the gate mandrel, a doped semiconductor (or any sacrificial material) is formed at the source / drain ends of the semiconductor device layer 215. In some embodiments, the raised source / drain regions are formed by depositing a heavily doped semiconductor suitable for any component of the semiconductor device layer 215. In the exemplary embodiments shown in FIGS. 22A and 22B, an epitaxial process is employed to form a single-crystalline raised source / drain semiconductor 640. Additionally, the field isolation dielectric 680 is then deposited over the raised source / drain semiconductor 640 and planarized with the gate mandrel, as further depicted in FIGS. 23A and 23B. In FIGS. 24A and 24B, the sacrificial gate material 2173 is selectively removed relative to the surrounding field isolation dielectric 680, exposing the semiconductor device layer 215. Any conventional technique can be used to remove the sacrificial gate mandrel. After removing the gate mandrel, the exposed field isolation dielectric 680 can be further selectively recessed into other regions, thereby further exposing at least a portion of the sub-fin semiconductor 1810 within the recess 2470. As shown, after the field isolation dielectric 680 is recessed, this portion of the sub-fin semiconductor 1810 embedded within the field isolation dielectric 680 is lowered into the region of the transistor semiconductor channel H sf,2 . As further shown in FIGS. 25A and 25B, a gate stack including a gate dielectric 845 and a gate electrode 673 is deposited into the recess 2470. Any gate stack backfill process known to be suitable for replacement gate applications can be performed. For a transistor in which the depth extension of the gate electrode is lower than the depth of the device layer, as further shown in FIGS. 26A-26C, 27A-27C, and 28A-28C depicting cross-sectional views along the A-A', B-B', and C-C' planes represented by the thick dotted lines in the plan view of the exemplary transistor structure 604 (FIG. 6), the gate electrode can be exposed from the back side (e.g., during the implementation of method 1101). This technique can be further combined with the exposure of one or more source / drain regions, for example, as described elsewhere herein. FIGS. 26A-26C further illustrate the front-side stack 690 disposed on the front-side cell surface. The front-side stack 690 is shown in dashed lines as part of the transistor structure hierarchy, which can vary without limitation and can, for example, include any number of back-end interconnect metal layers. The main substrate 202 can, for example, have any of the properties described elsewhere herein. As shown, the main substrate 202 is bonded to the front-side surface of the front-side stack 690, for example, by thermocompression bonding. As further shown in FIGS. 26A-26C, at least a portion of the donor substrate has been removed, exposing the back-side surface 2611 of the sub-fin semiconductor 1810. The donor substrate can be thinned and / or removed by any technique, such as but not limited to method 501 (FIG. 5). In method 501, for example, the intermediate layer can be one or more of the sub-fin semiconductor 1810 and the field isolation dielectric 680. Alternatively, the intermediate layer in method 501 can be the topmost layer of the back-side substrate 605. FIGS. 27A-27C depict the transistor structure 604 after the exposure of the back side 2712 of the gate electrode 673. To expose the back side of the gate electrode 673, portions of the sub-fin semiconductor 1810 can be ground back (e.g., CMP) and / or recess etched using wet and / or dry etching procedures, for example, as described above for operation 525 (FIG. 5). This etching procedure can be masked or unmasked. In some exemplary embodiments with high selectivity (e.g., 200-300:1), a CMP slurry of a semiconductor (e.g., Si) with a higher etching rate than the dielectric is employed, and the back-side grinding of the device layer 215 can be stopped when the gate dielectric 845 is exposed. Any amount of over-etching (over-grinding) can be performed. In some embodiments, the entire sub-fin of one or more semiconductor bodies within the transistor structure can be removed during the back-side exposure operation. In the exemplary embodiment shown in FIGS. 27A-27C, the gate electrode 673 is exposed before the source / drain semiconductor 640 is exposed, and the exposure procedure is stopped before the source / drain semiconductor 640 is exposed. For some embodiments, the backside metal is deposited on the backside surface of the gate electrode 673. For example, a low-power logic state signal can be transmitted from other transistor structures of the IC to the transistor structure 604 through the backside metal contacting the gate electrode 673. Thus, the backside metal can provide an interconnection for either or both of the source / drain and the gate electrode between transistor structures. In some other embodiments, the gate electrode 673 expands from the backside to form a nanowire or gate-all-around (GAA) transistor, where the gate electrode surrounds the semiconductor body on all sides. For such embodiments, the backside of the semiconductor device layer 215 is exposed, and a backside gate stack is deposited on the backside of the semiconductor device layer 215 and interconnected with the gate electrode 673. Figures 28A - 28C further depict the transistor structure 604 after the deposition of a backside gate stack including a backside gate dielectric 2845 and a backside gate electrode 2873. As shown in this embodiment, the backside gate stack is directly deposited on the exposed surface of the semiconductor device layer 215. As shown in Figures 28A - 28C, to expose the device layer 215, any remaining portions of the sub-fin semiconductor 1810 can be selectively etched (e.g., using wet or dry chemical etching), and the backside surface of the semiconductor fin can be recessed relative to the backside surface of the gate electrode 673 and / or the field isolation dielectric 680. For embodiments where the sub-fin semiconductor 1810 has a different composition from the device layer 215, the recess etching can be further selective for the device layer 215 and effectively stop when the device layer 215 is exposed. For embodiments where the sub-fin semiconductor 1810 has the same composition as the device layer 215 (e.g., both are silicon from fins patterned from the device layer), the recess etching can be of a predetermined fixed duration or can be stopped at the impurity dopant interface. The backside gate dielectric 2845 is deposited on or over the exposed device layer 215. The backside gate dielectric 2845 is another example of a non-native material deposited on the backside of a transistor semiconductor region. The backside gate dielectric 2845 can be any dielectric material known to be suitable for a field-effect transistor. In some exemplary embodiments, the backside gate dielectric is any of the materials described elsewhere herein for the gate dielectric 845 and can be the same material. The back gate electrode 2873, which can be deposited on the back gate dielectric 2845 and / or directly on the exposed surface of the gate electrode 673, is another example of a non-native material deposited on the back side of the transistor semiconductor region. The back gate electrode 2873 can be any doped semiconductor or metal known to be suitable for gate-controlled field effect transistors. In some exemplary embodiments, the back gate electrode 2873 is the material described elsewhere herein for the gate electrode 673 and can be the same material. For some embodiments of nanowire transistors, the back gate electrode 2873 can be deposited on the back gate dielectric 2845 and planarized (e.g., by CMP) with the surrounding back side surface of the gate electrode 673. In some embodiments, a subsequent back side metal layer (not depicted) is deposited to contact directly the gate electrode 673 and the back gate electrode 2873, as an interconnect between the gate electrode 673 and the back gate electrode 2873 and / or other IC nodes within other transistor structures. With the gate electrodes 2873 and 673 connected together at the same potential, the channel region of the FET can be fully depleted. In an alternative embodiment, the front gate electrode is independent of the back gate electrode. Such an independent back gate electrode is controllable to one of a plurality of predetermined voltage levels, each associated with a predetermined threshold voltage (V t ) of the transistor. By virtue of the ability to set different threshold voltages, the transistor becomes a multi-state device (i.e., having multiple states as compared to on / off). In some such embodiments, the potential of the back gate electrode is controlled through a back side interconnect metal that does not also contact the (front side) gate electrode. Similarly, the front gate electrode can be controlled by a front side interconnect metal, such as disposed within the front side stack, thereby implementing a four-terminal device. This dual-gate transistor structure can be easily fabricated according to method 170. For example, further referring to the front-side processing shown in FIGS. 18A-24A, the recess of the exposed field isolation dielectric 680 after the removal of the gate mandrel shown in FIG. 24A can be omitted, thereby avoiding any exposure of the sub-fin semiconductor 1810 within the recess 2470. For such an embodiment, the gate electrode 673 will then not extend along the sidewalls of the sub-fin semiconductor 1810 in the manner shown in FIG. 25A. Instead, the depth of the gate electrode 673 will be substantially coplanar with the interface of the device layer 215 and the sub-fin semiconductor 1810. The sub-fin semiconductor 1810 can then be selectively recessed or backgrinded by a predetermined amount without exposing the backside of the gate electrode 673. As further shown in FIGS. 28D, 28E, and 28F, for example, the sub-fin semiconductor 1810 has been selectively recessed from the backside of the field isolation dielectric 680. The resulting backside recess has been backfilled with a backside gate stack (gate dielectric 2845 and gate electrode 2873). A backside metal layer (not depicted) deposited directly in contact with the backside gate electrode 2873 will then be electrically isolated from the gate electrode 673. In some embodiments, the backside of the transistor gate mandrel is exposed. For such an embodiment, the gate mandrel can be fabricated using front-side transistor processing, such as using any known technique. The mandrel can then subsequently be exposed and replaced with a permanent gate electrode during backside processing. Thus, the performance of the backside processing can be relative to the front-side processing operations to delay the formation of one or more transistor device regions, e.g., until after the front-side interconnect metal layer and the interlayer dielectric (ILD) have been formed. Higher temperature processing can thus be performed prior to temperature-sensitive processing, potentially increasing the thermal margin of the transistor structure. For transistors in which the gate spindle depth extends below the depth of the device layer, as further shown in FIGS. 29A-29C, 30A-31C, and 32A-32C depicting cross-sectional views along the A-A', B-B', and C-C' planes represented by the thick dotted lines in the plan view of the exemplary transistor structure 604 (FIG. 6), the gate spindle can be exposed from the back side (e.g., during the implementation of method 1101). The transistor structures shown in FIGS. 29A-29C are substantially the same as the transistor structures shown in FIGS. 27A-27C. Thus, the transistor structures shown in FIGS. 29A-29C can be fabricated using front-side processing substantially as described for FIGS. 18A-25A, except that the gate electrode 673 and / or the gate dielectric 845 will subsequently be replaced with a sacrificial spindle. Thus, the gate electrode 673 and / or the gate dielectric 845 can have a composition selected for preferential etching of the semiconductor device layer 215. For example, the gate electrode 673 can have the same composition as the sacrificial gate material 2173 (e.g., polysilicon), where the semiconductor device layer 215 is not silicon (e.g., SiGe, III-V, or III-N). Alternatively, when the semiconductor device layer 215 is silicon, the gate electrode 673 can be another polycrystalline semiconductor, such as but not limited to SiGe or Ge. If also sacrificial, the gate dielectric 845 can be, for example, silicon dioxide. If not also sacrificial, the gate dielectric 845 can be, for example, a high-k material, such as any of those described above. FIGS. 29A-29C depict the transistor structure 604 after the back side 2912 of the (sacrificial) gate electrode 673 is exposed. Portions of the fin semiconductor 1810 can be polished back (e.g., CMP) and / or recess etched using wet and / or dry etching procedures, e.g., as described above for operation 525 (FIG. 5). In some exemplary embodiments with high selectivity (e.g., 200-300:1), a CMP slurry of a semiconductor (e.g., Si) with a higher etching rate than the dielectric is employed, and the backside polishing can be stopped when the (sacrificial) gate dielectric 845 is exposed. In some alternative embodiments performing dry or wet semiconductor etching, the etching can be stopped when the gate dielectric 845 is exposed. Any amount of over-etching (over-polishing) can be performed. In some embodiments, the entire fin of one or more semiconductor bodies within the transistor structure can be removed during the back side exposure operation. In the exemplary embodiment shown, the gate electrode 673 is exposed before the source / drain semiconductor 640 is exposed, and the exposure procedure is stopped before the source / drain semiconductor 640 is exposed. The gate electrode 673 is then removed using a selective etching process to form the void 3040 shown in FIGS. 30A - 30C. Any etching process known for etching (sacrificing) the gate electrode 673 can be employed. For example, a polysilicon etchant, a SiGe etchant, or a Ge etchant can be used to isotropically remove the gate electrode 673. After removal, the exposed surface of the semiconductor device layer 215 can then be covered with a permanent gate electrode stack. As further shown in FIGS. 31A - 31C, the back - side gate stack is directly deposited on the exposed surface of the semiconductor device layer 215. To fully expose the device layer 215, any remaining portions of the sub - fin semiconductor 1810 can be selectively etched (e.g., using wet or dry chemical etching) to recess the back - side surface of the semiconductor fin relative to the back - side surface of the field isolation dielectric 680. For embodiments where the sub - fin semiconductor 1810 has a different composition from the device layer 215, the recess etching can be further selective to the device layer 215 and effectively stop when the device layer 215 is exposed. For embodiments where the sub - fin semiconductor 1810 has the same composition as the device layer 215 (e.g., both are silicon from fins patterned from the device layer), the recess etching can be for a predetermined fixed duration. The back - side gate dielectric 2845 and the back - side gate electrode 2873 are then deposited on or over the exposed device layer 215 substantially as described above. It should be noted that even if the front - side and back - side gate stacks both employ the same gate stack materials, various structural features can, according to some embodiments herein, completely distinguish the nanowire transistor structures fabricated entirely from the front - side from those fabricated using back - side processing. For example, the presence of the back - side gate dielectric 2845 on portions of the device layer 215 that extend beyond the channel region contacted by the front - side gate dielectric 845 indicates that the back - side gate stack deposition and patterning processes are self - aligned to structures not used for the front - side patterning of the gate stack. Similarly, differences in the extent or position of the back - side gate electrode 2873 relative to the front - side gate electrode 673 indicate the back - side fabrication process. For example, as shown in both FIGS. 28A and 31A, when the recess is self - aligned to the semiconductor body, the back - side gate electrode 2873 extends greater than the longitudinal length of the gate electrode 673, but is approximately equal to or slightly less than the longitudinal length of the semiconductor device layer 215 fin length L f of the back - side surface of the semiconductor device layer 215. The backside processing of the exposed portion of the device layer can include the deprocessing and / or replacement of other transistor structures formed during the frontside manufacturing process. During such deprocessing, one or more materials deposited or structures formed during frontside processing can be removed during backside processing after such materials and / or temporary structures or mandrels are no longer needed in device manufacturing, and / or their residues as components of the device are not optimal for device operation. For example, sidewall spacer dielectrics are typically employed during frontside transistor processing to facilitate self-alignment of transistor features and / or prevent electrical shorts between adjacent features. However, such sidewall spacer dielectrics are not optimal for device operation, such as causing parasitic capacitance. Backside deprocessing can thus subsequently remove such spacer dielectrics from the device structure and improve device operation. Once removed, the spacer dielectric can be replaced with another material more favorable for device operation, or the void where the spacer dielectric was removed can be left as an artifact within the transistor layer. In some advantageous embodiments, the spacer dielectric employed in frontside processing is replaced during backside processing with another dielectric having a relative dielectric constant lower than that of the spacer dielectric. Generally, low-k materials are prone to damage when exposed to subsequent processes such as plasma etching. Thus, a high-k material as the spacer dielectric during frontside manufacturing can be advantageous. However, if retained in the transistor layer, this high-k material will increase the parasitic capacitance of the device during operation. After backside exposure according to some embodiments, the higher-k material is replaced with a low-k material. Backfilling with the low-k material can then avoid any damage associated with exposure to front-end processing. FIG. 32 is a flowchart of a backside processing method 3201 showing the removal of sidewall spacer dielectrics according to some embodiments. Method 3201 further illustrates the backside processing of a device (e.g., transistor structure) tier that may be no more than a few hundred nanometers in thickness. Method 3201 begins with an input 3205 of a donor-host substrate assembly that includes a device layer. The donor substrate can have one or more of the features described above, such as but not limited to an intermediate layer and a carrier layer. It is noted, however, that the carrier layer and / or the intermediate layer are not required to perform method 3201. At operation 3210, the backside of the device layer or the intermediate layer is exposed during backside exposure. In some embodiments, the backside exposure process performed at operation 3210 includes one or more of the operations of method 501 (FIG. 5). For example, the backside exposure procedure can expose the device layer or the intermediate layer by at least removing a portion of the donor substrate (e.g., the carrier layer). Figures 33A - 33C, 34A - 34C, 35A - 35C, and 36A - 36C depict cross-sectional views along the A - A', B - B', and C - C' planes represented by the thick dotted lines in the plan view of the exemplary transistor structure 604 (FIG. 6). The transistor structures shown in FIGS. 33A - 33C are substantially the same as those shown in FIGS. 10A - 10C after the backside exposure process that exposes the backside 1012 of the semiconductor body 610. In some embodiments, the transistor structures shown in FIGS. 33A - 33C can be fabricated using any frontside processing known to be suitable for manufacturing finFETs. In some embodiments, once the semiconductor body 610 is formed by any known technique, the frontside processing is carried out as described above in the context of FIGS. 20A - 25A. Figures 33A - 33C further depict the locations where dielectric sidewall spacers can be found for some illustrative embodiments. In FIG. 33A, the spacer dielectric 671 is disposed at the lateral ends of the gate electrode 673. Such sidewall spacers can be formed in embodiments where the spacer dielectric is deposited after the (sacrificial) gate electrode has been fully patterned. For example, the spacer dielectric is deposited at the end after the sacrificial gate material 2173 has been patterned (FIGS. 21A, B). Alternatively, if the sidewall spacer dielectric is deposited before such patterning, the spacer dielectric 671 may only appear on the longitudinal sidewalls of the gate electrode 673 as shown in FIG. 33B. The spacer dielectric may have been deposited for the purpose of forming self-aligned spacers along the sidewalls of the gate electrode that mark the boundary between the transistor channel and the source / drain regions. However, due to the non-planarity in the semiconductor body, self-aligned spacers can also be formed along one or more sidewalls of the semiconductor body as an artifact of the frontside processing. For example, FIG. 33C shows the spacer dielectric 671 further disposed along the sidewalls of the semiconductor body 610. Figures 34A - 34C further show how the backside exposure process can continue to completely remove the intermediate layer and expose the backside of the semiconductor body 610. It is noted that such removal can be carried out using a masking process and / or other selective techniques such that only the backside portion is exposed. To complete the structures shown in FIGS. 34A - 34C, for example, backside etching or CMP polishing through the (sub-fin) portion of the semiconductor body 610 can be performed for a predetermined time or terminated upon detection of one or more of the source / drain semiconductor 640, spacer dielectric 671, gate dielectric 845, gate electrode 673. As shown in FIGS. 34A - 34C, the exposure of the device layer also exposes the spacer dielectric 671 disposed between the gate electrode 673 and the source / drain semiconductor 640 and / or the source / drain metal 650. Returning to FIG. 32, method 3201 continues at operation 3220 to etch at least a portion of the exposed dielectric spacer. Ideally, the spacer dielectric etch is highly selective to the target dielectric material and does not significantly affect the surrounding semiconductors, dielectrics, and / or metals that are also exposed on the backside. In some embodiments, the dielectric spacer is removed using isotropic etching (e.g., wet chemical etching or plasma etching). For example, wet chemical etching can isotropically remove a spacer dielectric that includes one or more of silicon nitride (SiN), carbon-doped silicon (SiC), or carbon-doped silicon nitride (SiCN). In the example shown in FIGS. 35A - 35C, the removal of the spacer dielectric 671 is selective to the gate stack that includes the gate electrode 673 and the gate dielectric 845 that form the spacer recess 3512. Continuing with FIG. 32, at operation 3220, the recess formed from the deprocessing of the dielectric spacer can be backfilled with another material (e.g., a low-k dielectric), or alternatively sealed using any suitable dielectric material to incorporate one or more air gaps or voids into the transistor layer. In some advantageous embodiments, the dielectric material deposited at operation 3230 has a lower relative dielectric constant than the material removed at operation 3220. In some such embodiments, the dielectric material deposited at operation 3230 has a relative dielectric constant less than 4.5, advantageously less than 3.9, and more advantageously less than 3.5. For some embodiments where the voids are sealed, the dielectric material can be deposited using any non-conformal deposition technique, such as but not limited to physical vapor deposition (sputter deposition) or some chemical vapor deposition. Voids with a sufficiently high aspect ratio will then be sealed by the non-conformal dielectric material. In the example shown in FIGS. 36A - 36C, the backside dielectric 3671 backfills the spacer recess 3512 (FIGS. 35A - 35C). The backside dielectric 3671 can be any material known to have a low relative dielectric constant (e.g., less than about 4.5). Exemplary materials include SiOC, SiOCH, HSQ, or MSQ. The deposition technique can be any known technique suitable for backfilling the recess with the selected material, such as but not limited to chemical vapor deposition (CVD) and spin coating procedures. In the example shown in FIGS. 35A - 35C, the backside dielectric 3671 also covers the backside surfaces of the semiconductor body 610 and the source / drain semiconductors 640. If desired, the backside dielectric 3671 can subsequently be planarized with the backside surface of the semiconductor body 610. In another example shown in FIGS. 37A - 37C, the backside dielectric 3671 has insufficient conformality to backfill the high aspect ratio spacer recesses 3512 (FIGS. 35A - 35C), but closes the openings of the recesses to form voids 3771. The voids 3771 can then be permanently retained as a structural feature of the transistor structure 604. The method 3201 (FIG. 32) then substantially completes with the output 3240 of a device structure that includes low - k spacers and / or air gaps surrounding one or more transistor structures such as gate electrodes and / or semiconductor bodies. Any front - side device structure can be removed and / or replaced substantially as described in the context of the replacement of the above dielectric spacers. Depending on the device manufacturing process in which the backside processing is performed, sacrificial anchors of any part of a device layer (e.g., a transistor channel region) or a terminal (e.g., a transistor gate electrode or a transistor source / drain semiconductor and / or metal) can be exposed during the backside processing, selectively removed at least partially from the surrounding structures, and backfilled with a suitable replacement material. In some embodiments, for example, sacrificial device terminal materials (e.g., any suitable dielectric) can be formed during the front - side processing to facilitate their subsequent selective removal during the backside processing. Once removed, the terminal semiconductor (e.g., a transistor source / drain semiconductor) and / or metal (e.g., a transistor source / drain contact metal) can be deposited in the resulting recesses. The front - side device processing can then follow examples where various structures are fabricated to facilitate their subsequent exposure during the backside processing. For example, during the front - side processing, the depth (z - height) of the sacrificial structures to be removed from the backside can be made deeper than the non - sacrificial structures that will not be removed through the backside, such that the sacrificial structures are exposed earlier during the backside exposure process and can then be selectively replaced. Thus, any front - side structure (e.g., a transistor gate electrode, a source / drain contact metal, etc.) described elsewhere herein can be sacrificial and ultimately replaced during the backside processing. However, various structures fabricated during the front - side processing to facilitate their subsequent exposure during the backside processing need not be sacrificial. During the front - side processing, the depth (z - height) of a non - sacrificial structure (e.g., a source or drain semiconductor, a gate electrode, or a source / drain contact metal) that is in electrical contact through the backside can be made deeper than another non - sacrificial structure (e.g., a source or drain semiconductor, a gate electrode, or a source / drain contact metal) that is not in electrical contact through the backside. During the backside exposure process, the deeper structure is exposed before the shallower structure. Thus, any front - side structure (e.g., a transistor gate electrode, a source / drain semiconductor, or a contact metal, etc.) described elsewhere herein can be sacrificial and ultimately replaced during the backside processing, or non - sacrificial and ultimately contacted during the backside processing. It should be noted that any of the above backside exposure techniques and device architectures can be implemented globally over the entire wafer area or selectively over a subset of regions on the wafer. In some embodiments, a masking exposure technique can be employed to selectively expose regions of the non-planar power transistor structure to regions of the non-planar logic transistor structure, or vice versa. Additionally, the selective exposure process can be within a single device structure (e.g., on a per-cell basis), can be across multiple device structures (e.g., on an inter-cell basis), or on any regional basis. The device layer selectivity of the backside exposure process is facilitated by the permanent bonding and rigidity of the host-substrate architecture, e.g., as described above. The device layer selectivity of the backside exposure process is also facilitated by the adoption of highly selective exposure techniques, e.g., also as described above. Such selective exposure processing can provide a distinction between logic and power transistors or between any other types of transistors (e.g., RF and logic, memory access transistors and logic, planar and non-planar transistors, etc.). Exemplary embodiments further show the selective exposure techniques in the context of some of the above-described double-sided transistor architectures introduced above. These same techniques can be similarly applied to selectively fabricate stacked front / backside devices within some regions of other regions of the fabrication substrate (e.g., the wafer). FIG. 38A is a flowchart showing a backside exposure method 3801 according to some embodiments. For example, method 3801 can be employed to remove at least a portion of the carrier layer, an intermediate layer (if present), and / or a portion of the device layer of the donor-host substrate assembly to selectively expose the device layer or device region for backside processing. The device region can be any suitable material, such as semiconductor, metal, or dielectric. As described elsewhere herein, the exposure of the device region can provide backside contact to the device region for backside access to remove the device region or portions thereof, etc. As shown in FIG. 38A, method 3801 begins at the input of the donor-host substrate assembly at operation 3805. In some embodiments, the donor-host substrate assembly received at operation 3805 is donor-host substrate assembly 203 (refer to FIG. 3B). However, the donor-host substrate assembly received at operation 3805 can be any suitable donor-host substrate assembly discussed herein. The donor-host substrate assembly can include any suitable structure. In an embodiment, method 3801 provides techniques for manufacturing an integrated circuit, and the donor-host substrate assembly includes a substrate having a front-side device layer (e.g., a semiconductor device layer) on a back side layer. The device layer includes a first device region of a first device and a second device region of a second device. The first and / or second device regions can be any semiconductor, metal, or dielectric material or structure, such as a channel semiconductor, a source / drain semiconductor, a source / drain metal, a gate metal, a dielectric layer or material, or the like. The first device and the second device can be of the same type of device, or they can be different. Such a difference between the first and second devices can be functional, structural, or both. For example, the first and / or second devices can be any combination of logic transistors, memory transistors, power transistors, n-type transistors, p-type transistors, planar transistors, non-planar transistors, or the like. Additionally, the first device and the second device can be in the same architectural unit of the integrated circuit (e.g., such that the back-side exposed region within the unit is the same for each of many identical units), or they can be in different units of the integrated circuit (e.g., such that the back-side exposed region between units occurs between different units). Further, the first device region of the first device and the second device region of the second device can be the same or they can be different. For example, the first and / or second device regions can be any combination of a channel semiconductor, a source / drain semiconductor, a source / drain metal, a gate metal, a dielectric layer or material, or the like. In method 3801, the back side of the first device region is selectively exposed for the second device region by removing at least a local thickness of the aforementioned back side layer. Such selective exposure can advantageously provide access to the first device region via the back side while not exposing the second device region (i.e., protecting the second device region) for further processing. For example, further processing can thus be selectively applied to the first device region rather than the second device region. The selective back-side exposure of the back side of the first device region can be provided using any suitable technique or techniques, such as a masking exposure technique, a blanket exposure technique, or both. In an embodiment, a patterned mask is formed on the back side layer such that the patterned mask protects the back side of the second device region. Recesses are etched in the unmasked portion of the back side layer to expose the first device region while the second device region is protected by the patterned mask. The removed portion of the back side layer can be part of an intermediate layer and / or the device layer. Such techniques are further discussed herein with respect to FIGS. 38B and 39 - 45. In an embodiment, a complete dorsal removal of the dorsal layer is performed to expose the dorsal side of the front-side semiconductor device layer. A patterned dielectric hard mask layer is formed on the dorsal side of the front-side semiconductor device layer such that the patterned dielectric hard mask layer protects the dorsal side of the second device region. A recess is etched at least a partial thickness of the front-side semiconductor device layer in the unmasked portion of the front-side semiconductor device layer to expose the first device region, while the second device region is protected by the patterned dielectric. In this technique, the patterned dielectric hard mask layer can be retained after processing to provide isolation dielectric between devices. For example, the patterned dielectric hard mask layer can be an oxide or a nitride or the like. This technique is discussed herein with respect to FIGS. 38C and 46-54. In an embodiment, a partial thickness of the dorsal layer is removed across both the first device region of a first device and the second device region of a second device to expose the dorsal side of the first device region. For example, when a blanket is provided for an integrated circuit, the first device region of the first device and the second device region of the second device exposing the front-side semiconductor device layer may have structural differences such that the first device region is selectively exposed with respect to the second device region. This technique can include any operation or structure discussed herein. For example, as described above with respect to FIGS. 17 and 24-34, a structural feature differentiation of gate electrodes can be employed to selectively expose a subset of gate electrodes from the dorsal side of the device layer. For example, a first gate electrode of a first non-planar device (e.g., the first device region) can extend deeper into or through the device layer than a gate electrode of a second non-planar device (e.g., the second device region) such that, upon blanket exposure (e.g., planar processing), the first gate electrode is exposed while the second gate electrode is not exposed. As shown in FIG. 38A, method 3801 provides various processing branches for providing backside exposure and related techniques for a received donor-host substrate assembly. For example, operations 3820, 3850, 3825, and 3855 are shown as being coupled through a dashed line within a given level (e.g., L2) and through a solid line between two levels (e.g., L2 and L3) to illustrate various permutations possible. The selection of such processing branches can be (at least in part) based on the received donor-host substrate assembly, the desired structure to be manifested, and / or the desired processing to be performed on the backside exposed structure. As shown, a first level (e.g., L1) of method 3801 (e.g., operations 3810 and / or 3815) can include wafer-level full backside exposure, partial backside exposure, or both. The first level can provide for backside exposure techniques. A second level (e.g., L2) of method 3801 (e.g., operations 3820 and / or 3850) can include unit-level differentiation provided by the implemented exposure technique. The second level can provide exposure on an inter-unit basis, an intra-unit basis, or both (represented by dashed lines). A third level (e.g., L3) of method 3801 (e.g., operations 3825 and / or 3858) can include exposure types for partial backside exposure. The third level can provide for exposure types that will be masked exposure, blanket exposure, or both. All of these exposure types can be employed to achieve either inter-unit differentiation or intra-unit differentiation, as represented by the cross solid line connection between L2 and L3. Additionally, the third level can provide a basis for differentiating the exposure. For example, the exposure can be based on the functionality of the selectively exposed device, the structure of the selectively exposed device, or both. A fourth level (e.g., L4) of method 3801 (e.g., operations 3830, 3835, and / or 3840) can provide for functionality and / or structural differentiation options for the devices exposed by operations 3825 and / or 3858. For example, the exposure of the devices can be performed selectively based on whether the device is a logic, memory, or power device, based on whether the device is n-type or p-type, based on whether the device is non-planar or planar, or any combination thereof. As shown, method 3801 includes a branch from operation 3805 through operation 3810 to operation 130, which provides an output for a device layer - host substrate assembly. Operation 3810 provides a wafer - level full backside exposure of the received donor - host substrate assembly to provide the device layer - host substrate assembly at operation 130. This wafer - level full backside exposure technique has been discussed with respect to FIG. 5 and elsewhere in this document. For example, wafer - level full backside exposure can include grinding and / or etching through the thickness of the carrier layer, detecting the intermediate layer, and grinding and / or etching through the thickness of the intermediate layer. As the name implies, this processing is performed on the entirety of the received donor - host substrate assembly without masking or the like. In an embodiment, wafer - level full backside exposure is performed to expose the intermediate layer. In an embodiment, wafer - level full backside exposure is performed to expose the backside of the device layer. In an embodiment, the received donor - host substrate assembly does not include a carrier layer, and wafer - level full backside exposure removes the thickness or entirety of the intermediate layer. In an embodiment, wafer - level full backside exposure exposes the intermediate layer and / or the device layer such that further processing (e.g., masking or blanket exposure processing) is performed to selectively expose a first device region of a first device to a second device region of a second device. In an embodiment, wafer - level full backside exposure selectively exposes a first device region of a first device to a second device region of a second device as discussed above. For example, this wafer - level full backside exposure for selective device region exposure can be based on the structural differences between the first and second devices such that during the wafer - level full backside exposure process, the first device region is exposed while the second device region of the second device is not exposed after this processing. Also as shown, operations 3810 and 3815 connected by hatching, in some embodiments, the wafer - level full backside exposure provided by operation 3810, such as, can be after a partial backside exposure at operation 3815. For example, the wafer - level full backside exposure of the received donor - host substrate assembly at operation 3810 can expose the intermediate layer and / or the device layer (e.g., but not the device regions) and the partial backside exposure at operation 3815 via any of the branches shown can provide an exposure of the device layer or a portion thereof (e.g., a device region that will be selectively exposed to another device region). An example of such a wafer - level full backside exposure followed by a partial backside exposure is shown with respect to FIG. 38C and elsewhere in this document. Method 3801 also includes various branches from operation 3805 starting at operation 3815 (or the operation 3810 under discussion). At operation 3815, local dorsal exposure is set or initiated. This local dorsal exposure can provide a range of dorsal exposure options. In an embodiment, the dorsal exposure is based on the layout of the regions of the donor-host substrate assembly. For example, the dorsal exposure can provide selective exposure based on inter-cell exposure at operation 3820, intra-cell exposure at operation 3850, regional exposure (not shown), or the like. In this case, a cell is the smallest functional unit within a device layer. For example, a transistor cell includes one transistor, a 1T-1R memory cell includes one transistor and one resistor, and a 1T-1C memory cell includes one transistor and one capacitor. For a cell that includes passive devices (such as a resistor or a capacitor), the inter-cell exposure at operation 3820 can expose only the active device (e.g., the transistor), only the passive device, or both the active and passive devices, for example, as a function of their relative positions within the cell. The inter-cell dorsal exposure differentiation provided at operation 3820 provides dorsal exposure of the device regions within certain cells while leaving the device regions within other cells covered (or non-exposed). The device regions exposed within a cell can be any suitable one or more regions, such as channel semiconductor, source / drain semiconductor, source / drain metal, gate metal, dielectric layer or material, or the like. In some embodiments, as shown at operation 3825, this inter-cell dorsal exposure differentiation is set using a masked exposure technique. In other embodiments, as shown at operation 3858, this inter-cell dorsal exposure differentiation is set using a blanket exposure technique. Continuing at operation 3825, this inter-cell masking and revealing technique can provide a functional and / or structure-based differentiation such that the devices corresponding to the revealed device regions have different functionality and / or different structures from the devices having non-revealed device regions. As shown with respect to operations 3830, 3835, and 3840, this functional and / or structure-based differentiation can correspond to revealing only the device regions of transistors or other devices in various contexts. As shown with respect to operation 3830, the inter-cell functional and / or structure-based differentiation can correspond to selectively revealing only the device regions of logic transistors for the device regions of memory and / or power transistors, selectively revealing only the device regions of memory transistors for the device regions of logic and / or power transistors, selectively revealing only the device regions of power transistors for the device regions of logic and / or memory transistors, or the like. In some embodiments, this differentiation can be based on the design rules of the devices, the critical dimensions of the devices, or the like. As shown with respect to operation 3835, the inter-cell functional and / or structure-based differentiation can correspond to selectively revealing only n-type transistors for the device regions of p-type transistors, or vice versa. As shown with respect to operation 3840, the inter-cell functional and / or structure-based differentiation can correspond to selectively revealing only non-planar transistors (e.g., fin transistors) for the device regions of planar transistors, or vice versa. In addition, as shown with respect to operations 3830, 3835, and 3840 with the hatched connections, a differentiation in this combination of logic / memory / power revealing, n-type / p-type revealing, and non-planar / planar revealing is available. For example, the device regions of a logic n-type planar device can be selectively revealed for memory / power n-type planar devices, logic p-type planar devices, logic n-type non-planar devices, memory / power p-type planar devices, memory / power p-type non-planar devices, etc. By way of illustration, but as another example, the device regions of a power p-type planar device can be selectively revealed for logic / memory p-type planar devices, power n-type planar devices, power p-type non-planar devices, logic / memory n-type planar devices, or logic / memory n-type non-planar devices. For example, this selectivity can be provided in any permutation between device functional types (e.g., select from logic / memory / power), polarities (e.g., select from n-type / p-type), and / or device structures (e.g., select from planar / non-planar). In addition, additional options are available, such as differentiations between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. By way of example, device regions can be selectively revealed based on any suitable combination of functionality, type, structure, or other suitable characteristics. Returning to the third level of method 3801, as shown in operation 3855, the inter-cell backside exposure differentiation can be provided using a blanket exposure technique, where the selectivity of the exposure is a function of the structural differences in the device features created by the front-side processing. This blanket exposure technique can include grinding and / or etching through the thickness of one or more intermediate layers and / or the thickness of the device layer to expose the first device region while not exposing the second device region. This blanket exposure process is performed over the entirety of the intermediate layer and / or the device layer without masking. In an embodiment, the blanket exposure process selectively exposes the first device region of the first device with respect to the second device region of the second device based on the first device region being located in the area exposed by this blanket exposure process and the second device region being located in the area not exposed by this blanket exposure process. For example, the first device region or a portion thereof can extend below the second device region (e.g., in the direction towards the backside), such that in a planar operation or an etching operation, the first device region is exposed before the second device region. When the first device region is exposed and the second device region is not exposed, the blanket exposure process can be stopped (e.g., based on timing or marking, etc.). As shown in operation 3855, the selective blanket exposure process can depend on the structural differences between the first device and the second device with respect to the first device region and the second device region. The structural differences can be, for example, the first device region extending below the second device region as discussed, a material difference between the first and second device regions, or the like. In addition to the structural differences for backside exposure (e.g., backside exposure structural differences), the first and second devices can have any suitable functionality and / or other structural differences to provide inter-cell differentiation. For example, such backside exposure structural differences can be provided between different functional transistors, such that the first device (e.g., having the first device region that will be backside exposed) is a logic transistor, while the second device (e.g., having the second device region that is not exposed) is a memory or power transistor. In an embodiment, the backside exposure structural differences can be provided between transistors of different polarities, such that the first device (e.g., having the first device region that will be backside exposed) is an n-type transistor, while the second device (e.g., having the second device region that is not exposed) is a p-type transistor, or vice versa. In an embodiment, the backside exposure structural differences can be provided between transistors of different device structures, such that the first device (e.g., having the first device region that will be backside exposed) is a non-planar transistor, while the second device (e.g., having the second device region that is not exposed) is a planar transistor, or vice versa. In an embodiment, the backside exposure structural differences can be provided in devices with the same functionality, polarity, and / or other aspects of the structure. For example, as shown with respect to operations 3830, 3835, and 3840, the backside exposure structure differences can be provided in any permutation across device functional types (e.g., from logic / memory / power selection), polarities (e.g., from n-type / p-type selection), and / or device structures (e.g., from planar / non-planar selection). Additionally, additional options are available, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions can be selectively exposed based on any suitable combination of functionality, type, structure, or other suitable characteristics. Turning now to the intra-cell backside exposure differentiation provided at operation 3850, this intra-cell exposure provides backside exposure of one or more device regions of one or more specific devices while other regions of other devices within the same cell are not exposed (e.g., remain covered from the backside). The exposed device regions can be any suitable regions, such as channel semiconductor, source / drain semiconductor, source / drain metal, gate metal, dielectric layer or material, or the like. Additionally, as shown with respect to the hatched connections of operations 3820 and 3850, this inter-cell and intra-cell exposure differentiation can be used together in various combinations. For example, a differentiation can be provided such that no device regions of a first cell are exposed while specific device regions of a second cell are exposed. This differentiation provides an inter-cell differentiation between the first and second cells. Additionally, within the second cell, specific device regions of a first device are exposed while device regions of a second device are not exposed. This differentiation between the first and second devices within the second cell provides an intra-cell differentiation between the first and second devices of the second cell. Although discussed with respect to the differentiation between two cells and one cell with two device types, this differentiation can be set at the inter-cell level between any number of cell types, as well as at the intra-cell level between different exposed cells that are being differently exposed on a per-cell basis. For example, one of three cell types can be not exposed at all while the second and third may be exposed such that all devices within the second cell type have exposed device regions when an intra-cell differentiation is provided within the third cell (e.g., some devices in the third cell are not exposed while other devices have exposed device regions). In some embodiments, as shown at operation 3825, masked exposure techniques facilitate dorsal exposure differentiation. Additionally, such masked exposure techniques can provide functionality-based and / or structure-based differentiation such that devices corresponding to the exposed regions have different functionality relative to devices having unexposed regions. For example, as shown with respect to operation 3830, functionality-based and / or structure-based differentiation within a cell can correspond to selectively exposing the device regions of logic transistors only for device regions of memory and / or power transistors, selectively exposing the device regions of memory transistors only for device regions of logic and / or power transistors, selectively exposing the device regions of power transistors only for device regions of logic and / or memory transistors, or the like. In some embodiments, such differentiation can be based on device design rules, device critical dimensions, or the like. As shown with respect to operation 3835, functionality-based and / or structure-based differentiation within a cell can correspond to selectively exposing the device regions of n-type transistors only for device regions of p-type transistors, or vice versa. As shown with respect to operation 3840, functionality-based and / or structure-based differentiation within a cell can correspond to selectively exposing the device regions of non-planar transistors (e.g., fin transistors) only for device regions of planar transistors, or vice versa. Additionally, as discussed with respect to inter-cell differentiation and as shown by the hatching connecting operations 3830, 3835, and 3840, the differentiation among such combinations of logic / memory / power exposure, n-type / p-type exposure, and non-planar / planar exposure is based on the basis available within the cell. For example, such selectivity can be provided in any permutation among device function types (e.g., selected from logic / memory / power), polarities (e.g., selected from n-type / p-type), and / or device structures (e.g., selected from planar / non-planar). Additionally, additional options are available, such as differentiation among device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions can be selectively exposed based on any suitable combination of functionality, type, structure, or other suitable characteristics. Referring again to the third level of method 3801, as shown at operation 3855, the backside exposed region within the cell can be provided using a blanket exposure technique. As discussed, such a blanket exposure technique can include grinding and / or etching through the thickness of one or more intermediate layers and / or the thickness of the device layer to expose the first device region without exposing the second device region. The blanket exposure process can selectively expose the first device region of the first device to the second device region of the second device based on the first device region being configured to be exposed and the second device region being configured to avoid being exposed by such a blanket exposure process. For example, the first device region or a portion thereof can extend below (e.g., in a direction towards the backside) such that during a planarization operation or an etching operation, the first device region is exposed before the second device is exposed. When the first device region is exposed and the second device region is not exposed, the blanket exposure process can be stopped (e.g., based on timing or a marker, etc.). For within-cell differentiation, such a blanket exposure process can depend on structural differences between the first and second devices with respect to the first and second device regions. The structural differences can be, as discussed, the first device region extending below the second device region, or, for example, a material difference between the first and second device regions. In addition to the structural differences for backside exposure (e.g., the structural differences for backside exposure), the first and second devices can have any suitable functionality and / or other structural differences to provide within-cell differentiation. For example, such backside exposure structural differences can be provided between transistors of different functionality such that the first device (e.g., having the first device region to be backside exposed) is a logic transistor while the second device (e.g., having the second device region not to be exposed) is a memory or power transistor. In an embodiment, the backside exposure structural differences can be provided between transistors of different polarities such that the first device (e.g., having the first device region to be backside exposed) is an n-type transistor while the second device (e.g., having the second device region not to be exposed) is a p-type transistor, or vice versa. In an embodiment, the backside exposure structural differences can be provided between transistors of different device structures such that the first device (e.g., having the first device region to be backside exposed) is a non-planar transistor while the second device (e.g., having the second device region not to be exposed) is a planar transistor, or vice versa. In an embodiment, the backside exposure structural differences can be provided in devices having the same functionality, polarity, and / or other aspects of structure. For example, as shown with respect to operations 3830, 3835, and 3840, the structural differences can be provided in any permutation across device functional types (e.g., selection from logic / memory / power), polarities (e.g., selection from n-type / p-type), and / or device structures (e.g., selection from planar / non-planar). Additionally, additional options can be available, such as differentiation between device types (e.g., transistors, resistors, diodes, etc.) and / or other structures. For example, device regions can be selectively exposed based on any suitable combination of functionality, type, structure, or other suitable characteristics. As discussed, in some embodiments, the backside exposure is based on device functionality and / or structure within such regions, defining such regions, or as interspersed throughout the donor-substrate assembly. For example, the backside exposure can be provided between logic devices and memory devices, between logic devices and power devices, between memory devices and power devices, or as a selective exposure based on device functionality, device critical dimension, or the like (e.g., at operation 3830). In other examples, the backside exposure provides a selective exposure between n-type devices and p-type devices (e.g., at operation 3835), between fin or non-planar devices and planar devices (e.g., between operations 3840), or the like. Additionally, backside exposure options for other device types can be available. As discussed with respect to operation 3815, in some embodiments, the local backside exposure is set based on masked exposure. For example, such techniques can include masked areas, regions, IC cells, sub-cells, etc. that are not to be exposed, and selective removal of material (e.g., by etching, etc.) from unmasked areas, regions, cells, sub-cells, etc. Such techniques can provide selective backside exposure between cells (e.g., between-cell), within cells (e.g., within-cell), between devices of different functionality, between devices of different structures, etc. Additionally, as shown with respect to operation 3855, in certain embodiments, the partial backside exposure is provided by a blanket exposure process. In such embodiments, no masking is required, and the backside exposure can be provided based on structural differences between devices having regional exposure and those not having regional exposure (e.g., backside exposure structural differences). For example, the blanket exposure can provide selective backside exposure based on structural differences between exposed and non-exposed devices. Such structural differences can be between devices in different cells, sub-cells, or the like, and they can be provided between the same or different devices. Such different devices can be functionally, structurally different from the backside exposure structural differences or the like. The various branches of method 3801 provided by operations 3815, 3820, 3850, 3825, 3855, 3830, 3858, 3836, 3835, and 3840 can be implemented to produce a series of device layer - host substrate assemblies that would be the output at operation 130. For example, operations 3805, 3815, 3820, 3825, 3830, and 130 provide for a partial dorsal exposure (e.g., at operation 3815) of a received donor - host substrate assembly (e.g., received at operation 3805) to provide an inter - cell dorsal exposure differentiation (e.g., at operation 3820) between logic transistors and memories and / or power transistors, between memories and logic and / or power transistors, or between power and logic and / or memory transistors (e.g., at operation 3830). Operations 3805, 3815, 3850, 3825, 3835, and 130 provide for a partial dorsal exposure (e.g., at operation 3815) of a received donor - host substrate assembly (e.g., received at operation 3805) to provide an intra - cell dorsal exposure differentiation (e.g., at operation 3825) between n - type and p - type transistors (e.g., at operation 3830). As shown, a wide variety of other operations are available. For example, FIG. 38A of display method 3801 can be read to provide the following options to provide a selective dorsal exposure (e.g., a selective one device area to another device area) for the received donor - host substrate assembly (e.g., received at operation 3805). Either or both of a wafer - level full dorsal exposure and a partial dorsal exposure can be performed (e.g., at operations 3810 and 3815 of L1). An inter - cell and / or intra - cell dorsal exposure differentiation can be provided (e.g., at operations 3820 and 3850 of L2). Such inter - cell and / or intra - cell level differentiation can be provided by masking and / or blanket exposure (e.g., at operations 3825 and 3855 of L3). Masked exposure can provide a functionality - based and / or a structure - based differentiation in the dorsal exposure. The differentiation (e.g., inter - cell or intra - cell) provided by the selective dorsal exposure (e.g., using masked exposure or blanket exposure) can provide a differentiation among logic / memory / power transistors, between n - type and p - type transistors, between planar and non - planar transistors, or any combination thereof. As shown, a device layer - host substrate assembly output with selective dorsal exposure and / or additional processing is provided at operation 130. The discussion now turns to further illustrate specific exemplary techniques of method 3801. The first embodiment is set with respect to FIGS. 38B and 39 - 45, while the second embodiment is set with respect to FIGS. 38C and 46 - 54. The exemplary techniques described with respect to such embodiments can be extended to any particular method or branch of method 3801. FIG. 38B is a flowchart of method 3802 for selectively forming a non-planar transistor backside transistor source / drain semiconductor for a planar transistor and a contact metal that is selective for the planar transistor. Method 3802 begins with a donor-host substrate assembly that includes a planar transistor structure and a non-planar transistor structure as input 3806. The donor substrate may have one or more of the features described herein, such as, but not limited to, an intermediate layer and a carrier layer. However, a carrier layer is not required for performing method 3802. For example, the non-planar and / or planar transistor structures at the input of method 3802 may be fully operational. Alternatively, one or more terminals may be absent such that the non-planar transistor structure will not be operational until backside processing is complete. FIG. 39 is a plan view of a non-planar transistor structure 1304 lacking a source / drain metal 650 and a planar transistor structure 3904 having both source / drain metals 650, according to some embodiments. The thick dotted lines shown with respect to the non-planar transistor structure 1304 represent the planes of cross-sectional views further provided in FIGS. 40A-40C, 42A-42C, and 44A-44C. Similarly, the thick dotted lines shown with respect to the planar transistor structure 3904 represent the planes of cross-sectional views further provided in FIGS. 41A-41C, 43A-43C, and 45A-45C. Using the techniques discussed herein and shown with respect to method 3802, selective backside processing can be provided for the non-planar transistor structure 1304 without providing backside processing for the planar transistor structure 3904. Returning to FIG. 38B, the selective backside processing provided by method 3802 provides for the backside exposure of the source / drain semiconductor 640 (e.g., the first device region) of the non-planar transistor structure 1304 (e.g., the first device). Additionally, the selective backside processing provided by method 3802 selectively exposes the backside of the source / drain semiconductor 640 of the non-planar transistor structure 1304 to the planar transistor structure 3904 (e.g., the second device), and thereby selectively to each device region of the planar transistor structure 3904. For example, the selective backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 is selective with respect to the source / drain semiconductor 640, the source / drain metal 650, the spacer dielectric 671 that separates the gate electrode 673 from the source / drain metal 650 and / or the source / drain semiconductor 640, the field isolation dielectric 680, and the device layer 215 of the planar transistor structure 3904. Although discussed with respect to the selective backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 to the planar transistor structure 3904, method 3802 can provide for the selective backside exposure of any one or more device regions of the planar transistor structure 3904 to any one or more device regions of the non-planar transistor structure 1304. Additionally, method 3802 can provide for the selective backside exposure of any one or more device regions of the non-planar transistor structure 1304 to any one or more device regions of the planar transistor structure 3904. Additionally, method 3802 can provide for the placement (e.g., by deposition, etc.) of one or more non-native materials on the exposed source / drain semiconductor 640 (e.g., the exposed first device region). In an example of method 3802, a backside source / drain semiconductor 1640 and a backside source / drain metal 1650 are disposed on the exposed (e.g., backside-exposed) source / drain semiconductor 640. Although discussed with respect to the placement of the backside source / drain semiconductor 1640 and the backside source / drain metal 1650 on the source / drain semiconductor 640, any suitable non-native material can be disposed on any exposed device region. For example, the one or more non-native materials can include semiconductor materials, metal materials, or dielectric materials. As shown in FIG. 39, in some embodiments, non-planar transistors and planar transistors can be integrated in the same integrated circuit. For example, non-planar transistor structure 1304 and planar transistor structure 3904 can be integrated on IC die 601. In planar transistor structure 3904, the same numbering as that of non-planar transistor structure 1304 represents the same structure. For example, planar transistor structure 3904 includes gate electrode 673, source / drain semiconductor 640, source / drain metal 650, spacer dielectric 671 that separates gate electrode 673 from source / drain metal 650 and / or source / drain semiconductor 640, field isolation dielectric 680, and device layer 215. As will be appreciated, as compared to non-planar transistor structure 1304, gate electrode 673 (and gate dielectric 845 in FIG. 41) does not surround the channel region of the transistor channel. Regarding non-planar transistor structure 1304, in the absence of source or drain metal 650, the pitch and / or critical dimension constraints of source / drain metal 650 and / or other front-side metal levels (e.g., gate electrode 673 or higher metal levels) can be advantageously relaxed. The absence of source or drain metal 650 can render non-planar transistor structure 1304 inoperable until a third terminal connection is fabricated, e.g., using back-side transistor source / drain contact metallization method 3802 (FIG. 38B). Such back-side transistor source / drain contact metal can couple to a power rail (e.g., V cc ) to form a transistor structure, advantageously configuring power (source) and signals (gate electrode voltage) routed on opposite sides of the transistor structure layer. Notably, the selective back-side transistor source / drain contact metallization method 3802 can also be implemented on transistor structures fabricated entirely from the front side (e.g., including all device terminals). For such embodiments, the back-side transistor source / drain contact metallization method 3802 can be implemented to incorporate source / drain transistor terminals into interconnect traces disposed on both sides of the transistor layer, which can advantageously reduce the source / drain contact resistance and / or render the source / drain device region of the transistor a circuit node that directly fans out to at least two other circuit nodes. As further discussed herein and with respect to FIGS. 40-45, during this backside transistor source / drain contact metal of the non-planar transistor structure 1304, the planar transistor structure 3904 is masked and selectively not exposed (e.g., the device region of the planar transistor structure 3904 is not exposed during the backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304). For example, the selective backside transistor source / drain contact metallization method 3802 can be performed on the planar transistor structure 3904 such that the planar transistor structure is fully functional as manufactured from the front side (e.g., includes all device terminals), and the backside processing of the non-planar transistor structure 1304 does not affect the functionality of the planar transistor structure 3904. Returning to FIG. 38B, at operation 3808, the backside of the device layer (e.g., one or more intermediate layers) is exposed by removing the carrier layer. In some further embodiments, portions of any intermediate layer and / or front-side material deposited over the device layer may also be removed during the exposure operation 3808. As described elsewhere herein, in the context of some exemplary embodiments, the intermediate layer can contribute to a highly uniform exposure of the backside of the device layer, such as one or more of the etch stops of the etch markers employed in a wafer-level backside exposure process. For example, the intermediate layer can separate the device layer from the removed carrier layer such that, prior to removal, the intermediate layer is in direct contact with both the carrier layer and the device layer. As discussed, in some embodiments, the donor-host substrate assembly including the planar transistor structure and the non-planar transistor structure received at operation 3806 does not include a carrier layer, and in such embodiments, operation 3808 can be omitted. Method 3802 continues at operation 3812, where the backside of the planar transistor structure is masked. This selective masking of the backside of the planar transistor structure provides selective exposure or access to the backside of the non-planar transistor structure (e.g., access to the backside of the selective device region of the non-planar transistor structure). Additionally, at operation 3812, portions of the backside of the non-planar transistor are also masked to provide selective access to a particular structure of the non-planar transistor (e.g., the source / drain semiconductor region). The mask provided at operation 3812 can include any suitable mask applied using any suitable technique. Method 3802 continues with operation 3818, where the backside of at least one non-planar transistor source / drain region within the non-planar transistor structure is exposed. In some embodiments, the backside recess etching is performed at operation 3818 such that the backside recess etching has a pattern provided by a mask applied at operation 3812. The backside recess etching can selectively expose the source / drain semiconductor regions (e.g., the first device region) of the non-planar transistor structure (e.g., the first device) for other regions of the non-planar transistor structure (e.g., those device regions that are not to be exposed) and selectively for the device regions (e.g., one or more second regions) of the planar transistor structure (e.g., the second device). As discussed, the selectivity for the device regions of the planar transistor structure can provide selectivity for the entirety of the planar transistor structure (e.g., all device regions). Once the selective source / drain semiconductor regions of the non-planar transistor structure are exposed, method 3802 is completed at operation 3826, where non-native source / drain semiconductor is deposited from the backside and deposited over or above the exposed source / drain regions of the non-planar transistor, and / or contact metal is deposited over the source / drain semiconductor applied from the backside. The source / drain semiconductor and / or contact metal are examples of non-native materials that can be disposed over the backside-exposed semiconductor regions. As shown, operation 3826 outputs a non-planar transistor structure with contact metal on the backside source / drain semiconductor, which is integrated with the planar transistor structure that has been selectively unexposed by such backside processing. Figures 40A, 42A, and 44A show cross-sectional views of non-planar transistor structure 1304 along the A-A' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 41A, 43A, and 45A show cross-sectional views of planar transistor structure 3904 along the A-A' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 40B, 42B, and 44B show cross-sectional views of non-planar transistor structure 1304 along the B-B' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 41B, 43B, and 45B show cross-sectional views of planar transistor structure 3904 along the B-B' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 40C, 42C, and 44C show cross-sectional views of non-planar transistor structure 1304 along the C-C' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 41C, 43C, and 45C show cross-sectional views of planar transistor structure 3904 along the C-C' plane shown in FIG. 39, in accordance with some embodiments, of operations performed in method 3802. Figures 40A - 40C show cross-sectional views of structures present in an exemplary non-planar transistor structure 1304 after front-side processing and / or optional carrier removal. The structural features shown in Figures 40A - 40C may have any of the characteristics described herein for like reference symbols. Additionally, Figures 41A - 41C show structures present in an exemplary planar transistor structure 3904 after front-side processing and / or optional carrier removal. The structural features shown in Figures 41A - 41C may also have any of the characteristics described herein for like reference symbols. For example, Figures 40A - 40C and 41A - 41C show cross-sectional views of the non-planar transistor structure 1304 and the planar transistor structure 3904 after operation 3806 of method 3802 is performed (see Figure 38B). As shown in Figures 42A - 42C and 43A - 43C, an etch mask 1410 (e.g., a patterned mask) is aligned to the back-side structures of the non-planar transistor structure 1304 and the planar transistor structure 3904. Additionally, a substantial portion of the interlayer 210 and the transistor semiconductor body 610 (e.g., a portion of the device layer 215) is removed to provide a selectively exposed recess 1540 within the unmasked portion defined by the etch mask 1410. In alternative embodiments having structural differences (e.g., differences in depth) between source / drain regions, the etch mask 1410 may be restricted so as to protect only the structure 3904 while utilizing the continued processing of the structure 1304 as elsewhere described in the context of Figures 14D, 15D, and 16D. As shown, the etch mask 1410 masks the entirety of the back-side of the planar transistor structure 3904 (see Figures 43A - 43C). Additionally, the etch mask 1410 exposes a back-side portion of the non-planar transistor structure 1304, which allows access to the source / drain semiconductor 640 or exposes the source / drain semiconductor 640 via the selectively exposed recess 1540 (refer to Figures 42A - 42C). Alignment relative to the source / drain semiconductor 640 need not be precise such that overlap with the gate electrode 673 can be minimized or avoided. As discussed, the etch mask 1410 may be another interlayer of the back-side substrate deposited after exposure of the interlayer 210, a soft mask (e.g., a photosensitive resist) applied on the back-side surface of the interlayer 210, or the like. As discussed, the unprotected device regions (e.g., the unmasked or exposed regions) are then recess etched using any wet and / or plasma etch procedures known to be suitable for the applicable material compositions. Additionally, when removing a major portion of the interlayer 210 and the transistor semiconductor body 610, the finlet height H sfIs held in the region of the non-planar transistor structure 1304 protected by the etching mask 1410. The selectively exposed recess 1540 can be of any depth and lateral dimension. For example, the selectively exposed recess 1540 can completely remove the sub-fin of the semiconductor body 610 (e.g., the semiconductor portion of the intermediate layer 210) and expose the source / drain semiconductor 640. As shown, the etching mask 1410 masks the entirety of the back side of the planar transistor structure 3904 (see FIGS. 43A-43C). For example, FIGS. 42A-42C and 43A-43C respectively show cross-sectional views of the non-planar transistor structure 1304 and the planar transistor structure 3904 after operations 3812 and 3818 (FIG. 38B) are performed. FIGS. 44A-44C and 45A-45C show the non-planar transistor structure 1304 and the planar transistor structure 3904 after epitaxial growth or deposition of the p-type or n-type impurity-doped back-side source / drain semiconductor 1640 and subsequent deposition of the back-side source / drain metal 1650. As shown, the back-side source / drain semiconductor 1640 is disposed adjacent to or on the source / drain semiconductor 640. The back-side source / drain semiconductor 1640 can be disposed on the source / drain semiconductor 640 using any suitable one or more techniques, such as an epitaxial growth process, a deposition process, or a similar process. For example, the same epitaxial or deposition process used to form the source / drain semiconductor 640 can be employed to form the back-side source / drain semiconductor 1640. The back-side source / drain semiconductor 1640 can be any suitable material, such as, but not limited to, group-IV semiconductors (e.g., Si, Ge, SiGe), and / or group-III-V semiconductors (e.g., InGaAs, InAs) and / or group-III-N semiconductors (e.g., InGaN). As also shown in the figure, the backside source / drain metal 1650 is disposed adjacent to or on the backside source / drain semiconductor 1640. The backside source / drain metal 1650 can be disposed on the source / drain semiconductor 1640 using any suitable one or more techniques, such as a metal deposition process. For example, the same deposition process used to form the backside source / drain metal 650 can be used to form the backside source / drain metal 1650. The backside source / drain metal 650 can comprise any suitable material, such as Ti, W, Pt, its alloys, or the like. As also shown in the figure, in FIGS. 45A-45C, the planar transistor structure 3904 can continue to be masked by the etch mask 1410 such that neither the backside source / drain semiconductor nor the backside source / drain contact metal is disposed for the planar transistor structure 3904. For example, the backside source / drain semiconductor 1640 and the backside source / drain metal 1650 of non-native materials can be selectively provided to the non-planar transistor structure 1304 without being applied to the planar transistor structure 3904. For example, FIGS. 42A-42C and 43A-43C respectively show cross-sectional views of the non-planar transistor structure 1304 and the planar transistor structure 3904 after operation 3826 (FIG. 38B) is performed. In some further embodiments represented by FIGS. 44A-44C and 45A-45C, the backside metal overburden is removed by polishing (e.g., CMP), exposing the etch mask 1410 and / or the interlayer 210 again along with the source / drain contact metal, and then confined to backfill the selectively exposed recess 1540. Subsequent backside processing can also include the fabrication of at least one or more backside interconnect metal levels (not shown) that are at least electrically coupled to the source / drain metal 1650. In some such embodiments, such backside interconnect metals have different compositions from the frontside interconnect metal hierarchy and / or the backside interconnect metals have larger lateral dimensions or greater thicknesses than the corresponding levels of the frontside interconnect metals. For example, the frontside interconnect metals can have a higher proportion of copper relative to the backside interconnect metals and can be predominantly copper (e.g., predominantly Cu or a Cu-rich alloy). The backside interconnect metals can instead be predominantly not copper (e.g., mostly not copper, copper-depleted alloys, or copper-free alloys). The frontside interconnect metals can likewise be predominantly not copper while the backside interconnect metals can be predominantly copper. In the case where the interconnect metals are not copper-dominated, the backside interconnect metals can be any other suitable metal / metal alloy comprising one or more of Ru, Rh, Pd, Ir, Pt, Au, W, Cr, or Co. The separation of the metal compositions between the frontside and the backside of the device layer can advantageously partition the use of different material systems and interconnect technologies between the frontside (e.g., Ru) and the backside (e.g., Cu) processing. Between the front and back sides of the device layer, the lateral interconnect dimensions and / or thicknesses of a given level (e.g., Metal 1, Metal 2, etc.) can also be different. For example, compared to the front-side interconnect metal that is coupled to the gate terminal and / or drain terminal of a transistor via the front-side interconnect, the power line that is coupled to the source terminal of a transistor via the back-side interconnect metal can have a larger lateral dimension (e.g., line width) and / or thickness. The partitioning of the dimensions and thicknesses between the front-side and back-side interconnect metals can advantageously increase the degrees of freedom for the interconnect manufacturing process. In some embodiments where the back-side interconnect metal has a larger lateral dimension and / or thickness, the back-side interconnect metal is copper-based, while the front-side interconnect metal with a smaller lateral dimension and / or thickness is not copper (e.g., Ru-based). Using the techniques discussed, the back-side exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 is selective to the device region of the planar transistor structure 3904. This masked exposure technique can be extended to selectively expose any device region of the non-planar transistor structure 1304 (e.g., channel, gate dielectric, gate electrode, etc.) to any device region of the planar transistor structure 3904, or vice versa. Additionally, this selective exposure process can be on a per-cell basis (as shown), on a per-unit basis, on a regional basis, etc. This selective exposure process provides a distinction between non-planar and planar transistors. Such non-planar and planar transistors can also have a distinction based on functionality and / or polarity as discussed herein. In an embodiment, the non-planar transistor is a logic transistor, while the planar transistor is a memory and / or power transistor. FIG. 38C is a flowchart showing a method 3803 for selectively forming a non-planar transistor back-side transistor source / drain semiconductor and contact metal for other non-planar transistors according to some embodiments. Method 3803 begins with a donor-host substrate assembly that includes first and second (e.g., power and logic) non-transistor structures as input 3807. The donor substrate can have one or more of the features described herein, such as, but not limited to, an intermediate layer and a carrier layer. However, the carrier layer and / or the intermediate layer are not required to perform method 3803. The non-planar power and / or non-planar logic transistor structures at the input of method 3803 can be fully operational or one or more terminals can be absent such that the non-planar transistor structure is not operated until the back-side processing is complete. FIG. 46 is a plan view of a non-planar (e.g., power) transistor structure 1304 lacking a source / drain metal 650 and a non-planar (e.g., logic) transistor structure 604 having both source / drain metals 650, in accordance with some embodiments. The thick dotted lines shown with respect to the non-planar (e.g., power) transistor structure 1304 represent the planes along which cross-sectional views are further provided in FIGS. 48A-48C, 50A-50C, 52A-52C, and 54A-54C. Similarly, the thick dotted lines shown with respect to the non-planar (e.g., logic) transistor structure 604 represent the planes along which cross-sectional views are further provided in FIGS. 47A-47C, 49A-49C, 51A-51C, and 53A-53C. Using the techniques discussed herein with reference to method 3802, selective backside processing can be provided for the non-planar transistor structure 1304 without providing backside processing for the non-planar transistor structure 1304. Returning to FIG. 38C, the backside processing provided by method 3803 provides backside exposure of the source / drain semiconductor 640 (e.g., first device region) of the non-planar transistor structure 1304 (e.g., first device) such that the backside processing selectively exposes the backside of the source / drain semiconductor 640 of the non-planar transistor structure 1304 to the non-planar transistor structure 604 (e.g., second device), and thereby selectively etches the device region of the non-planar transistor structure 604. The backside exposure of the source / drain semiconductor 640 of the non-planar transistor structure 1304 is selective to the source / drain semiconductor 640, the source / drain metal 650, the spacer dielectric 671 separating the gate electrode 673 from the source / drain metal 650 and / or the source / drain semiconductor 640, the field isolation dielectric 680, and the device layer 215 of the non-planar transistor structure 604. Method 3803 can alternatively provide selective backside exposure for any one or more device regions of the non-planar transistor structure 604 that are selective to any one or more device regions of the non-planar transistor structure 1304. Additionally, method 3803 can provide selective backside exposure for any one or more device regions of the non-planar (e.g., power) transistor structure 1304 that are selective to any one or more device regions of the non-planar (e.g., logic) transistor structure 604. As also shown with respect to operation 3834, method 3803 may form (e.g., by deposition, etc.) one or more non-native materials on the exposed source / drain semiconductor 640 (e.g., the exposed first device region). In an example of method 3803, the backside source / drain semiconductor 1640 and the backside source / drain metal 1650 are disposed on the exposed (e.g., backside-exposed) source / drain semiconductor 640. Any suitable non-native material may be disposed on any exposed device region using method 3803. For example, the one or more non-native materials may include semiconductor materials, metal materials, or dielectric materials. As shown in FIG. 46, in some embodiments, non-planar power transistors and non-planar logic transistors may be integrated in the same integrated circuit. For example, non-planar transistor structures 1304 and 604 may be integrated as power and logic transistors, respectively, on an IC die 601. In FIG. 46, the same reference numerals for non-planar transistor structures 1304 and 604 denote similar structures as discussed elsewhere herein. As discussed with respect to FIG. 39, in the absence of source or drain metal 650 in non-planar transistor structure 1304, the pitch and / or critical dimension constraints of source / drain metal 650 and / or other front-side metal layers may be relaxed, and the absence of source or drain metal 650 may render non-planar (e.g., power) transistor structure 1304 inoperable until a third terminal connection is fabricated. Such a backside transistor source / drain contact metal may couple a power rail to the power transistor structure, configure the power, and route a signal (gate electrode voltage) on the opposite side of the transistor structure layer. Alternatively, a selective backside transistor source / drain contact metallization method 3803 may also be implemented on a fully functional front-side fabricated transistor structure such that a backside transistor source / drain contact metallization method 3802 may be implemented to incorporate a source or drain transistor terminal into interconnect traces disposed on both sides of the transistor layer. Furthermore, as further discussed herein and shown with respect to FIGS. 47-54, during backside transistor source / drain contact metallization of such non-planar (e.g., power) transistor structure 1304, non-planar (e.g., logic) transistor structure 604 is masked and kept unexposed. For example, a selective backside transistor source / drain contact metallization method 3803 may be performed on non-planar transistor structure 604 such that the non-planar power transistor structure is fully functional front-side fabricated and the backside processing of non-planar transistor structure 1304 does not affect the functionality of non-planar transistor structure 604. Returning to FIG. 38C, at operation 3809, the backside of the device layer (e.g., one or more intermediate layers) is exposed by removing the carrier layer. In some embodiments, portions of any intermediate layers and / or frontside materials deposited over the device layer may also be removed during operation 3809. As described herein, the intermediate layer(s) may facilitate highly uniform exposure of the backside of the device layer. For example, the intermediate layer(s) may separate the device layer from the removed carrier layer such that, prior to removal, the intermediate layer(s) are in direct contact with both the carrier layer and the device layer. As discussed, in some embodiments, the donor-host substrate assembly comprising the non-planar logic transistor structure and the non-planar power transistor structure received at operation 3807 does not include a carrier layer, and operation 3808 may be omitted. Method 3802 continues at operation 3813, where at least a thickness of the exposed intermediate layer is removed. In an example of the method 3802, the thickness of the exposed intermediate layer is removed by a grinding operation. However, the thickness of the exposed intermediate layer may be removed using any suitable technique(s). For example, one or more component layers of the one or more intermediate layers may be removed. In an embodiment, the thickness of the intermediate layer is uniformly removed by a grinding operation. In an embodiment, the thickness of the intermediate layer is removed using a masking or blanket etch process. Operation 3813 may employ the same grinding and / or etching process as used to remove the carrier layer at operation 3809, or operation 3813 may be a different process with different process parameters. For example, when the intermediate layer provides an etch stop for the carrier removal process, operation 3813 may employ a different grinding or etching process. Method 3802 continues at operation 3819, where a backside isolation dielectric is disposed on the backside of the non-planar logic transistor structure and the non-planar power transistor structure. The backside isolation dielectric may be disposed on the backside of the non-planar logic transistor structure and the non-planar power transistor structure using any suitable technique(s), such as a dielectric deposition technique. Additionally, the backside isolation dielectric may be any suitable material, such as silicon dioxide, silicon nitride, SiOC, SiOCH, HSQ, MSQ, SiON, or the like. Method 3802 continues at operation 3825, where the backside of at least one source / drain region within the non-planar power transistor structure is selectively exposed to the non-planar logic transistor structure. In some embodiments, the backside isolation dielectric is patterned to form an etch mask, and a backside recess etch is performed at operation 3825 such that the backside recess etch has a pattern defined by the etch mask. The patterning of the backside isolation dielectric to produce the etch mask can be performed using any suitable patterning technique such as lithography. Additionally, the backside recess etch can be performed using any suitable technique such as wet or dry etch techniques. The backside recess etch can selectively expose the source / drain semiconductor region (e.g., the first device region) of the non-planar power transistor structure to other regions of the non-planar power transistor structure (e.g., those device regions that will not be exposed) and selectively to the device regions (e.g., one or more second device regions) of the non-planar logic transistor structure (e.g., the second device). As discussed, the selectivity to the device regions of the non-planar logic transistor structure can provide selectivity to the entirety (e.g., all of the device regions) of the non-planar logic transistor structure. Once the selective source / drain semiconductor region of the non-planar power transistor structure is exposed, method 3803 is completed at operation 3834, where non-native source / drain semiconductor is deposited from the backside and deposited over or above the exposed source / drain region of the non-planar power transistor, and / or contact metal is deposited over the source / drain semiconductor applied from the backside. The source / drain semiconductor and / or contact metal are examples of non-native materials that can be disposed over the backside exposed semiconductor region. As shown, operation 3834 outputs a non-planar power transistor structure having backside terminal metal over the backside source / drain semiconductor integrated with the non-planar logic transistor structure that has been selectively unexposed by such backside processing. Figures 47A, 49A, 51A, and 53A show cross-sectional views of a non-planar transistor structure 1304 along the A-A' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 48A, 50A, 52A, and 54A show cross-sectional views of a non-planar transistor structure 604 along the A-A' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 47B, 49B, 51B, and 53B show cross-sectional views of a non-planar transistor structure 1304 along the B-B' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 48B, 50B, 52B, and 54B show cross-sectional views of a non-planar transistor structure 604 along the B-B' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 47C, 49C, 51C, and 53C show cross-sectional views of a non-planar transistor structure 1304 along the C-C' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 48C, 50C, 52C, and 54C show cross-sectional views of a non-planar transistor structure 604 along the C-C' plane shown in FIG. 46, depicting operations performed in method 3803, according to some embodiments. Figures 47A - 47C show cross-sectional views of structures present in an exemplary non-planar transistor structure 1304 after front-side processing and / or optional carrier removal, according to some embodiments. In some embodiments, the non-planar transistor structure 1304 is a power transistor. The structural features shown in Figures 47A - 47C may have any of the characteristics described herein for like reference symbols. Figures 48A - 48C show structures present in an exemplary non-planar transistor structure 604 after front-side processing and / or optional carrier removal. In some embodiments where the non-planar transistor structure 1304 is a power transistor, the non-planar transistor structure 604 is a logic transistor. The structural features shown in Figures 41A - 41C may also have any of the characteristics described herein for like reference symbols. For example, Figures 47A - 47C and 48A - 48C show cross-sectional views of the non-planar transistor structures 1304 and 604 after operation 3809 (FIG. 38C) is performed. As shown in FIGS. 49A - 49C and 50A - 50C, the backside 1012 of the semiconductor body 610 of the non - planar transistor structure 1304 and the non - planar transistor structure 604 and / or other structures (such as the field isolation dielectric 680) are exposed by removing the intermediate layer 210. This exposure can be performed using any suitable one or more techniques. For example, to expose the backside of the transistor semiconductor body 610, the portion of the bulk semiconductor to which the transistor semiconductor body 610 is fixed can be ground back and / or recess etched using, for example, the wet and / or dry etching procedures described herein with respect to operation 510 (refer to FIG. 5). In some embodiments, the backside grinding of the intermediate layer 210 can be stopped when the field isolation dielectric 680 is exposed. Any amount of over - etching (or over - grinding) can be performed to reduce the finlet height by further thinning the device layer that includes the semiconductor body 610 of the finlet and the adjacent field isolation dielectric 680. H sf . For example, FIGS. 49A - 49C and 50A - 50C show cross - sectional views of the non - planar transistor structure 1304 and the non - planar transistor structure 604 after performing operation 3813 (refer to FIG. 38C) of method 3803. As shown in FIGS. 51A - 51C and 52A - 52C, an etch mask 1410 (e.g., a patterned mask) is aligned to the backside structures of the non - planar transistor structure 1304 and the planar transistor structure 604. Additionally, a substantial portion of the transistor semiconductor body 610 (e.g., a portion of the device layer 215) is removed to provide a selectively exposed recess 1540 within the unmasked portion provided by the etch mask 1410. In the context of FIGS. 51A - 51C and 52A - 52C, the etch mask 1410 is a hard mask layer and a dielectric layer that will be retained to provide isolation. The etch mask 1410 can be provided using any suitable one or more techniques. In an embodiment, a backside isolation dielectric (e.g., backside isolation dielectric 1120) is deposited over the exposed backside. The backside isolation dielectric is an example of a non - native material that replaces a portion of the intermediate layer that was removed to expose the transistor semiconductor region, and the backside isolation dielectric can be any dielectric material suitable for electrical isolation of the transistor, such as silicon dioxide, a low dielectric constant material, a material having a relative dielectric constant less than that of the field isolation dielectric 680, a material having a relative dielectric constant less than 3.9 or less than 3.5, SiOC, SiOCH, HSQ, MSQ, SiN, SiON, or the like. The backside isolation dielectric is then patterned to provide the etch mask 1410. As shown, the etching mask 1410 masks the entirety of the non-planar transistor structure 604 (see FIGS. 51A - 51C). Additionally, the etching mask 1410 exposes the backside portion of the non-planar transistor structure 1304, which allows access to the source / drain semiconductor 640 or exposes the source / drain semiconductor 640 by selectively exposing the recess 1540 (refer to FIGS. 52A - 52C). Alignment relative to the source / drain semiconductor 640 need not be precise, such that overlap with the gate electrode 673 can be minimized or avoided. As discussed, the etching mask 1410 can be the isolation dielectric of the backside substrate deposited after the exposure of the backside 1012. Also as discussed, the unprotected device regions (e.g., the unmasked or exposed regions) are then recess etched using any wet and / or plasma etching procedures known to be suitable for the applicable material compositions. Additionally, when removing the major portion of the transistor semiconductor body 610, the sub-fin height H sf is maintained in the region of the non-planar transistor structure 1304 protected by the etching mask 1410. The selectively exposed recess 1540 can be of any depth and lateral dimension. For example, the selectively exposed recess 1540 can completely remove the sub-fin portion of the semiconductor body 610 (e.g., the semiconductor portion of the intermediate layer 210) and expose the source / drain semiconductor 640. As shown, the etching mask 1410 masks the entirety of the backside of the non-planar transistor structure 604 (see FIGS. 52A - 52C). For example, FIGS. 51A - 51C and 52A - 52C show cross-sectional views of the non-planar transistor structure 1304 and the non-planar transistor structure 604 after operation 3819 (FIG. 38C) is performed. FIGS. 53A - 53C and 54A - 54C show the non-planar transistor structure 1304 and the non-planar transistor structure 604 after the epitaxial growth or deposition of the p-type or n-type impurity doped backside source / drain semiconductor 1640 and the subsequent deposition of the backside source / drain metal 1650. As shown, the backside source / drain semiconductor 1640 is disposed adjacent to or on the source / drain semiconductor 640. The backside source / drain semiconductor 1640 can be disposed on the source / drain semiconductor 640 using any suitable one or more techniques, such as an epitaxial growth process, a deposition process, or a similar process. For example, the same epitaxial or deposition process used to form the source / drain semiconductor 640 can be employed to form the backside source / drain semiconductor 1640. The backside source / drain semiconductor 1640 can be any suitable material, such as, but not limited to, group-IV semiconductors (e.g., Si, Ge, SiGe), and / or group-III-V semiconductors (e.g., InGaAs, InAs) and / or group-III-N semiconductors (e.g., InGaN). As also shown in the figure, the back-side source / drain metal 1650 is disposed adjacent to or on the back-side source / drain semiconductor 1640. The back-side source / drain metal 1650 can be disposed on the source / drain semiconductor 1640 using any suitable technique or techniques, such as a metal deposition process. For example, the same deposition process used to form the back-side source / drain metal 650 can be used to form the back-side source / drain metal 1650. The back-side source / drain metal 650 can comprise any suitable material, such as Ti, W, Pt, alloys thereof, or the like. As also shown in the figure, in FIGS. 53A-53C, the non-planar transistor structure 604 can continue to be masked by the etch mask 1410 such that neither the back-side source / drain semiconductor nor the back-side source / drain contact metal is disposed for the non-planar transistor structure 604. For example, the back-side source / drain semiconductor 1640 and the back-side source / drain metal 1650 of non-native materials can be selectively provided to the non-planar transistor structure 1304 without being applied to the non-planar transistor structure 604. For example, FIGS. 52A-52C, 53A-53C, and 54A-54C show cross-sectional views of the non-planar transistor structure 1304 and the planar transistor structure 3904 after operation 3834 (FIG. 38B) is performed. In some further embodiments represented by FIGS. 53A-53C and 54A-54C, the back-side metal overburden is removed by polishing (e.g., CMP), along with the source / drain contact metal to re-expose the etch mask 1410, followed by confinement to backfill the selectively exposed recesses 1540. Subsequent back-side processing can also include the fabrication of at least one or more back-side interconnect metal levels (not shown) that are at least electrically coupled to the source / drain metal 1650. In some such embodiments, such back-side interconnect metals have different compositions than the front-side interconnect metal hierarchy and / or the back-side interconnect metals have larger lateral dimensions or greater thicknesses than the corresponding levels of the front-side interconnect metals. The above discussion describes various back-side processing operations that can be used to complete and / or modify the front-side transistor structure. Such methods can be used, for example, to prepare a device layer for dicing and packaging, or to bond to another device layer in a stacked 3D device layer embodiment. It should also be noted that back-side processing can be extended to fabricate a second device (e.g., FET, TFET, TFT, STTM) on the exposed back-side of the device layer. Such a dual-sided hierarchy fabrication can be considered a supplement or alternative to wafer-level hierarchical bonding where the exposed back-side is bonded to another prefabricated device layer. If such a dual-sided hierarchy is subsequently bonded to another hierarchy, the bonding interface will separate a pair of stacked devices from another device or another pair of stacked devices. A given device stack can be one or the other of prefabricated device layers that are a function of a hierarchy that is more suitable for the processing conditions and / or compatibility between materials required for dual-sided incremental device fabrication or bonding as a stacked device. For example, a backside device that requires high-temperature activation annealing (e.g., annealing after impurity doping implantation) or high-temperature semiconductor growth (e.g., epitaxial growth) may not be well-suited for incremental fabrication by backside processing because the backside processing conditions may be detrimental to the frontside device, in which case wafer-level backside bonding is preferred. In contrast, low-temperature compatible devices such as many TFTs, oxide semiconductor TFETs, or STTM devices may be well-suited for incremental fabrication by backside processing. It is noted that backside processing can be performed continuously after all frontside processing is completed, or before any frontside processing is performed, or interposed between various stages of frontside processing. Although parallel dual-sided processing is conceivable, a support (e.g., donor or host) substrate that emulates essentially all processing on the first side prior to processing on the second side is favored for performance. Thus, in some embodiments, essentially all frontside processing can be performed before the backside is exposed (e.g., all the way through multiple levels of back-end metal). After the backside is exposed, essentially all backside processing can be performed (e.g., all the way through one or more levels of back-end metal). Different frontside and backside metals can be realized with this fully serialized frontside and backside processing stage that is entirely in its entirety once started. Different frontside and backside devices can also be realized in this manner. In an alternative implementation where frontside and backside processing operations are interleaved, additional transfers between the donor and host substrates may be required, which increases the complexity and cost of the manufacturing process. For example, in the case where all backside processing is inserted between frontside device cell fabrication and frontside back-end interconnect metal, an additional transfer from the frontside host substrate to the backside host substrate can be made. As described above, backside processing can be purposefully differentiated from frontside processing. Backside processing can employ a different set of materials and / or processing conditions compared to frontside processing. For example, the frontside metal can be a first metal, such as a Cu-based metal (i.e., a metal alloy that is predominantly or more than 50% Cu), and the backside metal can be a second metal different from the Cu-based metal (i.e., a metal alloy that is predominantly or more than 50% of a metal different from Cu). The frontside device can first employ a material system (e.g., a semiconductor composition), while the backside device can employ a different second material system. In this same context, backside exposure and subsequent backside processing can be positioned within the manufacturing process relative to various frontside processing operations in order to partition the dual-sided manufacturing process in a manner that adds another degree of freedom for device integration. For example, backside processing can be used as a means to integrate planar FETs with non-planar FETs, or as a means to integrate devices with different thermal margins. For example, leveraging high-temperature processing (e.g., >350°C) for frontside processing, while backside processing is limited to low temperatures (e.g., <350°C). Backside processing of the exposed portion of the device layer can include implanting a substance into the structures formed during the frontside manufacturing process. Implantation is an example of a process that may require high-temperature processing (such as for activation annealing), in which case it can be integrated with frontside processing at a point before the frontside backend interconnects are formed. In some embodiments, dopant substances can be implanted from the exposed backside of the device and / or the intermediate layer into the device layer or the intermediate layer. Backside implantation techniques can utilize the backside exposure process as a means to modify the composition of one or more non-semiconductor regions of the device structure or the surrounding structures. For example, portions of dielectrics (gate spacers, gate dielectrics, etc.) or metals (e.g., gate metals, source / drain contact metals, etc.) can be modified after they are fabricated by frontside processing. The material modification by backside implantation can take the form of microstructural modification (e.g., amorphization) and / or compositional modification. Such material modification can, for example, serve as a basis for subsequent selective material removal or growth. Implantation techniques can also utilize a backside exposure process as a means for modifying the electrical characteristics of a semiconductor structure formed during frontside processing. Backside exposure implantations can effectively delay the introduction of dopants into one or more semiconductor structures, increase the thermal margin of a given device, and / or sharpen the dopant diffusion profile. A backside exposure implantation operation can also cause doping of a semiconductor region until the backside of the semiconductor region to be doped is exposed (e.g., by substrate thinning or removal), which would not be accessible from the frontside of the device and also not accessible from the backside of the device. A backside exposure implantation operation can modify an active device region (e.g., the channel, source, drain of a FET), couple the backside to the active device region, or enhance the backside isolation of the active device region. A backside exposure implantation operation that requires activation annealing can be performed between front-end device processing compatible with the activation annealing temperature and processing that is limited to lower temperature processes (such as frontside interconnect metals). A backside exposure implantation operation that requires activation annealing can also be performed after all front-end device processing is complete, including frontside interconnect metals for which the activation annealing requires a thermal process that maintains a large temperature gradient across the thickness of the donor host component. For example, the main substrate can be held at a first temperature well below 400°C while heat is rapidly applied to the exposed backside surface of the device layer. FIG. 55 is a flowchart showing a backside processing method 5501 that includes backside implanting dopants into a semiconductor device structure according to some embodiments. Method 5501 further illustrates backside processing at the device (e.g., transistor) unit level that can be no greater than a few hundred nanometers in thickness. Method 5501 begins with a donor-host substrate assembly that includes a device layer as an input 5505. The donor substrate can have one or more of the above-described features, such as but not limited to an intermediate layer and a carrier layer. However, it is noted that the carrier layer and / or the intermediate layer are not required to perform method 5501. At operation 5510, the backside of the device layer or the intermediate layer is exposed during a backside exposure process. In some embodiments, the backside exposure process performed at operation 5510 includes one or more of the operations of method 501 (FIG. 5). For example, the backside exposure process can expose the device layer or the intermediate layer by removing at least a portion of the donor substrate (e.g., the carrier layer). One or more dopants are then implanted into the exposed device layer and / or intermediate layer. Output 5515 includes a device unit having a backside doped layer that can be expected to have a dopant distribution indicative of the introduction of dopant material from the backside of the device structure and / or indicative of the introduction of dopant material after frontside structure fabrication. The dopant distribution can, for example, show a higher material concentration near the backside of the device structure than near the frontside of the device structure. The dopant material introduced from the backside can be present in the material surrounding the semiconductor structure formed during frontside processing prior to the backside implant process. The combination of materials containing the dopant material and / or the profile of the dopant material within these materials based on the surrounding frontside structure can indicate a post-backside exposure implant process according to embodiments of method 5501. FIGS. 56A, 57A show cross-sectional views of a transistor structure 604 along the A-A' plane labeled in FIG. 6 as performed in the operations of method 5501 according to some embodiments. FIGS. 56B, 57B show cross-sectional views of the transistor structure 604 along the B-B' plane labeled in FIG. 6 as performed in the operations of method 5501 according to some embodiments. FIGS. 56C, 57C show cross-sectional views of the transistor structure 604 along the C-C' plane labeled in FIG. 6 as performed in the operations of method 5501 according to some embodiments. Figures 56A-56C show the structures present in an exemplary transistor structure after front-side processing of the donor substrate. The semiconductor body 610 is a fin-shaped structure that extends vertically (e.g., in the z-dimension). The semiconductor body 610 includes a channel portion containing the device layer 215. In the embodiments shown in Figures 56A-56C, the semiconductor body 610 further includes sub-fins having the same semiconductor composition as the device layer 215 (e.g., Si). The semiconductor body 610 may have been formed, for example, using patterned front-side recess etching of the device layer 215. As further described elsewhere herein, the semiconductor fin body may optionally include sub-fin semiconductors of a different composition than the channel portion, in which case the device layer 215 may be present only within the device channel while the sub-fin semiconductors may be part of the intermediate layer 210 (Figure 3A). Alternatively, the sub-fin semiconductors may be considered spacers between the device layer 215 and the back-side substrate, which may also include an intermediate layer between the sub-fin semiconductors and the carrier layer. Surrounding one or more sidewalls of the semiconductor body 610 is the field isolation dielectric 680. Further shown in Figures 56A and 56B is a gate stack including a gate electrode 673 disposed on a gate dielectric 845 that intersects the channel portion of the transistor semiconductor body 610, while an intersection of the source / drain metal with the source / drain semiconductor 640 is shown in Figure 56C. In Figures 56A-56C, the back-side surface 3911 of the intermediate layer 210 has been exposed by any technique, such as but not limited to method 501 (Figure 5). For example, a marker or etch stop may have been present within the first intermediate layer 210 that terminates the carrier removal operation before the back-side of the field isolation dielectric 680 is exposed. Although not shown, the back-side of the transistor semiconductor body 610 may be exposed by further removing portions of the bulk semiconductor to which the transistor semiconductor body 610 is attached, for example, substantially as described above for operation 520 (Figure 5). With the back-side surface of the intermediate layer 210 (or of the body 610) exposed, a back-side implant 5610 is performed. The back-side implant 5610 can be a blanket implant with dopant material being implanted into the semiconductor body 610 as well as into surrounding materials such as the field isolation dielectric 680. The blanket implant takes advantage of the front-side patterning of the body 610 with all exposed portions receiving the dopant. If not all of the body 610 is to receive the implant, the back-side implant 5610 can be a selective (masked) implant. The back-side implant can utilize any dopant species, dopant level, and implant energy known to be suitable for the composition of the semiconductor body 610. In some embodiments, the back-side implant requires the implantation of impurity materials that can be electrically activated by a subsequent thermal anneal at any temperature above ambient (e.g., 400 - 800 °C) to impart n-type or p-type conductivity to the doped semiconductor. Figures 57A-57C show a transistor structure including semiconductor regions doped by one or more backside implants. As shown, the intermediate layer 210 and the sub-fin of the semiconductor body 610 have been doped with dopant material to distinguish the intermediate layer 210 of each semiconductor body 610 from the device layer 215. Such backside impurity doping can be used, for example, to form well structures, such as but not limited to an n-well suitable for manufacturing a PMOS FET having a p-type source / drain semiconductor 640. Such backside impurity doping can also be used as a punchthrough stopper. In some alternative embodiments, only the intermediate layer 210 is doped by backside implant, while the sub-fin of the semiconductor body 610 is doped. In other alternative embodiments, only a portion of the sub-fin region is doped by backside implant. In still other embodiments, multiple backside implants are performed to achieve doping gradients and / or complementary doped semiconductor junctions within or between the semiconductor body 610 and the intermediate layer 210. For example, p-type and n-type junctions can be formed by backside implant, where the backside portion of the semiconductor body 610 is doped to a light to moderate "p-" doping, while the source / drain semiconductor 640 is heavily doped n-type. For example, p-type and n-type junctions can be formed by backside implant, where the backside portion of the semiconductor body 610 is doped to a light to moderate "n-" doping, while the source / drain semiconductor 640 is heavily doped p-type. Such complementary backside doping of the semiconductor body 610 can be used to reduce leakage of the on-state between fins through the intermediate layer 210. For embodiments where the intermediate layer 210 is removed and fin-to-fin leakage is less important, backside doping of the semiconductor body 610 can provide a means for a manufacturing process that fabricates diodes without distinguishing the front-side processing of transistors from the front-side processing of p / n diodes. In some embodiments, the backside implant process requires multiple selective implant operations. For example, a first backside implant may dope a first semiconductor (e.g., the first body 610 and the intermediate layer 210 of FIGS. 57A-C) into a first conductivity type (e.g., p-type). A second backside implant may dope an adjacent second semiconductor region (e.g., the second body 610 and the intermediate layer 210 of FIGS. 57A-C) into a complementary second conductivity type (e.g., n-type). Two complementary doped semiconductor regions may form a p / n junction, for example, within the intermediate layer 210. Terminals to the complementary ends of the junction may pass through the frontside and / or backside metal. In one frontside metal embodiment, a first transistor structure (e.g., a PMOS FET) having a p-type doped source / drain semiconductor 640 is backside implanted to have a p-type sub-fin and a p-type intermediate layer surrounding the p-type sub-fin (e.g., a portion of the first body 610 and the intermediate layer 210 of FIGS. 57A-C). The backside p-type doping may be electrically coupled to the frontside metal, though the p-type doped source / drain semiconductor 640. In this case, the gate electrode 673 may become a residual structure in the context of a diode. A second transistor structure (e.g., an NMOS FET) having an n-type doped source / drain semiconductor 640 is backside implanted to have an n-type sub-fin and an n-type intermediate layer surrounding the n-type sub-fin (e.g., a portion of the second body 610 and the intermediate layer 210 of FIGS. 57A-C). The backside n-type doping may be electrically coupled to the frontside metal, though the n-type doped source / drain semiconductor 640. The interface between the p-type intermediate layer region and the n-type intermediate layer region defines the p / n junction of the diode. Alternatively, the p-type intermediate layer region may be separated from the n-type intermediate layer region by an intrinsic (undoped) portion of the intermediate layer to define a p-i-n diode. In some embodiments, backside processing of the exposed portion of the device layer includes epitaxially growing semiconductor material on the backside of the semiconductor device layer. Epitaxial growth is another example of a backside process that may require high processing temperatures and thus may be staged relative to frontside processing to be compatible with all materials on the device layer. In some such embodiments, the doped source / drain semiconductor may be epitaxially grown on the backside of the device layer together with the fabrication of the backside contact and / or interconnect metal. In other embodiments, backside processing includes epitaxial growth of semiconductor material that replaces other semiconductor material removed during a backside exposure process. The epitaxially grown semiconductor may be of a different composition and / or better crystal quality than that which replaces what is removed during the backside exposure process. To perform the high temperature processing, the backside exposure and backside epitaxial growth may occur, for example, in stages before the frontside metal. It is noted that epitaxial growth of semiconductor on the backside of the frontside device layer may also be utilized in subsequent incremental backside fabrication of various backside device structures, as further described elsewhere herein. Alternatively, low-temperature deposition can also be used to form polycrystalline (e.g., micro- or nanocrystalline) or amorphous semiconductor layers, such as but not limited to an oxide semiconductor layer (e.g., IGZO) on the back side of the exposed device layer. Any thin-film transistor (TFT) manufacturing process can then utilize this back-side thin-film semiconductor to form a back-side TFT circuit. FIG. 58 is a flowchart of a back-side processing method 5801 showing epitaxial growth or bonding of a back-side semiconductor layer including a substantially single-crystalline according to some embodiments. Polycrystalline or amorphous semiconductors can also be formed, e.g., at lower temperatures (e.g., 100 - 400°C). Method 5801 further illustrates back-side processing of device (e.g., transistor) unit layers that may be no more than a few hundred nanometers thick. Method 5801 begins with a donor-host substrate assembly including a device layer as input 5805. The donor substrate can have one or more of the above-described features, such as but not limited to an intermediate layer and a carrier layer. However, it is noted that for performing method 5801, a carrier layer and / or an intermediate layer is not necessary. In operation 5810, the back side of the device layer or the intermediate layer is exposed during a back-side exposure process. In some embodiments, the back-side exposure process performed at operation 5810 includes one or more of the operations of method 501 (FIG. 5). The back-side exposure process can, for example, expose the device layer or the intermediate layer by removing at least a portion (e.g., the carrier layer) of the donor substrate. One or more semiconductor layers are then grown or deposited on the exposed device layer. Alternatively, one or more semiconductor layers are bonded to the exposed device layer, e.g., using a semiconductor oxide bonding interface. Output 5815 includes a device unit having a single-crystalline semiconductor material disposed on the back side of device layer 215. Alternatively, if low-temperature deposition is employed, the output of method 5801 is a device having a polycrystalline or amorphous semiconductor material disposed above the back side of device layer 215. FIGS. 59A, 59B, 59C show cross-sectional views of III-N semiconductor device layers of some operations in method 5801 as performed on a donor-host assembly 203 according to some embodiments. As shown in FIG. 59A, a donor-host assembly 203 including a donor substrate 201 (e.g., substantially as described above with respect to FIGS. 4A - 4C) is connected to a host substrate 202 using any front-side stack 690 disposed therebetween. The front-side stack 690 is shown in dashed lines as part of the device unit layer, which can vary without limitation and can, for example, include any number of back-end interconnect metal layers. The host substrate 202 can, for example, have any of the attributes described elsewhere herein. As shown, the host substrate 202 is bonded to the front-side surface of the front-side stack 690, e.g., by thermocompression bonding. Device terminals that have not been formed on or coupled to device layer 215 are further shown in the embodiment to illustrate how back-side device layer processing can be very superior to front-side device layer processing. As further shown in FIG. 59B, the donor substrate 201 has been removed, exposing the backside of the intermediate layer 210, which includes semiconductor islands surrounded by isolation dielectric 480. The donor substrate 201 can be thinned and / or removed by any technique, such as but not limited to method 501 (FIG. 5). The exposed surface of the semiconductor can have a high number of defects 440, which propagate, for example, during heteroepitaxial growth. The intermediate layer 210 can then be removed from the device layer 215, exposing the backside of the device layer 215. The intermediate layer 210 can be removed by CMP, in which case both the semiconductor and the isolation dielectric 480 can be removed. Alternatively, the intermediate layer 210 can be removed with an etching process that is selective to the semiconductor, in which case the isolation dielectric 480 can be retained. For some embodiments, the backside surface of the device layer 215 (e.g., when the device layer 215 is GaN) has a significantly lower defect density (i.e., better crystal quality) compared to the semiconductor removed as part of the intermediate layer 210. The semiconductor layer 5915 is then deposited or grown on the backside surface of the device layer 215, e.g., using any epitaxial growth or deposition technique known to be suitable for the selected semiconductor material. The semiconductor layer 5915 can also be grown or deposited within the openings in the isolation dielectric 480 (if it is retained). Because the device layer 215 provides a high-quality seed surface, regrowth of the semiconductor layer 5915 is also high-quality, with few crystal defects 440. After backside epitaxial growth, which can be a high-temperature process (e.g., above 900°C for III-V embodiments), backside processing and / or frontside processing can continue with lower-temperature processes to fabricate devices (e.g., HFETs) in the device layer 215 and / or in the epitaxially grown semiconductor layer 5915. It is noted that the semiconductor layer 5915 does not need to have the same composition as the device layer 215. The compositional difference between the device layer 215 and the semiconductor layer 5915 can be exploited, e.g., to impart strain in layer 215 or 5915 through lattice mismatch engineering. In some embodiments where the device layer 215 is GaN, the semiconductor layer 5915 is a III-N alloy with a different lattice constant compared to the device layer 215. In some embodiments where the device layer 215 is Si, the semiconductor layer 5915 is a III-V or group-IV alloy with a different lattice constant compared to the device layer 215. For such embodiments, the semiconductor layer 5915 can advantageously impart uniaxial and / or biaxial strain in the device layer 215 or vice versa. In still other embodiments where the device layer 215 is a III-N alloy, the epitaxially grown semiconductor layer 5915 is a transition metal dichalcogenide (TMD or TMDC). Similar to graphene, TMDC exhibits as MX 2The semiconductor properties of a single-layer sheet, where M is a transition metal atom (e.g., Mo, W), and X is a chalcogen atom (S, Se, or Te). In a single-layer crystal sheet, one layer of M atoms is disposed between two layers of X atoms. After the growth of the TMDC sheet, backside processing can also include fabricating a transistor with a TMDC channel having any known architecture. In some embodiments, during the fabrication process of vertically stacked devices or vertically oriented devices, the backside semiconductor is epitaxially grown or deposited in polycrystalline or amorphous form. For some exemplary architectures, the front-side device layer is epitaxially grown on a donor substrate, and then upon removal of the donor substrate, the backside exposure can expose a semiconductor layer having crystallinity that facilitates the regrowth of the second (backside) device layer. The front-side and backside device layers within the device layer can then be used for separate functional regions of a vertically oriented transistor or can be used for two vertically stacked, laterally oriented transistors. One challenge faced by many vertically oriented device architectures is the fabrication of device terminals at opposite ends of the device, which can be difficult when relying solely on front-side processing. However, the backside exposure technique described herein, once exposed, enables a mode transition from "bottom-up" device fabrication to "center-outward" device fabrication by utilizing a first portion of the device grown epitaxially from the front side and a second portion of the device grown epitaxially from the back side. Thus, an exemplary vertical FET can be fabricated by first forming a source (or drain) semiconductor on the front side of the device layer that provides the transistor channel. The drain (or source) semiconductor that can be formed on the back side of the device layer is then coupled to backside metal after the backside exposure process. A bipolar transistor can be fabricated similarly, for example, by first forming an emitter (or collector) semiconductor on the front side of the device layer that provides the base of the transistor. The collector (or emitter) semiconductor is then formed on the back side of the device layer after the backside exposure process. Figures 60A, 60B, and 60C show cross-sectional views of semiconductor device layers when performing some operations in method 5801, according to some embodiments of stacked device layers. Method 5801 begins with receiving a donor-host assembly 203, which includes a host substrate 202 and a donor substrate 201, for example, substantially as described above with respect to FIG. 59A. However, in the embodiment shown in FIG. 60A, the donor-host assembly 203 includes a front-side device layer 215B above a core semiconductor device layer 215A. The semiconductor material of the core device layer 215A has been patterned into features (e.g., fins, pillars, dots, etc.) surrounded by field isolation dielectrics 6080. The semiconductor features of the front-side device layer 215B are above the features of the core device layer. A front-side stack 690 is above the front-side device layer 215B. In some embodiments, when the features of the front-side device layer are impurity-doped source / drain semiconductors, the front-side stack 690 may include front-side source / drain contact metals. The front-side stack 690 may also include gate electrodes coupled to the core semiconductor layer features. During back-side processing, the back-side of the core device layer 215A is exposed. For example, as further shown in FIG. 60B, the donor substrate 205 and the intermediate layer 210 have been removed during the back-side exposure operation, exposing the core device layer 215A and the field isolation dielectrics 6080. As shown in FIG. 60C, a back-side semiconductor layer 5915 is then epitaxially grown (e.g., selectively) or deposited on the back-side surface of the core device layer 215A. The semiconductor layer 5915 may be grown or deposited to form devices independent of the front-side device layer 215B or devices with lateral or vertical orientations depending on the front-side device layer 215B. A back-side stack 6090 is then fabricated and / or bonded to the double-sided hierarchy to interconnect the features in the back-side semiconductor layer 5915. For example, the back-side stack 6090 may include back-side source / drain contact metals. In some embodiments, the core device layer 215A provides electrical isolation between the front-side device layer 215B and the back-side semiconductor layer 5915. For example, the core device layer 215A may have a wider bandgap and / or bandgap offset in one or both of the conduction band and the valence band, such that charge carriers are respectively confined within the front-side and back-side device layers 215B, 5915. Embodiments of homogeneous semiconductors may also depend on the core device layer 215A to provide dopant junction isolation between the front-side device layer 215B and the back-side semiconductor layer 5915. For such an architecture, the front-side stack 690 may provide all terminals (e.g., gate, source, and drain) of a front-side laterally oriented device (e.g., FET) employing the front-side device layer 215B. An equivalent back-side stack may further provide all terminals (e.g., gate, source, and drain) to a back-side laterally oriented device (e.g., FET) employing the back-side semiconductor layer 5915. As an alternative to backside epitaxial growth or amorphous / polycrystalline film deposition, the backside semiconductor structure can be fabricated as fins by exposing sub-fins of the front-side fin structure, e.g., by selectively recessing the backside of the field isolation dielectric surrounding the front-side fins. Alternatively, the backside semiconductor body can be patterned from an intervening semiconductor layer that is exposed during the backside exposure. For such embodiments, backside epitaxy and / or backside implant can also be used to form a backside semiconductor layer 5915 that includes backside source / drain semiconductor regions. FIG. 61A shows a cross-sectional view of a transistor structure 604 stacked with a planar backside transistor structure 6104 along the A-A' plane shown in FIG. 6, according to some embodiments of stacked FETs. FIG. 61B shows a cross-sectional view of the transistor structure 604 stacked with the planar backside transistor structure 6104 along the B-B' plane shown in FIG. 6, according to some embodiments of stacked FETs. In some embodiments, the backside transistor structure 6104 is incrementally fabricated from the exposed backside of the transistor structure 604. For such embodiments, the backside exposure not only separates the front-side fabrication from the backside fabrication, but also separates the non-planar FET fabrication process from the planar FET fabrication process. In an alternative embodiment, the backside transistor structure 6104 is pre-fabricated and transferred as a second device layer that is bonded, e.g., at a bonding interface 6199, to the exposed backside of the transistor structure 604. Notably, while planar FETs are advantageous for many applications (e.g., high-current power FETs), the fabrication of planar FETs is often incompatible with the fabrication of finFETs, making it difficult to incorporate both transistor architectures in different regions of a substrate. Using dual-sided processing enabled by backside exposure techniques such as those described elsewhere herein, the fabrication of planar FETs can be continuously integrated with the fabrication of finFETs. As shown in FIG. 61A, the front-side device layer 215A layer is disposed on a semiconductor body 610 having a lateral length extending in the A-A' plane. The sub-fin portions of the semiconductor body 610 and any intervening layer 210 serve as the core device layer 215B (e.g., silicon or a suitably matched compound semiconductor). The back-side semiconductor layer 5915 can be epitaxially grown on the exposed back-side surface of the core device layer 215B. The semiconductor layer 5915 can be of any composition, such as any of those provided for the device layer 215A. In some embodiments, the semiconductor layer 5915 has a composition different from that of the device layer 215A. In some embodiments, the semiconductor layer 3915 has the same composition as the device layer 215A. In some embodiments, the semiconductor layer 5915 has a conductivity type complementary to that of the device layer 215A (e.g., the semiconductor layer 5915 is p-type and the device layer 215A is n-type, or vice versa). In some embodiments, the semiconductor layer 5915 is a single-crystalline III-V material and the device layer 215A is single-crystalline silicon. In other embodiments, the device layer 215A is a single-crystalline III-V material and the semiconductor layer 5915 is single-crystalline silicon. In some embodiments, the device layer 215A is silicon and the semiconductor layer 5915 is single-crystalline III-N (e.g., GaN). Instead of bonding or epitaxially growing the semiconductor layer 5915 (e.g., having an oxide bonding interface), the intervening layer 210 can serve as a foundation for the back-side device layer, e.g., having an FET channel region 6110 disposed within the intervening layer 210. A back-side gate stack including a back-side gate dielectric 6145 and a back-side gate electrode 6173 is disposed on the channel region 6110. The back-side source / drain semiconductor 6140 is epitaxially grown, deposited, or otherwise formed at opposite ends of the channel region 6110 and is electrically isolated from the back-side gate electrode 6173 by an intervening back-side dielectric spacer 6171. The back-side source / drain semiconductor 6140 can be of any composition, such as any of those provided for the source / drain semiconductor 640. In some embodiments, the source / drain semiconductor 6140 has the same composition as the source / drain semiconductor 640. In some embodiments, the source / drain semiconductor 6140 has a complementary conductivity type to that of the source / drain semiconductor 640 (e.g., 6140 is p-type and 640 is n-type, or vice versa). In some embodiments, the source / drain semiconductor 6140 and the source / drain semiconductor 640 are of the same conductivity type. The back-side field isolation dielectric 6180 surrounds the active device structure in the same manner as the field isolation dielectric 680. Note that, although as shown in FIG. 61B, the gate length of the front-side transistor structure 604 extends in the A-A' plane, as shown in FIG. 61A, the back-side planar transistor structure 6104 has a channel length that extends in the B-B' plane. Thus, the currents flowing through the stacked channel regions are not parallel and are advantageously orthogonal. Although the relative orientation of the stacked FET cells shown can provide advantages such as reduced parasitic effects (inductive, capacitive crosstalk), FET orientations with parallel channel currents are also possible. Similarly, although the examples shown in FIGS. 61A and 61B show that the planar transistor structure 6104 has a coverage area that is substantially equal to that of the transistor structure 604 employing two semiconductor bodies 610, the relative sizes of the front-side finFET and the back-side planar FET may vary. Additionally, although the examples shown in FIGS. 61A and 61B show that the planar transistor structure 6104 is vertically aligned with the transistor structure 604, stacked transistor embodiments can incorporate any number of lateral offsets between the front-side and back-side transistor structures. FIG. 62A shows a cross-sectional view of a transistor structure 604 stacked on a back-side transistor structure 6204 along the A-A' plane shown in FIG. 6, according to some embodiments of stacked FETs. FIG. 62B shows a cross-sectional view of a transistor structure 604 stacked on a back-side transistor structure 6204 along the B-B' plane shown in FIG. 6, according to some embodiments of stacked FETs. In some embodiments, the back-side transistor structure 6204 is incrementally fabricated from the exposed back side of the transistor structure 604. In alternative embodiments, the back-side transistor structure 6104 is pre-fabricated and transferred as a second device layer that is, for example, bonded to the exposed back side of the transistor structure 604 at a bonding interface 6199. Back-side exposure, semiconductor layer patterning, bonding, and / or subsequent epitaxial device layer growth or deposition can be used to increase the density of transistor gates for a given coverage area (e.g., doubling the amount of finFET cells in a given area). As shown in FIG. 62A, a front-side device layer 215A is disposed on a semiconductor body 610 having a lateral length that extends in the A-A' plane. The sub-fin and any intermediate layer 210 of the semiconductor body 610 serve as a core device layer 215B (e.g., silicon or a suitably matched compound semiconductor). A back-side semiconductor layer 5915 can be epitaxially grown or deposited as a polycrystalline or amorphous thin film on the exposed back-side surface of the core device layer 215B. The film growth or deposition can be restricted (or made selective) to form a non-planar back-side semiconductor body 6210, or a back-side patterning process can be used to define a non-planar back-side semiconductor body 6210 from an epitaxially grown or non-epitaxially deposited semiconductor layer. In some alternative embodiments, the intermediate layer 210 can alternatively serve as a back-side device layer that is patterned into a back-side fin body. A back gate stack including a back gate dielectric 6145 and a back gate electrode 6173 is disposed over a channel region of a back semiconductor body 6210. Back source / drain semiconductors 6140 are epitaxially grown, non-epitaxially deposited, and / or impurity doped at opposite ends of the channel region 6110, and are electrically isolated from the back gate electrode 6173 by intervening back dielectric spacers 6171. A back field isolation dielectric 6180 surrounds the active device structure in the same manner as the field isolation dielectric 680. Note that while, as shown in FIG. 62B, the gate length of the front-side transistor structure 604 extends in the A-A' plane, as shown in FIG. 62A, the back-side transistor structure 6204 has a channel length that extends in the B-B' plane. Thus, the currents flowing through the channel regions of the stack are not parallel and are advantageously orthogonal. While the relative orientation of the stacked FET cells shown can provide advantages such as reduced parasitic effects (inductive, capacitive crosstalk), a stacked FET orientation resulting in parallel channel currents is also possible. Similarly, although the examples shown in FIGS. 62A and 62B show the transistor structure 6204 having a coverage area that is substantially equal to that of the transistor structure 604, the relative sizes of the front-side and back-side finFETs may vary. Additionally, although the examples shown in FIGS. 62A and 62B show the transistor structure 6204 being vertically aligned with the transistor structure 604, stacked transistor embodiments can again incorporate any number of lateral offsets between the front-side and back-side transistor structures. FIG. 63A shows a cross-sectional view of the transistor structure 604 and the back-side transistor structure 6304 along the A-A' plane shown in FIG. 6 in accordance with some embodiments of stacked FETs. FIG. 63B shows a cross-sectional view of the transistor structure 604 and the back-side transistor structure 6304 along the B-B' plane shown in FIG. 6 in accordance with some embodiments of stacked FETs. For these embodiments, the back-side transistor structure 6304 is incrementally fabricated from the exposed back-side of the transistor structure 604. This back-side processing can utilize self-alignment techniques to fabricate additional FET structures in a semiconductor body fabricated on the front side. Thus, the front-side FET and the back-side FET have channel regions disposed in the front side and the back side of the semiconductor body, respectively. Contrasted with the examples shown in FIGS. 62A and 62B, the channel current in the back-side FET cell 6304 is substantially parallel to the channel current in the front-side transistor structure 604. For such embodiments, the back semiconductor body 6210 can be fabricated as a fin by exposing a sub-fin of the body 610, e.g., by selectively recessing the back side of the field isolation dielectric 680 surrounding the body. Alternatively, referring further to FIGS. 62A and 62B, the semiconductor body 6210 can be patterned from an intervening semiconductor layer exposed during the backside exposure. In other embodiments, the semiconductor body 6210 can be epitaxially grown from the backside seed surface of the body 610 during a backside epitaxial process. The backside epitaxial or semiconductor deposition process can also be used to form the backside source / drain semiconductor 6140. Alternatively, backside impurity implantation can be used to form the backside source / drain semiconductor 6140. In still other embodiments, the semiconductor body 6210 can be fabricated from an amorphous or polycrystalline thin film semiconductor (e.g., an oxide semiconductor) deposited on the backside surface of the body 610 during a backside TFT deposition process. For such embodiments, a thin film of the amorphous or polycrystalline semiconductor can be deposited on the backside isolation dielectric layer, e.g., fabricated according to method 701. In some embodiments further illustrated by FIGS. 63A and 63B, the backside source / drain semiconductor 6140 is in direct contact with the frontside source / drain semiconductor 640. In the illustrated example, the source / drain semiconductor 6140 extends beyond the exposed backside of the semiconductor body 610 (e.g., as described above in the context of fabricating the backside source terminal) to contact the frontside source / drain semiconductor 640. The source / drain semiconductor 6140 can be formed, for example, by masked backside implantation (e.g., according to method 4901), or by backside semiconductor deposition or epitaxial growth (e.g., according to method 5801). In some embodiments where the backside transistor structure 6304 is a TFET, the independent formation of the complementary doped source and drain further allows one of the source or drain to be formed deeper than the other to be able to directly contact only one of the frontside source / drain semiconductor regions. In some embodiments where the backside transistor structure 6304 is a TFT, the source / drain semiconductor 6140 can be formed from a portion of a semiconductor thin film (e.g., an oxide semiconductor) using any known technique. FIG. 64A shows a cross-sectional view of the transistor structure 604 and the backside transistor structure 6404 along the A-A' plane shown in FIG. 6 according to some embodiments of stacked FETs. FIG. 64B shows a cross-sectional view of the transistor structure 604 and the backside transistor structure 6404 along the B-B' plane shown in FIG. 6 according to some embodiments of stacked FETs. For these embodiments, the backside transistor structure 6404 is incrementally fabricated from the exposed backside of the transistor structure 604. Such backside processing can utilize self-alignment techniques to fabricate additional FET structures in the semiconductor body fabricated on the frontside. For the exemplary embodiment shown in FIGS. 64A - 64B, the front - side non - planar FET and the back - side planar FET have a source / drain semiconductor in direct contact. Contrasted with the example shown in FIG. 61, the channel current in the back - side transistor structure 6404 is substantially parallel to the channel current in the front - side transistor structure 6404. In this example, the source / drain semiconductor 6440 extends beyond the exposed back - side of the semiconductor body 610 to contact the front - side source / drain semiconductor 640. The source / drain semiconductor 6440 can be formed by masked back - side implantation or by back - side semiconductor material deposition. Alternatively, the source / drain semiconductor 640 can extend to the exposed back - side of the semiconductor body 610, which then makes a source / drain electrical contact with the back - side transistor structure 604 having only the interface between the source / drain semiconductor 640 and the source / drain semiconductor 6440, and then deviates from that shown in FIG. 64B, rather than being at the junctions of 215B and 5915. In some embodiments, a TFET is fabricated by front - side or back - side processing, while another device is fabricated on the opposite side of the TFET. A TFET is a transistor having a similar structure to a conventional metal - oxide - semiconductor field - effect transistor (TFT), except that the source and drain terminals of the TFET are of opposite conductive types. Thus, any TFT or any TFET can be fabricated on the back - side of the device layer. The common TFET device structure consists of a p - i - n (p - type - intrinsic - n - type) junction, where the gate electrode controls the electrostatic potential of the intrinsic region. The switching mechanism of the TFET regulates quantum tunneling through a barrier associated with the p - i - n junction, rather than regulating thermionic emission over a barrier as in a conventional MOSFET. The TFET is thus a promising candidate for low - energy electronics. As described above, back - side processing can be limited to lower processing temperatures, making it well - suited for integrating TFETs or other TFTs compatible with low - temperature processing with front - side FETs. Many oxide semiconductors can be formed at low temperatures, making such materials suitable for back - side TFT designs. For other TFT and TFET material systems (e.g., SiGe and / or III - V alloys), high processing temperatures (e.g., above 600 °C) may be required, which may be incompatible with typical CMOS circuits. For such embodiments, the TFT or TFET structures requiring high - temperature processing can be fabricated first during front - side processing, and then the low - temperature TFT structures are fabricated during back - side processing, subsequently exposing the back - side of the TFET. A back or front side TFT or TFET can be stacked with any front side / back side device, such as a FET, another TFET (or other TFT), a memory cell, a HFET, a HBT, a photodiode, a laser, etc. For example, one or more of the transistor structures 604, 6104, 6204, 6304, 6404 can be a TFET or a TFT. In some embodiments, the planar TFT 6404 can be fabricated on the back side of the non-planar FET 604. In some other embodiments, the transistor structures 604, 6104; 604 and 6204; 604 and 6204; or 604 and 6304 are all TFTs. One or more of such TFTs can further be a thin film tunneling transistor (e.g., a thin film TFET). In some such embodiments, the transistor structure 604 is an n-type TFET having an n-type source semiconductor 640, a p-type drain semiconductor 640, and an intrinsic semiconductor channel region, and the transistor structures 6104, 6204, 6304, or 6404 are p-type TFETs having a p-type source semiconductor 6140, an n-type drain semiconductor 6140, and an intrinsic semiconductor channel region 6110. In some other embodiments, the transistor structure 604 is an n-type FET or TFT having an n-type source and drain semiconductor 640 and an intrinsic semiconductor channel region, and the transistor structures 6104, 6204, 6304, or 6404 are p-type FETs or TFTs having a p-type source and drain semiconductor 6140. To fabricate such a TFET or TFT stack, the back side of the intrinsic semiconductor (e.g., the semiconductor body 610 or the intermediate layer 210) can be exposed, for example, using any of the techniques described elsewhere herein. If desired, a junction isolation layer can be formed, for example, through back side implantation and / or back side epitaxial semiconductor growth. The back side source / drain semiconductor 6140 can then be formed with the desired conductivity type (e.g., in series). In some TFET embodiments, the TFET includes a channel material that separates a p-type material having p-type conductivity from an n-type material having n-type conductivity. A gate dielectric material separates the gate electrode material from the channel material. In some embodiments, the TFET is an n-type device where the p-type material serves as the source and negative charge carriers tunnel from the valence band in the p-type material to the conduction band in the channel material. In some embodiments, the TFET is a p-type device where the p-type material serves as the drain and positive charge carriers tunnel from the conduction band in the n-type material to the valence band in the channel material. Back-side TFET or TFT embodiments may employ any materials known to be suitable for TFETs or TFTs, respectively. In some embodiments, at least one of the p-type material, channel material, or n-type material is a semiconductor oxide (i.e., an oxide semiconductor). Such embodiments are compatible with a back-side TFET (or any other TFT architecture) fabricated after a front-side FET, e.g., because they can be deposited at low temperatures. In some embodiments, only one of the p-type material, channel material, or n-type material is a semiconductor oxide, while the other materials are non-oxide semiconductors. Many oxide semiconductors have a high defect density closer to the valence band but exhibit good n-type electrical properties. Some oxide semiconductors have a high defect density in the conduction band but exhibit good p-type electrical properties. In some advantageous embodiments, the one oxide semiconductor is the p-type material. In other embodiments, the one oxide semiconductor is the channel material. In still other embodiments, the one oxide semiconductor is the n-type material. In some embodiments, two or more of the p-type material, channel material, or n-type material are oxide semiconductors. In some such embodiments, both the channel material and the n-type material are oxide semiconductors. In some embodiments, the two oxide semiconductors comprise the p-type material and the n-type material, and the two oxide semiconductor materials provide a type-II or type-III band offset. In still other embodiments, the source material, channel material, and drain material are all oxide semiconductors. The use of oxide semiconductors can result in the fabrication of low-temperature TFTs (which can be TFETs or FETs) and exhibit excellent transistor characteristics due to the ability to tune the bandgap and resistivity of the materials. Although such semiconductor oxides may exhibit some degree of ordering (e.g., nanocrystallinity), in some embodiments suitable for the lowest processing temperatures, the oxide semiconductors are amorphous. Various oxide semiconductors are known. Examples are metal oxides containing transition metals (e.g., IUPAC groups 4-6) or post-transition metals (e.g., IUPAC groups 11-14). These metal oxides can be suboxides (A 2 O), monoxides (AO), dioxides (AO 2 ), trioxides (ABO 3 ), and mixtures thereof. Some specific examples include tin oxide (SnO2 or SnO), zinc(II) oxide, ZnO, CuO X , and NiO XSome non-oxide semiconductors can also be formed with sufficient crystal quality at relatively low processing temperatures. For example, single-crystalline germanium and GeSn can be formed at 300 - 400 °C, while other Group-IV and III-V materials can also be produced in polycrystalline form at temperatures below 400 °C and in amorphous form at even lower temperatures. In some TFET embodiments, at least one of the p-type material, the channel material, and the n-type material is a different material from the others, such that at least one of the p / i or n / i junctions is a heterojunction. In some embodiments, the p-type material forms a heterojunction with the channel material. In some exemplary nTFET embodiments, the source p-type material and the channel material have either a type-II (staggered) or type-III (broken) band offset, which is beneficial for a higher tunneling probability and thus a higher on-state drain current. For embodiments that include such a heterojunction, the drain n-type material can form a second heterojunction with the channel material. In some embodiments, thin-film transistors (TFTs) are fabricated using front-side or back-side processing, while another device is fabricated on the opposite side of the TFT. Alternatively, the TFT layer is bonded to another layer. As described above, back-side processing can be limited to lower processing temperatures, making back-side TFTs well-suited for front-side FETs. Any TFT that is typically employed in the BEOL circuit as the top layer on a front-side FET can alternatively (or additionally) be implemented on the back side of the front-side FET after the back side is exposed. For some such embodiments, stacked TFTs and FETs can include planar TFTs fabricated on the back side of a non-planar FET. For other such embodiments, stacked TFTs and FETs can include non-planar TFTs fabricated on the back side of a non-planar FET. Since one or more FET terminals can be exposed during the back-side exposure process (e.g., after method 1201), the back-side TFT terminals can be in direct contact with the front-side FET terminals, as shown in FIG. 64B, for example. For TFT embodiments, a low-temperature back-side deposition process can form a polycrystalline or amorphous semiconductor film, rather than the crystalline semiconductor employed in non-TFT device embodiments. Thus, the back-side semiconductor (e.g., 5915 in FIGS. 64A, 64B) does not need to be single-crystalline and can be polycrystalline or amorphous material. Similarly, the source / drain semiconductor (e.g., 6440 in FIGS. 64A, 64B) can also be polycrystalline or amorphous. For example, device layer 5915 can include InGaO 3 (ZnO) 5 , which is commonly abbreviated as IGZO. In some embodiments, high-voltage transistors are fabricated using front-side or back-side processing, while low-voltage devices are fabricated on the opposite side of the high-voltage devices. As described above, dual-sided device fabrication can facilitate the integration of planar and non-planar transistors. In some embodiments, planar transistors are configured for high-voltage operation, while non-planar transistors are configured for low-voltage operation. For example, planar transistors can have dimensions of significantly larger gate widths than non-planar transistors. Planar transistors can also have dimensions of significantly larger gate lengths and / or larger non-intrinsic drain lengths than non-planar transistors. In some embodiments, a front-side finFET includes a source or drain that is directly coupled to the source or drain of a back-side planar FET. Such circuitry can be implemented using the stacked planar / non-planar FETs shown in FIGS. 61A, 61B, and FIGS. 64A, 64B. The coupling between the finFET and the planar FET can also be through a back-side source contact metal. In some such embodiments, the back-side source contact metal is also coupled to a back-side interconnect metal that couples the sources of a plurality of such front-side finFETs to the drain of a back-side planar FET. In addition to the laterally oriented back-side devices described above, one or more of the back-side processing techniques described herein can be used to form vertically oriented devices, such as but not limited to nanowire FETs, TFETs, bipolar transistors, or memory cells. For example, semiconductor deposition or epitaxial growth on both the front-side and back-side of a core device layer from a seed surface can be used to additively fabricate vertically oriented devices having terminals on both the front-side and back-side of a semiconductor device layer or layer stack. Additionally, or in the alternative, back-side metals can be deposited on the exposed back-side of a semiconductor layer to electrically couple one or more vertically oriented device terminals. FIG. 65 shows a plan view of an exemplary vertically oriented transistor structure 6504 in accordance with some exemplary embodiments. The transistor structure 6504 can be fabricated in accordance with method 1201 or 4101, for example, using any known front-side processing techniques supplemented with one or more of the back-side exposure operations described herein, followed by one or more of the back-side exposure operations described herein. FIG. 66 shows a cross-sectional view of a transistor structure 6504 along line A-A' shown in FIG. 65 according to some vertical-oriented FET embodiments. As shown in FIG. 66, the transistor structure 6504 includes a semiconductor material column surrounded on all four sides by a gate stack including a gate dielectric 845 and a gate electrode 673, which can be, for example, any of the materials described above. A front-side metal 650 is disposed on the front side of the semiconductor column. As further shown in FIG. 66, the semiconductor column includes a source / drain semiconductor 640 disposed on a semiconductor body 610. The gate dielectric 845 laterally separates the gate electrode 673 from the semiconductor body 610 that can operate as an FET channel. In the illustrated embodiment, the front-side device layer 215A includes the semiconductor body 610 and the source and drain semiconductors 640. The back side of the doped source (drain) semiconductor 640 is exposed during back-side processing, and a back-side metal 1650 is formed, for example, as described elsewhere herein. Alternatively, the back side of some other portion of the device layer 215A (e.g., the semiconductor body 610) is exposed, and a back-side device layer is then epitaxially grown or deposited on the exposed semiconductor surface to extend the z-height of the semiconductor column. Such epitaxial growth can complete the back side of a single vertical-oriented device or form a separate back-side vertical-oriented device stacked with the front-side vertical-oriented device. In some embodiments, front-side and back-side processing are used to fabricate a vertical-oriented TFET. The transistor structure 6504 can be a TFET cell, for example, where the source semiconductor 640 has a first conductivity type (e.g., n-type), and the semiconductor body 610 is an intrinsic semiconductor that will serve as the channel region. The back-side exposure process then exposes the back side of the semiconductor body 610, and a drain semiconductor 640 of a second conductivity type (e.g., p-type) is grown by back-side epitaxial or non-epitaxial deposition (e.g., using a low-temperature process). In some other embodiments, front-side and back-side processing are used to fabricate a vertical-oriented TFT. The transistor structure 6504 can be a TFT, for example, where the source semiconductor 640 has a first conductivity type (e.g., n-type), and the semiconductor body 610 is an intrinsic semiconductor that will serve as the channel region. The back-side exposure process then exposes the back side of the semiconductor body 610, and a drain semiconductor 640 of the first conductivity type (e.g., n-type) is deposited (e.g., using a low-temperature process). In some embodiments, front - side and back - side processing are used to fabricate memory cells. In some embodiments, a memory cell includes an access transistor and a memory element. In one example, the FET can be fabricated during front - side processing, while a memory device, such as but not limited to a capacitive memory element, can be fabricated as a stacked (1T1C) unit during back - side processing. In another example, the FET can be fabricated during front - side processing, while a memory device, such as but not limited to a resistive memory element, can be fabricated as a stacked (1T1R) unit during back - side processing. The resistive element can be an electron - spin - based memory device (e.g., including a magnetic or ferroelectric tunneling junction) fabricated during back - side processing. Some challenges currently faced by electron - spin - based memory devices relate to maintaining sufficient thermodynamic stability at the tunneling junction to retain a state. Thus, many spin - based memory fabrication procedures limit the processing temperature to a degree below what is typically required for transistor fabrication (e.g., 500 - 800 °C), and even lower than what is typically used for backend interconnects (e.g., 300 °C). This limitation, which can make it difficult to integrate spin - based memory devices with CMOS (FET) circuits, can be overcome by completing the fabrication of the CMOS circuit during front - side processing and then exposing the back - side during back - side processing of a subset of the FETs that will be integrated into memory cells with spin - based memory devices fabricated thereon. Fabricating a spin - based memory device close enough to the FET circuit is another challenge in some memory technologies. For example, the resistance change in a tunneling device that will be detected by an FET - type sensing circuit can be minuscule and, correspondingly, can be easily overwhelmed by parasitic wire resistance if there is not much routing between the FET circuit and the tunneling device. This difficulty can also be addressed through back - side fabrication of the tunneling device, as it can then be fabricated in close contact with the terminals of the front - side FET, while still isolating the tunneling device from the fabrication of all front - side CMOS circuits by staging the exposure of the back - side, and the tunneling device fabrication is designed to follow the fabrication of the CMOS circuit. An example of a tunneling memory device is a spin - transfer - torque memory (STTM) device, which is a non - volatile memory device that utilizes a phenomenon called tunneling magnetoresistance (TMR). For a structure that includes two ferromagnetic layers separated by a thin insulating tunneling layer, electrons are more likely to tunnel through the tunneling layer when the magnetizations of the two magnetic layers are in a parallel orientation compared to when they are not (non - parallel or antiparallel orientation). Thus, a magnetic tunneling junction (MTJ), which typically includes a fixed magnetic layer and a free magnetic layer separated by a tunneling barrier layer, can switch between two states of resistance, one state having a low resistance and one state having a high resistance. Limiting both the processing temperature and the routing resistance can be important for implementing a memory array that includes many such devices. FIG. 67A shows a cross-sectional view of a transistor structure 604 and a backside STTM device 6704 along the B-B' plane shown in FIG. 6 according to some stacked 1T1R embodiments. Applications for such 1T1R cells include embedded memory, embedded non-volatile memory (NVM), magnetic random access memory (MRAM), and non-embedded or stand-alone memory. For these exemplary embodiments, the source or drain terminal of the front-side non-planar transistor structure 604 is in direct contact with the electrode of the STTM device 6704. Such direct contact can be facilitated through selective backside processing (e.g., backside formation of the source / drain semiconductor 1640 and the backside metal 1650). Such direct contact can also be facilitated through selective front-side processing (e.g., front-side formation of the deep source / drain semiconductor 640) and the backside metal 1650. In some such embodiments, a metal containing titanium mediates the source or drain contact metal of the transistor structure 604 using the bottom electrode of the STTM device 6704. Alternatively, one or more tiers of backside interconnect wiring metals can be disposed between the electrode of the backside STTM device and the front-side FET. In FIG. 67A, the material layers of the STTM device 6704 can be built up step by step through additional backside processing, or a device layer containing a prefabricated STTM device 6704 can be bonded to the backside of the transistor structure 604 (e.g., using any known layer transfer process). The bonding interface 6199 (e.g., through a bonding metal such as Au) indicates such a bonding structure. FIG. 67B shows a cross-sectional view of a transistor structure 604 and a backside STTM device 6704 along the B-B' plane shown in FIG. 6 according to some alternative embodiments where the STTM device 6704 has been bonded to the exposed backside surface of the transistor structure 604. For such embodiments, during backside exposure, the filled deep vias 385 passing through the transistor structure 604 are exposed rather than directly contacting the source / drain terminals of the transistor structure 604, and are relied upon to make electrical contact to the metal electrode 6707. After backside exposure, a bonding metal can be deposited on the backside of the transistor structure 604 such that it contacts the filled deep vias 385. The bonding metal can then be bonded to another bonding metal to form the bonding interface 6199 that bonds the STTM device 6704 to the transistor structure 604. The STTM device 6704 can then be separated from the donor substrate (not depicted). The filled deep vias 385 extend through the entire transistor structure thickness using one end of the deep via metal that contacts the source / drain metal 650 and the other end of the deep via metal that contacts the bonding metal. T c 。 In the STTM device 6704 (FIGS. 67A or 67B), current-induced magnetization switching can be used to set the bit state. The polarization state of the ferromagnetic layer can be switched relative to the fixed polarization state of the second ferromagnetic layer by the spin-transfer torque phenomenon, such that the state of the MTJ will be set by the application of a current (e.g., received from the drain of the transistor structure 604). The angular momentum (spin) of electrons can be polarized through one or more structures and techniques (e.g., direct current, spin Hall effect, etc.). These spin-polarized electrons can transfer their spin angular momentum to the magnetization of the free layer and cause it to precess. Thus, the magnetization of the free magnetic layer can be switched by a current pulse exceeding a certain critical value (e.g., in about 1 - 10 nanoseconds), while the magnetization of the fixed magnetic layer remains unchanged as long as the current pulse is below some higher threshold associated with the fixed layer architecture. The STTM device 6704 includes a first metal electrode 6707 (e.g., bottom electrode) disposed on the intermediate layer 1410, which can be, for example, any dielectric material. The metal electrode 6707 can be electrically connected to the front-side metal interconnect (e.g., source line) through the transistor structure 604, and the transistor structure 604 can be further connected to another front-side metal interconnect (e.g., word line). The metal electrode 6707 can include a stack or plurality of material layers. In an exemplary embodiment, the surface layer of the metal electrode 6707 that contacts the FET metal 1650 includes titanium (Ti). In some such embodiments, the electrode surface layer includes titanium nitride (TiN), which can have a stoichiometric 1:1 Ti:N lattice composition containing Na-Cl crystallinity, or can have a sub-stoichiometric 1: m Ti:N lattice composition, where m is less than 1. The STTM device 6704 further includes a SAF stack 6712 disposed on the metal electrode 6707. In some exemplary embodiments, the SAF stack 6712 includes a first plurality of bilayers 6713 forming a superlattice of ferromagnetic materials (e.g., Co, CoFe, Ni) and non-magnetic materials (e.g., Pd, Pt, Ru). The bilayers 6713 can include a second plurality of bilayers 6715 (e.g., p[Co / Pt]) separated by an intervening non-magnetic spacer 6714 from n bilayers (e.g., n [Co / Pt] bilayers or n [CoFe / Pd] bilayers, etc.). The bilayers n and The number of p's can be, for example, between 2 and 8 and need not be equal. The range of layer thicknesses within the bilayer 6713 and 6715 can be, for example, from 0.1 to 0.4 nanometers. The spacer 6714 provides antiferromagnetic coupling between 6713 and 6715. The spacer 6714 can be, for example, a ruthenium (Ru) layer less than 1 nanometer thick. In the exemplary embodiment shown, the electrode interface material layer or stack 6710 and the seed layer 6711 are disposed between the electrode 6707 and the SAF stack 6712. The seed layer 6711 is a material having a suitable composition and microstructure to advantageously promote crystallinity in the SAF stack 6712. In some embodiments, the seed layer 6711 comprises Pt and can be substantially pure Pt (i.e., not an intentionally formed alloy). A seed layer of Pt is very suitable as the underlying layer for a Co / Pt type SAF structure. The Pt seed layer 6711 can have a thickness of, for example, 1 - 5 nanometers. The electrode interface material layer or stack 6710 is used to promote a favorable FCC structure having a (111) texture in the seed layer 111. Pt seed layers are typically deposited with an FCC structure unless strongly templated by the underlying layer. The presence of the electrode interface material layer / stack 6710 can prevent the seed layer from templating its crystal structure based on the surface of the electrode 6707, such as TiN. Thus, the electrode interface material layer / stack 6710 can then be regarded as a crystal enhancing layer, which enhances the crystallinity of the seed layer 6711 (and the SAF stack 6712, etc.) relative to the crystallinity achieved when the seed layer 6711 is deposited directly on the electrode 6707. According to some embodiments, the electrode interface material / stack 6710 comprises at least one material layer containing CoFeB. CoFeB tends to have an amorphous microstructure deposited by physical vapor deposition. The seed layer 6711 (e.g., of Pt) will form the desired FCC crystal structure with a (111) texture in the presence of the CoFeB material layer 6710. The subsequent solid phase epitaxial process within the CoFeB can then close-template the seed layer 6711, converting the CoFeB from amorphous to FCC with a (111) texture after it has served its purpose, to improve the crystallinity of the deposited seed layer 6711. A fixed magnetic material layer or stack 6720 including one or more layers of magnetic material is disposed on the SAF stack 6712. A tunneling dielectric material layer 6730 is disposed on the fixed magnetic material layer or stack 6720. A free magnetic material layer or stack 6740 is disposed on the tunneling dielectric material layer 6730. The free magnetic material layer or stack 6740 includes one or more free magnetic material layers. In the exemplary embodiment shown, a dielectric material layer 6770 such as a metal oxide (e.g., MgO, VdO, TaO, WO, MoO, HfO) is disposed on the free magnetic material layer / stack 6740. Such a capping layer may be absent for spin Hall effect (SHE) implementation. A second metal electrode 6780 (e.g., a top electrode) is disposed on the capping material layer 6770. The metal electrode 6780 may be electrically coupled to a backside metal interconnect (e.g., a bit line). It should be noted that the order of the material layers 6707 - 6780 may be reversed with respect to the transistor structure 604. In some embodiments, the STTM device 6704 is a vertical system where the spin of the magnetic layer is perpendicular to the plane of the material layer (i.e., the easy axis of magnetization is in the z - direction out of the plane of the area occupied by the device). The fixed magnetic layer or stack 6720 may be composed of any material or stack of materials suitable for maintaining a fixed magnetization direction, while the free magnetic material stack 6755 is magnetically soft (i.e., the magnetization can be easily rotated to parallel and antiparallel states relative to the fixed layer). In some embodiments, the STTM device 6704 is based on a CoFeB / MgO system, which has a MgO tunneling material layer 6730, a CoFeB fixed magnetic layer / stack 6720, and a CoFeB free magnetic layer 6740. In advantageous embodiments, all the CoFeB layers have a body - centered cubic (BCC) (001) out - of - plane texture, where the texture refers to the distribution of crystal orientations within the layers of the STTM device 6704. For at least some such embodiments, a high percentage of the CoFeB crystals have a preferred (001) out - of - plane orientation (i.e., the degree of texture is high). In some embodiments, the (001) - oriented CoFeB magnetic material layers 6720 and 6740 are iron - rich alloys (i.e., iron > Co) to increase magnetic perpendicularity. In some embodiments, the content of Fe is at least 66%. Exemplary embodiments include 20 - 30% of B (e.g., Co 20 Fe 60 B 20 ). Other embodiments with equal parts of cobalt and iron are also possible (e.g., Co 40 Fe 40 B 20 )。 Compositions of other magnetic materials for the fixed and / or free magnetic layers are also possible, such as but not limited to: Co, Fe, Ni, and non-boron alloys of these metals (e.g., CoFe). The film thicknesses of the fixed and free magnetic layers 6720, 6740 can be 0.1 - 2.0 nanometers. The tunneling material layer 6730 is composed of a material or material stack suitable for allowing the current of majority spins to pass through the layer while hindering the current of minority spins (i.e., a spin filter), thereby affecting the tunneling magnetoresistance associated with the STTM device 6704. In some exemplary embodiments, the tunneling material layer 6730 is magnesium aluminum oxide (MgAlO). In other embodiments, the tunneling material layer 6730 is any material known to be suitable for this purpose. The tunneling material layer 6730 can also provide a crystal template (e.g., polycrystalline BCC with (001) texture) for the free magnetic material layer 140 and / or the fixed magnetic material layer 6720 of solid-phase epitaxy, particularly in the embodiment of CoFeB / MgO / CoFeB. As described above, backside exposure can be performed at the wafer level (e.g., method 101) or selectively (e.g., method 3801). As also pointed out, wafer-level backside exposure can be particularly useful for bonding a front-side device (e.g., FET) layer to another layer of a device prefabricated on a donor substrate. Thus, although some of the above discussions have described how backside processing can create a backside device (e.g., FET, TFET, TFT, STTM) relative to or facing the front-side device, wafer-level bonding of the exposed backside layer is another technique that can produce a device stack. Any of these techniques can be more suitable as a function of the level of compatibility between the processing conditions and / or materials required for the front-side and backside devices for a particular device stack. For example, a backside device that requires high-temperature semiconductor growth or thermal annealing may not be very suitable for incremental manufacturing by backside processing unless the backside processing is integrated into the front-end operations of the front-side processing. Low-temperature compatible devices such as many TFTs, oxide semiconductor TFETs, or STTM devices may be well-suited for incremental manufacturing by backside processing. However, other devices can be more easily integrated through wafer-level backside bonding. For example, another example of a spin memory device is ferroelectric memory (FEM), where a ferroelectric tunnel junction (FTJ) includes an FE barrier disposed between two metal e...

Claims

1. An integrated circuit (IC) structure comprising: a front-side device including: a body of a single-crystal semiconductor material adjacent to an isolation dielectric; a gate stack adjacent to a sidewall of the body, the gate stack including gate electrodes spaced apart from the sidewalls through a gate dielectric; and a source and a drain coupled to the body on opposite sides of the gate stack; a front-side interconnect metal layer located above the front side of the body and coupled to at least one of the source, the drain, or the gate electrodes; and a back-side device including: a back-side device layer located above a back-side surface of the body opposite to the front-side interconnect metal layer, wherein the back-side device layer comprises an oxide semiconductor material, a metal chalcogenide material, or a ferroelectric material; and a back-side device terminal electrically coupled to the back-side device layer.

2. The IC structure of claim 1, wherein the back-side device is a transistor, and the back-side device terminal is one of the source, drain, or gate terminal of the transistor.

3. The IC structure of claim 2, wherein the transistor is one of a thin-film transistor (TFT) or a tunneling field-effect transistor (TFET).

4. The IC structure of claim 3, wherein the back-side device is a TFT and the back-side device layer comprises a metal and a chalcogenide element.

5. The IC structure of claim 4, wherein the back-side device is a TFT and the back-side device layer comprises metal and oxygen.

6. The IC structure of claim 5, wherein the back-side device layer comprises oxygen, indium, gallium, and zinc.

7. The IC structure of claim 1, wherein the back-side device is a non-volatile memory (NVM) device, and wherein the back-side device terminal is an electrode of the NVM device.

8. The IC structure of claim 7, wherein the front device and the back device are interconnected through a via to form a vertical 1T1R unit.

9. The IC structure of claim 8, wherein the via is adjacent to and in contact with the sidewall of the source or the drain.

10. The IC structure of claim 7, wherein the NMV device includes a magnetic tunneling junction (MTJ) and the back-side device layer includes a ferroelectric material.

11. The IC structure of claim 7, wherein the source or drain of the front-side device is in direct contact with the electrode of the NVM device.

12. A vertically stacked integrated circuit (IC) device structure comprising: a field-effect transistor (FET) including: a single-crystal silicon body adjacent to an isolation dielectric; a gate stack adjacent to a sidewall of the body, the gate stack including gate electrodes spaced apart from the sidewall through a gate dielectric; and a source and a drain coupled to the body on opposite sides of the gate stack; a front-side interconnect metal layer located above the front side of the body and coupled to at least one of the source, the drain, or the gate electrodes; and a thin-film transistor (TFT) including: a channel material layer located above a back surface of the body opposite to the front-side interconnect metal layer, wherein the channel layer comprises a metal and a chalcogenide element or comprises a metal and oxygen; and a back-side device terminal electrically coupled to the channel material layer.

13. The IC device structure of claim 12, wherein the source or the drain is in direct contact with the back-side device terminal.

14. The IC device structure of claim 13, wherein the channel layer comprises oxygen and at least one of indium, gallium, or zinc.

15. The IC device structure of claim 14, wherein the channel layer comprises oxygen, indium, gallium, and zinc.

16. A method for processing a double-sided device, comprising: forming a field-effect transistor (FET) comprising: a single-crystal silicon body adjacent to an isolation dielectric; a gate stack adjacent to a sidewall of the body, the gate stack including gate electrodes separated from the sidewalls by a gate dielectric; and a source and a drain coupled to the body on opposite sides of the gate stack; forming a front-side interconnect metal layer located above the front side of the body and coupled to at least one of the source, the drain, or the gate electrodes; removing a single-crystal silicon material of a certain thickness from the back side of the FET; forming a back-side layer of semiconductor material above the back side of the FET, the back-side layer of semiconductor material comprising an oxide semiconductor material, a metal chalcogenide material, or a ferroelectric material; and forming a thin-film transistor (TFT) or non-volatile memory (NVM) device comprising the back-side semiconductor material.

17. The method of claim 16, wherein forming the backside layer of the semiconductor material comprises depositing a polycrystalline or amorphous semiconductor material comprising a metal and oxygen, or comprising a metal and chalcogenides.

18. The method of claim 16, wherein forming the backside layer of the semiconductor material includes bonding an donor substrate over the backside of the FET, the donor substrate comprising the backside layer of the semiconductor material.

19. The method of claim 16, wherein forming the backside layer of the semiconductor material comprises epitaxially growing the backside layer of the semiconductor material from single-crystal silicon retained on the backside of the FET.

20. The method of claim 16, wherein forming the transistor or the non-volatile memory device includes forming a device terminal on the back side of the source or drain of the FET interconnected to the FET.

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