Connection plate and packaging structure

Abstract

This invention discloses a connecting plate and its packaging structure. The connecting plate includes a carrier element, multiple conductor elements, and multiple first buffer elements. The carrier element has multiple through-holes and multiple inner wall surfaces, each inner wall surface corresponding to one of the through-holes. The multiple conductor elements are respectively disposed through one of the through-holes. The multiple first buffer elements have a layered structure, each first buffer element covering one of the inner wall surfaces, and each first buffer element is located between its corresponding conductor element and the inner wall surface. Therefore, the connecting plate and packaging structure of this invention can improve reliability and product manufacturing yield and lifespan.

Description

[Technical Field]

[0001] This invention relates to a capacitor packaging structure, and more particularly to a connecting plate with a stress buffer structure and a packaging structure. [Previous Technology]

[0002] In the past, integrating chips together mostly used System in a Package (SiP) technology, such as PiP (Package in Package) and PoP (Package on Package). However, with the development of applications such as smartphones and smartwatches, not only is higher performance required, but also small size and low power consumption must be maintained. Under such circumstances, it is necessary to find ways to stack more chips to further reduce the size. Therefore, in addition to the original SiP, current packaging technologies are also developing towards 3D packaging technology.

[0003] In general terms, 3D packaging means directly using a silicon wafer to make a "silicon interposer" to package multiple chips with different functions into a single chip with higher performance. In other words, it involves stacking silicon chips on top of silicon in a stacking manner to improve process costs and overcome physical limitations. The most well-known 3D packaging methods are 2.5D and 3D packaging. Taking 2.5D packaging as an example, the main concept is to arrange processors, memory chips, or other chips side by side on a silicon interposer. First, they are connected by microbumps, allowing the metal lines inside the silicon interposer to connect the electronic signals of different chips. Then, through-silicon vias (TSVs) are used to connect the metal bumps below, and then through a lead carrier to connect the external metal balls, achieving a tighter interconnection between the chips and the packaging substrate.

[0004] However, on the silicon interposer, due to the large difference in the coefficients of thermal expansion between the copper pillar and the silicon interposer, the thermal stress generated by both when heated can cause delamination of the interface or cracking of the material, thereby affecting the reliability of the silicon perforation.

[0005] Therefore, how to overcome the above-mentioned defects through structural design improvements has become one of the important issues that this project aims to address. [Summary of the Invention]

[0006] The technical problem to be solved by the present invention is to provide a connecting plate and a packaging structure to address the shortcomings of the prior art.

[0007] To solve the above-mentioned technical problems, one of the technical solutions adopted by the present invention is to provide a connecting plate, which includes a carrier plate element, a plurality of conductor elements, and a plurality of first buffer elements. The carrier plate element has a plurality of through holes and a plurality of inner wall surfaces, each of the inner wall surfaces corresponding to one of the through holes. The plurality of conductor elements are respectively disposed in one of the through holes. The plurality of first buffer elements have a layered structure, each of the first buffer elements covering one of the inner wall surfaces, and each of the first buffer elements is located between the corresponding conductor element and the inner wall surface.

[0008] In one feasible or preferred embodiment, the thickness of the at least one first buffer element is between 1 and 30 µm. Each of the first buffer elements is a multi-layer stacked structure.

[0009] In one feasible or preferred embodiment, each conductor element has a main body, a top end, and a bottom end. One end of the main body is connected to the top end, and the other end of the main body is connected to the bottom end. The top end has a top side edge surface, and the bottom end has a bottom side edge surface. Each first buffer element covers both sides of the carrier element. One end of each first buffer element has a top end surface, and the other end of each first buffer element has a bottom end surface. The top end surface is flush with the top side edge surface, and the bottom end surface is flush with the bottom side edge surface.

[0010] In one feasible or preferred embodiment, the plurality of first buffer elements are connected to each other to form an integrated structure.

[0011] In one feasible or preferred embodiment, the length of each of the first buffer elements is equal to the thickness of the carrier plate element. The connecting plate further includes a plurality of second buffer elements and a plurality of third buffer elements. The plurality of second buffer elements are layered, each covering one side of the carrier plate element and connected to one end of one of the first buffer elements. The plurality of third buffer elements are layered, each covering the other side of the carrier plate element and connected to the other end of one of the first buffer elements. Each second buffer element is located between its corresponding conductor element and one side of the carrier plate element, and each third buffer element is located between its corresponding conductor element and the other side of the carrier plate element.

[0012] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a packaging structure, which includes a first plate, a connecting plate, and at least one second plate. The connecting plate includes a carrier element, a plurality of conductor elements, and a plurality of first buffer elements. The carrier element is located on one side of the first plate, and the carrier element has a plurality of through holes and a plurality of inner wall surfaces, each of the inner wall surfaces corresponding to one of the through holes. The plurality of conductor elements are respectively disposed in one of the through holes. The plurality of first buffer elements have a layered structure, each of the first buffer elements covers one of the inner wall surfaces, and each of the first buffer elements is located between the corresponding conductor element and the inner wall surface. At least one second plate is located on the side of the connecting plate opposite to one of the first plates.

[0013] In one feasible or preferred embodiment, the thickness of the at least one first buffer element is between 1 and 30 µm; wherein each of the first buffer elements is a multi-layer stacked structure.

[0014] In one feasible or preferred embodiment, each conductor element has a main body, a top end, and a bottom end, one end of the main body is connected to the top end, and the other end of the main body is connected to the bottom end. The top end has a top side edge surface, and the bottom end has a bottom side edge surface. Each first buffer element covers both sides of the carrier element. One end of each first buffer element has a top end surface, and the other end of each first buffer element has a bottom end surface. The top end surface is flush with the top side edge surface, and the bottom end surface is flush with the bottom side edge surface.

[0015] In one feasible or preferred embodiment, the plurality of first buffer elements are connected to each other to form an integrated structure.

[0016] In one feasible or preferred embodiment, the length of each first buffer element is equal to the thickness of the carrier plate element. The connecting plate further includes a plurality of second buffer elements and a plurality of third buffer elements. The plurality of second buffer elements are layered, each covering one side of the carrier plate element and connected to one end of one of the first buffer elements. The plurality of third buffer elements are layered, each covering the other side of the carrier plate element and connected to the other end of one of the first buffer elements. Each second buffer element is located between its corresponding conductor element and one side of the carrier plate element, and each third buffer element is located between its corresponding conductor element and the other side of the carrier plate element.

[0017] One of the beneficial effects of the present invention is that the connecting plate provided by the present invention can improve reliability and product production yield and lifespan through the technical solution of "a carrier plate element having a plurality of through holes and a plurality of inner wall surfaces, each of the inner wall surfaces corresponding to one of the through holes. A plurality of conductor elements are respectively disposed in one of the through holes. A plurality of first buffer elements are layered structures, each of the first buffer elements covering one of the inner wall surfaces, and each of the first buffer elements being located between the corresponding conductor element and the inner wall surface".

[0018] Another beneficial effect of the present invention is that the packaging structure provided by the present invention can improve reliability and product production yield and lifespan through the technical solution of "the connecting plate includes a carrier element, a plurality of conductor elements and a plurality of first buffer elements. The carrier element is located on one side of the first plate, the carrier element has a plurality of through holes and a plurality of inner wall surfaces, each of the inner wall surfaces corresponding to one of the through holes. The plurality of conductor elements are respectively disposed in one of the through holes. The plurality of first buffer elements are layered structures, each of the first buffer elements covers one of the inner wall surfaces, and each of the first buffer elements is located between the corresponding conductor element and the inner wall surface. At least one second plate is located on the side of the connecting plate opposite to one of the first plates".

[0019] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention.

Implementation Method

[0029] The following specific embodiments illustrate the implementation of the "connecting plate and packaging structure" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. In addition, the accompanying drawings of this invention are only simple schematic illustrations and are not depictions based on actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention.

[0030] It should be understood that although terms such as "first," "second," and "third" may be used herein to describe various components, these components should not be limited by these terms. These terms are primarily used to distinguish one component from another. In addition, the term "or" as used herein may, as appropriate, include any combination of one or more of the associated listed items.

[0031] [First Embodiment]

[0032] Please refer to Figures 1 to 5, which are respectively a first cross-sectional view of the packaging structure according to the first embodiment of the present invention, an enlarged view of part II of Figure 1, a second cross-sectional view of the packaging structure, a third cross-sectional view of the packaging structure, and a fourth cross-sectional view of the packaging structure. As shown in the above figures, the first embodiment of the present invention provides a packaging structure Z, which may include a first plate 1, a connecting plate D, and at least one second plate 2.

[0033] As shown in Figures 1 and 2, the first board 1 can be a printed circuit board (PCB), various types of chips, or other types of electronic components (such as memory, logic chips, passive electronic components, etc., but not limited thereto); in this embodiment, the first board 1 is exemplified by a printed circuit board, but is not limited thereto. The first board 1 can be located at the bottom of the connecting board D, that is, the first board 1 can be located under one side of the connecting board D that is opposite to the second board 2.

[0034] Next, referring to Figures 1 and 2, the connecting plate D may include a carrier plate element D1, a plurality of conductor elements D2, and a plurality of first buffer elements D3. The carrier plate element D1 may be located on one side of the first plate 1. The carrier plate element D1 may have a plurality of through holes D10 and a plurality of inner wall surfaces D11, each inner wall surface D11 corresponding to one of the through holes D10. The plurality of conductor elements D2 may be respectively disposed in one of the through holes D10. The plurality of first buffer elements D3 may be a layered structure. Each first buffer element D3 may cover a portion of the body of the carrier plate element D1 and one of the inner wall surfaces D11, and each first buffer element D3 may be located between the corresponding conductor element D2 and the inner wall surface D11.

[0035] For example, the carrier element D1 can be a silicon substrate, glass, sapphire substrate, or other types of rigid substrate. The conductor element D2 can be a metal pillar (e.g., copper, but not limited thereto). The first buffer element D3 can be made of BCB (Benzocyclobutene), polyimide (PI), SINR (silicone), or SU-8. The first buffer element D3 can be an elastic and expansion-resistant material, and the expansion resistance coefficient of the first buffer element D3 can be less than that of silicon. The first buffer element D3 can be formed into a layered structure on the carrier element D1 by photolithography. The thickness T1 of the first buffer element D3 can be between 1 and 100 µm, preferably between 1 and 30 µm or 30 and 50 µm, and each first buffer element D3 can cover one of the through holes D10. The multiple first buffer elements D3 do not contact each other. The multiple through-holes D10 of the carrier element D1 can be formed using semiconductor lithography, etching, laser processing, or traditional processing methods (such as plasma). Each conductor element D2 may have a main body D20, a top portion D21, and a bottom portion D22. One end of the main body D20 may be connected to the top portion D21, and the other end of the main body D20 may be connected to the bottom portion D22. The top portion D21 may have a top side edge surface D21a, and the bottom portion D22 may have a bottom side edge surface D22a. The main body D20, the top portion D21, and the bottom portion D22 may be an integrated structure, i.e., the conductor element D2 is a single component. Each first buffer element D3 may cover one of the inner wall surfaces D11 of the carrier element D1 and a portion of the surfaces of both sides of the carrier element D1. Each first buffer element D3 may be attached to the corresponding conductor element D2 and the inner wall surface D11. Each first buffer element D3 may have a top surface D3a at one end and a bottom surface D3b at the other end. The top surface D3a of each first buffer element D3 may be flush with the top edge surface D21a of the corresponding conductor element D2, and the bottom surface D3b of each first buffer element D3 may be flush with the bottom edge surface D22a of the corresponding conductor element D2.

[0036] Next, as shown in Figures 1 and 2, at least one second board 2 may be located on one side of the connecting board D opposite to the first board 1. For example, the second board 2 may be a circuit board, various types of chips, or other types of electronic components (e.g., memory, logic chips, passive electronic components, etc., but not limited thereto). The second board 2 may be located on top of the connecting board D.

[0037] Therefore, when the packaging structure Z of the present invention is applied to an electronic device (such as a smartphone, a smartwatch, a tablet computer, etc., but not limited thereto), and the carrier element D1 and the multiple conductor elements D2 are in a heated state, since the first buffer element D3 is located between the carrier element D1 and the conductor elements D2, the first buffer element D3 can absorb and eliminate the thermal stress changes caused by the thermal expansion of both the carrier element D1 and the conductor elements D2, thereby preventing the conductor elements D2 from partially separating from the carrier element D1, or the conductor elements D2 from causing the carrier element D1 to break.

[0038] Accordingly, the packaging structure Z of the present invention, by means of the above-described technical solution, utilizes a first buffer element D3 provided between the carrier element D1 and the conductor element D2 to absorb and eliminate the thermal stress changes caused by thermal expansion of both the carrier element D1 and the conductor element D2, thereby preventing the conductor element D2 from partially separating from the carrier element D1, or the conductor element D2 from causing the carrier element D1 to break, thereby improving production yield, product lifespan and product reliability (stability).

[0039] Further, as shown in Figures 1 to 3, each first buffer element D3 can be a multi-layer stacked structure; in this embodiment, two layers are used as an example, but this is not a limitation. For example, each first buffer element D3 may include a first stack D30 and a second stack D31, the first stack D30 and the second stack D31 may be made of BCB (Benzocyclobutene), polyimide (PI), SINR (silicone), or SU-8 materials; wherein the materials of the first stack D30 and the second stack D31 may be the same or different, preferably different. Each first stack D30 may be attached to the corresponding conductor element D2 and the second stack D31, and the second stack D31 may be attached to the corresponding inner wall surface D11.

[0040] Furthermore, in conjunction with Figures 1 to 5, one end of each first buffer element D3 may extend outward to form a first extension D32, and the other end of each first buffer element D3 may extend outward to form a second extension D33. The first extension D32 is exposed outside the corresponding conductor element D2 and is located between the carrier element D1 and the second plate 2. The second extension D33 is exposed outside the corresponding conductor element D2 and is located between the carrier element D1 and the first plate 1.

[0041] In addition, according to the above, the present invention further provides a connecting plate D, which may include a carrier plate element D1, a plurality of conductor elements D2, and a plurality of first buffer elements D3. The carrier plate element D1 may have a plurality of through holes D10 and a plurality of inner wall surfaces D11, each inner wall surface D11 corresponding to one of the through holes D10. The plurality of conductor elements D2 may be respectively disposed in one of the through holes D10. The plurality of first buffer elements D3 may be a layered structure, each first buffer element D3 may cover one of the inner wall surfaces D11, and each first buffer element D3 may be located between the corresponding conductor element D2 and the inner wall surface D11.

[0042] However, the examples given above are merely one possible embodiment and are not intended to limit the present invention.

[0043] [Second Embodiment]

[0044] Please refer to Figures 6 and 7, which are respectively a first cross-sectional view and a second cross-sectional view of the packaging structure of the second embodiment of the present invention, and also refer to Figures 1 to 5. As shown in the figures, the packaging structure Z of this embodiment is generally similar to the packaging structure Z of the above embodiments. Therefore, the arrangement or operation of the same components will not be described again here. The difference between this embodiment and the above embodiments is that in this embodiment, multiple first buffer elements D3 are connected to each other to form an integrated structure.

[0045] For example, as shown in FIG6, the first buffer element D3 on the connecting plate D of the packaging structure Z in this embodiment can be a single component. The first buffer element D3 can cover both sides of the carrier plate element D1 and multiple inner wall surfaces D11. In other embodiments, the first buffer element D3 can also cover the carrier plate element D1 and cover multiple inner wall surfaces D11 of the carrier plate element D1.

[0046] Further, as shown in Figures 6 and 7, the first buffer element D3 can be a multi-layer stacked structure; in this embodiment, two layers are used as an example, but it is not limited thereto. For example, the first buffer element D3 may include a first stack D30 and a second stack D31, the first stack D30 and the second stack D31 may be made of BCB (Benzocyclobutene), polyimide (PI), SINR (silicone), or SU-8 materials; wherein the materials of the first stack D30 and the second stack D31 may be the same or different, preferably different. The first stack D30 may cover the carrier element D1, and the second stack D31 may cover the first stack D30 and be located between the conductor element D2 and the first stack D30.

[0047] However, the examples given above are merely one possible embodiment and are not intended to limit the present invention.

[0048] [Third Embodiment]

[0049] Please refer to Figures 8 and 9, which are respectively a first cross-sectional view and a second cross-sectional view of the packaging structure of the third embodiment of the present invention, and also refer to Figures 1 to 7. As shown in the figures, the packaging structure Z of this embodiment is generally similar to the packaging structures Z of the above embodiments. Therefore, the arrangement or operation of the same components will not be described again here. The difference between this embodiment and the above embodiments is that, in this embodiment, the length L1 of each first buffer element D3 can be equal to the thickness T2 of the carrier element D1. Furthermore, the connecting plate D may also include multiple second buffer elements D4 and multiple third buffer elements D5. The multiple second buffer elements D4 may be a layered structure, and each second buffer element D4 may cover one side of the carrier element D1 and be connected to one end of one of the first buffer elements D3. The multiple third buffer elements D5 may be a layered structure, and each third buffer element D5 may cover the other side of the carrier element D1 and be connected to the other end of one of the first buffer elements D3. Each second buffer element D4 may be located between one side of the corresponding conductor element D2 and the carrier element D1, and each third buffer element D5 may be located between the other side of the corresponding conductor element D2 and the carrier element D1.

[0050] For example, as shown in Figure 8, the length of each first buffer element D3 can be equal to the thickness of the carrier element D1. The materials of the second buffer element D4 and the third buffer element D5 can be BCB (Benzocyclobutene), polyimide (PI), SINR (silicone), SU-8, etc. The second buffer element D4 can be an elastic and expansion-resistant material, and the expansion resistance coefficient of the second buffer element D4 can be less than that of silicon. The materials of the first buffer element D3, the second buffer element D4, and the third buffer element D5 can be at least the same or different from each other, preferably different from each other. The thickness of the second buffer element D4 and the third buffer element D5 can be between 1 and 100 µm, preferably between 1 and 30 µm or 30 and 50 µm. Each second buffer element D4 has a portion of its body located between the corresponding conductor element D2 and the carrier element D1, and another portion of its body exposed outside the corresponding conductor element D2 and located between the carrier element D1 and the second plate 2. Each third buffer element D5 has a portion of its body located between the corresponding conductor element D2 and the carrier element D1, and another portion of its body exposed outside the corresponding conductor element D2 and located between the carrier element D1 and the first plate 1.

[0051] Further, as shown in Figures 3, 8, and 9, the first buffer element D3, the second buffer element D4, and the third buffer element D5 can be a multi-layer stacked structure; in this embodiment, two layers are used as an example, but this is not a limitation. For example, each first buffer element D3 may include a first stack D30 and a second stack D31, wherein the first stack D30 and the second stack D31 in this embodiment are the same as the first stack D30 and the second stack D31 described in the first embodiment, and will not be specifically described here. Each second buffer element D4 may include a third stack D40 and a fourth stack D41. The third stack D40 and the fourth stack D41 may be made of materials such as BCB (Benzocyclobutene), Polyimide (PI), SINR (silicone), or SU-8. The third stack D40 and the fourth stack D41 may be made of elastic and expansion-resistant materials, and the expansion resistance coefficient of the third stack D40 and the fourth stack D41 may be less than that of silicon. The materials of the third stack D40 and the fourth stack D41 may be the same or different, preferably different. Each third stack D40 may be attached to the corresponding conductor element D2 and the fourth stack D41, while the fourth stack D41 may be attached to the carrier element D1. Each third buffer element D5 may include a fifth stack D50 and a sixth stack D51. The fifth stack D50 and the sixth stack D51 may be made of materials such as BCB (benzocyclobutene), polyimide (PI), SINR (silicone), or SU-8. The fifth stack D50 and the sixth stack D51 may be made of elastic and expansion-resistant materials, and their coefficient of expansion resistance may be less than that of silicon. The materials of the fifth stack D50 and the sixth stack D51 may be the same or different, preferably different. Each fifth stack D50 may be attached to its corresponding conductor element D2 and sixth stack D51, while the sixth stack D51 may be attached to the carrier element D1.

[0052] However, the examples given above are merely one possible embodiment and are not intended to limit the present invention.

[0053] [Beneficial Effects of the Embodiments]

[0054] One of the beneficial effects of the present invention is that the connecting plate D provided by the present invention can improve reliability and product production yield and lifespan through the technical solution of "the carrier plate element D1 has a plurality of through holes D10 and a plurality of inner wall surfaces D11, each inner wall surface D11 corresponding to one of the through holes D10. A plurality of conductor elements D2 are respectively disposed in one of the through holes D10. A plurality of first buffer elements D3 are layered structures, each first buffer element D3 covers one of the inner wall surfaces D11, and each first buffer element D3 is located between the corresponding conductor element D2 and the inner wall surface D11".

[0055] Another beneficial effect of the present invention is that the packaging structure Z provided by the present invention can improve reliability and product production yield and lifespan through the technical solution of "the connecting plate D includes a carrier element D1, a plurality of conductor elements D2 and a plurality of first buffer elements D3. The carrier element D1 is located on one side of the first plate 1, the carrier element D1 has a plurality of through holes D10 and a plurality of inner wall surfaces D11, each inner wall surface D11 corresponding to one of the through holes D10. The plurality of conductor elements D2 are respectively disposed in one of the through holes D10. The plurality of first buffer elements D3 are layered structures, each first buffer element D3 covers one of the inner wall surfaces D11, and each first buffer element D3 is located between the corresponding conductor element D2 and the inner wall surface D11. At least one second plate 2 is located on one side of the connecting plate D facing away from the first plate 1".

[0056] Furthermore, the packaging structure Z of the present invention, by means of the above-mentioned technical solution, utilizes a first buffer element D3 provided between the carrier element D1 and the conductor element D2 to absorb and eliminate the thermal stress changes caused by thermal expansion of both the carrier element D1 and the conductor element D2, thereby preventing the conductor element D2 from partially separating from the carrier element D1, or the conductor element D2 from causing the carrier element D1 to break, thereby improving the production yield, product life and product reliability (stability).

[0057] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention. [Simplified Explanation of the Diagram]

[0020] Figure 1 is a first cross-sectional schematic diagram of the packaging structure of the first embodiment of the present invention.

[0021] Figure 2 is an enlarged schematic diagram of part II of Figure 1.

[0022] Figure 3 is a second cross-sectional schematic diagram of the packaging structure of the first embodiment of the present invention.

[0023] Figure 4 is a third cross-sectional view of the packaging structure of the first embodiment of the present invention.

[0024] Figure 5 is a fourth cross-sectional view of the packaging structure of the first embodiment of the present invention.

[0025] Figure 6 is a first cross-sectional schematic diagram of the packaging structure of the second embodiment of the present invention.

[0026] Figure 7 is a second cross-sectional schematic diagram of the packaging structure of the second embodiment of the present invention.

[0027] Figure 8 is a first cross-sectional schematic diagram of the packaging structure of the third embodiment of the present invention.

[0028] Figure 9 is a second cross-sectional schematic diagram of the packaging structure of the third embodiment of the present invention.

Claims

1. A connecting plate, comprising: A carrier element having a plurality of perforations and a plurality of inner wall surfaces, each inner wall surface corresponding to one of the perforations; a plurality of conductor elements respectively disposed in one of the perforations; and a plurality of first buffer elements having a layered structure, each first buffer element covering one of the inner wall surfaces, and each first buffer element being located between the corresponding conductor element and the inner wall surface.

2. The connecting plate as described in claim 1, wherein, The thickness of the at least one first buffer element is between 1 and 30 µm; wherein each of the first buffer elements is a multi-layer stacked structure.

3. The connecting plate as described in claim 1, wherein, Each conductor element has a main body, a top end, and a bottom end. One end of the main body is connected to the top end, and the other end of the main body is connected to the bottom end. The top end has a top side edge surface, and the bottom end has a bottom side edge surface. Each first buffer element covers both sides of the carrier plate element. One end of each first buffer element has a top end surface, and the other end of each first buffer element has a bottom end surface. The top end surface is flush with the top side edge surface, and the bottom end surface is flush with the bottom side edge surface.

4. The connecting plate as described in claim 1, wherein, The multiple first buffer elements are connected to each other to form an integrated structure.

5. The connecting plate as described in claim 1, wherein, The length of each first buffer element is equal to the thickness of the carrier plate element; wherein, the connecting plate further includes: a plurality of second buffer elements, which are layered structures, each second buffer element covering one side of the carrier plate element and connected to one end of one of the first buffer elements; and a plurality of third buffer elements, which are layered structures, each third buffer element covering the other side of the carrier plate element and connected to the other end of one of the first buffer elements; wherein, each second buffer element is located between the corresponding conductor element and one side of the carrier plate element, and each third buffer element is located between the corresponding conductor element and the other side of the carrier plate element.

6. A packaging structure comprising: First component; A connecting plate includes: a carrier element located on one side of the first plate, the carrier element having a plurality of through holes and a plurality of inner wall surfaces, each inner wall surface corresponding to one of the through holes; a plurality of conductor elements respectively disposed in one of the through holes; a plurality of first buffer elements having a layered structure, each first buffer element covering one of the inner wall surfaces, and each first buffer element being located between the corresponding conductor element and the inner wall surface; and at least one second plate located on the side of the connecting plate opposite to one of the first plates.

7. The encapsulation structure as described in claim 6, wherein, The thickness of the at least one first buffer element is between 1 and 30 µm; wherein each of the first buffer elements is a multi-layer stacked structure.

8. The encapsulation structure as described in claim 6, wherein, Each conductor element has a main body, a top end, and a bottom end. One end of the main body is connected to the top end, and the other end of the main body is connected to the bottom end. The top end has a top side edge surface, and the bottom end has a bottom side edge surface. Each first buffer element covers both sides of the carrier plate element. One end of each first buffer element has a top end surface, and the other end of each first buffer element has a bottom end surface. The top end surface is flush with the top side edge surface, and the bottom end surface is flush with the bottom side edge surface.

9. The encapsulation structure as described in claim 6, wherein, The multiple first buffer elements are connected to each other to form an integrated structure.

10. The encapsulation structure as described in claim 6, wherein, The length of each first buffer element is equal to the thickness of the carrier plate element; wherein, the connecting plate further includes: a plurality of second buffer elements, which are layered structures, each second buffer element covering one side of the carrier plate element and connected to one end of one of the first buffer elements; and a plurality of third buffer elements, which are layered structures, each third buffer element covering the other side of the carrier plate element and connected to the other end of one of the first buffer elements; wherein, each second buffer element is located between the corresponding conductor element and one side of the carrier plate element, and each third buffer element is located between the corresponding conductor element and the other side of the carrier plate element.

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