Decoding method, system on chip, and decoding device including the same

Abstract

The present invention provides a decoding method, a system-on-a-chip (SoC), and a decoding apparatus including the thereof. A decoding method according to some embodiments includes: reading first input data containing information about a first coded bitstream buffer address from an input data buffer; reading first DPB data containing information about a first DPB address from a DPB data buffer; generating a first decoded image by decoding a first coded bitstream stored at the first coded bitstream buffer address; and storing the first decoded image at the first DPB address.

Description

Technical Field

[0001] The present disclosure relates to a decoding method, a system-on-chip (SOC), and a decoding device comprising the same.

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2023-0169865 filed in the Korean Intellectual Property Office on November 29, 2023, and the entire disclosure of the application is incorporated herein by reference. Prior Art

[0003] Electronic devices such as smartphones, tablet PCs, notebook computers, desktop computers, and digital cameras may be equipped with digital video capabilities. These electronic devices may implement video compression technology to efficiently transmit, receive, encode, decode, and / or store digital video information.

[0004] As the demand for high-definition video increases, electronic devices need to process large amounts of digital video information. Since encoding or decoding digital video information takes a considerable amount of time, research is ongoing to reduce latency. Summary of the invention

[0005] The present disclosure aims to provide a decoding method, a system on a chip and a decoding device comprising the same, which are capable of storing a plurality of decoded pictures in a limited or uninterrupted manner.

[0006] The present disclosure aims to provide a decoding method, a system on a chip and a decoding device comprising the same with reduced decoding delay.

[0007] According to some embodiments, a decoding method is used to solve technical challenges, including: reading first input data containing information about a first encoded bitstream buffer address from an input data buffer; reading first DPB data containing information about the first DPB address from a DPB data buffer; generating a first decoded image by decoding a first encoded bitstream stored at the first encoded bitstream buffer address; and storing the first decoded image at the first DPB address.

[0008] According to some embodiments, the system-on-chip includes: a processor configured to write first input data including information about a first encoded bitstream buffer address into an input data buffer, and write first DPB data including information about a first DPB address into a DPB data buffer; and The codec is configured to read first input data from an input data buffer, read first DPB data from a DPB data buffer, generate a first decoded image by decoding a first coded bit stream stored at a first coded bit stream buffer address, and store the first decoded image at a first DPB address.

[0009] According to some embodiments, a decoding device includes: a working memory, which includes: a coded bit stream buffer, configured to store multiple coded bit streams; an input data buffer, configured to store multiple input data including information about multiple coded bit stream buffer addresses; a decoded picture buffer (DPB), configured to store multiple decoded images; and a DPB data buffer, configured to store multiple DPB data including information about multiple DPB addresses; and a system single chip, configured to: read first input data including information about a first coded bit stream buffer address from the input data buffer; read first DPB data including information about the first DPB address from the DPB data buffer; read a first coded bit stream stored at the first coded bit stream buffer address; generate a first decoded image by decoding the first coded bit stream; and store the first decoded image at the first DPB address of the decoded picture buffer. Simple diagram description

[0010] FIG. 1 is a block diagram of a video coding device including a system on a chip according to some embodiments. FIG. 2 is a block diagram illustrating a codec according to some embodiments. FIG. 3 is a diagram showing a working memory according to a comparative example. FIG. 4 is a diagram showing an input data buffer of a working memory according to the comparative example. FIG5 is a flowchart showing a decoding method according to the comparative example. FIG. 6 is a diagram illustrating a working memory according to some embodiments. 7 is a diagram illustrating a decoded picture buffer (DPB) data buffer of a working memory according to some embodiments. FIG8 is a flow chart illustrating a decoding method according to some embodiments. FIG. 9 is a flow chart illustrating a method of using DPB data in a DPB data buffer according to some embodiments. FIG. 10 is a diagram illustrating a DPB and a DPB data buffer according to some embodiments. FIG. 11 is a flow chart illustrating a method of updating DPB data in a DPB data buffer according to some embodiments. FIG. 12 is a diagram illustrating a DPB and a DPB data buffer according to some embodiments. FIG. 13 is a flow chart illustrating a decoding method according to some embodiments. Implementation

[0011] In the following detailed description, only certain embodiments of the present invention have been shown and described by way of illustration only. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0012] Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive. Throughout this specification, the same reference numerals designate the same elements. In the flowcharts described with reference to the drawings, the order of operations may be changed, several operations may be combined, some operations may be divided, and certain operations may not be performed.

[0013] In addition, expressions written in the singular form can be understood in the singular form or the plural form unless explicit expressions such as "a", "an" or "single" are used. Terms including ordinal numbers such as first and second are used to describe various constituent elements, but the constituent elements are not limited to these terms. These terms are used only to distinguish one constituent element from other constituent elements.

[0014] FIG. 1 is a block diagram of a video encoding device including a system-on-a-chip according to some embodiments.

[0015] 1 , the video encoding device 100 may be implemented as a television, a digital TV (DTV), an Internet protocol TV (IPTV), a set-top box, a personal computer (PC), a notebook computer, a desktop computer, a computer workstation, a smart phone, a tablet personal computer, a digital camera, a video game platform (or a video game console), a server, or the like. The video encoding device 100 may refer to various devices capable of processing two-dimensional (2D) or 3D graphic data and displaying the processed data.

[0016] The video encoding device 100 may include a system-on-chip (SoC) 110 , a video source 120 , a display 130 , an input device 140 , a working memory 150 , and a memory interface 118 .

[0017] The video source 120 may be implemented as a camera equipped with a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) image sensor. The video source 120 may capture a subject, generate data about the subject, and provide the generated data to the system-on-chip 110.

[0018] The system-on-chip 110 can control the overall operation of the video encoding device 100. For example, the system-on-chip 110 may include an integrated circuit (IC), a motherboard, an application processor (AP), or a mobile application processor. The system-on-chip 110 can process data output from the video source 120, and display the processed data through the display 130, store the processed data in the storage device 160, or transmit the processed data to another data processing system. The data output from the video source 120 can be transmitted to the pre-processing circuit 111 via an interface, such as a mobile industry processor interface (MIPI) camera serial interface (CSI).

[0019] The system on chip 110 may include a pre-processing circuit 111 , a codec 112 , a processor 113 , a modem 114 , a display controller 115 , a user interface 116 , a memory controller 117 , a memory interface 118 , and a bus 119 .

[0020] The codec 112, the processor 113, the modem 114, the display controller 115, the user interface 116, the memory controller 117, and the memory interface 118 may transmit and receive data to and from each other via the bus 119. For example, the bus 119 may be implemented by at least one selected from a peripheral component interconnect bus (PCI bus), a PCI express (PCIe) bus, an advanced microcontroller bus architecture (AMBA), an advanced high performance bus (AHB), an advanced peripheral bus (APB), an advanced extensible interface (AXI) bus, and combinations thereof, but is not limited thereto.

[0021] The pre-processing circuit 111 may receive data output from the video source 120. The pre-processing circuit 111 may process the received data and output the processed data to the codec 112. The pre-processing circuit 111 may be implemented as, for example, an image signal processor (ISP). In FIG. 1 , the pre-processing circuit 111 is shown to be implemented inside the system-on-chip 110; however, the pre-processing circuit 111 may be implemented outside the system-on-chip 110.

[0022] The codec 112 may perform an encoding (or encryption) operation on the data processed by the pre-processing circuit 111. The codec 112 may perform a decoding (or decryption) operation on the data from the processor 113 or stored in the working memory 150. The encoding operation and the decoding operation may use encoding and decoding technologies such as joint photographic experts group (JPEG), moving picture experts group (MPEG), MPEG-2, MPEG-4, VC-1, VP9, ​​AV1, H.264, H.265, high efficiency video coding (HEVC), etc., but are not limited thereto. The codec 112 may be implemented as a hardware codec or a software codec.

[0023] In some embodiments, the codec 112 may read each input data for reading data (e.g., a coded bit stream of video data) stored in the working memory 150, and the DPB data on the decoded picture buffer from the working memory 150. The codec 112 may decode the coded bit stream and store the decoded picture in the DPB indicated by the DPB data in the working memory 150. The codec 112 may store the decoded picture in the DPB indicated by the DPB data by referring to the flag data corresponding to the DPB data. For example, when the flag data of the DPB data is a first value (e.g., "0"), the codec 112 may not store the decoded picture in the DPB indicated by the DPB data. The codec 112 may wait until the flag data of the DPB data is changed to a second value (e.g., "1") different from the first value. When the flag data of the DPB data is a second value, the codec 112 may store the decoded picture in the first DPB indicated by the DPB data.

[0024] The processor 113 can control the operation of the system single chip 110. The processor can execute software (applications, operating systems and / or device drivers). The processor 113 can execute the operating system (OS) loaded in the working memory 150. The processor 113 can execute various application programs to be run on the operating system. The processor 113 can be provided as a homogeneous multi-core processor or a heterogeneous multi-core processor.

[0025] The modem 114 may output data encoded by the codec 112 or the processor 113 to the outside using wireless communication technology. The modem 114 may be configured as a one-way communication interface or a two-way communication interface, and may be configured to, for example, transmit and receive messages for establishing a connection, and to check and exchange any other information related to data transmission, such as transmission and / or encoded data of the communication link.

[0026] The display controller 115 may transmit data output from the codec 112 or the processor 113 to the display 130. The display controller 115 may transmit the data to the display 130 via a MIPI display serial interface (DSI). The display 130 may be or include any type of display configured to display decoded images, such as an integrated or external display or monitor. For example, the display may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), a digital light processor (DLP), or any other type of display.

[0027] The input device 140 may receive user input inputted by the user, and transmit the input signal to the user interface 116 as a response to the user operation. The input device 140 may be implemented as a touch panel, a touch screen, a voice recognizer, a stylus, a keyboard, a mouse, a track point, etc., but is not limited thereto. For example, when the input device 140 is a touch screen, the input device 140 may include a touch panel and a touch panel controller. In addition, when the input device 140 is a voice recognizer, the input device 140 may include a voice recognition sensor and a voice recognition controller. The input device 140 may be connected to the display 130, or may be implemented separately from the display 130.

[0028] The user interface 116 may receive input signals from the input device 140 and transmit data generated by the input operation to the processor 113 .

[0029] The memory controller 117 can read the data stored in the working memory 150 under the control of the codec 112 or the processor 113, and transmit the read data to the codec 112 or the processor 113. In addition, the memory controller 117 can write the data output from the codec 112 or the processor 113 into the working memory 150 under the control of the codec 112 or the processor 113.

[0030] The working memory 150 may receive and store data encoded and / or decoded by the codec 112. In addition, the working memory 150 may transmit the data stored in the working memory 150 to the processor 113 or the modem 114. In some exemplary embodiments, the input data and the DPB data may be stored in different memory areas of the working memory 150. In other words, in an area of ​​the working memory 150 including continuous addresses, at least one piece of input data may be stored, and in another area of ​​the working memory 150 including continuous addresses, at least one piece of DPB data may be stored. One area and another area may be arranged discontinuously in the working memory 150.

[0031] The working memory 150 may be implemented as a volatile memory. The volatile memory may be implemented as a random-access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a thyristor RAM (T-RAM), a zero capacitor RAM (Z-RAM), or a twin transistor RAM (TTRAM).

[0032] The memory interface 118 accesses the storage device 160 according to the request of the processor 113. In other words, the memory interface 118 provides an interface between the system on a chip and the storage device 160. For example, data processed by the processor 113 is stored in the storage device 160 via the memory interface 118. As another example, the data stored in the storage device 160 can be provided to the processor 113 via the memory interface 118.

[0033] The storage device 160 can be provided as a storage medium of the video encoding device 100. The storage device 160 can store user data, working system images, application programs, etc. The storage device 160 can be implemented as a non-volatile memory.

[0034] The non-volatile memory may be implemented as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin transfer torque MRAM, a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), or a resistive RAM (RRAM). In addition, the non-volatile memory may be implemented as a multimedia card (MMC), an embedded multimedia card (eMMC), a universal flash storage (UFS), a solid state drive (SSD), a USB flash drive, or a hard disk drive (HDD).

[0035] FIG. 2 is a block diagram illustrating a codec according to some embodiments.

[0036] 2, the codec 200 can restore the encoded bit stream into a decoded image by decoding, and encode the image to generate the encoded bit stream. The codec 200 may include a codec memory 210 and a processing unit 220.

[0037] The codec memory 210 may be a write buffer or a read buffer connected to temporarily store data input to the codec 200. The codec memory 210 may be configured to store various information required for the operation of the codec 200. For example, the codec memory 210 may store software, firmware, and / or information related to encoding operations and decoding operations. In some exemplary embodiments, the codec memory 210 may be a static random access memory; however, the scope of the present invention is not limited thereto, and the codec memory 210 may be implemented as various types of memory devices, such as a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), or a phase change random access memory (PRAM). In FIG. 2 , for the sake of simplifying the drawing and facilitating the explanation, the codec memory 210 is shown to be included in the codec 200; however, the scope of the present invention is not limited thereto. The codec memory 210 may be located outside the codec 200, and the codec 200 may communicate with the buffer memory through a separate communication channel or interface.

[0038] The codec memory 210 may include a counter register 211. The counter register 211 may include a first counter register referenced to read input data, a second counter register indicating an index of the completion of processing of the input data, and a third counter register referenced to store output data. In some exemplary embodiments, when the input data is written to the working memory, the count value of the first counter register may be increased. For example, the processor 113 may store the input data in the working memory 150 and change the value of the first counter register of the codec 200. The codec 200 may refer to the count value of the first counter register to determine the address in the working memory 150 and read the input data stored at the determined address. In addition, in some exemplary embodiments, the second counter register may count the number of decoded input data. In some exemplary embodiments, the third counter register may count the number of decodings. When the codec 200 completes decoding of the encoded bit stream, the third counter register may increase the number of decodings. The codec 200 may refer to the count value of the third counter register to determine the address in the working memory 150, and write the output data related to the decoded image at the determined address.

[0039] The firmware 212 may be loaded into the codec memory 210. The firmware 212 may transmit the pre-processed image data and the encoded bit stream to the codec processing unit 220. For example, when the codec 200 receives an interrupt signal from the processor 113, the firmware 212 may read the input data stored in the working memory 150 by the processor 113. The firmware 212 may transmit the encoded bit stream read based on the input data to the codec processing unit 220. In some exemplary embodiments, the firmware 212 may read the DPB data, and may or may not refer to the flag data of the DPB data to use the DPB indicated by the DPB data. The firmware 212 may change the value of the flag data of the DPB data indicating the used DPB. For example, when the flag data of the DPB data is the second value, the firmware 212 may store the decoded image in the DPB indicated by the DPB data. If the DPB indicated by the DPB data has been used, the firmware 212 may change the flag data of the DPB data from the second value to the first value. When the flag data of the DPB data is the first value, the firmware 212 may not use the DPB indicated by the DPB data. The firmware 212 may use the read indicator to read the DPB data. The read indicator may sequentially indicate the DPB area containing multiple DPB data in the working memory 150. The read indicator may cyclically indicate the DPB area containing multiple DPB data in the working memory 150.

[0040] The codec memory 210 may include special function registers (SFRs) that can be used to decode the encoded bit stream in an interlaced scanning manner.

[0041] The processing unit 220 may include a decoder 221 and an encoder 222. The decoder 221 decodes the encoded bit stream received from the firmware 212, and the encoder 222 encodes the pre-processed image data.

[0042] The decoder 221 may receive a coded bit stream and provide a decoded image. The encoder 222 (also referred to as a video encoder) may receive pre-processed image data, process the pre-processed image data, and provide a coded bit stream.

[0043] Each of the decoder 221 and the encoder 222 can be implemented using various suitable circuits, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, hardware, or any combination thereof. If this technology is partially implemented using software, the device can store software instructions in a suitable non-transitory computer-readable storage medium and use hardware such as one or more processors to execute these instructions to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered as one or more processors.

[0044] FIG. 3 is a diagram illustrating a working memory according to a comparative example.

[0045] 3, the working memory 300 may include a plurality of buffers 310, 320, 330, and 340. In the first area 310, a coded bit stream may be stored. In the second area 320, input data may be stored. In the third area 330, output data may be stored. In the fourth area 340, a decoded image may be stored. The first to fourth areas 310, 320, 330, and 340 may be arranged discontinuously in the working memory 300, and the size of each area may be set in various ways. Hereinafter, the first to fourth areas 310, 320, 330, and 340 will be referred to as a coded bit stream buffer, an input data buffer, an output data buffer, and a decoded image buffer, respectively.

[0046] In some embodiments, the working system 151 may allocate the address range from ADDR10 to ADDR1n in the working memory 300 as the first area 310, the address range from ADDR20 to ADDR2m as the second area 320, the address range from ADDR30 to ADDR3p as the third area 330, and the address range from ADDR40 to ADDR4q as the fourth area 340. The first area 310 may include a plurality of coded bit stream buffers in the address range from ADDR10 to ADDR1n. The second area 320 may include a plurality of input data buffers in the address range from ADDR20 to ADDR2m. The third area 330 may include a plurality of output data buffers in the address range from ADDR30 to ADDR3p. The fourth area 340 may include a plurality of DPB areas in the address range from ADDR40 to ADDR4q. Here, n, m, p, and q may be any natural number greater than 0 (e.g., 5, 10, 15, etc., jointly or independently).

[0047] FIG. 4 is a diagram showing an input data buffer of a working memory according to the comparative example.

[0048] 4, the input data buffer 400 may include a plurality of input data 410. One input data 410a may include information of a coded bit stream buffer address 411, a frame data size 412, and a DPB address 413. The input data 410 may be generated by the processor 113. When the operating system 151 allocates a DPB for storing coded bit stream data to the processor 113, the processor may generate the input data 410 including information about the DPB address 413 indicating the allocated DPB.

[0049] FIG5 is a flowchart showing a decoding method according to the comparative example.

[0050] 1 to 5, the operating system 151 allocates a plurality of buffers 310, 320, 330, and 340 in the working memory 300, and notifies the processor 113 of information about the plurality of buffers 310, 320, 330, and 340 (S500). For example, the operating system 151 may notify the processor 113 of address information about the plurality of buffers and size information of each area. The processor 113 may transmit the information about the plurality of buffers 310, 320, 330, and 340 to the codec 112.

[0051] The processor 113 stores the input data including the DPB address in the working memory 150 (S510 to S513). The processor 113 may generate input data including the address in the coded bitstream buffer where the coded bitstream is stored, the size of the coded bitstream, and the DPB address. For example, for multiple coded bitstreams, the processor 113 may generate input data including DPB addresses 0, 1, 2, and 3 respectively. The processor 113 may store the input data generated for multiple coded bitstreams in the input data buffer of the working memory 150.

[0052] If the input data item is stored, the processor 113 transmits an interrupt signal H0 to the codec 112 (S514). The processor 113 may transmit the interrupt signal H0 each time the storage of a piece of input data is completed, or when a predetermined (or, alternatively, expected or selected) number of input data storages are completed. The interrupt signal H0 transmitted when the predetermined (or, alternatively, expected or selected) number of input data storages are completed may include the number of stored input data items.

[0053] The codec 112 reads input data 0 from the input data buffer of the working memory 150 based on the interrupt signal H0 (S515). The codec 112 may receive the address range of the input data buffer from the processor 113 before operation S515. When the interrupt signal H0 is received for the first time, the codec 112 may read input data 0 from the base address of the input data buffer.

[0054] The codec 112 decodes the coded bitstream 0 stored in the coded bitstream buffer address with reference to the input data 0 (S516). The codec 112 may read the coded bitstream 0 from the working memory 150 based on the coded bitstream buffer address included in the input data 0, and decode the coded bitstream 0 to generate a decoded image 0.

[0055] The codec 112 writes the decoded picture 0 into the DPB with reference to the input data 0 ( S517 ). The codec 112 may write the decoded picture 0 into the working memory 150 based on the DPB address 0 included in the input data 0 .

[0056] The codec 112 writes the output data 0 associated with the decoded picture 0 into the output data buffer (S518). When the decoding is completed for the first time, the codec 112 may write the output data into the base address of the output data buffer.

[0057] When the writing of the output data is completed, the codec 112 transmits an interrupt signal C0 to the processor 113 (S519).

[0058] The processor 113 receives the interrupt signal C0 and reads the output data 0 from the output data buffer (S520). The processor 113 can determine the address of the output data 0 stored in the output data buffer based on the number of times the interrupt signal C0 is received. The processor 113 can read the output data 0 from the determined address.

[0059] The processor 113 transmits a control signal for displaying the decoded image 0 to the display controller 115 (S521). The control signal may include a DPB address 0 determined based on the output data 0.

[0060] The display controller 115 reads the stored decoded picture 0 from the DPB address 0 of the DPB ( S522 ).

[0061] The display controller 115 may display the decoded image 0 on the display 130 ( S523 ).

[0062] After the interrupt signal C0 is transmitted, the codec 112 reads the input data 1 from the input data buffer (S524). When decoding is completed, the codec 112 may read the input data 1 from the next address of the base address of the input data buffer (for example, an address obtained by adding the index of the input data that has been decoded (such as the count value of the second counter register) and the product of the offset address size to the base address).

[0063] The codec 112 decodes the coded bit stream 1 stored in the coded bit stream buffer address corresponding to the input data 1 (S525). The codec 112 can read the coded bit stream 1 from the working memory 150 based on the coded bit stream buffer address included in the input data 1, and decode the coded bit stream 1 to generate a decoded image 1.

[0064] The coded bitstream 1 may be multi-frame data. In other words, the coded bitstream 1 may be a bitstream obtained by encoding images of several frames. The coded bitstream 1 may be encoded by encoding techniques such as VP9, ​​AOMedia Video 1 (AV1) or the like.

[0065] The codec 112 refers to the input data 1 and writes the decoded image 1 into the DPB (S526). When the coded bit stream 1 includes three frames of images, the codec 112 can complete the decoding of one frame of images and write the decoded one frame of images into the DPB. The codec 112 can write the decoded image 1 into the working memory 150 based on the DPB address 1 included in the input data 1.

[0066] The codec 112 writes the output data 1 associated with the decoded image 1 into the output data buffer (S527). The codec 112 may write the output data 1 to an address next to the base address of the output data buffer.

[0067] When writing of the output data 1 is completed, the codec 112 transmits an interrupt signal C1 to the processor 113 (S528).

[0068] When the coded bit stream 1 includes undecoded data, the codec 112 requests the processor 113 for a DPB address (S529).

[0069] The coded bitstream 1 may include information on the number of coded images. The codec 112 may decode the coded bitstream 1 and determine whether decoding of the coded images in the coded bitstream 1 has been completed based on the information on the number of coded images.

[0070] When decoding of an image of one frame from the coded bitstream 1 is completed, the codec 112 may determine whether decoding of the coded image in the coded bitstream 1 is completed based on whether the coded bitstream 1 contains undecoded data. The coded bitstream 1 may contain information of the size of the coded bitstream 1. The codec 112 may determine whether the coded bitstream 1 contains undecoded data by comparing the size of the coded bitstream 1 with the size of the decoded data of the coded bitstream 1.

[0071] Since the coded bitstream 1 is multi-frame data, the coded bitstream 1 may include undecoded data even after the operation S525 is performed. The codec 112 may decode the undecoded data included in the coded bitstream 1, such as the remaining data. However, since each input data includes a DPB address, the input data 1 of the coded bitstream 1 may also include only one DPB address 1. Therefore, if the decoded image 1 is already stored at the DPB address 1, the codec 112 needs an additional DPB address to store the image obtained by decoding the data to be decoded (such as the remaining data).

[0072] The processor 113 requests the working system 151 to release the memory allocated to the input data (S530). The working system 151 may release the input data stored in the working memory 300. Each input data may include a DPB address, and the codec 112 may read the input data sequentially starting from the base address of the input data buffer storing the input data. Therefore, when input data 1 including a new DPB address (e.g., DPB address 2) is additionally stored in the input data buffer, it is necessary to perform decoding of the coded bit stream indicated by the input data 1 after completing decoding of the coded bit streams indicated by the other input data 2 and input data 3 stored in the input data buffer, thereby possibly reducing the processing capacity of the codec memory 210. In addition, when the display order of the decoded image is the order of input data 1, input data 2, and input data 3, the decoding of the coded bit stream indicated by the input data 1 is performed after completing decoding of the coded bit stream indicated by the input data 3, thereby possibly failing to display the input data 1 normally. For this reason, the processor 113 may request the working system 151 to release the input data from the working memory and store the input data sequentially starting from the base address of the input data buffer. In addition, the counter register 211 for reading the input data of the codec 200 may be reset.

[0073] The processor 113 may request the operating system 151 to allocate a DPB address ( S531 ).

[0074] The operating system 151 allocates the used DPB address to the processor 113 (S532). For example, the operating system 151 may allocate the DPB address that has been read (eg, used) by the display controller 115 as a new DPB address to the processor 113.

[0075] The processor 113 stores the input data including the new DPB address in the working memory 150 (S533 to S535). The processor 113 may generate input data including DPB address 2, DPB address 3, and DPB address 4 for the plurality of coded bit streams, respectively. The processor 113 may store the input data generated for the plurality of coded bit streams in an input data buffer in the working memory 150.

[0076] After storing the input data item, the processor 113 transmits an interrupt signal H1 to the codec 112 (S536).

[0077] The codec 112 reads input data 1 from the input data buffer of the working memory 150 based on the interrupt signal H1 (S537). Since the counter register 211 of the codec 112 has been reset, when the codec 112 receives the interrupt signal H1, it can read the input data 1 from the base address of the input data buffer.

[0078] The codec 112 decodes the coded bitstream 1 with reference to the input data 1 (S538). When the coded bitstream buffer address included in the input data 1 is the same as the coded bitstream buffer address included in the input data 1 read in operation S524, the codec 112 may decode the remaining data not decoded in operation S525. The codec 112 may decode the remaining data of the coded bitstream 1 to generate a decoded image 11.

[0079] The codec 112 writes the decoded image 11 into the DPB with reference to the input data 1 (S539). The codec 112 may write the decoded image 11 into the working memory 150 based on the DPB address 2 included in the input data 1.

[0080] The codec 112 writes the output data 2 associated with the decoded image 11 into the output data buffer (S540). The codec 112 may write the output data 2 to the next address of the output data buffer in which the output data 1 is stored.

[0081] When the writing of the output data 2 is completed, the codec 112 transmits an interrupt signal C2 to the processor 113 (S541).

[0082] When the coded bit stream 1 contains undecoded data, the codec 112 requests the processor 113 for the DPB address again (S542).

[0083] The processor 113 transmits a control signal for displaying the decoded image 10 to the display controller 115 ( S543 ). The control signal may include a DPB address 1 determined based on the output data 1 .

[0084] The display controller 115 reads the decoded image 10 stored at the DPB address 1 of the DPB ( S544 ).

[0085] The display controller 115 may display the decoded image 10 on the display 130 ( S545 ).

[0086] Operations S529 to S537 and / or operation S542 of decoding the coded bitstream 1 (which is a plurality of frames of data) and requesting the processor 113 and the operating system 151 for the DPB address to store the decoded image may cause a delay greater than the time required for the codec 112 to decode one frame of image.

[0087] FIG. 6 is a diagram illustrating a working memory according to some example embodiments.

[0088] 6, the working memory 600 may include a plurality of buffers 610, 620, 630, 640, and 650. In the first area 610, a coded bit stream may be stored. In the second area 620, input data may be stored. In the third area 630, output data may be stored. In the fourth area 640, a decoded image may be stored. In the fifth area 650, DPB data may be stored. In some example embodiments, the input data may not include information about the DPB address, and the DPB data may include information about the DPB address. The first to fifth areas 610, 620, 630, 640, and 650 may be arranged discontinuously in the working memory 600, and the size of each area may be set in various ways. Hereinafter, the fifth area 650 will be referred to as the DPB data buffer.

[0089] In some example embodiments, the working system 151 may allocate an address range from ADDR10 to ADDR1n as a first region 610, an address range from ADDR20 to ADDR2m as a second region 620, an address range from ADDR30 to ADDR3p as a third region 630, an address range from ADDR40 to ADDR4q as a fourth region 640, and an address range from ADDR50 to ADDR5r as a fifth region 650 in the working memory 600. Here, n, m, p, q, and r may be any natural number greater than 0 (e.g., 2, 5, 15, etc., jointly or independently).

[0090] FIG. 7 is a diagram illustrating a DPB data buffer of a working memory according to some embodiments.

[0091] 7, the DPB data buffer 700 may include a plurality of DPB data 710. One DPB data 710a may include flag data 711 and information about a DPB address 712. The flag data 711 may indicate whether the DPB data 710a is available. When the operating system 151 allocates a DPB for storing encoded bitstream data to the processor 113, the processor may generate the DPB data 710 including information about a DPB address 712 indicating the allocated DPB.

[0092] In some example embodiments, the processor 113 may update the DPB data 710a according to the flag data 711 of the DPB data 710a. For example, when the flag data 711 of the DPB data 710a is a first value, the processor 113 may change the flag data 711 of the DPB data 710a to a second value and store information about the allocated DPB address in the DPB data 710a. In other words, the processor may write the DPB data 710a including the flag data 711 having the second value and the information about the allocated DPB address at the address where the DPB data 710a has been stored. After storing the new DPB data 710a, the processor 113 may read the next DPB data 710b of the DPB data 710a. When the flag data 711 of the DPB data 710a is a second value, the processor 113 may wait until the flag data 711 of the DPB data 710a is changed to the first value.

[0093] When the flag data 711 of the DPB data 710a is the second value, the codec 112 may store the decoded image at the DPB address 712 of the DPB data 710a. The codec 112 may store the decoded image at the DPB address 712 and change the flag data 711 of the DPB data 710a to the first value. After using the DPB data 710a, the codec 112 may read the next DPB data 710b of the DPB data 710a. When the flag data 711 of the DPB data 710a is the first value, the codec 112 may wait until the flag data 711 of the DPB data 710a is changed to the second value.

[0094] FIG8 is a flow chart illustrating a decoding method according to some embodiments.

[0095] 1, 2, and 6 to 8, the operating system 151 allocates a plurality of buffers 610, 620, 630, 640, and 650 in the working memory 600, and notifies the processor 113 of information about the plurality of buffers 610, 620, 630, 640, and 650 (S800). For example, the operating system 151 may notify the processor 113 of information about addresses of the plurality of buffers and information about sizes of respective regions. The processor 113 may transmit the information about the plurality of buffers 610, 620, 630, 640, and 650 to the codec 112.

[0096] The processor 113 stores the input data in the working memory 150 (S810). The processor 113 may generate input data including the address of the coded bit stream buffer storing the coded bit stream and the coded bit stream size. For example, the processor 113 may store a plurality of input data 1 to input data 3 generated in response to a plurality of coded bit streams in the input data buffer in the working memory 600.

[0097] The processor 113 stores the DPB data in the working memory 150 (S811). For example, the processor 113 may generate a plurality of DPB data 1 to DPB data 3 corresponding to a plurality of coded bit streams. The plurality of DPB data 1 to DPB data 3 may respectively include a DPB address. The processor 113 may store the plurality of DPB data sequentially starting from the base address of the DPB data buffer.

[0098] If the input data and the DPB data items are stored, the processor 113 transmits the interrupt signal H10 to the codec 112 (S812). The processor 113 may transmit the interrupt signal H10 each time the storage of one input data and one DPB data is completed, or when the storage of a predetermined (or, alternatively, expected or selected) number of input data and DPB data is completed. The interrupt signal H10 transmitted when the storage of a predetermined (or, alternatively, expected or selected) number of input data and DPB data is completed may include the number of stored input data and stored DPB data items.

[0099] The codec 112 reads input data 1 from the input data buffer of the working memory 150 based on the interrupt signal H10 (S813). The codec 112 may receive the address range of the input data buffer from the processor 113 before operation S813. When the interrupt signal H10 is received for the first time, the codec 112 may read the input data 1 from the base address of the input data buffer.

[0100] The codec 112 reads the DPB data 1 from the DPB data buffer of the working memory 150 based on the interrupt signal H10 (S814). The codec 112 may receive the address range of the DPB data buffer from the processor 113 before operation S813. When the interrupt signal H10 is received for the first time, the codec 112 may read the DPB data 1 from the base address of the DPB data buffer.

[0101] The codec 112 decodes the coded bit stream 1 stored at the coded bit stream buffer address for the input data 1 (S815). Here, the coded bit stream 1 may be multi-frame data. The codec 112 may read the coded bit stream 1 from the working memory 150 based on the coded bit stream buffer address included in the input data 1, and decode the coded bit stream 1 to generate a decoded image 1A.

[0102] The codec 112 refers to the DPB data 1 and writes the decoded image 1A into the DPB ( S816 ). The codec 112 may write the decoded image 1A into the working memory 150 based on the DPB address 1 included in the DPB data 1 .

[0103] The codec 112 writes the output data 1A related to the decoded image 1A into the output data buffer (S817). When the decoding is completed for the first time, the codec 112 may write the output data into the base address of the output data buffer.

[0104] When the writing of the output data is completed, the codec 112 transmits an interrupt signal 1A to the processor 113 (S818).

[0105] The processor 113 receives the interrupt signal 1A and reads the output data 1A from the output data buffer (S819). The processor 113 may determine the address at which the output data 1A has been stored in the output data buffer based on the number of times the interrupt signal 1A is received. The processor 113 may read the output data 1A from the determined address. The processor 113 may determine the display order of the decoded image 1A from the output data 1A. It is assumed below that the decoded image 1A is displayed after the decoded image 1B is displayed. Therefore, the processor 113 may not transmit the control signal to the display controller 115 after reading the output data 1A until the output data 1B related to the decoded image 1B is read.

[0106] When the coded bit stream 1 includes undecoded data, the codec 112 reads the DPB data 2 from the DPB data buffer of the working memory 150 (S820). How the codec 112 determines whether the coded bit stream 1 includes undecoded data is the same or similar to the description of FIG. 5 , and thus will not be described in detail. When decoding is completed, the codec 112 can read the DPB data 2 from the next address of the base address of the DPB data buffer (for example, the address obtained by adding the product of the number of decoding completions and the offset address size to the base address).

[0107] The codec 112 decodes the remaining data of the encoded bitstream 1 ( S821 ). The codec 112 may decode the undecoded data in the encoded bitstream 1 to generate a decoded image 1B.

[0108] The codec 112 refers to the DPB data 2 and writes the decoded image 1B into the DPB ( S822 ). The codec 112 may write the decoded image 1B into the working memory 150 based on the DPB address 2 included in the DPB data 2 .

[0109] The codec 112 writes the output data 1B related to the decoded image 1B into the output data buffer (S823). The codec 112 may write the output data into the output data buffer at the next address of the address where the output data 1A is stored.

[0110] When the writing of the output data 1B is completed, the codec 112 transmits an interrupt signal 1B to the processor 113 (S824).

[0111] When the coded bit stream 1 includes undecoded data, the codec 112 reads the DPB data 3 from the DPB data buffer of the working memory 150 (S825).

[0112] The codec 112 decodes the remaining data of the encoded bitstream 1 (S826). The codec 112 may decode the undecoded data in the encoded bitstream 1 to generate a decoded image 1C.

[0113] The codec 112 refers to the DPB data 3 and writes the decoded image 1C into the DPB (S827). The codec 112 may write the decoded image 1C into the working memory 150 based on the DPB address 3 included in the DPB data 3.

[0114] The codec 112 writes the output data 1C related to the decoded image 1C into the output data buffer (S828). The codec 112 may write the output data into the output data buffer at an address next to the address where the output data 1C is stored.

[0115] When the writing of the output data is completed, the codec 112 transmits an interrupt signal 1C to the processor 113 (S829).

[0116] The processor 113 receives the interrupt signal 1B and reads the output data 1B from the output data buffer (S830). The processor 113 can determine the address of the output data buffer where the output data 1B is stored based on the number of times the interrupt signal 1B is received. The processor 113 can read the output data 1B from the determined address.

[0117] The processor 113 transmits a control signal for displaying the decoded image 1B to the display controller 115 (S831). The control signal may include a DPB address 2 determined based on the output data 1B.

[0118] The display controller 115 reads the decoded image 1B stored at the DPB address 2 of the DPB ( S832 ).

[0119] The display controller 115 may display the decoded image 1B on the display 130 ( S833 ).

[0120] The processor 113 transmits a control signal for displaying the decoded image 1A to the display controller 115 (S834). The control signal may include a DPB address 1 determined based on the output data 1A.

[0121] The display controller 115 reads the decoded image 1A stored at the DPB address 1 of the DPB ( S835 ).

[0122] The display controller 115 may display the decoded image 1A on the display 130 ( S836 ).

[0123] According to some embodiments, when the codec 112 needs a DPB address, it can read the DPB address from the DPB data buffer without requiring an additional DPB address, thereby reducing the delay caused by the DPB address allocation (see “Delay” in FIG. 5 ).

[0124] For example, according to some embodiments, based on the above decoding method, the speed, accuracy and / or power efficiency of the memory device may be improved. Therefore, the improved device and method overcome the shortcomings of the traditional device and decoding method related to decoding / encoding image data, while reducing resource consumption, improving data accuracy, and improving resource allocation (e.g., latency). In addition, by providing the capabilities disclosed herein, such as those related to DPB addressing and memory storage architecture, the communication and reliability of the device are improved.

[0125] The following will describe how the codec 112 and the processor 113 use the DPB data buffer with reference to FIGS. 9 to 12 .

[0126] FIG. 9 is a flow chart illustrating a method of using DPB data in a DPB data buffer according to some embodiments, and FIG. 10 is a diagram illustrating a DPB and a DPB data buffer according to some embodiments.

[0127] 9 and 10 , the codec 112 reads the flag data of the DPB data 1030 b indicated by the read pointer 1 from the DPB data buffer 1020 (S900). The DPB data buffer 1020 may include a plurality of DPB data 1030 a to 1030 e. The DPB 1000 may include a plurality of DPB areas 1010 a to 1010 e. Each of the plurality of DPB areas 1010 a to 1010 e may store a decoded image. The DPB areas 1010 c and 1010 e including the decoded image may be in a “used” state, while the DPB areas 1010 a, 1010 b, and 1010 d not including the decoded image may be in an “unused” state. The plurality of DPB data 1030 a to 1030 e may indicate the plurality of DPB areas 1010 a to 1010 e. When the DPB areas 1010a to 1010e indicated by the plurality of DPB data 1030a to 1030e are in a "used" state, the flag data of the plurality of DPB data 1030a to 1030e may have a first value ("0"), and when the DPB areas 1010a to 1010e indicated by the plurality of DPB data 1030a to 1030e are in an "unused" state, the flag data may have a second value ("1").

[0128] The codec 112 determines whether the value of the flag data is the second value ("1") (S910). The codec 112 can determine whether the DPB area 1010b indicated by the DPB data 1030b is in a "used" state or an "unused" state based on the value of the flag data of the DPB data 1030b.

[0129] When the flag data of the DPB data 1030b is the second value ("1"), the codec 112 uses the DPB area 1010b of the DPB data 1030b (S920). For example, when the DPB area 1010b indicated by the DPB data 1030b is in an "unused" state, the codec 112 may store a decoded image in the DPB area 1010b.

[0130] The codec 112 changes the flag data of the DPB data 1030b to the first value (“0”) (S930). The codec 112 may change the flag data of the DPB data 1030b to the first value (“0”) to indicate that the DPB area 1010b indicated by the DPB data 1030b is in the “used” state.

[0131] When the flag data of the DPB data 1030b is the first value ("0"), the codec 112 may read the flag data of the DPB data 1030b indicated by the read pointer 1 from the DPB data buffer 1020 again. The codec 112 may re-read the flag data of the DPB data 1030b at a predetermined (or, alternatively, desired or selected) interval. Therefore, the codec 112 may wait until the flag data of the DPB data 1030b is changed to the second value ("1").

[0132] After using the DPB data 1030b, the read pointer is incremented / moved (S940). Then, the codec 112 may read the DPB data 1030c indicated by the read pointer 2. The read pointer may indicate the DPB data to be read when looping through the DPB data buffer 1020. For example, in operation S900, the read pointer may indicate the address of the DPB data buffer 1020 where the last DPB data 1030e has been stored, and is incremented in operation S940 to indicate the base address.

[0133] FIG. 11 is a flow chart illustrating a method of updating DPB data in a DPB data buffer according to some embodiments, and FIG. 12 is a diagram illustrating a DPB and a DPB data buffer according to some embodiments.

[0134] 11 and 12 , the processor 113 reads the flag data of the DPB data 1230 e indicated by the write pointer 1 from the DPB data buffer 1020 ( S1100 ).

[0135] The processor 113 determines whether the value of the flag data is the first value ("0") (S1110). The processor 113 can determine whether the DPB area 1210b indicated by the DPB data 1230e is in a "used" state or an "unused" state based on the value of the flag data of the DPB data 1230e.

[0136] When the flag data of the DPB data 1230e is the first value ("0"), the processor 113 stores the DPB data 1230e indicating the new DPB area 1210f (S1120). For example, when the DPB area 1210e indicated by the DPB data 1230e is in the "used" state, the processor 113 may store the DPB data 1230e indicating the DPB area 1210f having the "unused" state at the area indicated by the write pointer 1.

[0137] The processor 113 changes the flag data of the DPB data 1230e to the second value (“1”) (S1130). The processor 113 may change the flag data of the DPB data 1230e to the second value (“1”) to indicate that the DPB area 1210e indicated by the DPB data 1230e is in an “unused” state.

[0138] When the flag data of the DPB data 1230e is the second value ("1"), the processor 113 may read the flag data of the DPB data 1230e indicated by the write pointer 1 from the DPB data buffer 1220 again. The processor 113 may re-read the flag data of the DPB data 1230e at a predetermined (or, alternatively, desired or selected) interval. Therefore, the processor 113 may wait until the flag data of the DPB data 1230e is changed to the first value ("0").

[0139] After the new DPB data 1230e is stored, the write pointer is increased (S1140). Then, the processor 113 can read the next DPB data 1230a of the DPB data 1230e. The write pointer can indicate the DPB data to be read when circulating through the DPB data buffer 1220.

[0140] FIG. 13 is a flow chart illustrating a decoding method according to some embodiments.

[0141] 1, 2, 6, 7 and 13, the operating system 151 allocates a plurality of buffers 610, 620, 630, 640 and 650 in the working memory 600, and notifies the processor 113 of information about the plurality of buffers 610, 620, 630, 640 and 650 (S1300). For example, the operating system 151 may notify the processor 113 of information about addresses of the plurality of buffers and information about sizes of respective regions. The processor 113 may transmit the information about the plurality of buffers 610, 620, 630, 640 and 650 to the codec 112.

[0142] The processor 113 stores the input data in the working memory 150 (S1310). The processor 113 may generate input data including a coded bit stream buffer address and a coded bit stream size of the stored coded bit stream. For example, the processor 113 may store a plurality of input data 4 to input data 7 generated in response to a plurality of coded bit streams in the input data buffer in the working memory 600.

[0143] The processor 113 stores the DPB data in the working memory 150 (S1311). For example, the processor 113 may generate a plurality of DPB data 4 to DPB data 7 corresponding to a plurality of coded bit streams. The plurality of DPB data 4 to DPB data 7 may respectively include a DPB address. The processor 113 may store the plurality of DPB data sequentially starting from the base address of the DPB data buffer.

[0144] If the input data and DPB data items are stored, the processor 113 transmits an interrupt signal H20 to the codec 112 (S1312). The processor 113 may transmit the interrupt signal H20 each time the storage of one input data and one DPB data is completed, or when the storage of a predetermined (or, alternatively, expected or selected) number of input data and DPB data is completed. The interrupt signal H20 transmitted when the storage of a predetermined (or, alternatively, expected or selected) number of input data and DPB data is completed may include the number of stored input data 4 to input data 7 and stored DPB data 4 to DPB data 7.

[0145] The codec 112 reads the input data 4 from the input data buffer of the working memory 150 based on the interrupt signal H20 (S1313). The codec 112 may receive the address range of the input data buffer from the processor 113 before operation S1313. When the interrupt signal H20 is received for the first time, the codec 112 may read the input data 4 from the base address of the input data buffer.

[0146] The codec 112 reads the DPB data 4 from the DPB data buffer of the working memory 150 based on the interrupt signal H20 (S1314). The codec 112 may receive the address range of the DPB data buffer from the processor 113 before operation S1313. When the interrupt signal H20 is received for the first time, the codec 112 may read the DPB data 4 from the base address of the DPB data buffer.

[0147] The codec 112 decodes the coded bit stream 4 stored at the coded bit stream buffer address for the input data 4 (S1315). Here, the coded bit stream 4 may be an interlaced image. For example, the coded bit stream 4 may be a top field image or a bottom field image. The coded bit stream 4 may include information about whether the decoded image has been arranged according to the interlaced scanning type, and information about whether the decoded image is a top field image or a bottom field image, as information about the image arrangement method. The codec 112 may read the coded bit stream 4 from the working memory 150 based on the coded bit stream buffer address included in the input data 4, and decode the coded bit stream 4 to generate top field data of an interlaced image of one frame.

[0148] The codec 112 refers to the DPB data 4 and writes the decoded image 4 into the DPB (S1316). The codec 112 may write the decoded image 4 into the working memory 150 based on the DPB address 4 included in the DPB data 4.

[0149] The codec 112 writes the output data 4 associated with the decoded picture 4 into the output data buffer (S1317). When the decoding is completed for the first time, the codec 112 may write the output data to the base address of the output data buffer. The output data 4 may include information indicating that the top field decoding of the interlaced picture has been completed.

[0150] When the writing of the output data is completed, the codec 112 transmits an interrupt signal C4 to the processor 113 (S1318).

[0151] The processor 113 receives the interrupt signal C4 and reads the output data 4 from the output data buffer (S1319). The processor 113 may determine the address at which the output data 4 has been stored in the output data buffer based on the number of times the interrupt signal C4 is received. The processor 113 may read the output data 4 from the determined address. The processor 113 may determine from the output data 4 that the decoded image 4 is the top field data of the interlaced image of one frame. Therefore, the processor 113 may not transmit the control signal for displaying the interlaced image of one frame to the display controller 115 after reading the output data 4 until the output data (e.g., output data 5) indicating that the decoding of the interlaced image of one frame has been completed is read.

[0152] If the decoding of the interlaced image has not been completed, the codec 112 reads the input data 5 from the input data buffer of the working memory 150 (S1320).

[0153] The codec 112 decodes the coded bit stream 5 stored at the coded bit stream buffer address for the input data 5 (S1321). The codec 112 can generate bottom field data of an interlaced image of one frame.

[0154] The codec 112 writes the decoded image 5 into the DPB based on the DPB address 4 where the top field data is stored (S1322).

[0155] The codec 112 writes the output data 5 associated with the decoded image 5 into the output data buffer (S1323). The codec 112 may generate the output data 5 including information indicating that the decoding of the interlaced image of one frame has been completed. The codec 112 may write the output data into the output data buffer at the next address of the address where the output data 4 has been stored.

[0156] When the writing of the output data 5 is completed, the codec 112 transmits an interrupt signal C5 to the processor 113 (S1324).

[0157] The processor 113 receives the interrupt signal C5 and reads the output data 5 from the output data buffer (S1325). The processor 113 can determine the address of the output data 5 stored in the output data buffer based on the number of times the interrupt signal C5 is received. The processor 113 can read the output data 5 from the determined address.

[0158] The processor 113 transmits a control signal for displaying the decoded image 4 and the decoded image 5 to the display controller 115 based on the output data 5 (S1326). The processor 113 may check the information indicating that the interlaced image decoding of one frame in the output data 5 has been completed, and generate a control signal for displaying the decoded image 4 and the decoded image 5. The control signal may include the DPB address 4 determined based on the output data 5.

[0159] The display controller 115 reads the decoded image 4 and the decoded image 5 stored at the DPB address 4 of the DPB ( S1340 ).

[0160] The display controller 115 may display the decoded image 4 and the decoded image 5 on the display 130 ( S1340 ).

[0161] After transmitting the interrupt signal C5, the codec 112 reads the input data 6 from the input data buffer (S1328).

[0162] The codec 112 reads the DPB data 5 from the DPB data buffer of the working memory 150 based on the interrupt signal H20 (S1329).

[0163] The codec 112 decodes the coded bit stream 6 stored at the coded bit stream buffer address for the input data 6 (S1330).

[0164] The codec 112 refers to the DPB data 5 and writes the decoded image 6 into the DPB (S1331). The codec 112 may write the decoded image 6 into the working memory 150 based on the DPB address 5 included in the DPB data 5.

[0165] The codec 112 writes the output data 6 associated with the decoded image 6 into the output data buffer (S1332).

[0166] When the writing of the output data is completed, the codec 112 transmits an interrupt signal C6 to the processor 113 (S1333).

[0167] The processor 113 receives the interrupt signal C6 and reads the output data 6 from the output data buffer (S1334).

[0168] The processor 113 transmits a control signal for displaying the decoded image 6 to the display controller 115 ( S1335 ). The control signal may include the DPB address 5 determined based on the output data 6 .

[0169] The display controller 115 reads the decoded image 6 stored at the DPB address 5 of the DPB ( S1336 ).

[0170] The display controller 115 may display the decoded image 6 on the display 130 ( S1337 ).

[0171] According to the method using the working memory 150 described with reference to FIG. 5 , the top field data and the bottom field data of the bit stream encoded in the interlaced scanning mode can be stored in different DPB areas, respectively. Therefore, the bit stream encoded in the interlaced scanning mode can be decoded using the special function register in the codec memory 210. In the case of using the special function register, when the codec 112 is decoding the encoded bit stream stored in the special function register, the processor 113 cannot use the new encoded bit stream in the special function register because the special function register is in use. In addition, when the processor 113 is processing the decoded image, the codec 112 cannot perform the decoding operation until the processor 113 stores the new encoded bit stream in the special function register. Therefore, in the decoding method using the special function register, a delay may occur.

[0172] According to some example embodiments, in the case of decoding a bit stream encoded in an interlaced scanning manner, the codec 112 may store the top field data and the bottom field data in one DPB area. Therefore, according to some example embodiments, the delay may be reduced compared to the case of using a special function register.

[0173] For example, according to some example embodiments, based on the above decoding method, the speed, accuracy and / or power efficiency of the memory device may be improved. Therefore, the improved device and method overcome the defects of the traditional device and decoding method related to decoding / encoding image data, while reducing resource consumption, improving data accuracy, and improving resource allocation (e.g., latency). In addition, by providing the functions disclosed herein, such as those related to DPB address and memory storage architecture, the communication capability and reliability of the device are improved.

[0174] In some example embodiments, each constituent element or a combination of two or more constituent elements described with reference to FIGS. 1 to 13 may be implemented as a digital circuit, a programmable or non-programmable logic device or array, a special application integrated circuit, and the like.

[0175] As described herein, any electronic device and / or portion thereof according to any example embodiment may include, may be included in, and / or may be implemented by one or more instances of processing circuits, such as hardware including logic circuits; hardware / software combinations, such as processors that execute software; or any combination thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application-specific integrated circuit, a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuit may include a non-transitory computer-readable storage device (e.g., memory), such as a dynamic random access memory (DRAM) device, for storing an instruction program, and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and / or methods performed by any device, system, module, unit, controller, circuit, architecture and / or portion thereof, and / or any portion thereof according to any example embodiment.

[0176] Although the present invention has been described in detail with particular reference to exemplary embodiments of the present invention, the exemplary embodiments described herein are not intended to be exhaustive or to limit the scope of the present invention to the precise forms disclosed. On the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0177] 100: Video encoding device 110: System on Chip 111: Pre-processing circuit 112, 200: Codec 113: Processor 114: Modem 115: Display controller 116: User Interface 117:Memory Controller 118:Memory Interface 119: Bus 120:Video source 130: Display 140: Input device 150, 300, 600: working memory 151:Working System 160: Storage device 210:Codec memory 211: Counter register 212:Firmware 220: Processing unit / codec processing unit 221:Decoder 222: Encoder 310: Buffer zone / first zone 320: Buffer / Second Area 330: Buffer zone / third zone 340: Buffer zone / fourth zone 400: Input data buffer 410: Input data 411: Encoded bitstream buffer address 412: Frame data size 413, 712: DPB address 610: Buffer zone / first zone 620: Buffer / Second Area 630: Buffer zone / third zone 640: Buffer zone / fourth zone 650: Buffer zone / Fifth zone 700, 1020, 1220: DPB data buffer 711: Logo Information 1000:DPB 1010a, 1010b, 1010c, 1010d, 1010e, 1210a, 1210b, 1210c, 1210d, 1210e, 1210f: DPB area 1030a, 1030b, 1030c, 1030d, 1030e, 1230a, 1230b, 1230c, 1230d, 1230e, 710, 710a, 710b: DPB data S500, S510, S511, S512, S513, S515, S516, S517, S518, S519, S520, S521, S522, S52 3. S524, S525, S526, S527, S528, S529, S530, S531, S532, S533, S534, S535, S536, S5 37. S538, S539, S540, S541, S542, S543, S544, S545, S800, S810, S811, S812, S813, S 814, S815, S816, S817, S818, S819, S820, S821, S822, S823, S824, S825, S826, S827, S828, S829, S830, S831, S832, S833, S834, S835, S836, S900, S910, S920, S930, S940 , S1100, S1110, S1120, S1130, S1140, S1300, S1310, S1311, S1312, S1313, S1314, S1 315, S1316, S1317, S1318, S1319, S1320, S1321, S1322, S1323, S1324, S1325, S1326, S1328, S1329, S1330, S1331, S1332, S1333, S1334, S1335, S1336, S1337, S1340: Operation

Claims

1. A decoding method, comprising: Read first input data containing information about the address of a first coded bit stream buffer from an input data buffer; Read first DPB data containing information about a first DPB address and flag data from a DPB data buffer, wherein the flag data indicates whether the first DPB data is available, the first DPB data containing information about the first DPB address indicating an allocated DPB for storing encoded bitstream data; generate a first decoded image by decoding a first encoded bitstream stored at the first encoded bitstream buffer address; and store the first decoded image at the first DPB address.

2. The decoding method as described in claim 1 further includes: Determining whether the value of the flag data of the first DPB data is a first value; wherein, storing the first decoded image at the first DPB address includes: storing the first decoded image at the first DPB address based on the value of the flag data of the first DPB data being the first value.

3. The decoding method as described in claim 2 further includes: Based on storing the first decoded image at the first DPB address, the value of the flag data in the first DPB data is changed to a second value.

4. The decoding method as described in claim 2 further includes: Based on the value of the flag data of the first DPB data being a second value, a second DPB data is read from the address following the address of the first DPB data already stored in the DPB data buffer.

5. The decoding method as described in claim 1 further includes: Read a second DPB data containing information about a second DPB address from the DPB data buffer; A second decoded image is generated by decoding the first encoded bitstream; and the second decoded image is stored at the second DPB address.

6. The decoding method as described in claim 5, wherein reading the second DPB data includes reading the second DPB data from the address following the address of the first DPB data already stored in the DPB data buffer.

7. The decoding method as described in claim 5 further includes: Read a second input data containing information about the address of a second coded bit stream buffer from the input data buffer; Read a third DPB data containing information about a third DPB address from the DPB data buffer; generate a third decoded image by decoding a second encoded bitstream stored at the second encoded bitstream buffer address; and store the third decoded image at the third DPB address.

8. The decoding method as described in claim 1 further includes: Read a second input data containing information about the address of a second coded bit stream buffer from the input data buffer; A second decoded image is generated by decoding a second encoded bitstream stored at the address of the second encoded bitstream buffer; and the second decoded image is stored at the address of the first DPB.

9. The decoding method of claim 8, wherein the first decoded image and the second decoded image are top field data and bottom field data of a frame of interlaced image, respectively, and the decoding method further includes writing output data into an output data buffer, the output data containing information indicating that the decoding of a frame of the interlaced image has been completed.

10. The decoding method as described in claim 1, further comprising: A second DPB data containing information about a second DPB address is written into the DPB data buffer.

11. The decoding method of claim 10, wherein writing the second DPB data includes the following: determining whether the value of the flag data of the first DPB data is a second value; and writing the second DPB data at an address where the first DPB data has been stored, based on the value of the flag data of the first DPB data being the second value.

12. A system-on-a-chip, comprising: A processor is configured to write first input data, including information about a first coded bitstream buffer address, into an input data buffer, and first DPB data, including information about a first DPB address, into a DPB data buffer; and a codec is configured to read the first input data from the input data buffer, read the first DPB data including flag data from the DPB data buffer, wherein the flag data indicates whether the first DPB data is available, the first DPB data including information about a first DPB address indicating an allocated DPB for storing coded bitstream data, generate a first decoded image by decoding a first coded bitstream stored at the first coded bitstream buffer address, and store the first decoded image at the first DPB address.

13. The system-on-a-chip as claimed in claim 12, wherein the codec is further configured to determine whether the value of the flag data of the first DPB data is a first value, store the first decoded image at the first DPB address based on the value of the flag data of the first DPB data being the first value, and change the value of the flag data of the first DPB data to a second value based on storing the first decoded image at the first DPB address.

14. The system-on-a-chip as claimed in claim 13, wherein the codec is further configured to read a second DPB data from the address following the address of the first DPB data stored in the DPB data buffer, based on the value of the flag data of the first DPB data being the second value.

15. The system-on-a-chip as claimed in claim 12, wherein the processor is further configured to determine whether the value of the flag data of the first DPB data is a second value, and based on the value of the flag data of the first DPB data being the second value, to write a second DPB data containing information about a second DPB address at the address where the first DPB data is stored.

16. The system-on-a-chip as claimed in claim 12, wherein the codec is further configured to read a second DPB data containing information about a second DPB address from the DPB data buffer, generate a second decoded image by decoding the first coded bitstream, and store the second decoded image at the second DPB address.

17. The system-on-a-chip as claimed in claim 16, wherein the codec is further configured to read a second input data containing information about a second coded bitstream buffer address from the input data buffer, read a third DPB data containing information about a third DPB address from the DPB data buffer, generate a third decoded image by decoding a second coded bitstream stored at the second coded bitstream buffer address, and store the third decoded image at the third DPB address.

18. The system-on-a-chip as claimed in claim 12, wherein the codec is further configured to read a second input data containing information about a second coded bitstream buffer address from the input data buffer, generate a second decoded image by decoding a second coded bitstream stored at the second coded bitstream buffer address, and store the second decoded image at the first DPB address.

19. A decoding device, comprising: A working memory includes a coded bitstream buffer configured to store multiple coded bitstreams, an input data buffer configured to store multiple input data containing information about the addresses of the multiple coded bitstream buffers, a decoded image buffer (DPB) configured to store multiple decoded images, and a DPB data buffer configured to store multiple DPB data containing information about the addresses of the multiple DPBs. And a system-on-a-chip configured to read first input data containing information about a first coded bitstream buffer address from the input data buffer, read first DPB data containing information about a first DPB address and flag data from the DPB data buffer, wherein the flag data indicates whether the first DPB data is available, the first DPB data containing information about the first DPB address indicating an allocated DPB for storing coded bitstream data, read a first coded bitstream stored at the first coded bitstream buffer address, generate a first decoded image by decoding the first coded bitstream, and store the first decoded image at the first DPB address of the decoded image buffer.

20. The decoding apparatus of claim 19, wherein the plurality of DPB data further comprises a plurality of flag data, and the system chip is further configured to use or update the plurality of DPB data based on the plurality of flag data.

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