Electrical package and fabricating method thereof

Abstract

An electronic package and its manufacturing method are disclosed. A first recess and a second recess are formed on a first side and a second side of a core board, respectively. A first electronic component and a second electronic component are then disposed in the first recess and the second recess, respectively. An insulating layer is then filled into the first recess and the second recess to cover the first electronic component and the second electronic component. A circuit layer is formed on the insulating layer, and a plurality of conductive blind vias are formed in the insulating layer to electrically connect the circuit layer with the first electronic component and the second electronic component. This ensures that the first electronic component and the second electronic component do not shift when the insulating layer is filled into the first recess and the second recess.

Description

[Technical Field]

[0001] This invention relates to a semiconductor packaging technology, and more particularly to an electronic package and its manufacturing method. [Previous Technology]

[0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. In this type of device, a chip is placed on a packaging substrate and electrically connected to the packaging substrate. The chip is then covered with a packaging colloid. In order to meet the need for thinning, the industry has embedded the chip in a packaging substrate to reduce the overall size of the semiconductor device and improve its electrical functions, which has become a packaging trend.

[0003] Figures 1A to 1G are cross-sectional schematic diagrams of the manufacturing process of a conventional semiconductor package 1.

[0004] As shown in Figure 1A, a core board 10 is provided, having wiring layers 101 on its upper and lower sides, and at least one conductive via 102 electrically connected to the wiring layers 101 is formed in the core board 10.

[0005] As shown in Figure 1B, an opening 100 is formed on the core plate 10 that penetrates the core plate 10.

[0006] As shown in FIG1C, a semiconductor wafer 11 having a plurality of electrode pads 110 is accommodated in the opening 100.

[0007] As shown in Figure 1D, a dielectric layer 14 is pressed onto the upper and lower sides of the core plate 10, so that the dielectric layer 14 fills the opening 100 to cover the semiconductor wafer 11.

[0008] As shown in FIG1E, a plurality of blind vias 140 are formed on the dielectric layer 14 so that a portion of the surface of each electrode pad 110 and the wiring layer 101 is exposed to the blind vias 140.

[0009] As shown in FIG1F, a circuit layer 13 is formed on each of the dielectric layers 14, and the circuit layer 13 forms a plurality of conductive blind holes 130 electrically connecting the electrode pad 110 and the wiring layer 101 in each of the blind holes 140.

[0010] As shown in FIG1G, a solder resist layer 15 is formed on each of the dielectric layer 14 and the circuit layer 13, and a plurality of openings 150 are formed on the solder resist layer 15 so that a portion of the surface of the circuit layer 13 is exposed to the openings 150.

[0011] However, in the conventional method for manufacturing the semiconductor package 1, an opening 100 needs to be formed in the core board 10 to place the semiconductor chip 11. If the depth D of the opening 100 is greater than the thickness H of the semiconductor chip 11, when the dielectric layer 14 is filled into the opening 100, it will impact the semiconductor chip 11 and cause the semiconductor chip 11 to shift (as shown in FIG. 1D, the left and right spacings t1, t2 between the semiconductor chip 11 and the hole wall of the opening 100 are different, where t1 < t2), or even skew, resulting in that in the subsequent process, the electrode pad 110 of the semiconductor chip 11 cannot be accurately aligned with the blind hole 140, causing the conductive blind hole 130 and the electrode pad 110 to fail to be effectively electrically connected, thereby leading to poor reliability of the product.

[0012] Therefore, how to avoid the deficiencies of the conventional technology has actually become an urgent issue to be solved currently.

SUMMARY OF THE INVENTION

[0013] In view of the above-mentioned various deficiencies of the conventional technology, the present invention provides an electronic package, which includes: a core board having opposite first and second sides, and respectively provided with a first recess and a second recess on the first and second sides that do not penetrate the core board; a first electronic component disposed in the first recess; a second electronic component disposed in the second recess; an insulating layer disposed on the first and second sides of the core board and filled into the first and second recesses to cover the first and second electronic components; a circuit layer disposed on the insulating layer; and a plurality of conductive blind holes disposed in the insulating layer to electrically connect the circuit layer with the first and second electronic components.

[0014] The present invention also provides a method for manufacturing an electronic package, which includes: providing a core board having opposite first and second sides, and respectively provided with a first recess and a second recess on the first and second sides that do not penetrate the core board; placing a first electronic component in the first recess and placing a second electronic component in the second recess; forming an insulating layer on the first and second sides of the core board, and the insulating layer is filled into the first and second recesses to cover the first and second electronic components; and forming a circuit layer on the insulating layer and forming a plurality of conductive blind holes in the insulating layer to electrically connect the plurality of conductive blind holes with the circuit layer and the first and second electronic components.

[0015] In the above-mentioned electronic package and its manufacturing method, the positions of the first recess and the second recess are not aligned.

[0016] In the aforementioned electronic package and its manufacturing method, the position of the first electronic component and the position of the second electronic component are not aligned.

[0017] In the aforementioned electronic package and its manufacturing method, the first side and the second side are respectively provided with wiring layers; conductive vias electrically connected to the wiring layers are formed in the core board.

[0018] In the aforementioned electronic package and manufacturing method thereof, the insulating layer has a plurality of blind holes, so that the conductive blind holes are formed in the blind holes.

[0019] As can be seen from the above, in the electronic package and manufacturing method of the present invention, the first electronic component and the second electronic component are accommodated by opening misaligned and non-penetrating recesses on both sides of the core board. When the insulating layer is filled into the first recess and the second recess, the first electronic component and the second electronic component will not be offset or skewed. Therefore, compared with the prior art, when the blind hole is manufactured, the first electronic component and the second electronic component can be precisely aligned with the blind hole, so that each conductive blind hole can be effectively electrically connected to the first electronic component and the second electronic component, thereby improving the reliability of the product. [Simplified Explanation of the Diagram]

[0020] Figures 1A to 1G are cross-sectional schematic diagrams of conventional semiconductor package manufacturing methods.

[0021] Figures 2A to 2G are cross-sectional schematic diagrams of the manufacturing method of the electronic package of the present invention.

Implementation Method

[0022] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0023] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention. At the same time, the terms such as "above," "first," "second," and "a" used in this specification are only for the clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0024] Figures 2A to 2G are cross-sectional schematic diagrams of the manufacturing method of the electronic package 2 of the present invention.

[0025] As shown in FIG2A, a core board 20 is provided, having a first side 20a and a second side 20b opposite to each other, and a wiring layer 201 is respectively provided on the first side 20a and the second side 20b, and at least one conductive via 202 electrically connected to the wiring layers 201 is formed in the core board 20.

[0026] In this embodiment, the core board 20 may be a board containing bis(cis-butadiene)imide / triazine (BT), prepreg (PP) or other boards, and the wiring layer 201 may be formed by electroplating metal (such as copper) or other methods.

[0027] Furthermore, the conductive via 202 is a hollow copper pillar, the hollow portion of which can be filled with a plugging material 203. For example, the plugging material 203 can be an insulating material or a conductive material, etc., without particular limitation. It should be understood that in other embodiments, the conductive via 202 can also be a solid metal pillar, without the need to fill it with plugging material 203.

[0028] As shown in FIG2B, a first recess S1 is formed on the first side 20a of the core plate 20, and a second recess S2 is formed on the second side 20b of the core plate 20, so that the positions of the first recess S1 and the second recess S2 are not aligned.

[0029] In this embodiment, the position of the first recess S1 and the position of the second recess S2 are offset from each other.

[0030] Furthermore, the first recess S1 and / or the second recess S2 may be formed by drilling, etching, laser or other methods. It should be understood that the first recess S1 and the second recess S2 may be formed by the same or different methods.

[0031] As shown in Figure 2C, the first electronic component 21 is placed in the first recess S1 and the second electronic component 22 is placed in the second recess S2, so that the positions of the first electronic component 21 and the second electronic component 22 are not aligned.

[0032] In this embodiment, the first electronic component 21 may be an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the first electronic component 21 is a semiconductor wafer having opposing active surfaces 21a and non-active surfaces 21b, and the active surface 21a has a plurality of electrode pads 210, so that the first electronic component 21 is fixed in the first recess S1 by the adhesive layer 26 with its non-active surface 21b facing outwards. Furthermore, conductive bumps 211, such as copper pillars, may be formed on the electrode pads 210 as needed.

[0033] Furthermore, the second electronic component 22 can be an active component, a passive component, or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the second electronic component 22 is a semiconductor wafer having opposing active surfaces 22a and non-active surfaces 22b, and the active surface 22a has a plurality of electrode pads 220, so that the second electronic component 22 is fixed in the second recess S2 by means of the non-active surface 22b by the adhesive layer 26, with the active surface 22a facing outward. Further, conductive bumps 221, such as copper pillars, can be formed on the electrode pads 220 as needed.

[0034] Furthermore, the thickness H1 of the first electronic component 21 (together with the adhesive layer 26) is greater than or equal to the depth D1 of the first recess S1, and the thickness H2 of the second electronic component 22 (together with the adhesive layer 26) is greater than or equal to the depth D2 of the second recess S2.

[0035] In addition, the positions of the first electronic component 21 and the second electronic component 22 are offset from each other.

[0036] As shown in FIG2D, an insulating layer 24 is formed on the first side 20a and the second side 20b of the core plate 20, such that the insulating layer 24 fills the first recess S1 and the second recess S2.

[0037] In this embodiment, the insulating layer 24 is a dielectric layer, such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials.

[0038] As shown in FIG2E, a plurality of blind holes 240 are formed on each of the insulating layers 24 so that each of the electrode pads 210, 220 (or each of the conductive bumps 211, 221) is exposed in the blind holes 240.

[0039] In this embodiment, the blind holes 240 can be formed by drilling, etching, laser, exposure development or other patterning methods, and the blind holes 240 can expose part of the surface of the wiring layer 201 as needed.

[0040] As shown in FIG2F, a circuit layer 23 is formed on each of the insulating layers 24, and a plurality of conductive blind holes 230 electrically connecting the electrode pads 210, 220 (or each of the conductive bumps 211, 221) and the wiring layer 201 are formed in each of the blind holes 240.

[0041] In this embodiment, the circuit layer 23 and the conductive blind via 230 can be integrally formed by electroplating metal (such as copper) or other methods.

[0042] As shown in FIG2G, an insulating protective layer 25 is formed on each of the insulating layers 24 and the circuit layer 23, and a plurality of openings 250 are formed on the insulating protective layer 25 so that a portion of the surface of the circuit layer 23 is exposed to the openings 250.

[0043] In this embodiment, the insulating protective layer 25 is a solder resist material such as green paint, ink or other materials.

[0044] Therefore, the present invention mainly utilizes staggered and non-penetrating recesses on both sides of the core plate 20 to accommodate the first electronic component 21 and the second electronic component 22. When the insulating layer 24 is filled into the first recess S1 (and / or the second recess S2), the first electronic component 21 (and / or the second electronic component 22) will not shift or tilt. Therefore, compared with the prior art, when the blind via 240 is manufactured, the electrode pads 210, 220 and the blind via 240 can be precisely aligned, so that the conductive blind via 230 and the electrode pads 210, 220 can be effectively electrically connected, thereby improving the reliability of the product. In addition, the first recess S1 and the second recess S2 do not penetrate the core plate 20, thereby allowing multiple electronic components to be embedded on both sides of the core plate 20, thereby improving the electrical function of the overall electronic package.

[0045] Furthermore, by designing that the positions of the first recess S1 and the second recess S2 are not aligned (or the positions of the first electronic component 21 and the second electronic component 22 are not aligned), the impact force on the first electronic component 21 and the second electronic component 22 when the insulating layer 24 is filled into the first recess S1 and the second recess S2 is reduced. Therefore, the positioning of the first electronic component 21 and the second electronic component 22 can be better ensured, so as to avoid problems such as the first electronic component 21 and the second electronic component 22 being offset or skewed.

[0046] The present invention also provides an electronic package 2, which includes: a core plate 20, at least one first recess S1, at least one second recess S2, at least one first electronic component 21, at least one second electronic component 22, an insulating layer 24, a circuit layer 23, and a plurality of conductive blind vias 230.

[0047] The core plate 20 has a first side 20a and a second side 20b opposite to each other, and a first recess S1 and a second recess S2 are respectively provided on the first side 20a and the second side 20b.

[0048] The first electronic component 21 is disposed in the first recess S1.

[0049] The second electronic component 22 is disposed in the second recess S2.

[0050] The insulating layer 24 is disposed on the first side 20a and the second side 20b of the core plate 20 and filled into the first recess S1 and the second recess S2 to cover the first electronic component 21 and the second electronic component 22.

[0051] The circuit layer 23 is disposed on the insulating layer 24.

[0052] The conductive blind via 230 is disposed in the insulating layer 24 to electrically connect the circuit layer 23 with the first electronic component 21 and the second electronic component 22.

[0053] In one embodiment, the position of the first recess S1 is not aligned with the position of the second recess S2.

[0054] In one embodiment, the position of the first electronic element 21 is not aligned with the position of the second electronic element 22.

[0055] In one embodiment, the insulating layer 24 has a plurality of blind holes 240, such that the conductive blind hole 230 is formed in the blind hole 240.

[0056] In summary, the electronic package and its manufacturing method of the present invention are based on the provision of staggered and non-penetrating recesses on both sides of the core board for accommodating electronic components. When the insulating layer is filled into the recesses, the electronic components will not be shifted or skewed. Therefore, the electronic components of the present invention can be effectively electrically connected to the conductive blind vias to improve the reliability of the product.

[0057] The above embodiments are used to illustrate the principles and effects of the present invention, and are not intended to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

Claims

1. An electronic package, comprising: A core board has a first side and a second side facing each other, and a first recess and a second recess that do not penetrate the core board are respectively provided on the first side and the second side; a first electronic component is disposed in the first recess; a second electronic component is disposed in the second recess; an insulating layer is simultaneously laid on the first side of the core board and filled into the first recess to cover the first electronic component, and simultaneously laid on the second side of the core board and filled into the second recess to cover the second electronic component; a circuit layer is disposed on the insulating layer; and a plurality of conductive blind vias are disposed in the insulating layer to electrically connect the circuit layer and the first electronic component in the first recess, and to electrically connect the circuit layer and the second electronic component in the second recess, and the plurality of conductive blind vias are aligned or correspond to a plurality of electrode pads of the first electronic component in the first recess and a plurality of electrode pads of the second electronic component in the second recess; The core board has conductive vias that electrically connect to the circuit layer but do not penetrate the second electronic component, and the second electronic component and the conductive vias are located at different positions on the core board and do not directly contact each other.

2. The electronic package as described in claim 1, wherein, The positions of the first recess and the second recess are not aligned.

3. The electronic package as described in claim 1, wherein, The positions of the first electronic component and the second electronic component are not aligned.

4. The electronic package as described in claim 1, wherein, The first side and the second side each have a wiring layer.

5. The electronic package as described in claim 4, wherein, The conductive via is electrically connected to the wiring layer.

6. The electronic package as claimed in claim 1 further includes an insulating protective layer formed on the insulating layer and the circuit layer, and a plurality of openings are formed on the insulating protective layer to expose a portion of the surface of the circuit layer through the plurality of openings.

7. A method for manufacturing an electronic package, comprising: A core board is provided, having a first side and a second side opposite to each other, and a first recess and a second recess that do not penetrate the core board are respectively provided on the first side and the second side; a first electronic component is placed in the first recess and a second electronic component is placed in the second recess; an insulating layer is simultaneously formed on the entire surface of the first side of the core board and filled into the first recess to cover the first electronic component, and the insulating layer is simultaneously formed on the entire surface of the second side of the core board and filled into the second recess to cover the second electronic component; A circuit layer is formed on the insulating layer, and a plurality of conductive blind vias are formed in the insulating layer so that the plurality of conductive blind vias electrically connect the circuit layer to the first electronic component in the first recess, and electrically connect the circuit layer to the second electronic component in the second recess. The plurality of conductive blind vias are aligned or correspond to the plurality of electrode pads of the first electronic component in the first recess and the plurality of electrode pads of the second electronic component in the second recess. A conductive via is formed in the core plate that electrically connects to the circuit layer but does not penetrate the second electronic component. The second electronic component and the conductive via are located at different positions on the core plate and do not directly contact each other.

8. The method for manufacturing an electronic package as described in claim 7, wherein, The positions of the first recess and the second recess are not aligned.

9. The method for manufacturing an electronic package as described in claim 7, wherein, The positions of the first electronic component and the second electronic component are not aligned.

10. The method for manufacturing an electronic package as described in claim 7, wherein, The first side and the second side each have a wiring layer.

11. The method for manufacturing an electronic package as described in claim 10, wherein, The conductive via is electrically connected to the wiring layer.

12. The method of manufacturing an electronic package as described in claim 7 further includes forming an insulating protective layer on the insulating layer and the circuit layer, and forming a plurality of openings on the insulating protective layer such that a portion of the surface of the circuit layer is exposed through the plurality of openings.

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