Self calibration digital to analog converter (DAC) and calibration method for dac

Abstract

A preferred embodiment of the present invention relates to a self-calibrating digital-to-analog converter circuit and a calibration method for the digital-to-analog converter. This circuit includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a calibration switching circuit. In normal operation mode, the resistor circuit receives a common voltage for conversion. In calibration mode, the circuit performs self-calibration in two steps: sampling time and comparison time. During sampling time, the resistor circuit receives a reference voltage and a first calibration digital value, and the buffer amplifier input samples the voltage. During comparison time, the resistor circuit receives the common voltage and a second calibration digital value, and the fine-tuning circuit adjusts the calibration data until the buffer amplifier output voltage flips, recording the calibration value corresponding to the second calibration digital value. Through this self-calibration mechanism, this circuit can output a theoretically correct digital-to-analog conversion result under both the reference voltage and the common voltage.

Description

[Technical Field]

[0001] This invention relates to a digital-to-analog converter technology, and more particularly to a self-correcting digital-to-analog converter circuit and a correction method for the digital-to-analog converter. [Previous Technology]

[0002] In the design of digital and analog systems, digital-to-analog converters (DACs) play a crucial role in converting digital information into analog voltage or analog current. However, due to factors such as process variations and component aging, the output value of DACs often deviates from the ideal value, leading to a decrease in conversion accuracy. To ensure the performance of DACs, calibration becomes an indispensable step.

[0003] Traditionally, there are two main methods for calibrating digital-to-analog converters. The first method is to directly measure the output voltage of the digital-to-analog converter and then correct the resistor array. Correction methods include using an electronic fuse to burn out specific resistors or using laser cutting to remove resistors, thereby adjusting the resistance value. While this method can effectively improve conversion linearity, it requires special processes to embed the electronic fuse or laser cutting equipment, significantly increasing manufacturing complexity and cost.

[0004] The second calibration method is to use an additional calibration DAC connected in parallel with the original DAC to compensate for the output deviation of the original DAC. This approach does not require special manufacturing processes, but it requires additional silicon area to accommodate the calibration DAC. Moreover, the calibration DAC continuously consumes power during operation, increasing the system power consumption.

[0005] Regardless of the calibration method used, a full code scan of the digital-to-analog converter is required in a controlled measurement environment to accurately measure the output voltage or current corresponding to each digital input. These measurement processes are not only time-consuming and labor-intensive, but also require high-precision testing equipment, such as high-precision digital voltmeters, which keeps the calibration cost high.

[0006] Although existing digital-to-analog converter calibration techniques can improve conversion accuracy to some extent, they all suffer from drawbacks such as complex manufacturing processes, large indirect costs (area, power consumption, etc.), and high testing costs. Therefore, a new low-cost and high-efficiency calibration scheme is needed. [Summary of the Invention]

[0007] Embodiments of the present invention provide a self-correcting digital-to-analog converter circuit and a correction method for the digital-to-analog converter, for correcting output inaccuracies caused by impedance drift within the digital-to-analog converter circuit.

[0008] Embodiments of the present invention provide a self-calibrating digital-to-analog converter circuit, which includes a resistor circuit, a buffer amplifier, a fine-tuning circuit, and a calibration switching circuit. The resistor circuit includes a plurality of bit input terminals, a reference voltage input terminal, an output terminal, and a common calibration terminal, wherein the reference voltage input terminal of the resistor circuit receives a reference voltage. The first input terminal of the fine-tuning circuit is coupled to the output terminal of the resistor circuit, the output terminal of the fine-tuning circuit is coupled to the first input terminal of the buffer amplifier, and the second input terminal of the fine-tuning circuit is coupled to the output terminal of the buffer amplifier. The first terminal of the calibration switching circuit is coupled to the second input terminal of the buffer amplifier, and the second terminal of the calibration switching circuit is coupled to the output terminal of the buffer amplifier.

[0009] In normal operation, the aforementioned self-calibrating digital-to-analog converter circuit receives a common voltage at the common calibration terminal of the resistor circuit, and the first and second terminals of the calibration switching circuit are short-circuited. In calibration mode, the aforementioned self-calibrating digital-to-analog converter circuit includes a sampling time and a comparison time. During the sampling time, the first and second terminals of the calibration switching circuit are short-circuited, wherein the common calibration terminal of the resistor circuit receives the reference voltage, and a first calibration bit value is input to a plurality of bit input terminals of the resistor circuit. The first terminal of the calibration switching circuit samples and temporarily stores the voltage at the second input terminal of the buffer amplifier. During the comparison time, a common voltage is input to the common correction terminal of the resistor circuit, and a second correction bit value is input to the majority bit input terminals of the resistor circuit. The first and second terminals of the correction switching circuit are disconnected, and the voltage sampled by the first terminal of the correction switching circuit is output to the second input terminal of the buffer amplifier. During the comparison time, the fine-tuning circuit adjusts a correction data and adjusts the voltage at the output terminal of the fine-tuning circuit according to the correction data until the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage.

[0010] Wherein, the fine-tuning circuit records the correction data when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage as the correction value corresponding to the second correction bit value. Wherein, when the common correction terminal of the resistor circuit is input with a reference voltage and the resistor circuit is input with the first correction bit value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. Wherein, when the common correction terminal of the resistor circuit is input with a common voltage and the resistor circuit is input with the second correction bit value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. Wherein, the first theoretical voltage is equal to the second theoretical voltage.

[0011] Another embodiment of the present invention provides a calibration method for a digital-to-analog converter. This calibration method includes: providing a buffer amplifier and a resistor circuit; dividing a calibration time into a sampling time and a comparison time; during the sampling time: controlling the second input terminal of the buffer amplifier to be short-circuited with the output terminal of the buffer amplifier; inputting a first calibration digit value through the resistor circuit and inputting a reference voltage to the common calibration terminal of the resistor circuit, causing the resistor circuit to generate a first voltage, which is output to the first input terminal of the buffer amplifier; sampling the first voltage through the second input terminal of the buffer amplifier; during the comparison time: controlling the second input terminal of the buffer amplifier to be open-circuited with the output terminal of the buffer amplifier; inputting a common voltage to the common calibration terminal of the resistor circuit and inputting a second calibration digit value to the resistor circuit, causing the resistor circuit to generate a second voltage, which is output to the first input terminal of the buffer amplifier. The first input terminal of the buffer amplifier; outputs the sampled voltage to the second input terminal of the buffer amplifier; adjusts a correction data, and adjusts the voltage according to the correction data until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage; and records the correction data at the time when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage as the correction value corresponding to the second correction bit value, wherein, when the common correction terminal of the resistor circuit is input with the reference voltage, and the resistor circuit is input with the first correction bit value, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage, wherein, when the common correction terminal of the resistor circuit is input with the common voltage, and the resistor circuit is input with the second correction bit value, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage, wherein, the first theoretical voltage is equal to the second theoretical voltage.

[0012] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

Implementation Method

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Where possible, the same element symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the present invention, and the following examples are not intended to limit the present invention.

[0017] Figure 1 illustrates a circuit block diagram of a self-calibrating digital-to-analog converter circuit according to a preferred embodiment of the present invention. Referring to Figure 1, this self-calibrating digital-to-analog converter circuit includes a resistor circuit 101, a buffer amplifier 102, a fine-tuning circuit 103, and a calibration switching circuit 104. In this embodiment, the resistor circuit 101 itself is a digital-to-analog converter. In this embodiment, the resistor circuit 101 is implemented using an R-2R resistor ladder circuit for an 8-bit least significant bit (LSB) portion, that is, each second resistor R is coupled between first resistors 2R. The first resistor in this embodiment is used as a calibration resistor X2R. Under normal operation, the calibration resistor X2R is coupled to the common voltage Vcom through the calibration switch Scal. In calibration mode, the calibration resistor X2R is coupled to the reference voltage Vref through the calibration switch Scal. In other embodiments, in calibration mode, the calibration resistor X2R can be coupled to the common voltage Vcom.

[0018] The 4-bit Most Significant Bit (MSB) portion is implemented using a thermometer code circuit. Therefore, a preferred embodiment of the present invention is a 12-bit digital-to-analog converter. Since the thermometer code circuit is an encoding that determines the number of "logic 1s" output sequentially based on the size of the digit, in this embodiment, the least significant bits b0 to b7 represent T0 of the thermometer code, while T1 to T15 will vary according to the 4-bit most significant bit. For example, assuming the most significant bit is 0110, it means that T1 to T6 are turned on to the reference voltage Vref, and the corresponding resistors are input with a logic high voltage, while the remaining T7 to T15 are turned on to a logic low voltage, that is, connected to the common voltage Vcom.

[0019] In this embodiment, the correction switching circuit 104 includes a first switch S1, a second switch S2, a third switch S3, a sampling capacitor CSP, and a control circuit CTRL. In this embodiment, the control circuit CTRL is used to control the conduction states of the first switch S1, the second switch S2, and the third switch S3. In this embodiment, the fine-tuning circuit 103 includes an offset voltage adjustment circuit 131 and a data adjustment circuit 132. The first input terminal of the offset voltage adjustment circuit 131 receives the voltage Vout from the output terminal of the resistor circuit. The output terminal of the offset voltage adjustment circuit 131 is coupled to the first input terminal of the buffer amplifier 102, and the second input terminal of the offset voltage adjustment circuit 131 receives data from the data adjustment circuit 132 to adjust the offset voltage.

[0020] As can be seen from the resistor circuit 101 in the above embodiment, this circuit is a segment-type digital-to-analog converter. The worst case of a segment-type digital-to-analog converter usually occurs during the conversion between the two, which in this embodiment is when 255 (b0 to b7 are all equal to logic 1) is converted to 256 (b0 to b7 are all equal to logic 0, and T1 is logic 1). In order to correct for the worst case, in this embodiment, a correction mode is entered. At this time, the input digital data is 255. However, the correction resistor X2R is coupled to the reference voltage Vref. Therefore, the output voltage Vout of node N1, under ideal conditions (all components are error-free), will be equal to the output voltage Vout where T1 is logic 1 and the remaining least significant bits b0 to b7 are all logic 0.

[0021] In this embodiment, the calibration mode is divided into two times, the sampling time as well as the comparison time. At sampling time, the control circuit CTRL controls the above control switch S1, control switch S2, and control switch S3 to be turned on. At this time, the buffer amplifier 102 is used as a buffer. In other words, the voltage at the output of the buffer amplifier 102 will be equal to the voltage at the positive input of the buffer amplifier 102 . In addition, at sampling time, the calibration resistor At this time, the output voltage Vout of the resistor circuit 101 is equivalent to input 256 . At this time, the fine-tuning circuit 103 does not move, so the voltage Vout will be equal to the voltage at the positive input of the buffer amplifier 102 . Also, since the positive input of the buffer amplifier 102 is virtually shorted to the negative input of the buffer amplifier 102 , at this time, the voltage at the negative input of the buffer amplifier 102 is also equal to Vout. Therefore, the sampling capacitor CSP can sample the voltage Vout to the positive input of the buffer amplifier 102 . In order to separate the time of voltage, the voltage sampled by the sampling capacitor CSP here will be expressed in the text Vout[0].

[0022] Next, the calibration mode will enter the comparison time. At the comparison time, the control circuit CTRL controls the first switch S1 to break the circuit, after which the end point of the correction resistor In addition, at this time, the first switch S1 of the calibration switch circuit 104 is controlled and breaks, the second switch S2 as well as the third switch S3 are turned on, and the voltage Vout[0] last sampled by the sampling capacitor CSP is output to the negative input of the buffer amplifier 102. However, the positive input of the buffer amplifier 102 receives the voltage Vout[1] of T1 as the logic

[0023] At this time, those skilled in the art can see that, since the first switch S1 is open, the buffer amplifier 102 is equivalent to a voltage comparator. When the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is greater than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, the output terminal of the buffer amplifier 102 will output a positive saturation voltage; when the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is less than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, the output terminal of the buffer amplifier 102 will output a negative saturation voltage. For ease of explanation, let's assume that the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is greater than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102. At this time, the fine-tuning circuit 103 starts to operate. When the data adjustment circuit 132 of the fine-tuning circuit 103 receives a positive saturation voltage, it will adjust the correction data Dcal output by the data adjustment circuit 132 to a negative direction. At this time, the offset voltage adjustment circuit 131 receives a negative correction data Dcal and will adjust the offset voltage Voffset to a negative voltage. Then, it will continue to receive the voltage at the output terminal of the buffer amplifier 102 and continue to adjust the correction data Dcal and the offset voltage Voffset until the positive saturation voltage turns into a negative saturation voltage. At this time, it means that the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 minus the offset voltage Voffset is very close to the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, which is the voltage sampled last time. Thus, this correction is completed. Afterwards, in normal mode, as long as the data input is 256, the data adjustment circuit 132 of the fine-tuning circuit 103 will directly output the correction data Dcal after the last adjustment, and the offset voltage adjustment circuit 131 will output the corresponding offset voltage Voffset to output correction for this data 256.

[0024] Similarly, suppose the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 is less than the voltage Vout[0] at the negative input terminal of the buffer amplifier 102. At this time, the fine-tuning circuit 103 starts to operate. When the data adjustment circuit 132 of the fine-tuning circuit 103 receives the negative saturation voltage, it will adjust the correction data Dcal output by the data adjustment circuit 132 in the positive direction. At this time, when the offset voltage adjustment circuit 131 receives the positive correction data Dcal, it will adjust the offset voltage Voffset to a positive voltage. Then, it continues to receive the voltage at the output terminal of the buffer amplifier 102 and continues to adjust the correction data Dcal and the offset voltage Voffset until the negative saturation voltage turns into a positive saturation voltage. At this time, it means that the voltage Vout[1] at the positive input terminal of the buffer amplifier 102 plus the offset voltage Voffset is very close to the voltage Vout[0] at the negative input terminal of the buffer amplifier 102, which is the voltage sampled last time. In this way, the correction is completed. Subsequently, in normal mode, as long as the data input is 256, the data adjustment circuit 132 of the fine-tuning circuit 103 will directly output the correction data Dcal after the last adjustment, and the offset voltage adjustment circuit 131 will output the corresponding offset voltage Voffset to correct the output of this data 256.

[0025] As can be seen from the above embodiments, this self-correcting digital-to-analog converter circuit can automatically correct the conversion accuracy during operation by designing the sampling time and comparison time, eliminating circuit offset caused by factors such as process changes, component aging, or mixing of different digital-to-analog converters. Furthermore, although the above embodiments use 255 as an example of the first correction digital value and 256 as an example of the second correction digital value, those skilled in the art should understand that the main principle of this invention is that when the common correction terminal of resistor circuit 101 (i.e., the endpoint of correction resistor X2R) is input with a reference voltage Vref, and the first correction digital value is input to resistor circuit 101, the theoretical value of the output voltage Vout of resistor circuit 101 will be equal to the theoretical value of the output voltage Vout of resistor circuit 101 when the common correction terminal of resistor circuit 101 (i.e., the endpoint of correction resistor X2R) is input with a common voltage Vcom, and the second correction digital value is input to resistor circuit 101. Taking the R-2R resistor ladder circuit of this embodiment as an example, if the first correction bit value is 1 (that is, b0 equals logic 1, and b1 to b7 are all equal to logic 0), and the second correction bit value is 2 (that is, b1 equals logic 1, and b0, b2 to b7 are all equal to logic 0), when a reference voltage Vref is input to the terminal of the former correction resistor X2R, the theoretical value of the output voltage Vout of the resistor circuit 101 will be equal to the common voltage Vcom input to the terminal of the latter correction resistor X2R, and the output voltage Vout of the resistor circuit 101. In other words, if the embodiment is changed to have the first correction bit value as 1 and the second correction bit value as 2, the circuit will still operate normally. Therefore, the present invention is not limited thereto.

[0026] Similarly, while the above embodiments appear to use a segment-type digital-to-analog converter that combines an R-2R resistor ladder circuit and a thermometer-encoded digital-to-analog converter circuit, those skilled in the art should recognize that numerical correction can be performed using either a simple R-2R resistor ladder circuit or a simple thermometer-encoded digital-to-analog converter circuit. This invention is not limited thereto. In other words, as long as the above spirit is met, how the resistor circuit 101 changes is not the focus of this invention, and this invention is not limited to the above circuit.

[0027] From the above embodiments, a calibration method for a digital-to-analog converter can be summarized. Figure 2 illustrates a flowchart of a calibration method for a digital-to-analog converter according to a preferred embodiment of the present invention. Referring to Figure 2, this calibration method for a digital-to-analog converter includes the following steps:

[0028] Step S201: Start.

[0029] Step S202: Provide a buffer amplifier and a resistor circuit.

[0030] Step S203: Divide a calibration time into a sampling time and a comparison time.

[0031] Step S204: Enter sampling time.

[0032] Step S205: Short-circuit the second input terminal of the buffer amplifier with the output terminal of the buffer amplifier.

[0033] Step S206: A first correction digital value is input from the resistor circuit, and a reference voltage is input to the common correction terminal of the resistor circuit, so that the resistor circuit generates a first voltage and outputs it to the first input terminal of the buffer amplifier.

[0034] Step S207: Sample the first voltage from the second input terminal of the buffer amplifier.

[0035] Step S208: Enter the comparison time.

[0036] Step S209: Open the second input terminal of the buffer amplifier with the output terminal of the buffer amplifier. At this time, the buffer amplifier acts as a comparator.

[0037] Step S210: Input a common voltage to the common correction terminal of the resistor circuit, and input a second correction digit value to the resistor circuit, so that the resistor circuit generates a second voltage and outputs it to the first input terminal of the buffer amplifier.

[0038] Step S211: Output the sampled voltage to the second input terminal of the buffer amplifier.

[0039] Step S212: Determine whether the output voltage of the buffer amplifier is the first saturation voltage or the second saturation voltage. If it is determined to be the first saturation voltage, proceed to step S213. If it is determined to be the second saturation voltage, proceed to step S216.

[0040] Step S213: Adjust the correction data using the first direction, and adjust the voltage according to the correction data. For example, if the voltage is a positive saturation voltage as described above, then adjust the correction data using the negative direction.

[0041] Step S214: Determine whether the voltage at the output terminal of the buffer amplifier has switched from the first saturation voltage to the second saturation voltage. If the determination is negative, return to step S213. If the determination is positive, proceed to step S215.

[0042] Step S215: Record the correction data. Record the correction data when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage, and use this data as the correction value corresponding to the second correction bit value.

[0043] Step S216: Adjust the correction data using the second direction, and adjust the voltage according to the correction data. For example, if the voltage is a negative saturation voltage as described above, adjust the correction data using the positive direction.

[0044] Step S217: Determine whether the voltage at the output terminal of the buffer amplifier has switched from the second saturation voltage to the first saturation voltage. If the determination is negative, return to step S216. If the determination is positive, proceed to step S218.

[0045] Step S218: Record the correction data. Record the correction data when the voltage at the output terminal of the buffer amplifier switches from the second saturation voltage to the first saturation voltage, and use this data as the correction value corresponding to the second correction bit value.

[0046] Step S219: End.

[0047] In summary, the self-calibrating digital-to-analog converter circuit proposed in a preferred embodiment of the present invention, through the design of sampling and comparison times, can automatically correct the conversion accuracy during operation, eliminating circuit deviations caused by factors such as process variations, component aging, or the mixing of different digital-to-analog converters, ensuring long-term stable and reliable conversion accuracy. Furthermore, the calibration process requires no external instruments; it can be completed simply by switching the internal circuit connections, making it convenient and cost-effective. At the same time, this circuit retains the structural advantages of traditional resistor-parallel digital-to-analog converters, featuring small size, low power consumption, and good process compatibility. Therefore, the self-calibrating digital-to-analog converter circuit of the preferred embodiment of the present invention has practical value and can be widely applied in analog / digital systems requiring high precision and high reliability, improving overall system performance and product lifespan.

[0048] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereof will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims. [Simplified Explanation of the Diagram]

[0013] The accompanying drawings are provided to enable those skilled in the art to further understand the invention, and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification of the invention to explain the principles of the invention.

[0014] Figure 1 shows a circuit block diagram of a self-correcting digital-to-analog converter circuit according to a preferred embodiment of the present invention.

[0015] Figure 2 is a flowchart illustrating a correction method for a digital-to-analog converter according to a preferred embodiment of the present invention.

Claims

1. A self-correcting digital-to-analog converter circuit, comprising: A resistor circuit includes a plurality of bit input terminals, a reference voltage input terminal, an output terminal, and a common correction terminal, wherein the reference voltage input terminal of the resistor circuit receives a reference voltage; a buffer amplifier includes a first input terminal, a second input terminal, and an output terminal; a fine-tuning circuit includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the fine-tuning circuit is coupled to the output terminal of the resistor circuit, the output terminal of the fine-tuning circuit is coupled to the first input terminal of the buffer amplifier, and the second input terminal of the fine-tuning circuit is coupled to the output terminal of the buffer amplifier; and a correction switching circuit includes a first terminal and a second terminal, wherein the first terminal of the correction switching circuit is coupled to the second input terminal of the buffer amplifier, and the second terminal of the correction switching circuit is coupled to the output terminal of the buffer amplifier, wherein, in normal operation, the common correction terminal of the resistor circuit is input with a common voltage, and the first terminal and the second terminal of the correction switching circuit are short-circuited; The self-calibrating digital-to-analog converter circuit, in a calibration mode, includes: a sampling time: the first and second terminals of the calibration switching circuit are short-circuited, wherein the common calibration terminal of the resistor circuit is input with the reference voltage, and the plurality of bit input terminals of the resistor circuit are input with a first calibration digital value; the first terminal of the calibration switching circuit samples and temporarily stores the voltage at the second input terminal of the buffer amplifier; and a comparison time: the common calibration terminal of the resistor circuit is input with a common voltage, and the plurality of bit input terminals of the resistor circuit are input with a second calibration digital value; the first and second terminals of the calibration switching circuit are open-circuited; the voltage sampled by the first terminal of the calibration switching circuit is output to the second input terminal of the buffer amplifier; wherein, during the comparison time, the fine-tuning circuit adjusts a calibration data, and adjusts the voltage at the output terminal of the fine-tuning circuit according to the calibration data, until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage. The fine-tuning circuit records the correction data when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage, and uses this data as the correction value corresponding to the second correction digit value. When the reference voltage is input to the common correction terminal of the resistor circuit and the first correction digit value is input to the resistor circuit, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. When the common correction terminal of the resistor circuit is input to the common voltage and the second correction digit value is input to the resistor circuit, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. The first theoretical voltage is equal to the second theoretical voltage.

2. The self-correcting digital-to-analog converter circuit according to claim 1, wherein, The resistor circuit includes: an R-2R resistor ladder circuit, comprising: a plurality of switch circuits, each of the plurality of switch circuits including a control terminal, a first terminal, and a second terminal, wherein the first terminal of each of the plurality of switches is coupled to a reference voltage terminal of the resistor circuit to receive the reference voltage, and the control terminals of the plurality of switches are respectively coupled to the plurality of bit input terminals; a plurality of first resistors, each of the plurality of first resistors including a first terminal and a second terminal, wherein the first terminals of the plurality of first resistors are respectively coupled to the second terminals of the plurality of switch circuits; a plurality of second resistors, each of the plurality of second resistors including a first terminal and a second terminal, wherein the first terminal of the Kth second resistor is coupled to the second terminal of the Kth first resistor, and the second terminal of the Kth second resistor is coupled to the second terminal of the (K+1)th first resistor; and a calibration resistor, including a first terminal and a second terminal, wherein the first terminal of the calibration resistor is coupled to a common calibration terminal, and the second terminal of the calibration resistor is coupled to the second terminal of the first first resistor and the first terminal of the first second resistor. Where K is a natural number, and K is greater than 0 and less than the total number of the first resistors.

3. The self-correcting digital-to-analog converter circuit according to claim 2, wherein, The resistor circuit further includes: a thermometer code DAC (thermo DAC) circuit, including an input terminal and an output terminal, wherein the input terminal of the thermometer code DAC circuit is coupled to the second terminal of the Jth first resistor, and the output terminal of the thermometer code DAC circuit is coupled to the first input terminal of the fine-tuning circuit.

4. The self-correcting digital-to-analog converter circuit according to claim 1, wherein, The correction switching circuit further includes: a first switch, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch is coupled to the second input terminal of the buffer amplifier, and the second terminal of the first switch is coupled to the output terminal of the buffer amplifier; a second switch, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the second input terminal of the buffer amplifier; a sampling capacitor, including a first terminal and a second terminal, wherein the first terminal of the sampling capacitor is coupled to the second terminal of the second switch; a third switch, including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the second terminal of the sampling capacitor, and the second terminal of the third switch is coupled to the common voltage; and a control circuit coupled to the control terminals of the first switch, the second switch, and the third switch, wherein during normal operation, the control circuit controls the first switch to be turned on, and the second switch and the third switch to be turned off, wherein during the sampling time, the control circuit controls the first switch, the second switch, and the third switch to be turned on. During the comparison period, the control circuit controls the first switch to turn off, while the second and third switches turn on.

5. The self-correcting digital-to-analog converter circuit according to claim 1, wherein, The fine-tuning circuit includes: an offset voltage adjustment circuit, including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the offset voltage adjustment circuit is coupled to the output terminal of the resistor circuit, and the output terminal of the offset voltage adjustment circuit is coupled to the first input terminal of the buffer amplifier; and a data adjustment circuit, including an input terminal and an output terminal, wherein the input terminal of the data adjustment circuit is coupled to the output terminal of the buffer amplifier, and the output terminal of the data adjustment circuit outputs the correction data to the second input terminal of the offset voltage adjustment circuit, wherein the data adjustment circuit determines the adjustment direction of the correction data according to the first saturation voltage of the output terminal of the buffer amplifier, until the voltage of the output terminal of the buffer amplifier switches to the second saturation voltage.

6. A calibration method for a digital-to-analog converter, comprising: A buffer amplifier and a resistor circuit are provided. A calibration time is divided into a sampling time and a comparison time. During the sampling time: the second input terminal of the buffer amplifier is short-circuited to the output terminal of the buffer amplifier; a first calibration bit value is input to the resistor circuit, and a reference voltage is input to the common calibration terminal of the resistor circuit, causing the resistor circuit to generate a first voltage, which is output to the first input terminal of the buffer amplifier; the first voltage is sampled from the second input terminal of the buffer amplifier. During the comparison time: the second input terminal of the buffer amplifier is open-circuited to the output terminal of the buffer amplifier; a common voltage is input to the common calibration terminal of the resistor circuit, and a second calibration bit value is input to the resistor circuit, causing the resistor circuit to generate a second voltage, which is output to the first input terminal of the buffer amplifier; the sampled voltage is output to the second input terminal of the buffer amplifier. Adjust a calibration data and adjust the voltage according to the calibration data until the voltage at the output terminal of the buffer amplifier switches from a first saturation voltage to a second saturation voltage; and record the calibration data at the time when the voltage at the output terminal of the buffer amplifier switches from the first saturation voltage to the second saturation voltage as the calibration value corresponding to the second calibration digit value. When the reference voltage is input to the common calibration terminal of the resistor circuit and the first calibration digit value is input to the resistor circuit, the ideal voltage at the output terminal of the resistor circuit is a first theoretical voltage. When the common calibration terminal of the resistor circuit is input to the common calibration terminal and the second calibration digit value is input to the resistor circuit, the ideal voltage at the output terminal of the resistor circuit is a second theoretical voltage. The first theoretical voltage is equal to the second theoretical voltage.

7. The correction method for a digital-to-analog converter according to claim 6, wherein, The resistor circuit includes: an R-2R resistor ladder circuit, comprising: a plurality of switch circuits, each of the plurality of switch circuits including a control terminal, a first terminal, and a second terminal, wherein the first terminal of each of the plurality of switches receives the reference voltage, and the control terminals of the plurality of switches are respectively used to receive the first correction digital value and the second correction digital value; a plurality of first resistors, each of the plurality of first resistors including a first terminal and a second terminal, wherein the first terminals of the plurality of first resistors are respectively coupled to the second terminals of the plurality of switch circuits; a plurality of second resistors, each of the plurality of second resistors including a first terminal and a second terminal, wherein the first terminal of the Kth second resistor is coupled to the second terminal of the Kth first resistor, and the second terminal of the Kth second resistor is coupled to the second terminal of the (K+1)th first resistor; and a correction resistor, wherein the correction resistor includes a first terminal and a second terminal, wherein the first terminal of the correction resistor is coupled to the common correction terminal, and the second terminal of the correction resistor is coupled to the second terminal of the first first resistor and the first terminal of the first second resistor. Where K is a natural number, and K is greater than 0 and less than the total number of the first resistors.

8. The correction method for the digital-to-analog converter according to claim 7, wherein, The resistor circuit further includes: a thermometer code DAC (thermo DAC), wherein the thermometer code DAC includes an input terminal and an output terminal, wherein the input terminal of the thermometer code DAC is coupled to the second terminal of the Jth first resistor, and the output terminal of the thermometer code DAC is coupled to the first input terminal of the fine-tuning circuit.

9. The correction method for a digital-to-analog converter according to claim 6, wherein, The first correction digit is 2N - 1, and the second correction digit is 2N, where N is a natural number.

10. The correction method for the digital-to-analog converter according to claim 6 further includes: The direction of adjustment for the correction data is determined based on the polarity of the first saturation voltage.

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