Monolithic multilayered ceramic capacitor

Abstract

A monolithic multilayer ceramic capacitor and electronic device are provided. The monolithic multilayer ceramic capacitor includes a plurality of capacitive coupling elements encapsulated in a continuous ceramic layer. The continuous ceramic layer also includes ceramic separators between adjacent capacitive coupling elements. Each capacitive coupling element includes an active electrode, wherein a first active electrode of an adjacent active electrode of each capacitive coupling element is in electrical contact with a first external terminal, and a second active electrode of an adjacent active electrode of each capacitive coupling element is in electrical contact with a second external terminal.

Description

Technical Field

[0001] The present invention relates to monolithic multilayer ceramic capacitors and electronic devices, and more particularly to a monolithic multilayer ceramic container (MLCC) with improved performance. Prior Art

[0002] Multilayer ceramic capacitors are widely used throughout the electronics industry. Advances in electronic devices, and the increased capabilities they offer, have created a continuous demand for increased functionality and improved volumetric efficiency.

[0003] There is a constant effort to meet the often conflicting demands for increased functionality and improved volume efficiency. One such effort focuses on form factor, where individual MLCCs are assembled into stacks and mounted to a circuit board as stacked units with common leads or as leadless stacks. While advantageous, further miniaturization of MLCCs complicates the assembly process, leading to increased costs and issues related to alignment and bonding integrity between individual MLCCs.

[0004] Despite these advances, there remains a desire for improvements in capacitors, particularly multilayer ceramic capacitors, capacitor assemblies, and electronic assemblies. This document provides significant improvements in the manufacture of monolithic multilayer ceramic capacitors and improved monolithic multilayer ceramic capacitors thereby provided. Also provided herein are improved electronic assemblies that are usable as a result of the improved monolithic multilayer ceramic capacitors. Summary of the Invention

[0005] An object of the present invention is to provide an improved monolithic multilayer ceramic capacitor and an electronic device including the improved monolithic multilayer ceramic capacitor.

[0006] A particular feature of the present invention is that it provides improved volumetric efficiency compared to leaded and leadless stacks, and achieves more capacitance within the available circuit board area in addition to improved physical and electrical performance.

[0007] A particular advantage is the ability to fabricate the improved monolithic multilayer ceramic capacitor using conventional fabrication techniques typically used to form multilayer ceramic capacitors.

[0008] These and other advantages are realized in a monolithic multilayer ceramic capacitor comprising a plurality of capacitive coupling elements encapsulated in a continuous ceramic. The continuous ceramic further comprises a ceramic separator between adjacent capacitive coupling elements. Each capacitive coupling element comprises an active electrode, wherein a first active electrode of an adjacent active electrode of each capacitive coupling element is in electrical contact with a first external terminal, and a second active electrode of an adjacent active electrode of each capacitive coupling element is in electrical contact with a second external terminal.

[0009] Another embodiment is provided in an electronic device including a circuit board, the circuit board including traces. A monolithic multilayer ceramic capacitor is provided, the capacitor including at least one capacitive coupling element, the capacitive coupling element including active electrodes, wherein adjacent active electrodes are in electrical contact with separate external terminals. Each external terminal is on a surface of the monolithic multilayer ceramic capacitor, and each external terminal is in electrical contact with a separate trace. The active electrodes are in at least one parallel stack separated by ceramic, and the active electrodes are perpendicular to the circuit board. Simple diagram description

[0010] FIG. 1 is a schematic top partial cross-sectional view representation of an embodiment of the present invention.

[0011] FIG. 2 is an isolated schematic exploded representation of an embodiment of the present invention.

[0012] FIG3 is a schematic perspective shaded representation of an embodiment of the present invention.

[0013] FIG4 is an electrical schematic diagram of an embodiment of the present invention.

[0014] FIG5 is a schematic diagram of an embodiment of the present invention.

[0015] FIG6 is a schematic diagram of an embodiment of the present invention.

[0016] FIG7 is a schematic cross-sectional representation of an embodiment of the present invention.

[0017] FIG8 is an electrical schematic diagram of an embodiment of the present invention.

[0018] FIG. 9 is a schematic side view representation of an embodiment of the present invention.

[0019] FIG10 is a schematic cross-sectional representation of an embodiment of the present invention.

[0020] FIG. 11 is a schematic cross-sectional representation of an embodiment of the present invention.

[0021] 12 is a schematic perspective, partially cut-away representation of an embodiment of the present invention.

[0022] 13 is a schematic side perspective, partially cut-away representation of an embodiment of the present invention.

[0023] 14 is a schematic side perspective, partially cut-away representation of an embodiment of the present invention.

[0024] FIG15 is a representation of an embodiment of the present invention.

[0025] FIG. 16 is a graphical representation of the advantages provided by embodiments of the present invention.

[0026] FIG. 17 is a graphical representation of the advantages provided by embodiments of the present invention. Implementation Method

[0027] The present invention relates to improved monolithic multilayer ceramic capacitors and improved methods of forming monolithic multilayer ceramic capacitors. More particularly, the present invention relates to improvements in electronic devices resulting from the enhanced performance provided by monolithic multilayer ceramic capacitors.

[0028] More particularly, the present invention relates to monolithic multilayer ceramic capacitors that can provide multiple independent capacitive couplings within a common monolithic body or have a significantly improved aspect ratio relative to the terminals, wherein the improved aspect ratio provides significant improvements to electronic devices formed therewith.

[0029] The present invention will be described with reference to the accompanying drawings, which are an integral part of the description provided for the clarity of the present invention, but are not intended to be limiting. In the various drawings, similar elements will be numbered accordingly.

[0030] An embodiment of the present invention will be described with reference to FIG1 . In FIG1 , a laminate 10 is schematically shown in a top, partial cross-sectional view. The laminate is formed as alternating layers including active electrodes 12, wherein adjacent electrodes in capacitive couplings 16 are parallel and offset, as will be further described herein. Ceramic 14 is positioned between adjacent electrodes of the capacitive couplings and between the capacitive couplings, as will be more fully described herein. Cut line 20 separates a 2-C monolithic body including two capacitive couplings 16 from a ceramic dielectric separator 14 between the 2-C monolithic bodies, as will be more fully understood from further discussion. Cut line 22 separates an n-C monolithic body including n capacitive couplings 16 from a ceramic dielectric separator 14 therebetween, where n is the number of capacitive couplings in the monolithic body, as will be more fully understood from further discussion, where n is an integer from 0 to 20, more preferably from 0 to 15, even more preferably from 0 to 10, and even more preferably from 0 to 5, with 0 or 1 being most preferred. As will be implemented, a value of n from 0 to 20 represents 22 capacitive coupling elements, where alternative expressions for the value of n are the number of capacitive coupling elements greater than 2. For purposes of discussion and clarification, the term "nC monolithic body" refers to a continuous monolithic body having n capacitive coupling elements. As will be implemented, the active electrode of each capacitive coupling element is coplanar with the active electrode of an adjacent capacitive coupling element. More preferably, each active electrode of a capacitive coupling element is coplanar with the active electrode of each additional capacitive coupling element.

[0031] For clarity, a portion of a single capacitive coupling is shown in an isolated schematic exploded view in FIG2 . In FIG2 , each layer 24 comprises a ceramic 14 on which an active electrode 12 is formed, as is known in the art. These layers are stacked with alternating active electrodes offset so that the alternating active electrodes terminate at opposing cut lines 20. Cutting, dicing, or separation at the cut lines exposes adjacent active electrodes, as is well known to those skilled in the art. External terminals are formed on the sides that make electrical contact with the active electrodes, thereby forming a multilayer ceramic capacitor, as is known in the art. While a limited number of layers is shown in the figure for clarity, the actual number may be considerably larger. Those skilled in the art will recognize that at least two layers are required to form a capacitive coupling, and in practice, hundreds of layers are used.

[0032] An embodiment of the present invention will be described with reference to FIG3 , in which a 2-C monolithic body, shown in a schematic perspective shaded view, is shown as a monolithic body without external terminals. The 2-C monolithic body of FIG3 represents a monolithic body obtained by separation along cut line 20 of FIG1 . In FIG3 , two capacitive couplings 26 are formed by separate stacks of active electrodes 12, with ceramic between alternating active electrodes and extending to opposing faces 28 where external terminals will be formed. Capacitive couplings 26 are separated by ceramic, so that the complete capacitor is represented by the electrical schematic diagram of FIG4 .

[0033] Embodiments of the present invention will be described with reference to Figures 5 and 6. Figure 5 illustrates a representative embodiment as a 2-C monolithic body, including two capacitive couplings, as further described herein. Figure 6 illustrates a representative embodiment as a 3-C monolithic body, as further described herein. For ease of illustration and discussion, the monoliths in Figures 5 and 6 are unterminated. In Figure 5, a 2-C monolithic body 30 is schematically illustrated, wherein the 2-C monolithic body includes two capacitive couplings 26, each of which includes internal electrodes 12, with a ceramic separator 34 formed between the internal electrodes 12. As can be appreciated from Figure 1, the ceramic separator is a ceramic portion between adjacent stacks. In Figure 6, a 3-C monolithic body 32 is schematically illustrated, wherein the 3-C monolithic body includes three capacitive couplings 26, each of which includes internal electrodes 12, with a ceramic separator 34 between adjacent capacitive couplings. The collection of capacitive coupling elements is surrounded by a continuous ceramic dielectric box comprising a first side 36, a second side 38 parallel to the first side, a top 40 perpendicular to and continuous with the first and second sides, and a bottom 42 parallel to the top and perpendicular to and continuous with the first and second sides. The face 28 showing the alternating exposed electrodes is free of ceramic covering. It will be appreciated that the opposing face is identical to the visible face, except for the exposed alternating adjacent electrodes. The ceramic of the monolithic multilayer ceramic capacitor is continuous, which is defined herein to indicate that the individually formed ceramics are free of dislocations or bonds. The entire ceramic surrounding the capacitive coupling elements is preferably formed from a continuous ceramic precursor.

[0034] An embodiment of the present invention will be described in the cross-sectional schematic diagram of FIG7 . In FIG7 , each stack of bias-shifted active electrodes 12 forms a capacitive coupling element 26 . A top portion 40 and a bottom portion 42 enclose the capacitive coupling element, and a ceramic separator 34 electrically isolates the capacitive coupling element. External terminals 44 on each exposed side 28 of the monolithic piece provide electrical conductivity to the capacitive coupling element to the circuit. It will be appreciated that each external terminal electrically contacts an alternating active electrode and therefore has opposite polarity, thereby producing a monolithic multilayer ceramic capacitor 46 comprising n individual capacitive coupling elements encapsulated in a common continuous ceramic with ceramic separators between adjacent capacitive coupling elements, wherein the ceramic insulator is continuous with the encapsulating ceramic represented by the top portion 40, the bottom portion 42, and the sides not visible in this view. The monolithic multilayer ceramic capacitor 46 of FIG7 will have n capacitive coupling elements, where n is an integer from 0 to 10, more preferably 0 to 5, and most preferably 0 or 1. For non-limiting purposes, when n is 0, the monolithic multilayer ceramic capacitor is a 2-C monolithic body, and when n is 1, the monolithic multilayer ceramic capacitor is a 3-C monolithic body. The monolithic multilayer ceramic capacitor of FIG. 7 would have the electrical schematic shown in FIG.

[0035] A particular feature of the monolithic multilayer ceramic capacitor of the present invention is the ability to mount the device with all active electrodes perpendicular to the substrate. An embodiment of the present invention will be described with reference to FIG. 9 , which shows a monolithic multilayer ceramic capacitor 46 mounted to a circuit board 52. As will be appreciated from the description herein, the monolithic multilayer ceramic capacitor, representing a nC monolithic body, has external terminals 44, as discussed above. Each external terminal is in electrical contact with a trace 48, which is preferably attached via solder fillet 50 or a similar attachment method. As shown in FIG. 7 , it will be appreciated that the active electrodes can all be perpendicular to the circuit board. Advantages of mounting a monolithic multilayer ceramic capacitor with active electrodes perpendicular to the circuit board include lower ESR, which results in less heating during use with alternating current (AC) applications. Mounting a monolithic multilayer ceramic capacitor with active electrodes perpendicular to the circuit board also results in lower ESL, resulting in less inductive losses.

[0036] The monolithic multilayer ceramic capacitor of the present invention is compatible with other MLCC technologies, including shielded electrodes and floating electrodes.

[0037] An embodiment of the present invention will be described with reference to FIG10 , which illustrates a schematic cross-sectional view of a monolithic multilayer ceramic capacitor. In FIG10 , a monolithic multilayer ceramic capacitor 46 includes active electrodes 12 with ceramic 14 serving as a dielectric between internal electrodes. A shield electrode 54 is illustrated, where a shield electrode is defined as a coplanar active electrode of opposite polarity positioned as the outermost internal electrode in the monolith. The shield electrode electrically contacts the external terminals and suppresses arcing from the external terminals to the active electrode of opposite polarity. The shield electrode does not significantly contribute to capacitance and preferably spans the length of the monolith, from a first side to a second side, as defined herein.

[0038] An embodiment of the present invention will be described with reference to FIG11 , which illustrates a schematic cross-sectional view of a monolithic multilayer ceramic capacitor. In FIG11 , a monolithic multilayer ceramic capacitor 46 includes coplanar active electrodes 12 of opposite polarity to floating electrodes 56 in a plane parallel to the coplanar active internal electrodes. Preferably, each floating electrode has coplanar active internal electrodes adjacent to each side. Ceramic 14 between adjacent electrodes serves as a dielectric. Active electrodes are defined herein as internal electrodes that are in electrical contact with external terminals. Floating electrodes are internal electrodes that are not in electrical contact with external terminals. The floating electrodes are located within a capacitive coupling element.

[0039] Compared to stacked MLCCs, monolithic nCs offer a particular advantage in terms of improved volumetric efficiency and higher capacitance per unit area. Eliminating the need for wires to connect multiple capacitors together, or forming a leadless stack, eliminates individual failure modes. Many failure modes of stacked capacitors, whether using wires or leadless, are due to thermal or mechanical stress-induced bond failure. This invention avoids the need for bonding between discrete capacitors.

[0040] An embodiment of the present invention will be described with reference to FIG12 . In FIG12 , a monolithic multilayer ceramic capacitor 60 is shown in a schematic, partially cutaway perspective view. The monolithic capacitor has a length L, a height H, and a thickness T, wherein, when assembled in a circuit board, the ratios L / T ≥ 1, L / H ≥ 1, and T / H are at least 0.3 and no greater than 0.9, as shown in FIG13 . In FIG12 , it can be appreciated that dielectric 64 is located between adjacent electrodes. The thickness T of the capacitor is not necessarily limiting but is highlighted for purposes of orientation and discussion. Adjacent active electrodes 62 and 63 terminate at opposing faces, such that alternating electrodes are in electrical contact with opposing external terminals 66.

[0041] The advantages of the embodiment shown in FIG12 will be discussed with reference to FIG13. In FIG13, a monolithic multilayer ceramic capacitor 60 is shown in electrical contact with circuit traces 68 on a circuit board 70, for example, via solder fillets 72. The circuit board is integrated into an electronic device 74, wherein the traces are preferably coplanar. As described above, by mounting a monolithic multilayer ceramic capacitor to a circuit board with active electrodes perpendicular to the circuit board, several advantages are achieved. Mounting a monolithic multilayer ceramic capacitor to a circuit board with active electrodes perpendicular to the circuit board is contrary to the prior art, which believed that it was necessary to maximize the amount of external terminal surface area in electrical contact with the circuit board to minimize ESR and ESL. By minimizing ESR, lower AC ripple current heating can be achieved because power dissipation P = 1²ESR, and lower ESL reduces circuit resonance issues.

[0042] Embodiments of the present invention will be described with reference to Figures 14 and 15. In Figure 14, a monolithic multilayer ceramic capacitor 78 is illustrated as being in electrical contact with circuit traces 68 on a circuit board 70, for example, via solder fillets 72. A partial external termination 82 is shown, where a partial external termination is defined as an external termination that does not extend the length L of the monolithic chip. Partial external terminations are advantageous because they mitigate the risk of arcing from the top portion of the monolithic multilayer ceramic capacitor to the secondary components. A particular advantage of using partial external terminations is the ability to use active electrodes 76 including tabs 80 that extend outside the monolithic chip. It will be appreciated that adjacent tabs are oriented so that the tabs extend in opposite directions.

[0043] The ceramic surrounding the collection of capacitive couplings and the separators between adjacent capacitive couplings has a sufficient thickness to prevent current flow between adjacent capacitive couplings or arcing between electrodes of the capacitive couplings and external components. More specifically, the ceramic surrounding the collection of capacitive couplings and the separators is thicker than the distance between adjacent parallel electrodes in adjacent capacitive couplings, and more preferably at least twice the distance between adjacent parallel electrodes in the capacitive couplings.

[0044] Multilayer ceramic capacitors (MLCCs) are formed by alternating thin layers of ceramic insulator electrodes of opposite polarity and sintering them together to produce a monolithic component. The layering process requires the ceramic and electrodes to be suspended in an organic dielectric. Typically, the ceramic and metal layers are alternately cast using one of a variety of techniques to form a monolithic piece, which is first heated to remove volatiles and then sintered into a single piece.

[0045] MLCCs are made by layering ceramic precursors and conductor precursors in a properly registered order as known in the art. After a sufficient number of layers have been built up, the assembly is heated to form alternating layers of internal conductor and sintered ceramic.

[0046] There are no specific limitations on the ceramic material used as the dielectric herein. Suitable materials for the monolithic ceramic capacitors are Pb-free and include at least 92% by weight of barium, calcium, strontium, magnesium, potassium or sodium titanate, zirconate, niobate, or tantalate, and combinations thereof. Dielectrics that meet the EIA temperature coefficients specified for the capacitance design of C0G, U2J, X8G, X9G, X7R, X5R, X6S, X7T, or X8R capacitors are particularly well-suited for use in the demonstration of this invention due to their widespread use in the manufacture of MLCCs.

[0047] Each dielectric layer preferably has a thickness of up to about 50 µm, more preferably up to about 20 µm. The lower limit of the thickness is about 0.5 µm, preferably about 2 µm. The number of stacked dielectric layers and active layers is typically between 2 and about 2000, preferably between 2 and about 450.

[0048] The conductors forming the internal electrode layers are not limited herein, although base metals are preferably used because the dielectric materials of commonly used dielectric layers generally have anti-reduction properties. Typical base metals are nickel and nickel alloys. Preferred nickel alloys are alloys of nickel with at least one of Mn, Cr, Co, Al, W, Mo, Sn, and Nb, with nickel alloys containing at least 95% by weight nickel being more preferred. It should be noted that nickel and nickel alloys may contain up to about 0.1% by weight of phosphorus and other trace elements. Other conductors that can be used as internal electrodes include copper, precious metals, or alloys thereof, with particularly preferred precious metals selected from palladium, silver, platinum, and gold. It should be understood that for internal electrodes containing copper or precious metals, lower firing temperatures are preferred.

[0049] The thickness of the internal electrode layer can be appropriately determined according to the specific purpose and application, but the upper limit is generally about 25 μm, more preferably about 2.5 μm, and the lower limit is generally about 0.5 μm. A thickness of about 1 μm is most preferred.

[0050] The conductor forming the external terminal is not particularly limited, although inexpensive metals such as nickel, copper, and their alloys are preferred. The thickness of the external terminal can be appropriately determined depending on the specific use and application, but it is generally in the range of about 10 µm to about 50 µm. In one embodiment, a conductive metal (preferably silver)-filled epoxy terminal is used as the terminal.

[0051] The multilayer ceramic chip capacitors of the present invention are typically manufactured using a conventional printing and sheeting method using a slurry to form a green chip. After firing and separating the chip or monolithic sheet, the external terminals, also known as external electrodes, are formed by printing or transferring a precursor for the external terminals onto the surface, contacting the internal electrodes terminated at the surface, and then baking.

[0052] The slurry for forming the dielectric layer can be obtained by mixing a raw dielectric material with an organic vehicle. The raw dielectric material can be a mixture of oxides and complex oxides. Also useful are various compounds that convert to such oxides and complex oxides upon firing. These compounds include, for example, carbonates, oxalates, nitrates, hydroxides, and organometallic compounds. The dielectric material is obtained by selecting appropriate species from these oxides and compounds and mixing them. The proportion of such compounds in the raw dielectric material is determined so that a specific dielectric layer composition is achieved after firing. The raw dielectric material is typically used in powder form, with an average particle size of about 0.1 to about 3 µm, preferably about 0.5 µm.

[0053] The paste for forming the internal electrode layer is obtained by mixing a conductive material with an organic vehicle. The conductive material used herein includes conductors, such as the conductive metals and alloys described above, as well as various compounds that convert to such conductors upon firing, such as oxides, organometallic compounds, and resinates. The binder used herein is not critical and can be appropriately selected from conventional binders, such as ethyl cellulose. In addition, the organic solvent used herein is not critical and can be appropriately selected from conventional organic solvents, such as terpineol, butyl carbinol, acetone, and toluene, depending on the specific application method, such as printing or sheeting.

[0054] The paste used to form the external electrodes (also called external terminals) is prepared by the same method as the internal electrodes (also called active electrodes) to form a layer of paste.

[0055] There are no specific restrictions on the organic vehicle content of each slurry. The slurry typically contains approximately 1 to 5 wt% of a binder and approximately 10 to 50 wt% of an organic solvent. If desired, the slurry may contain any additional additives, such as dispersants, plasticizers, dielectric compounds, and insulating compounds. The total content of these additives preferably reaches approximately 10 wt%.

[0056] Green wafers can be produced from a paste forming a dielectric layer and a paste forming an internal electrode layer. In the case of a printing method, for example, the green wafer is produced by alternately printing the paste onto a polyethylene terephthalate (PET) substrate to form a layered stack, cutting the layered stack into a predetermined shape, and separating it from the substrate.

[0057] A sheet method is also useful, in which a green sheet is formed from a paste forming a dielectric layer, a paste forming an internal electrode layer is printed on each green sheet, and the printed green sheets are stacked to produce a green wafer. As is known in the art, capacitors having a large number of layers can be produced in this manner.

[0058] The method of forming the capacitor is not particularly limited herein.

[0059] The binder is removed from the green wafer and fired. Binder removal can be performed under conventional conditions, preferably when the internal electrode layers are formed from base metal conductors such as nickel and nickel alloys.

[0060] For binder removal, the heating rate is preferably approximately 5 to 300°C / hour, more preferably 10 to 100°C / hour. The holding temperature is preferably approximately 200 to 400°C, more preferably 250 to 300°C, and the holding time in air is preferably approximately 1 / 2 to 24 hours, more preferably 5 to 20 hours. An inert or reducing atmosphere may be provided at temperatures exceeding 225°C to limit oxidation of the internal electrodes. The green wafer is fired in an atmosphere that can be determined based on the type of conductor in the paste forming the internal electrode layer. When the internal electrode layer is formed from a base metal conductor such as nickel and nickel alloys, the firing atmosphere can have an oxygen partial pressure of 10-8 to 10-12 atm. Extremely low oxygen partial pressures should be avoided, as at such low pressures, the conductor may be abnormally sintered and may become disconnected from the dielectric layer. At oxygen partial pressures above this range, the internal electrode layer may oxidize.

[0061] For firing, the wafer is preferably held at a temperature of 1100°C to 1400°C, more preferably 1250°C to 1400°C. Lower hold temperatures below this range will provide insufficient densification, while higher hold temperatures above this range may result in poor DC bias performance. The heating rate is preferably 50 to 500°C / hour, more preferably 200 to 300°C / hour, with a hold time of 1 / 2 to 8 hours, more preferably 1 to 3 hours. The cooling rate is preferably 50 to 500°C / hour, more preferably 200 to 300°C / hour. The firing atmosphere is preferably a reducing atmosphere. An exemplary atmospheric gas is a humidified mixture of N2 and H2 gases.

[0062] Annealing is preferably performed after firing the capacitor wafer in a reducing atmosphere. Annealing is effective for reoxidizing the dielectric layer, thereby optimizing the ceramic's resistance to dielectric breakdown. The annealing atmosphere can have an oxygen partial pressure of at least 10-6 atm, preferably 10-5 to 10-4 atm. The dielectric layer may not reoxidize sufficiently at low oxygen partial pressures below this range, while the internal electrode layers may be oxidized at oxygen partial pressures above this range.

[0063] For annealing, the wafer is preferably held at a temperature below 1100°C, more preferably between 500°C and 1000°C. Lower hold temperatures below this range will oxidize the dielectric layer to a lesser extent, resulting in a shorter lifetime. Higher hold temperatures above this range can cause oxidation of the internal electrode layer, which reduces capacitance and reacts with the dielectric material, resulting in a shorter lifetime. Annealing can be accomplished simply by heating and cooling. In this case, the hold temperature is equal to the highest temperature during heating, and the hold time is zero.

[0064] Binder removal, firing, and annealing can be performed sequentially or separately. If performed sequentially, the process includes the following steps: binder removal, changing the atmosphere without cooling, raising the temperature to the firing temperature, holding the wafer at that temperature for firing, lowering the temperature to the annealing temperature, changing the atmosphere to that temperature, and annealing.

[0065] If performed separately, after binder removal and cooling, the wafer temperature is raised to the binder removal temperature in dry or humid nitrogen. The atmosphere is then changed to a reducing atmosphere and the temperature is further increased for firing. The temperature is then lowered to the annealing temperature, the atmosphere is again changed to dry or humid nitrogen, and cooling continues. Alternatively, once cooled, the temperature can be raised to the annealing temperature in a nitrogen atmosphere. The entire annealing step can be performed in a humid nitrogen atmosphere.

[0066] For example, before printing or transferring and baking the external electrode forming paste to form the external electrodes, the resulting wafer may be polished at the end surface by barrel tumbling and sandblasting. The external electrode forming paste may be fired in an inert nitrogen atmosphere at about 600° C. to 800° C. for about 10 minutes to about 1 hour.

[0067] After the monolithic sintering, connections must be made to the internal electrodes by applying a termination material (usually a thick film paste) followed by an additional sintering step to contact the internal electrodes of the MLCC. This sintering step can be detrimental to the ceramic and / or internal conductors.

[0068] The external terminals are preferably formed by dipping or other methods such as inkjet coating where applicable. Once deposited, these external terminals are sintered or cured to adhere them to the ceramic and connect them to the internal electrodes.

[0069] MLCCs can be overmolded with non-conductive polymers or resins. The materials used for overmolding are not specifically limited herein. Overmolding can be performed to isolate the MLCC from electrical interactions with other components of a circuit or to protect the package or its components from environmental changes. Overmolding can also facilitate labeling and use with pick-and-place equipment, as overmolding can be applied to specific geometries that can be discerned by optical or mechanical equipment.

[0070] [Example]

[0071] The 2-C and 3-C monolithic bodies of the present invention were fabricated with 4.7μF, 50V ceramic capacitor couplings. Comparative multilayer ceramic capacitors were formed in the same manner, followed by forming either two capacitors stacked without leads or three capacitors stacked without leads, as described in U.S. Patent No. 11,227,719. The equivalent series resistance (ESR) of the present invention and comparative capacitors was measured as a function of frequency, with the results shown in Figure 16 for two capacitor couplings and Figure 17 for three capacitor couplings. In each case, the present invention capacitors demonstrated improved ESR as a function of frequency. In addition to the improved ESR, the present invention capacitors also demonstrated improved equivalent series inductance (ESL). For the example with two capacitor couplings, the present invention example had an ESL of 204 pH, compared to 237 pH for the comparative example. For the example with three capacitor couplings, the present invention example had an ESL of 208 pH, compared to 224 pH for the comparative example.

[0072] The present invention has been described with reference to preferred embodiments, but is not limited thereto. Additional embodiments will be realized by those skilled in the art as described and illustrated in the appended claims.

[0073] 10: Laminate 12,12 1~12 n: active electrode 14: Ceramic dielectric separator 16: Capacitive coupling 20: Cutting line 24: Layer 26,26 1~26 n: Capacitive coupling 28: Noodles 30:2-C monolithic body 32:3-C monolithic body 34: Ceramic separator 36: First side 38: Second side 40: Top 42: bottom 44:External terminal 46: Ceramic capacitors 48: trace 50:Solder fillet 52: Circuit board 54: Mask electrode 56: floating electrode 60: Monolithic multilayer ceramic capacitors 62: Active electrode 63: Active electrode 64: Dielectric 66:External terminal 68: Circuit traces 70: Circuit board 72:Solder fillet 74: Electronic devices 76: Active electrode 78: Monolithic multilayer ceramic capacitors 80: Lug 82:External terminal

Claims

1. A monolithic multilayer ceramic capacitor comprising 3 to 22 parallel and offset capacitive coupling elements encapsulated in a continuous ceramic layer, wherein, The continuous ceramic also includes a ceramic separator between adjacent capacitive couplers; wherein each capacitive coupler includes an active electrode, wherein a first active electrode of an adjacent active electrode of each capacitive coupler is in electrical contact with a first external terminal, and a second active electrode of an adjacent active electrode of each capacitive coupler is in electrical contact with a second external terminal.

2. The monolithic multilayer ceramic capacitor as claimed in claim 1, comprising 3 to 17 of the said capacitive coupling elements.

3. The monolithic multilayer ceramic capacitor as claimed in claim 2, comprising 3 to 12 of the said capacitive coupling elements.

4. The monolithic multilayer ceramic capacitor as claimed in claim 3, comprising 3 to 10 of the said capacitive coupling elements.

5. The monolithic multilayer ceramic capacitor as claimed in claim 4, comprising 3 to 7 of the said capacitive coupling elements.

6. The monolithic multilayer ceramic capacitor as claimed in claim 1, wherein, Each of the capacitive couplers includes adjacent parallel active electrodes.

7. The monolithic multilayer ceramic capacitor as claimed in claim 6, wherein, The adjacent parallel active electrodes of adjacent capacitive couplers are coplanar.

8. The monolithic multilayer ceramic capacitor as claimed in claim 6, wherein, The adjacent parallel active electrodes are located in an alternating layer.

9. The monolithic multilayer ceramic capacitor as claimed in claim 6, wherein, The adjacent parallel active electrodes are located in a coplanar layer.

10. The monolithic multilayer ceramic capacitor as claimed in claim 9, further comprising floating electrodes located between the coplanar layers.

11. The monolithic multilayer ceramic capacitor as claimed in claim 1, further comprising at least one shielding electrode.

12. The monolithic multilayer ceramic capacitor as claimed in claim 1, wherein, The ceramic comprises at least 92% by weight barium, calcium, strontium, magnesium, potassium titanate or sodium titanate, zirconate, niobate or tantalate, and combinations thereof.

13. The monolithic multilayer ceramic capacitor as claimed in claim 1, wherein, The ceramic is selected from C0G, U2J, X8G, X9G, X7R, X5R, X7S, X7T and X8R.

14. The monolithic multilayer ceramic capacitor as claimed in claim 1, wherein, The active electrode comprises a material selected from base metals and noble metals.

15. The monolithic multilayer ceramic capacitor as claimed in claim 14, wherein, The active electrode comprises a material selected from nickel, copper, palladium, silver, platinum, and gold.

16. The monolithic multilayer ceramic capacitor as claimed in claim 15, wherein, The material is a nickel alloy, which includes at least one selected from Mn, Cr, Co, Al, W, Mo, Sn and Nb.

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