High electron mobility transistor

Abstract

This invention relates to a high electron mobility transistor, comprising a substrate, a barrier layer, a semiconductor layer, and an intermediate layer. The barrier layer is disposed on the substrate and comprises aluminum gallium indium nitride (AIGaIn). The semiconductor layer is disposed between the substrate and the barrier layer. The intermediate layer is disposed between the semiconductor layer and the barrier layer and comprises AIGaIn.

Description

[Technical Field]

[0001] This invention relates to a high electron mobility transistor, and more particularly to a gallium nitride high electron mobility transistor. [Previous Technology]

[0002] High electron mobility transistors (HEMTs) have gradually gained attention in recent years. They have advantages such as fast switching speed, high electron mobility, high breakdown electric field, good thermal stability and wide bandgap, and can be applied to high voltage electronic components or high frequency electronic components.

[0003] Current high electron mobility transistor systems use gallium nitride as the channel layer, and form ternary or quaternary barrier layers on the channel layer. However, due to problems such as lattice mismatch between the barrier layer and the channel layer and differences in growth temperature, epitaxial quality is often deteriorated and leakage current is increased, which in turn affects the performance of the transistor.

[0004] Therefore, in order to meet the future application of radio frequency power devices, it is urgent to propose an improved high electron mobility transistor to further improve device current and output power, and eliminate or mitigate the above problems. [Summary of the Invention]

[0005] The high electron mobility transistor system of the present invention comprises an intermediate layer between the barrier layer and the channel layer of the semiconductor layer, and the intermediate layer comprises aluminum gallium nitride material. This intermediate layer acts as an intermediary, thereby improving lattice matching or enhancing the quality of the barrier layer, resulting in a smoother interface and enhanced structural integrity. Furthermore, the intermediate layer significantly improves surface roughness, electron mobility, polarization of the two-dimensional electron gas (2DEG), or reduces leakage current, thus significantly enhancing the performance of the high electron mobility transistor.

[0006] In view of this, according to one aspect of the present invention, a high electron mobility transistor is provided, comprising a substrate, a barrier layer, a semiconductor layer, and an intermediate layer. The barrier layer is disposed on the substrate and comprises aluminum gallium indium nitride. The semiconductor layer is disposed between the substrate and the barrier layer. The intermediate layer is disposed between the semiconductor layer and the barrier layer and comprises aluminum gallium nitride.

[0007] In this invention, the substrate may be a quartz substrate, a glass substrate, a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, or a combination thereof, for example, the substrate is a silicon substrate.

[0008] In this invention, the aluminum gallium indium nitride material can be In 1-x-yAl xGa yN, where x can be in the range of 0.1 to 0.8 and y can be in the range of 0.8 to 0.1.

[0009] In this invention, the thickness of the barrier layer may be between 3 nm and 40 nm, for example, between 3 nm and 35 nm, between 3 nm and 30 nm, between 3 nm and 25 nm, between 3 nm and 20 nm, between 3 nm and 15 nm, between 3 nm and 10 nm, between 5 nm and 40 nm, between 5 nm and 35 nm, between 5 nm and 30 nm, between 5 nm and 20 nm, between 5 nm and 15 nm, or approximately 6 nm.

[0010] In this invention, the semiconductor layer may include a nucleation layer, a buffer layer, and a gallium nitride layer. The gallium nitride layer may be disposed on the nucleation layer, and the buffer layer may be disposed between the nucleation layer and the gallium nitride layer. The nucleation layer may include aluminum nitride material, and the buffer layer may include aluminum gallium nitride material and gallium nitride material. Furthermore, the thickness of the nucleation layer may be between 50 nm and 300 nm, for example, between 50 nm and 250 nm, between 50 nm and 200 nm, between 50 nm and 150 nm, or approximately 100 nm; the thickness of the buffer layer may be between 50 nm and 5000 nm, for example, between 50 nm and 4000 nm, between 50 nm and 3000 nm, between 50 nm and 2000 nm, approximately 200 nm, or approximately 2500 nm.

[0011] In this invention, the thickness of the intermediate layer may be between 1 nm and 15 nm, for example, between 1 nm and 12 nm, between 1 nm and 10 nm, between 1 nm and 8 nm, between 1 nm and 5 nm, between 1 nm and 3 nm, about 1 nm, or about 2 nm.

[0012] In this invention, the aluminum gallium nitride material may be Al zGa 1-zN, and z may be in the range of 0.1 to 0.8, for example, z is in the range of 0.1 to 0.7, z is in the range of 0.1 to 0.6, z is in the range of 0.1 to 0.5, z is in the range of 0.1 to 0.4, z is in the range of 0.1 to 0.3, z is in the range of 0.2 to 0.7, z is in the range of 0.2 to 0.6, z is in the range of 0.2 to 0.5, z is in the range of 0.2 to 0.4, z is about 0.15, or z is about 0.22.

[0013] In this invention, the high electron mobility transistor may further include a passivation layer disposed on the barrier layer. The passivation layer may include a silicon nitride material.

[0014] In this invention, the high electron mobility transistor may further include a drain, a source, and a gate, wherein the drain and the source may be disposed on a barrier layer, and the gate may be disposed on a passivation layer.

[0015] In this invention, the materials of the drain, source, and gate may be copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, copper alloy, aluminum alloy, molybdenum alloy, tungsten alloy, gold alloy, chromium alloy, nickel alloy, platinum alloy, titanium alloy, other suitable metals, or combinations thereof, and the drain, source, and gate may be single-layer or multi-layer metal layers.

[0016] Other objects, advantages and novel features of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings.

Implementation Method

[0018] The following provides different embodiments of the present invention. These embodiments are used to illustrate the technical content of the present invention, and are not intended to limit the scope of the present invention. A feature of one embodiment may be applied to other embodiments through suitable modifications, substitutions, combinations, or separations.

[0019] It should be noted that, unless otherwise specified herein, having "a" element is not limited to having a single element, but may include one or more elements.

[0020] Furthermore, in this document, the terms “up,” “down,” “left,” “right,” “front,” “back,” or “between” are used only to describe the relative positions between multiple elements and can be extended to include translation, rotation, or mirroring.

[0021] In addition, unless otherwise specified herein, the phrase "one element on another element" or similar statements do not necessarily indicate that the element is in contact with the other element.

[0022] Furthermore, unless otherwise specified herein, a numerical value may cover a range of ±10% of the value, and in particular a range of ±5% of the value. Unless otherwise specified, a numerical range consists of multiple subranges defined by the smaller endpoint, the smaller quartile, the median, the larger quartile, and the larger endpoint.

[0023] Example 1

[0024] Figure 1 shows a schematic diagram of the high electron mobility transistor of Embodiment 1 of the present invention.

[0025] As shown in Figure 1, the high electron mobility transistor 100 of this embodiment includes a substrate 1, a barrier layer 2, a semiconductor layer 3, an intermediate layer 4, a passivation layer 5, a drain 61, a source 62, and a gate 63. The barrier layer 2 is disposed on the substrate 1 and includes aluminum gallium indium nitride (AIGaIn) material. The semiconductor layer 3 is disposed between the substrate 1 and the barrier layer 2 and includes a nucleation layer 31, a buffer layer 32, and a gallium nitride layer 33. The gallium nitride layer 33 is disposed on the nucleation layer 31, and the buffer layer 32 is disposed between the nucleation layer 31 and the gallium nitride layer 33. The nucleation layer 31 includes aluminum nitride material. The intermediate layer 4 is disposed between the semiconductor layer 3 and the barrier layer 2, and the intermediate layer 4 includes aluminum gallium nitride material. Furthermore, the passivation layer 5 is disposed on the barrier layer 2 and includes silicon nitride material. The drain 61 and the source 62 are disposed on the barrier layer 2, and the gate 63 is disposed on the passivation layer 5.

[0026] The method for fabricating the high electron mobility transistor 100 in this embodiment includes the following steps: providing a silicon substrate 1, and sequentially growing a 100 nm AlN nucleation layer 31, a buffer layer 32 including 200 nm Al 0.15Ga 0.85N and 2.5 µm carbon-doped GaN, and a 500 nm GaN gallium nitride layer 33 on the silicon substrate 1 by metal-organic chemical vapor deposition (MOCVD) to form a semiconductor layer 3. Next, a 2 nm Al 0.15Ga 0.85N intermediate layer 4 and a 6 nm In 0.04Al 0.66Ga 0.3N barrier layer 2 are sequentially formed on the semiconductor layer 3. A 200 Å Ti / 1200 Å Al / 250 Å Ni / 1000 Å Au metal layer, serving as drain 61 and source 62, was deposited on barrier layer 2 using an electron gun. After removing the remaining portion, the layer was annealed in a nitrogen atmosphere at 820 °C. A 25 nm SiN passivation layer 5 was then deposited using atomic layer deposition (ALD) and rapidly thermally annealed (RTA) at 300 °C. Subsequently, a 500 Å Ni / 3000 Å Au metal layer was deposited as gate 63 using an electron gun. Finally, etching was performed using chlorine inductively coupled plasma (ICP) to obtain a high electron mobility transistor 100. The gate linewidth Lg is 2 µm, the gate-source distance Lgs is 3 µm, and the gate-drain distance Lgd is 5 µm.

[0027] Example 2

[0028] This embodiment is similar to Embodiment 1, except that the intermediate layer 4 in this embodiment is 4 nm Al 0.15Ga 0.85N.

[0029] Example 3

[0030] This embodiment is similar to Embodiment 1, except that the intermediate layer 4 in this embodiment is 6 nm Al 0.15Ga 0.85N.

[0031] Example 4

[0032] This embodiment is similar to Embodiment 3, except that the barrier layer 2 in this embodiment is 4 nm In 0.04Al 0.66Ga 0.3N.

[0033] Example 5

[0034] This embodiment is similar to Embodiment 1, except that the barrier layer 2 in this embodiment is 7 nm In 0.04Al 0.66Ga 0.3N.

[0035] Example 6

[0036] This embodiment is similar to Embodiment 1, except that the intermediate layer 4 in this embodiment is 2 nm Al 0.22Ga 0.78N.

[0037] Comparative Example 1

[0038] Comparative Example 1 is similar to Example 1, except that the intermediate layer 4 of Comparative Example 1 is 1 nm AlN.

[0039] Comparative Example 2

[0040] Comparative Example 2 is similar to Example 1, except that Comparative Example 2 does not have an intermediate layer 4.

[0041] Comparative Example 3

[0042] Comparative Example 3 is similar to Example 1, except that the intermediate layer 4 of Comparative Example 3 is 2 nm AlN.

[0043] Comparative Example 4

[0044] Comparative Example 4 is similar to Comparative Example 3, except that the barrier layer 2 of Comparative Example 4 is 23 nm Al 0.2Ga 0.8N.

[0045] Experimental Results

[0046] Figure 2 shows the AFM diagram of Example 1.

[0047] Figure 3 shows the AFM plot of Comparative Example 2.

[0048] As shown in Figures 1 to 3, the high electron mobility transistor 100 of Example 1 uses an intermediate layer 4 to act as an intermediary between the gallium nitride layer 33 and the barrier layer 2, thereby making the lattice constant closer to that between the gallium nitride layer 33 and the barrier layer 2. This results in significantly improved epitaxial quality and surface morphology. Furthermore, the interface between the intermediate layer 4 and the gallium nitride layer 33 is smoother, which can reduce the binding energy of indium atoms and help improve the growth of the barrier layer 2.

[0049] Furthermore, the surface roughness (root mean square (RMS) of the barrier layer 2 of the high electron mobility transistor 100 in Example 1 is 0.471 nm, the surface roughness of the barrier layer 2 of the high electron mobility transistor 100 in Example 2 is 0.383 nm, and the surface roughness of the barrier layer 2 of the high electron mobility transistor 100 in Example 3 is 0.357 nm. As the thickness of the intermediate layer 4 increases, the epitaxial quality can be improved due to the longer migration length and growth time. However, the surface roughness of Comparative Example 2 is 0.521 nm, and it produces more pits and hillocks, which causes interface and quality problems. Therefore, compared with Comparative Example 2, the high electron mobility transistors 100 of Examples 1, 2, and 3 have lower interface scattering due to improved epitaxial quality and alloy scattering, which helps to achieve better electron mobility.

[0050] Figure 4 shows the band diagrams of Embodiment 1, Comparative Example 1 and Comparative Example 2 of the present invention.

[0051] Figure 5 shows the I DV G diagram of Embodiment 1, Comparative Example 1 and Comparative Example 2 of the present invention.

[0052] As shown in Figures 1, 4, and 5, the leakage mechanism is first investigated in depth using band diagrams. The intermediate layer 4 of the high electron mobility transistor 100 in Example 1 forms an additional quantum well through a heterostructure with the barrier layer 2 and the gallium nitride layer 33, effectively trapping electrons in the off-state, thus playing a crucial role in reducing gate leakage current. Furthermore, compared to Comparative Examples 1 and 2, the intermediate layer 4 of the high electron mobility transistor 100 in Example 1 exhibits a flatter conduction band slope, hindering electrons from passing through the barrier and dielectric interface, and forming an additional quantum well at the interface between the barrier layer 2 and the intermediate layer 4, introducing an additional barrier height, thereby hindering electron movement and promoting their trapping. Therefore, the off-state leakage current of the high electron mobility transistor 100 in Example 1 is lower (as shown in Figure 5).

[0053] Figure 6 shows the I-D-D diagrams of Embodiment 1, Comparative Example 1 and Comparative Example 2 of the present invention.

[0054] Figure 7 shows the CV diagram of Embodiment 1 and Comparative Example 2 of the present invention.

[0055] As shown in Figures 1 and 6, by optimizing epitaxy and introducing additional quantum wells, the leakage current of the high electron mobility transistor 100 of Example 1 is significantly reduced by two orders of magnitude compared to Comparative Example 1. Furthermore, the breakdown voltage of the high electron mobility transistor 100 of Example 1 reaches 450V, an increase of 120V compared to Comparative Example 1. Moreover, as shown in Figures 1 and 7, the intermediate layer 4 of the high electron mobility transistor 100 of Example 1 introduces additional capacitance. Since the summation of individual capacitances involves reciprocals, the overall total capacitance decreases. Furthermore, at a gate voltage of -18V, an additional slope becomes apparent in the capacitance curve. This phenomenon is attributed to the release of electrons previously trapped at the heterojunction between the barrier layer 2 and the intermediate layer 4 during the formation of the additional quantum wells. The presence of trapped electrons affects the capacitance slope within the gate voltage range of -20 to -15V. As more positive gate voltage is applied, the capacitance curve exhibits another slope related to channel behavior, similar to the trend observed in Comparative Example 2.

[0056] On the other hand, the results of sheet resistance, electron mobility and carrier density of Examples 1, 2, 5, 6 and Comparative Example 4 are shown in Table 1 below.

[0057] Table 1 sheet resistor (Ω / □) electron mobility (cm 2 / Vs) Carrier density (10 13 cm -2 ) Maximum drain current (mA / mm) Example 1 330 1450 -1.30 1228 Example 2 289 1590 -1.36 1280 Example 5 376 1210 -1.40 1560 Example 6 276 1500 -1.51 - Comparative Example 4 420 1600 -0.95 -

[0058] As can be seen from the results in Table 1, and with reference to Figure 1, the high electron mobility transistors 100 of Examples 1, 2, 5 and 6 have better sheet resistance. As the thickness of the intermediate layer 4 increases, greater piezoelectric polarization is generated, resulting in more electrons and better epitaxial quality, which helps to reduce sheet resistance and maintain high electron mobility and high carrier density, thereby having high drain current and helping to enhance the performance of the high electron mobility transistor 100.

[0059] In summary, the high electron mobility transistor of the present invention can improve epitaxial quality, enhance electronic performance, or improve reliability. Furthermore, the high electron mobility transistor of the present invention can also improve the polarization of the two-dimensional electron gas or reduce leakage current, and alleviate leakage current problems by forming additional quantum wells in the heterostructure of the barrier layer and the intermediate layer. On the other hand, the high electron mobility transistor of the present invention can further reduce interface scattering, thereby improving the overall epitaxial quality.

[0060] Although the present invention has been described through various embodiments, it should be understood that many other possible modifications and variations may be made without departing from the spirit of the present invention and the claims made in the patent application. [Simplified Explanation of the Diagram]

[0017] Figure 1 shows a schematic diagram of the high electron mobility transistor of the present invention. Figure 2 shows the AFM diagram of Example 1. Figure 3 shows the AFM diagram of Comparative Example 2. Figure 4 shows the band structure diagrams of Example 1, Comparative Example 1, and Comparative Example 2 of the present invention. Figure 5 shows the I / O-V / G diagrams of Example 1, Comparative Example 1, and Comparative Example 2 of the present invention. Figure 6 shows the I / O-V / D diagrams of Example 1, Comparative Example 1, and Comparative Example 2 of the present invention. Figure 7 shows the CV diagrams of Example 1 and Comparative Example 2 of the present invention.

Claims

1. A high electron mobility transistor, comprising: One substrate; A barrier layer is disposed on the substrate, wherein the barrier layer comprises an aluminum gallium indium nitride material; wherein the aluminum gallium indium nitride material is In1-x-yAlxGayN, x is in the range of 0.1 to 0.8, and y is in the range of 0.8 to 0.1, and the thickness of the barrier layer is between 3 nm and 15 nm; a semiconductor layer is disposed between the substrate and the barrier layer; and an intermediate layer is disposed between the semiconductor layer and the barrier layer, wherein the intermediate layer comprises an aluminum gallium nitride material, and the intermediate layer is in direct contact with the barrier layer; wherein the aluminum gallium nitride material is AlzGa1-zN, and z is in the range of 0.1 to 0.

4.

2. The high electron mobility transistor as described in claim 1, wherein, The semiconductor layer includes a nucleation layer, a buffer layer and a gallium nitride layer, the gallium nitride layer being disposed on the nucleation layer and the buffer layer being disposed between the nucleation layer and the gallium nitride layer.

3. The high electron mobility transistor as described in claim 2, wherein, The nucleation layer comprises an aluminum nitride material.

4. The high electron mobility transistor as described in claim 1, wherein, The thickness of the intermediate layer is between 1 nm and 15 nm.

5. The high electron mobility transistor as described in claim 1, wherein, z is in the range of 0.1 to 0.

3.

6. The high electron mobility transistor as described in claim 1 further includes a passivation layer disposed on the barrier layer.

7. The high electron mobility transistor as described in claim 6, wherein, The passivation layer comprises a silicon nitride material.

8. The high electron mobility transistor as described in claim 6 further includes a drain, a source, and a gate, wherein the drain and the source are disposed on the barrier layer, and the gate is disposed on the passivation layer.