Memory system

Abstract

This invention provides a memory system that can reduce the latency of processing corresponding to write requests. According to one embodiment, the memory system includes non-volatile memory comprising multiple blocks and a controller. The controller allocates a first erased block, in which data erasure operations have been completed, as a general block. When a first stream is started, if two or more erased blocks in which data erasure operations have been completed are included in multiple blocks, the controller allocates a second erased block as a write destination block corresponding to the first stream. When the first stream is started, if two or more erased blocks in which data erasure operations have been completed are not included in multiple blocks, the controller sets the general block as the write destination block.

Description

Memory system [Related Applications] This application claims priority from Japanese Patent Application No. 2024-001843 (filing date: January 10, 2024), the entire contents of which are incorporated herein by reference. An embodiment of the present invention relates to a memory system for controlling a non-volatile memory. In recent years, memory systems that include non-volatile memory have become widely popular. One such memory system is a solid-state drive (SSD) that includes NAND (Not AND) flash memory. SSDs are used as main storage in various computing devices. Memory systems sometimes have a multi-stream function. This function receives a write request associated with one of multiple streams from a host and writes the data associated with the write request to a block in non-volatile memory allocated to the stream. Multiple streams are used, for example, to write data of different lifespans to different blocks. When a stream starts to be used, for example, a block where data erasure is completed (erased block) is allocated to the stream. However, sometimes a sufficient number of erased blocks are not secured when a stream starts being used. If the allocation of erased blocks to a stream that starts being used is delayed, the execution of a process corresponding to a write request associated with the stream is delayed. One embodiment provides a memory system that can reduce delay in processing corresponding to a write request. According to an embodiment, a memory system is capable of being connected to a host. The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks. The controller is electrically connected to the non-volatile memory. The controller manages a plurality of streams. The controller allocates a first erased block in a plurality of blocks where a data erase operation is completed as a universal block, wherein the universal block can write data that is not associated with any of the plurality of streams and data that is associated with any of the plurality of streams. When the first stream is started to be used, if two or more erased blocks in which a data erase operation is completed are included in a plurality of blocks, the controller allocates a second erased block as a write destination block corresponding to the first stream. When the first stream is started to be used, if two or more erased blocks in which a data erase operation is completed are not included in a plurality of blocks, the controller sets the universal block as a write destination block corresponding to the first stream. Hereinafter, embodiments will be described with reference to the drawings. First, the structure of an information processing system 1 including a memory system according to an embodiment will be described with reference to Fig. 1. The information processing system 1 includes a host device 2 and a memory system 3. The host device 2 may be a storage server that stores a large amount of diverse data in the memory system 3 or a personal computer. Hereinafter, the host device 2 is also referred to as the host 2. Memory system 3 is a storage device that writes data to and reads data from non-volatile memory. Non-volatile memory is, for example, NAND flash memory 4. Memory system 3 is also referred to as a storage device or semiconductor storage device. Memory system 3 is implemented, for example, as an SSD that includes NAND flash memory 4. The following examples primarily illustrate the case where the non-volatile memory is NAND flash memory 4. The memory system 3 has a multi-stream function. The multi-stream function is a function that receives a write request associated with one of multiple streams from an external source (here, the host 2), and writes the user data associated with the write request to a block within the NAND flash memory 4 allocated to the stream. Multiple streams are used, for example, to write user data of different lifespans to different blocks. Receiving a write request associated with a stream, more specifically, means receiving a write request that specifies the stream. A write request is, for example, a write command. The write request may include information (stream ID) that can uniquely identify the specified stream. Hereinafter, a write request is referred to as a write command. The memory system 3 can be used as a storage of the host 2. The memory system 3 can be built into the host 2 or connected to the host 2 via a cable or a network. The interface for connecting the host 2 and the memory system 3 is based on Peripheral Component Interconnect Express (PCIEX). TM , PCIe TM ), Ethernet TM (Ethernet TM ), Fibre Channel, Non Volatile Memory Express TM ,NVMe TM ) and other standards. The host 2 includes, for example, a central processing unit (CPU) 21 and a random access memory (RAM) 22 . The CPU 21 and the RAM 22 are connected via, for example, a bus 20 . The CPU 21 is, for example, at least one processor and controls the operations of various components within the host 2 . The RAM 22 is, for example, a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The memory system 3 includes, for example, a NAND flash memory 4 , a DRAM 5 , and a controller 6 . The NAND flash memory 4 includes a plurality of blocks B0, B1, B2, ..., and Bm-1. The plurality of blocks B0, B1, B2, ..., and Bm-1 each function as the minimum unit of data erasure operation. Blocks are sometimes also referred to as erase blocks or physical blocks. The plurality of blocks B0, B1, B2, ..., and Bm-1 each include a plurality of pages P0, ..., and Pn-1. The plurality of pages P0, ..., and Pn-1 each include a plurality of memory cells connected to a single word line. The plurality of pages P0, ..., and Pn-1 each function as a unit of data write operation and data read operation. Furthermore, a word line can also function as a unit of data write operation and data read operation. There is an upper limit on the number of program / erase cycles (P / E cycles) for each block, known as the maximum P / E cycle number. A P / E cycle for a block includes both an erase operation (erasing all memory cells within the block) and a programming operation (writing data to each page within the block). DRAM 5 is a volatile memory. Its storage area is allocated, for example, to store firmware (FW) 51, a cache area for a logical-to-physical address translation table 52, and an area for storing control information 53. Control information 53 includes, for example, the target erased block number. The storage area of ​​DRAM 5 can also be allocated as a buffer area for temporarily storing user data. The FW 51 is a program for controlling the operation of the controller 6. The FW 51 is loaded into the DRAM 5 from the NAND flash memory 4, for example. The logical-physical address conversion table 52 is a table for managing the mapping between logical addresses and physical addresses. A logical address is an address used by the host 2 to specify a storage area in the memory system 3. A logical address is, for example, a logical block address (LBA). The target number of erased blocks is data indicating the number of erased blocks to be secured in the NAND flash memory 4. Erased blocks are blocks where data has been erased and programming has not yet been performed. Controller 6 can include circuitry such as a system-on-a-chip (SoC). It can also include multiple semiconductor chips. Controller 6 is electrically connected to NAND flash memory 4 and is configured to control NAND flash memory 4. The functions of each component within controller 6 can be implemented by dedicated hardware within controller 6 or by a processor executing firmware. The controller 6 can also function as a Flash Translation Layer (FTL) configured to perform data management and block management of the NAND flash memory 4. The data management performed by the FTL includes (1) the management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing for concealing the difference between data read / write operations in page units and data erase operations in block units. Block management includes management of bad blocks, wear leveling, and garbage collection (GC). The management of the mapping between each logical address and each physical address is performed, for example, using the logical-physical address conversion table 52. The controller 6 uses the logical-physical address conversion table 52 to manage the mapping between each logical address and each physical address in units of a specific management size. The physical address corresponding to a certain logical address represents the physical storage location in the NAND flash memory 4 where the data of the logical address is written. The controller 6 uses the logical-physical address conversion table 52 to manage multiple storage areas obtained by logically dividing the storage area of ​​the NAND flash memory 4. The size of each of the multiple storage areas is the management size. The multiple storage areas correspond to multiple logical addresses, respectively. That is, the multiple storage areas are each specified by a logical address. The logical-physical address conversion table 52 can also be loaded from the NAND flash memory 4 to the DRAM 5 when the memory system 3 is started. Data writing to a memory cell can only be performed once for each P / E cycle. Therefore, the controller 6 writes the updated data corresponding to a certain logical address to another physical storage location, rather than to the physical storage location that stores the previous data corresponding to the logical address. In addition, the controller 6 invalidates the previous data by updating the logical-physical address conversion table 52 to associate the logical address with the other physical storage location. The data referenced by the logical-physical address conversion table 52 (i.e., the data associated with the logical address) is called valid data. In addition, data that is not associated with any logical address is called invalid data. Valid data is data that can be read from the host 2 later. Invalid data is data that can no longer be read from the host 2. Blocks within the NAND flash memory 4 are broadly divided into active blocks and free blocks. Active blocks store valid data and cannot be newly written. Free blocks, by not storing valid data, can be used to write new data through a data erase operation. In other words, free blocks are used as new write destination blocks through a data erase operation. Write destination blocks can store valid data. Free blocks that have completed a data erase operation are called erased blocks. Furthermore, free blocks that are in the process of being erased are also called "in-progress" blocks. GC is the process of copying valid data from a mix of valid and invalid data within several currently used blocks to another block (e.g., an erased block). By copying the valid data to another block, GC frees up the blocks containing only invalid data as free blocks. Therefore, GC can increase the number of free blocks within the NAND flash memory 4. The controller 6 includes, for example, a host interface circuit (host I / F) 11, a DRAM interface circuit (DRAM I / F) 12, a NAND interface circuit (NAND I / F) 13, and a CPU 14. The host I / F 11, DRAM I / F 12, NAND I / F 13, and CPU 14 are connected via, for example, a bus 10. The host I / F 11 is a circuit configured to receive various commands (e.g., I / O commands and various control commands) and data from the host 2, and to transmit responses to the commands and the data to the host 2. Examples of I / O commands include write and read commands. Examples of control commands include de-map commands (TRIM commands), open commands, and close commands. A de-map command requests the invalidation of data corresponding to a specified logical address (or logical address range). An open command requests the start of stream use. A close command requests the end of stream use. The DRAM I / F 12 is a DRAM control circuit configured to control access to the DRAM 5 . The NAND I / F 13 is a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F 13 can also be connected to multiple memory chips within the NAND flash memory 4 via multiple channels. By driving multiple memory chips in parallel, the access bandwidth between the controller 6 and the NAND flash memory 4 is increased. The CPU 14 is a processor configured to control the host I / F 11, DRAM I / F 12, and NAND I / F 13. The CPU 14 performs various processes by executing the FW 51 loaded from the NAND flash memory 4 into the DRAM 5. The FW 51 is a control program containing a group of commands for causing the CPU 14 to execute various processes. The CPU 14 can execute command processing, etc., for processing various commands from the host 2. The operation of the CPU 14 is controlled by the FW 51 executed by the CPU 14. The functions of each unit in the controller 6 may be implemented by dedicated hardware in the controller 6 or by the CPU 14 executing the FW 51 . The CPU 14 functions as, for example, a stream management unit 141, an allocation control unit 142, an erase control unit 143, and a write control unit 144. The CPU 14 functions as the aforementioned units by, for example, executing the FW 51. The stream management unit 141 manages a plurality of streams. Specifically, the stream management unit 141 manages the start (open) and end (close) of use of a stream. In response to receiving a command from the host 2 indicating the start of use of a particular stream, the stream management unit 141 sets the stream to an open state. The command indicating the start of use of a stream may be, for example, an initial write command specifying the stream. Alternatively, an open command specifying the stream may be used as the command indicating the start of use of the stream. Furthermore, the stream management unit 141 may also set the corresponding stream to an open state in response to a response to the open command sent to the host 2. The stream management unit 141 notifies the allocation control unit 142 of the stream opening, for example. The stream management unit 141 sets the stream to a closed state in response to detecting that either a close command specifying a stream has been received from the host 2, or that a write command specifying a stream has not been received from the host 2 within a predetermined time. The stream management unit 141 notifies the allocation control unit 142, for example, of the stream closure. Furthermore, the stream management unit 141 sets the stream to an open state again in response to receiving a write command specifying the stream (or an open command specifying the stream) from the host 2 after setting the stream to a closed state. The allocation control unit 142 controls the allocation of general purpose blocks and dedicated blocks, and the setting of write destination blocks. A general block is a block into which user data associated with a write command that does not specify any stream, as well as user data associated with a write command that specifies a stream, can be written. A write command that does not specify any stream is also referred to as a non-stream write command. User data associated with a non-stream write command is also referred to as non-stream user data. Non-stream user data is user data that is not associated with any stream. A general block can be used as a write destination block for non-stream user data, and it can also be used as a write destination block for user data associated with a stream. A dedicated block is a block that can only be written with user data associated with a write command that specifies a corresponding stream. A write command that specifies a stream is also referred to as a stream write command. User data associated with a stream write command is also referred to as stream-associated user data. A dedicated block serves as the destination block for writing user data associated with a corresponding stream. The allocation control unit 142 allocates erased blocks within the NAND flash memory 4 as general-purpose blocks. Erased blocks within the NAND flash memory 4 are blocks that have not yet been allocated as either general-purpose blocks or dedicated blocks. Specifically, the allocation control unit 142 allocates erased blocks as general-purpose blocks, for example, in response to the startup of the memory system 3. Furthermore, the allocation control unit 142 allocates new erased blocks as general-purpose blocks in response to the completion of data writing to all general-purpose blocks. The allocation control unit 142 allocates erased blocks within the NAND flash memory 4 as dedicated blocks corresponding to an open stream. Specifically, when a stream is open, the allocation control unit 142 may allocate erased blocks as dedicated blocks corresponding to the stream. Furthermore, upon completion of writing data to the entire dedicated block allocated to a stream, the allocation control unit 142 may allocate a new erased block as a dedicated block corresponding to the stream. Furthermore, if there are no erased blocks that can be allocated as dedicated blocks corresponding to a stream, the allocation control unit 142 sets a general-purpose block as the write destination block for the stream. Furthermore, upon detecting that a stream has been closed, the allocation control unit 142 may change the dedicated block corresponding to the stream to a general-purpose block. The allocation control unit 142 determines the target number of erased blocks based on the number of open streams. For example, the allocation control unit 142 sets the target number of erased blocks as the number of open streams plus one. In this case, the target number of erased blocks corresponds to the sum of the number of erased blocks to be allocated as dedicated blocks to each open stream and the number of erased blocks to be allocated as general-purpose blocks to each open stream. The erase control unit 143 selects a free block from one or more free blocks within the NAND flash memory 4 and performs a data erase operation on the selected free block. Specifically, the erase control unit 143 controls the execution of the data erase operation on the free block based on the number of erased blocks in the NAND flash memory 4 and the target number of erased blocks. The erase control unit 143 performs the data erase operation on the free block while the number of erased blocks in the NAND flash memory 4 is less than the target number of erased blocks. The erase control unit 143 does not perform the data erase operation on the free block while the number of erased blocks in the NAND flash memory 4 is greater than the target number of erased blocks. The write control unit 144 performs processing corresponding to write commands received from the host 2. Specifically, the write control unit 144 writes the associated user data to a general-purpose block in response to a non-stream write command. In response to a stream write command, the write control unit 144 writes the associated user data to a write-destination block corresponding to the stream. The write-destination block corresponding to a stream is either a dedicated block or a general-purpose block allocated to the stream. In this manner, the stream management unit 141, the allocation control unit 142, the erase control unit 143, and the write control unit 144 implement data writing operations corresponding to the multi-stream function. A more specific example of the operation of the stream management unit 141, the allocation control unit 142, the erase control unit 143, and the write control unit 144 will be described later with reference to Figures 5 to 9. Here, two cases of delay in executing a write command in a memory system of a comparative example are described. The memory system of the comparative example has a multi-stream function. The delay in executing a write command may be caused, for example, by insufficient erased blocks allocated as the write destination block. Figure 2 illustrates a situation in which, in a comparative example memory system, insufficient erased blocks occur when multiple streams are opened in a short period of time (hereinafter referred to as the first situation). In the first situation, the zeroth block WB0, the first block WB1, and the second block WB2 are allocated to the non-stream 30C (non-stream), the first stream 31C (stream #1), and the second stream 32C (stream #2), respectively. The zeroth block WB0 stores user data 41 for the non-stream 30C. The first block WB1 stores user data 42 associated with the first stream 31C. The second block WB2 does not yet store any data. Furthermore, the NAND flash memory within the memory system includes an erased block EB0 and an erasing block EB1. In the first case, the third stream 33C and the fourth stream 34C are opened simultaneously ((1) in FIG2 ). In response to the opening of the third stream 33C, the erased block EB0 is allocated as the write destination block of the third stream 33C ((2) in FIG2 ). On the other hand, since no erased blocks are guaranteed to be allocated, an erased block cannot be allocated as the write destination block for the fourth stream 34C in response to the opening of the fourth stream 34C. Therefore, the erased block EB1 is not allocated to the fourth stream 34C until the data erase operation on the erase-in-progress block EB1 is completed and the erased block EB1 is acquired ((3) in FIG2 ). Therefore, in the memory system of the comparative example, in the first case, the execution delay of the write command of the fourth stream 34C is specified. FIG3 illustrates a case in which insufficient erased blocks exist when data is written to the entirety of multiple blocks in a short period of time in a memory system according to a comparative example (hereinafter referred to as the second case). In the second case, the relationship between the non-stream 30C, the first stream 31C, the second stream 32C, the zeroth block WB0, the first block WB1, the second block WB2, the erased block EB0, and the erasing block EB1 is the same as in the first case. In the second case, data is written to the entirety of both the zeroth block WB0 and the first block WB1 within a short period of time ((1) in FIG3 ). Upon completion of writing data to the entirety of the zeroth block WB0 , the erased block EB0 is newly allocated as the write destination block for the non-stream 30C ((2) in FIG3 ). On the other hand, since no erased blocks are available for allocation, an erased block cannot be allocated as the write destination block for the first stream 31C in response to the completion of data writing to the entire first block WB1. Therefore, until the data erase operation for the erased block EB1 is completed and the erased block EB1 is acquired, the erased block EB1 is not allocated to the first stream 31C ((3) in Figure 3). Therefore, in the memory system of the comparative example, in the second case, the execution delay of the write command of the first stream 31C is specified. Furthermore, in the memory system of the comparative example, the storage area allocated to the blocks of the stream may be wasted. FIG4 illustrates a case in which the storage area allocated to blocks for streams is wasted in a memory system according to a comparative example (hereinafter referred to as the third case). In the third case, the relationship between the non-stream 30C, the first stream 31C, the second stream 32C, the zeroth block WB0, the first block WB1, the second block WB2, the erased block EB0, and the erasing block EB1 is the same as in the first case. In the third case, the host no longer receives write commands for the first stream 31C and the second stream 32C ((1) in FIG4 ). That is, the host no longer receives write commands specifying the first stream 31C and the second stream 32C. In this case, in the first block WB1, after writing user data partway through, the storage area where the data has not yet been written (unwritten area) is wasted because no write command specifying the first stream 31C is received ((2) in FIG4 ). Furthermore, in the second block WB2, after being allocated to the second stream 32C, no write command specifying the second stream 32C is received, and the entire storage area is wasted ((3) in FIG4 ). Therefore, in the memory system of the comparative example, in the third case, since the write command designating the stream is no longer received from the host 2 , the storage area of ​​the block allocated to the stream may be wasted. As described above, in the memory system of the comparative example, the execution of a write command specifying a stream may be delayed, and the storage area of ​​the block allocated to the stream may be wasted. In contrast, in the memory system 3 of this embodiment, when a stream begins to be used, (A) if there are two or more erased blocks, the controller 6 allocates an erased block (dedicated block) as the write-destination block corresponding to the stream; (B) if there are not two or more erased blocks, the controller 6 sets a general-purpose block as the write-destination block corresponding to the stream. Specifically, the controller 6 allocates an erased block (dedicated block) as the write-destination block for the stream, or sets a general-purpose block as the write-destination block for the stream, depending on the number of erased blocks contained in the NAND flash memory 4. This allows the controller 6 to execute write commands specifying the stream without delay, regardless of whether there are erased blocks that can be allocated as the write-destination block for the stream. In addition, when a stream is finished being used, the controller 6 changes the dedicated block allocated to the stream to a general-purpose block. This allows the controller 6 to store user data without wasting the unwritten area of ​​the dedicated block allocated to the finished stream. Furthermore, the controller 6 may change the general purpose blocks to dedicated blocks again in response to restarting the use of the stream after changing the dedicated blocks allocated to the stream to general purpose blocks. Therefore, the controller 6 may also continue to allocate the dedicated blocks to the stream that has been restarted. 5 to 9 , the operations of the stream management unit 141 , the allocation control unit 142 , the erase control unit 143 , and the write control unit 144 of the memory system 3 will be described in detail. Figure 5 shows an example of how memory system 3 allocates dedicated blocks to a stream that has just been used (i.e., a stream that has entered the open state). In the example shown in Figure 5 , it is assumed that general block GB is allocated to non-stream 30, and first dedicated block DB1 is allocated to first stream 31 (stream #1). General block GB stores user data 61 for non-stream 30. First dedicated block DB1 stores user data 62 associated with first stream 31. Since there is only one open stream, the target number of erased blocks is, for example, 2 (= the number of open streams + 1). NAND flash memory 4 includes two erased blocks, EB0 and EB1. In response to receiving the first write command designating the second stream 32 (stream# 2 ), the stream management unit 141 opens the second stream 32 (( 1 ) in FIG. 5 ). The allocation control unit 142 changes the target erased block count from 2 to 3 ((2) in FIG5 ) based on the number of streams in the open state. That is, the allocation control unit 142 increases the target erased block count by 1 in response to the second stream 32 becoming open. In response to the number of erased blocks being less than the target erased block count, the erase control unit 143 begins erasing data on free blocks. Next, since two or more erased blocks EB0 and EB1 are included in the NAND flash memory 4, the allocation control unit 142 allocates the erased block EB0 as the dedicated block DB2 (second dedicated block DB2) of the second stream 32 ((3) in FIG5 ). This is because even if the data writing to the entire general block GB is completed after the erased block EB0 is allocated to the second stream 32, the erased block EB1 can be allocated as the next general block GB. The allocation control unit 142 allocating the erased block EB0 as the second dedicated block DB2 means setting the second dedicated block DB2 (=erased block EB0) as the dedicated write destination block for the second stream 32. Furthermore, the allocation control unit 142 can also allocate the erased block EB1 as the second dedicated block DB2. In response to the write command specifying the second stream 32, the write control unit 144 writes the associated user data to the second dedicated block DB2. In this manner, when the second stream 32 is in the open state while two or more erased blocks are included in the NAND flash memory 4, the allocation control unit 142 allocates any erased block as the second dedicated block DB2 corresponding to the second stream 32. This allows the write control unit 144 to execute write commands from the second stream 32 without delay, using the second dedicated block DB2 as the write destination block. Furthermore, the allocation control unit 142 changes the target number of erased blocks according to the number of streams in the open state. In NAND flash memory 4, erased blocks that are reserved but not used for data writing reduce the storage capacity available for writing in memory system 3. Therefore, reserving an excessive number of erased blocks may lead to performance degradation in memory system 3. For example, this excessive number of erased blocks corresponds to the maximum number of streams that can be managed in memory system 3. Furthermore, in this case, while the allocation of erased blocks to open streams is not delayed, erased blocks may be generated that require time from the completion of data erasure until the actual use of data writing. The quality of data stored in these erased blocks may deteriorate. In the memory system 3, the allocation control unit 142 sets the target number of erased blocks based on the number of open streams, thus avoiding the need to secure an excessive number of erased blocks. Consequently, the memory system 3 maintains excess capacity (over-provisioning (OP)) and ensures sufficient total writable capacity even when no streams are open. FIG6 illustrates an example of setting a general block as the write destination block for a stream to be started in memory system 3. Here, it is assumed that general block GB is allocated to non-stream 30. General block GB stores user data 63 for non-stream 30. Since there are no open streams, the target erased block number is, for example, 1. NAND flash memory 4 includes one erased block EB0. In response to receiving the first write command designating the first stream 31 , the stream management unit 141 opens the first stream 31 (( 1 ) in FIG. 6 ). Based on the number of open streams, the allocation control unit 142 changes the target erased block count from 1 to 2 ((2) in FIG6 ). That is, in response to the first stream 31 becoming open, the allocation control unit 142 increases the target erased block count by 1. In response to the number of erased blocks being less than the target erased block count, the erase control unit 143 begins erasing data on free blocks. Here, the free block in the middle of the data erasure operation is the in-progress block EB1. Since only one erased block EB0 is included in the NAND flash memory 4 (i.e., there are not more than two erased blocks), the allocation control unit 142 does not allocate the erased block EB0 to the first stream 31 ((3) in FIG6 ). The allocation control unit 142 sets the general block GB as the write destination block for the first stream 31 ((4) in FIG6 ). Thus, the write control unit 144 can write the user data 64 associated with the write command of the first stream 31 into the general block GB without waiting for the data erase operation of the erased block EB1 to be completed. Therefore, even if the erased block that can be allocated to the first stream 31 in the open state is not included in the NAND flash memory 4, the write control unit 144 can use the general block GB as the write destination block and execute the write command of the first stream 31 without delay. Furthermore, the allocation control unit 142 may change the write destination block of the stream from the general-purpose block GB to the dedicated block. FIG. 7 shows an example of an operation of changing the write destination block of the first stream 31 in the example shown in FIG. 6 from the general-purpose block GB to the dedicated block. After setting the general purpose block GB as the write destination block for the first stream 31, the allocation control unit 142 predicts whether a new erased block will be acquired before data writing to the general purpose block GB is completed. Specifically, the allocation control unit 142 predicts whether the erase control unit 143 will complete erasing the data in the currently-erasing block EB1 before data writing to the general purpose block GB is completed. This prediction uses, for example, the maximum data write speed for blocks within the NAND flash memory 4 and the time required to erase data for one block (data erase time). The maximum data write speed is, for example, the data write speed at which the write performance based on the specifications of the memory system 3 is fully utilized. For example, the maximum data write speed can be the maximum speed of programming operations within the NAND flash memory 4. For example, the maximum data write speed can be the maximum rate at which user data can be received from the host 2 over a certain period of time. More specifically, for example, the allocation control unit 142 calculates the time (first time) at which data writing to the entire general-purpose block GB is completed based on the size of the unwritten area within the general-purpose block GB (i.e., the remaining storage capacity within the general-purpose block GB) and the maximum data writing speed for the blocks within the NAND flash memory 4. Furthermore, the allocation control unit 142 calculates the time (second time) at which the data erasing operation for the erasing block EB1 is completed based on the time at which the data erasing operation begins and the data erasure time per block. If the second time is earlier than the first time, the allocation control unit 142 predicts that a new erased block EB1 will be acquired before data writing to the entire general-purpose block GB is completed. If the second time is later than the first time, the allocation control unit 142 predicts that a new erased block EB1 will not be acquired before data writing to the entire general-purpose block GB is completed. If it is predicted that a new erased block EB1 will be acquired before the entire data write to the general-purpose block GB is completed, the allocation control unit 142 allocates the erased block EB0 as the first dedicated block DB1 corresponding to the first stream 31 ((1) in FIG7 ). The allocation control unit 142 then changes the write destination block for the first stream 31 from the general-purpose block GB to the first dedicated block DB1 ((2) in FIG7 ). In other words, through the actions (1) and (2) in FIG7 , the erased block EB0 is allocated as the write destination block for the first stream 31. Thus, the write control unit 144 can write the user data associated with the write command designating the first stream 31 into the first dedicated block DB1 instead of into the general block GB. Furthermore, when the writing of data to the entire dedicated block allocated to the stream is completed, the allocation control unit 142 allocates the new erased block as a dedicated block corresponding to the stream (i.e., a dedicated write destination block) or sets the general block as the write destination block of the stream, similar to the actions shown in Figures 5 to 7. Figure 8 shows an example of how a dedicated block allocated to a terminated stream (i.e., a stream whose closure has been detected) is used as a general-purpose block in the memory system 3. Here, it is assumed that the general-purpose block GB is allocated to the non-stream 30, and the first dedicated block DB1 is allocated to the first stream 31. The general-purpose block GB stores user data 65 for the non-stream 30. The first dedicated block DB1 stores user data 66 associated with the first stream 31. Since there is only one open stream, the target number of erased blocks is, for example, two. The NAND flash memory 4 includes two erased blocks, EB0 and EB1. The stream management unit 141 detects the closing of the first stream 31 ((1) in FIG8 ). The stream management unit 141 detects the closing of the first stream 31, for example, based on either receiving a close command from the host 2 or failing to receive a write command specifying the first stream 31 from the host 2 within a predetermined time. Based on the number of streams currently open, the allocation control unit 142 changes the target erased block count from 2 to 1 ((2) in FIG8 ). Specifically, the allocation control unit 142 decreases the target erased block count by 1 in response to detecting the closing of the first stream 31. The allocation control unit 142 then changes the first dedicated block DB1 allocated to the first stream 31 to a general-purpose block ((3) in FIG8 ). The general-purpose block after the change from the first dedicated block DB1 is referred to as the first general-purpose block DB1. Next, in response to the completion of writing data to the entire general-purpose block GB ((4) in FIG8 ), the allocation control unit 142 changes the general-purpose block used as the write-destination block (hereinafter also referred to as the write-destination general-purpose block) from the general-purpose block GB to the first general-purpose block DB1 ((5) in FIG8 ). In other words, the first dedicated block DB1 allocated to the first stream 31 whose shutdown was detected is used as the new write-destination general-purpose block. This allows the write control unit 144 to write user data to the first general-purpose block DB1. For example, user data 67 associated with streams other than stream 30 and user data associated with streams not allocated dedicated blocks can be written to the first general-purpose block DB1. Therefore, the unwritten area within the first dedicated block DB1 can be used to store user data without wasting it. Furthermore, when the first stream 31 detected to be shut down is restarted, the allocation control unit 142 may also return the first general-purpose block DB1 to the first dedicated block DB1. FIG9 shows an example of operations in which a dedicated block allocated to a closed stream is changed to a general-purpose block and then returned to the dedicated block in the memory system 3. Operations (1) to (3) in FIG9 are the same as operations (1) to (3) in FIG8 . After the first dedicated block DB1 is changed to the first general-purpose block DB1 , the stream management unit 141 opens the first stream 31 again in response to receiving a write command designating the first stream 31 from the host 2 , for example ( ( 4 ) in FIG. 9 ). In response to the first stream 31 being opened again, the allocation control unit 142 returns the target erased block number from 1 to 2 ((5) in FIG9 ). Then, in response to the first stream 31 being opened again after the first dedicated block DB1 is changed to the first general-purpose block DB1 and before new user data is written to the first general-purpose block DB1, the allocation control unit 142 returns the first general-purpose block DB1 to the first dedicated block DB1 ((6) in FIG9 ). In other words, the allocation control unit 142 reassigns the first general-purpose block DB1 as the first dedicated block DB1 corresponding to the first stream 31. In this manner, if the write control unit 144 receives a write command specifying the first stream 31 from the host 2 before writing new user data to the first general-purpose block DB1, the allocation control unit 142 returns the target erased block count and the first general-purpose block DB1 to the state before detecting the shutdown of the first stream 31. This allows the write control unit 144 to continue writing associated user data to the first dedicated block DB1 in response to write commands specifying the first stream 31. Therefore, for example, user data associated with multiple write commands each specifying the first stream 31 can be stored throughout the entire first dedicated block DB1. For example, there's a high probability that consecutive user data will be associated with multiple consecutive write commands specifying the same stream. This contiguous user data may be demapped simultaneously. For example, if all user data stored in a block is demapped simultaneously, the block becomes a free block and is not subject to GC. Therefore, by storing user data associated with write commands specifying the same stream within the entire block, the amount of processing required to set the block as a free block can be reduced. Next, the processing executed in the memory system 3 will be described with reference to FIG. 10 to FIG. 12 . FIG10 is a flowchart illustrating an example of the flow of the first allocation process executed by the CPU 14. The first allocation process is a process for setting a write destination block for an open stream. The CPU 14 executes the first allocation process, for example, in response to a stream being opened. Hereinafter, the open stream is referred to as the first target stream. First, the CPU 14 increases the target erased block count by 1 (step S101 ). Next, the CPU 14 determines whether the NAND flash memory 4 includes two or more erased blocks (step S102 ). If the NAND flash memory 4 contains two or more erased blocks (yes in step S102), the CPU 14 allocates the erased blocks as dedicated blocks for the first target stream (step S103). The CPU 14 then proceeds to step S109. The dedicated blocks are used as the write destination blocks for the first target stream. Specifically, user data associated with the write command specifying the first target stream is written to the dedicated blocks. If the NAND flash memory 4 does not contain two or more erased blocks (no in step S102), the CPU 14 sets the general-purpose block as the write destination block for the first target stream (step S104). This causes the user data associated with the write command specifying the first target stream to be written to the general-purpose block rather than to the dedicated block. The CPU 14 then determines whether the NAND flash memory 4 contains an erased block (step S105). If the NAND flash memory 4 does not contain any erased blocks (No in step S105), the CPU 14 returns to step S105. That is, the process in step S105 is repeated until it is determined that there is one erased block. If the NAND flash memory 4 contains an erased block (YES in step S105), the CPU 14 determines whether to acquire a new erased block before the entire general-purpose block is fully written (step S106). The CPU 14 determines whether to acquire a new erased block before the entire general-purpose block is fully written, for example, based on the maximum data write speed for the blocks of the NAND flash memory 4 and the data erase time for a single block. If a new erased block is not acquired before data writing to the entire general purpose block is completed (No in step S106), the CPU 14 returns to step S105. That is, the processing of steps S105 and S106 is repeated until it is determined that there is an erased block in the NAND flash memory 4 and a new erased block is acquired before data writing to the entire general purpose block is completed. If a new erased block is acquired before writing data to the entire general-purpose block is complete (YES in step S106), the CPU 14 allocates the erased block as a dedicated block for the first target stream (step S107). The CPU 14 then changes the write destination block for the first target stream from the general-purpose block to the dedicated block (i.e., the allocated erased block) (step S108). Following this processing by the CPU 14, the process proceeds to step S109. After performing either step S103 or step S108, the CPU 14 determines whether the target number of erased blocks exceeds the number of erased blocks (step S109). If the target number of erased blocks exceeds the number of erased blocks (yes in step S109), the CPU 14 selects a free block in the NAND flash memory 4 and begins erasing data in the free block (step S110), terminating the first allocation process. On the other hand, if the target number of erased blocks is less than the number of erased blocks (no in step S109), the CPU 14 terminates the first allocation process. Through the above-described first allocation process, the CPU 14 allocates an erased block to the first target stream if the NAND flash memory 4 contains two or more erased blocks. Alternatively, if the NAND flash memory 4 does not contain two or more erased blocks, the CPU 14 sets a general-purpose block as the write destination block for the first target stream. Then, in response to a state where one erased block exists in the NAND flash memory 4 and a new erased block is acquired before data is written to the entire general-purpose block, the CPU 14 allocates the erased block (dedicated block) to the first target stream. This allows the CPU 14 to execute write commands specifying the first target stream without delay, regardless of whether an erased block exists that can be allocated as the write destination block for the first target stream. Furthermore, even when writing data to the entire dedicated block allocated to the first target stream is complete, the CPU 14 similarly performs a process for newly setting the write destination block for the first target stream. This process is, for example, the process of removing step S101 from the first allocation process. Therefore, even when writing data to the entire dedicated block allocated to the first target stream is complete, the CPU 14 can execute the write command specifying the first target stream without delay, regardless of whether there are new erased blocks that can be allocated as the write destination block for the first target stream. Figure 11 is a flowchart illustrating an example of the flow of allocation change processing executed by the CPU 14. Allocation change processing utilizes the dedicated block allocated to the stream whose closure has been detected. The CPU 14 executes allocation change processing in response to detecting the closure of a stream. Hereinafter, the stream whose closure has been detected is referred to as the second target stream. It is assumed that a dedicated block has been allocated to the second target stream. First, the CPU 14 decrements the target erased block count by 1 (step S201 ) and changes the dedicated block allocated to the second target stream to a general-purpose block (hereinafter referred to as a second general-purpose block) (step S202 ). Next, the CPU 14 determines whether a write command designating the second target stream has been received (step S203 ). That is, the CPU 14 determines whether a write command designating the second target stream has been received again after detecting the closing of the second target stream. Upon receiving a write command specifying the second target stream (YES in step S203), the CPU 14 determines whether to write new user data to the second general-purpose block (step S204). Specifically, the CPU 14 determines whether any of the user data associated with a stream not allocated a dedicated block or non-stream user data has been written to the second general-purpose block since step S202. If new user data is being written to the second general-purpose block (YES in step S204), the CPU 14 executes the first allocation process for the second target stream (step S205) and terminates the allocation change process. Specifically, since the dedicated block allocated to the second target stream is already being used as a general-purpose block, the CPU 14 executes the first allocation process to set a new write-destination block for the second target stream. The flow of the first allocation process is as described above with reference to FIG10 . If no new user data has been written to the second general-purpose block (No in step S204), the CPU 14 returns the second general-purpose block to the dedicated block for the second object stream (step S206). The dedicated block is then used again as the write destination block for the second object stream. The CPU 14 then increments the target erased block count by 1 (step S207), terminating the allocation change process. If a write command specifying the second object stream is not received (No in step S203), the CPU 14 determines whether new user data is written to the second general-purpose block (step S208). If no new user data is written to the second general-purpose block (No in step S208), the CPU 14 returns to step S203. That is, if a write command specifying the second object stream is received after the dedicated block for the second object stream is changed to the second general-purpose block, the CPU 14 performs steps S203 through S207 to resume use of the second object stream. If user data is newly written to the second general-purpose block (YES in step S208 ), the CPU 14 terminates the allocation change process. Specifically, if user data is newly written to the second general-purpose block without receiving a write command specifying the second target stream, the CPU 14 determines that the second general-purpose block is being used as a general-purpose block. Through the above allocation change process, the CPU 14 can use the dedicated block allocated to the closed second object stream as a general-purpose block. Specifically, the CPU 14 can use the unwritten storage area within the dedicated block as a general-purpose block without wasting it. Furthermore, after changing the dedicated block to a general-purpose block, and before writing new user data to the general-purpose block, when the second object stream is resumed, the CPU 14 returns the general-purpose block to the dedicated block. In this way, the CPU 14 changes the usage of the allocated block based on the usage of the second object stream, thereby effectively utilizing the block's storage area. FIG12 is a flowchart showing an example of the flow of the second allocation process executed by the CPU 14. The second allocation process is a process for allocating general-purpose blocks. The CPU 14 executes the second allocation process, for example, in response to the completion of writing data to the entire general-purpose block serving as the write-destination block (the write-destination general-purpose block). First, the CPU 14 determines whether a general-purpose block different from the current write destination is included in the NAND flash memory 4 (step S31). The other general-purpose block is, for example, a general-purpose block that has been changed from the dedicated block of the stream in response to detection of stream closure. When another general-purpose block is included in the NAND flash memory 4 (YES in step S31 ), the CPU 14 sets the other general-purpose block as a new general-purpose block of the write destination (step S32 ), and ends the second allocation process. When another general purpose block is not included in the NAND flash memory 4 (No in step S31 ), the CPU 14 allocates the erased block as a new general purpose block for writing (step S33 ), and ends the second allocation process. By the above second allocation process, the CPU 14 can set either another general block or an erased block as a new write-destination general block in response to completion of data writing to the entire general block currently being written to. When another general-purpose block is set as the general-purpose block of the write destination, the CPU 14 can effectively utilize, for example, an unwritten area within the general-purpose block after the change from the dedicated block. Furthermore, when an erased block is allocated as a general-purpose block for writing, the CPU 14 can allocate the erased block as a general-purpose block without delay. The CPU 14 ensures that the erased block can be newly allocated as a general-purpose block at the time when writing data to the general-purpose block is completed. In other words, there will be no shortage of erased blocks to be newly allocated as general-purpose blocks at the time when writing data to the general-purpose block is completed. Therefore, even when the entire data has been written to the general block of the write destination, the CPU 14 can write the associated user data to the general block of the new write destination without delay based on a non-stream write command or a stream write command that specifies an unallocated dedicated block. As described above, this embodiment can reduce the delay in processing corresponding to a write request. The stream management unit 141 can manage multiple streams. The allocation control unit 142 allocates the first erased block in the multiple blocks included in the NAND flash memory 4, where the data erase operation is completed, as a general block. The general block can write data that is not associated with any of the multiple streams and data that is associated with any of the multiple streams. When the first stream is started, if two or more erased blocks in which the data erase operation is completed are included in the multiple blocks, the allocation control unit 142 allocates the second erased block as the write destination block corresponding to the first stream. When the first stream is started, if two or more erased blocks in which the data erase operation is completed are not included in the multiple blocks, the allocation control unit 142 sets the general block as the write destination block corresponding to the first stream. Thus, the write control unit 144 can write the associated user data to the write destination block, which is either the second erased block or the general-purpose block, without delay in response to a write request received in the first stream (e.g., a write command specifying the first stream). Therefore, in the memory system 3 with multi-stream functionality, the delay in processing write requests can be reduced. The various functions described in this embodiment can each be implemented by a circuit (processing circuit). Examples of processing circuits include a programmed processor such as a central processing unit (CPU). The processor performs the described functions by executing a computer program (command group) stored in memory. The processor can be a microprocessor that includes circuits. Examples of processing circuits also include a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a microcontroller, a controller, and other circuit components. Components other than the CPU described in this embodiment can also be implemented by a processing circuit. While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or modifications thereof are included within the scope and spirit of the invention and are included within the scope of the invention described in the claims and their equivalents. 1: Information processing system 2: Host / host device 3: Memory system 4: NAND flash memory 5: DRAM 6: Controller 10, 20: Bus 11: Host I / F 12: DRAM I / F 13: NAND I / F 14, 21: CPU 22: RAM 30, 30C: Non-stream 31, 31C: First stream 32, 32C: Second stream 33C: Third stream 34C: Fourth stream 41, 42, 61, 62, 63, 64, 65, 66, 67: User data 51: FW 52: Logical-physical address conversion table 53: Control information 141: Stream management unit 142: Allocation control unit 143: Erase control unit 144: Write control unit B0, B1, B2~Bm-1: Block DB1: First dedicated block / First general block DB2: Dedicated block / Second dedicated block EB0: Erased block EB1: Erased block / Erasing block GB: General block P0~Pn-1: Pages S31, S32, S33, S101, S102, S103, S104, S105, S106, S107, S108, S109, S110, S201, S202, S203, S204, S205, S206, S207, S208: Step WB0: Zeroth block WB1: First block WB2: Second block FIG1 is a block diagram illustrating an example configuration of an information processing system including a memory system according to an embodiment. FIG2 illustrates a situation in which, in a memory system according to a comparative example, insufficient erased blocks are available when multiple streams are started (opened) in a short period of time. FIG3 illustrates a situation in which, in a memory system according to a comparative example, insufficient erased blocks are available when data is written to the entirety of multiple blocks in a short period of time. FIG4 illustrates a situation in which, in a memory system according to a comparative example, storage area allocated to blocks of a stream is wasted. FIG5 illustrates an example of the operation of allocating a dedicated block to a stream that is starting to be used in the memory system according to the embodiment. FIG6 illustrates an example of the operation of setting a general-purpose block as the write destination block for a stream that is starting to be used in the memory system according to the embodiment. FIG7 illustrates an example of the operation of changing the write destination block of a stream from a general-purpose block to a dedicated block in the memory system according to the embodiment. FIG8 illustrates an example of the operation of using a dedicated block allocated to a stream that has ended its use as a general-purpose block in the memory system according to the embodiment. FIG9 is a diagram illustrating an example of operations in the memory system of the embodiment for changing a dedicated block allocated to a finished stream into a general-purpose block and then returning the dedicated block to the general-purpose block. FIG10 is a flowchart illustrating an example of the flow of a first allocation process executed in the memory system of the embodiment. FIG11 is a flowchart illustrating an example of the flow of an allocation change process executed in the memory system of the embodiment. FIG12 is a flowchart illustrating an example of the flow of a second allocation process executed in the memory system of the embodiment. S101, S102, S103, S104, S105, S106, S107, S108, S109, S110: Steps

Claims

1. A memory system capable of connecting to a host computer, the memory system comprising: Non-volatile memory, containing multiple blocks; The system includes a controller electrically connected to the non-volatile memory and configured to manage multiple streams. A first erased block, where data erasure has been completed within the multiple blocks, is allocated as a general block. This general block can be written to data not associated with any of the multiple streams, as well as data associated with any of the multiple streams. When the first stream is started, if two or more erased blocks where data erasure has been completed are included in the multiple blocks, a second erased block is allocated as a write destination block corresponding to the first stream. When the first stream is started, if two or more erased blocks where data erasure has been completed are not included in the multiple blocks, the general block is set as a write destination block corresponding to the first stream. The controller is further configured to, after predicting that the general block will be set as the write destination block corresponding to the first stream, include the third erased block in the plurality of blocks after the data erasure operation is completed, and allocate the third erased block as the write destination block corresponding to the first stream if a new erased block is obtained before the data is written to the general block as a whole.

2. The memory system as described in claim 1, wherein, The controller is configured to predict whether a new erased block will be acquired before the data is written to the entire general block, using the maximum data write speed for the general block and the time required to perform the data erasure operation on the blocks in the non-volatile memory.

3. The memory system as described in claim 1, wherein, The controller is further configured to, in response to the end of use of the first stream, change the third erased block, which was allocated as the write destination block corresponding to the first stream, to the general block.

4. The memory system as described in claim 3, wherein, The controller is further configured to, in response to restarting the use of the first stream after the third erased block has been changed to the general block and before writing new data to the third erased block that has been changed to the general block, reallocate the third erased block as a write destination block corresponding to the first stream.

5. The memory system as described in claim 1, wherein, The controller is further configured to, in response to the end of use of the first stream, change the second erased block, which was allocated as the write destination block corresponding to the first stream, to the general block.

6. The memory system as described in claim 5, wherein, The controller is further configured to, in response to restarting the use of the first stream after the second erased block has been changed to the general block and before writing new data to the second erased block that has been changed to the general block, reallocate the second erased block as a write destination block corresponding to the first stream.

7. The memory system as described in any one of claims 1 to 6, wherein, The controller is configured to determine a second number of erased blocks to be ensured based on a first number of streams used, and to perform the data erasure operation on blocks that do not store valid data within the plurality of blocks to ensure the second number of erased blocks.

8. The memory system as described in claim 7, wherein, The controller is configured to increase the second quantity by 1 when the first stream is started, and decrease the second quantity by 1 when the first stream is stopped.

9. The memory system as described in claim 1, wherein, The controller is further configured to, in response to receiving a first write request from the host that does not specify any stream, write the data associated with the first write request to the general block, and in response to receiving a second write request from the host that specifies the first stream, write the data associated with the second write request to the write destination block corresponding to the first stream.

10. The memory system as claimed in claim 1, wherein, The controller is further configured such that, when the writing of data to the entire second erased block, which is assigned as the write destination block corresponding to the first stream, is completed, if two or more erased blocks in which the data erasure operation is completed are included in the plurality of blocks, then the third erased block is assigned as the write destination block corresponding to the first stream; when the writing of data to the entire second erased block, which is assigned as the write destination block corresponding to the first stream, is completed, if two or more erased blocks in which the data erasure operation is completed are not included in the plurality of blocks, then the general block is set as the write destination block corresponding to the first stream.

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