Photonic integrated circuit device and method of forming the same

Abstract

A photonic integrated circuit (PIC) includes a stress structure that generates a stress field to enhance an optical device. This enhancement can amplify the optical mode of the optical device, control the optical mode of the optical device, induce a transition between a preferred TM mode and a preferred TE mode, thereby configuring the optical device to operate as a mode converter, increase the coupling efficiency of the optical device, alter the absorption spectrum of the optical device, or cancel stress noise to prevent the stress noise from degrading the performance of the optical device. The stress structure may consist of islands of material having a CTE mismatch or similar contrast with the surrounding material. The islands may be periodically spaced along the length of the device and may be symmetrically arranged on opposite sides of the device.

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 552,307, filed on February 12, 2024, the entire contents of which are incorporated herein by reference. Prior Art

[0002] Photonic integrated circuits (PICs) are widely used in communications and are increasingly being used for sensing and computing. PICs can operate at higher speeds than electronic integrated circuits (ICs) and can be combined with ICs to enhance functionality. PICs consist of two or more optical devices coupled to form a circuit. Examples of optical devices include waveguides, splitters, multiplexers, filters, modulators, sensors, and switches. PICs can interface with optical transmitters or receivers (such as lasers or optical fibers) using grating couplers, edge couplers, or similar devices. Simple diagram description

[0003] The aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Figure 1A shows a cross-sectional view of an optical device having a stress structure according to some embodiments, and Figure 1B shows a plan view thereof. Figure 1A is a cross-sectional view taken along line AA' of Figure 1B. 2 to 5 illustrate cross-sectional views of optical devices having stress structures according to various embodiments. FIG6 shows a plan view of an optical device having a stress structure according to another embodiment. 7 to 14 illustrate cross-sectional views of optical devices having stress structures according to various embodiments. Figure 15A shows a cross-sectional view of an optical device having a stress structure according to some embodiments, while Figure 15B shows a plan view thereof. Figure 15A is a cross-sectional view taken along line AA' of Figure 15B. 16A to 20A illustrate cross-sectional views of optical devices having stress structures according to various embodiments, while 16B to 20B illustrate plan views thereof. FIG "A" is a cross-sectional view taken along line AA' in FIG "B." 21A to 21C illustrate cross-sectional views of a mode converter having a stress structure according to an embodiment, while FIG. 21D illustrates a plan view thereof. FIG. 21A, FIG. 21B, and FIG. 21C are cross-sectional views taken along lines AA', BB', and CC', respectively, of the plan view of FIG. 21D. FIG22 is a graph showing the relationship between the TM mode and TE mode refractive index and stress for an exemplary waveguide and stress structure. 23A to 24A show cross-sectional views of a mode converter having a stress structure according to various embodiments, while FIG. 23B to 24B show plan views thereof. FIG. "A" is a cross-sectional view taken along line AA' in FIG. "B". 25 to 28 illustrate cross-sectional views of mode converters having stress structures according to various embodiments. Figure 29A shows a cross-sectional view of a PiN adjuster having a stress structure according to an embodiment, and Figure 29B shows a plan view thereof. Figure 29A is a cross-sectional view taken along line AA' of Figure 29B. Figure 30A shows a cross-sectional view of a ring resonator having a stress structure according to an embodiment, and Figure 30B shows a plan view thereof. Figure 30A is a cross-sectional view taken along line AA' of Figure 30B. FIG31A shows a cross-sectional view and FIG31B shows a plan view showing a group of electro-absorption regulators having various stress structures according to an embodiment. FIG31A is a cross-sectional view taken along line AA' of FIG31B. 32-51 provide a series of cross-sectional views illustrating processes according to some embodiments. FIG52 provides a flow chart illustrating a process according to some embodiments. FIG53 provides a flow chart illustrating a design process according to an embodiment. Implementation Method

[0004] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed.

[0005] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and similar terms may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0006] Optical devices can be very sensitive to changes in refractive index. These changes can be caused by stress. The optical propagation region of an optical device within a PIC can be subject to stress from adjacent structures with internal stress. Materials and structures can have internal stress due to manufacturing temperatures, mismatches in coefficient of thermal expansion (CTE) relative to surrounding materials, or other effects. If the stress field is unintended, it can tend to degrade the performance of the optical device.

[0007] Certain aspects of the present disclosure relate to a photonic integrated circuit (PIC) device comprising a stress structure that generates a stress field that enhances an optical device. In some embodiments, the enhancement expands the optical mode of the optical device (the wavelength range transmitted by the optical device). In some embodiments, the enhancement controls the mode of the optical device, causing a region of the optical device to be a preferred TM mode or a preferred TE mode. In some embodiments, the enhancement induces a conversion between a preferred TM mode and a preferred TE mode, causing the optical device to function as a mode converter. In some embodiments, the enhancement improves the coupling efficiency of the optical device. In some embodiments, the enhancement alters the absorption spectrum of the optical device. In some embodiments, the enhancement counteracts stress noise (unintended stress) to prevent the stress noise from degrading the performance of the optical device.

[0008] The stress structure may be the result of a coefficient-of-thermal expansion (CTE) mismatch with the adjacent material. The CTE mismatch is typically at least about 1 x 10-6 / K. In some embodiments, the CTE mismatch is typically at least about 5 x 10-6 / K. The difference between the manufacturing temperature and the operating temperature is typically at least about 200K. In some embodiments, the difference is at least about 500K. In some embodiments, the difference is at least about 800K. The stress structure may also be created by ion implantation or other processes that produce localized changes in the material's density or crystal structure. Typically, the stress structure is not part of any circuit or PIC other than providing stress to enhance the function of the optical device. In some embodiments, the stress structure has the same composition as the adjacent material, and the CTE mismatch is the result of differences in doping, density, crystal structure, or similar factors. Providing the stress structure with the same composition as the surrounding material can improve optical performance. In some embodiments, the stress structure has a different composition than the adjacent material. Using different materials for the stress structure helps control stiffness and CTE to produce a desired amount of stress.

[0009] In some embodiments, the stress structure comprises multiple islands of material that have a CTE mismatch or other material differences with adjacent materials, resulting in internal stress. In some embodiments, the adjacent material surrounds each island in a horizontal plane. In some embodiments, the islands are periodically spaced. This periodic spacing may induce low-amplitude oscillations in the stress field along the transmission path of the optical device. Providing the stress structure as a group of islands rather than a monolithic structure helps prevent excessive stress concentrations that could cause wafer cracking or warping.

[0010] In some embodiments, the islands are symmetrically arranged around the optical device. In some embodiments, the optical device defines a light transmission path, and the islands form rows 119 parallel to the light transmission path. In some embodiments, the islands form two or more rows on opposite sides of the optical device. In some embodiments, the islands are symmetrically arranged around the optical device to form four or more rows. In some embodiments, the stress structure has a rounded lower surface. In some embodiments, the stress structure has a rounded upper surface. In some embodiments, the stress structure has rounded side surfaces. The rounded structure provides a more uniform stress field.

[0011] The PIC device may include a buried oxide (BOX) substrate 117. The BOX substrate 117 includes a handle substrate 101, a buried oxide layer 103, and a top layer 105. The photonic integrated circuit portion is provided by the top layer 105. A capping layer 107 may be disposed on the top layer 105. Metal interconnect structures 115 having electrical connections to the PIC may be disposed on the capping layer 107. In some embodiments, a stress structure is embedded in the top layer 105.

[0012] In some embodiments, the stress structure is embedded in the cover layer 107. In some embodiments, the stress structure embedded in the cover layer 107 is adjacent to the optical device. In some embodiments, the stress structure embedded in the cover layer 107 is at the same height as the optical device. In some embodiments, the stress structure embedded in the cover layer 107 is located to the side of and above the optical device. In some embodiments, the stress structure embedded in the cover layer 107 is located directly above the optical device.

[0013] In some embodiments, the stress structure is embedded in the metallization layer 120 of the metal interconnect structure 115. In some embodiments, the stress structure is provided by dummy metal in the metallization layer 120. In some embodiments, the stress structure disposed in the metallization layer 120 shares a common composition with the interlayer dielectric layer 801 of the metallization layer 120, but has a CTE mismatch or other stress-inducing property difference with the interlayer dielectric layer 801. In some embodiments, the stress structure embedded in the metallization layer 120 has a different composition than the metal of the metallization layer 120 and the interlayer dielectric layer 801. In some embodiments, the stress structure embedded in the metallization layer 120 extends down into the capping layer 107.

[0014] An optical device can be any device that transmits, receives, propagates, generates, modifies, or detects an optical signal, any device that converts an optical signal into an electrical signal, or any device that converts an electrical signal into an optical signal. Examples of optical devices that transmit, receive, propagate, generate, modify, or detect an optical signal include waveguides 11, splitters, multiplexers, filters, modulators (e.g., phase shifters, PiN modulators 290, or electro-absorption modulators 310), sensors, switches (e.g., Mach-Zehnder interferometers), amplifiers, edge couplers, grating couplers, ring resonators 300, etc. Examples of optical devices that convert an electrical signal into an optical signal include laser diodes, light-emitting diodes, etc. Examples of optical devices that convert an optical signal into an electrical signal include photodiodes 190, etc. In some embodiments, a PIC contains multiple instances of an optical device, each associated with an equivalent and corresponding stress structure. In some embodiments, a PIC contains multiple instances of an optical device, each associated with one of a series of different stress structures. The range of corresponding stress structures can include systematic changes that provide a set of optical devices having a range of predetermined device characteristics.

[0015] In some embodiments, the optical device is a photodiode 190. The absorption spectrum of the photodiode 190 can be modulated by the stress structure. In some embodiments, the PIC includes a plurality of photodiodes 190 having a range of different absorption spectra, where the differences in the absorption spectra are modulated by the stress structure associated with the photodiodes 190.

[0016] In some embodiments, the optical device is an electroabsorption modulator 310. The absorption spectrum of the electroabsorption modulator 310 can be modulated by the stress structure. In some embodiments, the PIC includes multiple electroabsorption modulators 310 having a range of different absorption spectra, where the differences in the absorption spectra are determined by differences in the stress field modulated by the stress structure associated with the electroabsorption modulator 310.

[0017] In some embodiments, the optical device is a waveguide 11. In some embodiments, the waveguide 11 is in a preferred TM mode or a preferred TE mode due to the stress field modulated by the stress structure. In some embodiments, the optical device is a PiN regulator 290, and the stress structure regulates whether the PiN regulator 290 is in a preferred TM mode or a preferred TE mode at a specific operating voltage.

[0018] In some embodiments, the optical device is a ring resonator 300. The coupling wavelength of the ring resonator 300 can be tuned by a stress structure. In some embodiments, the PIC includes multiple ring resonators 300 with a range of different coupling wavelengths, where the differences in the coupling wavelengths are determined by differences in the stress field modulated by the stress structure associated with the ring resonator 300.

[0019] In some embodiments, the optical device is a mode converter 210. In some embodiments, the mode converter 210 functions via a stress structure. Specifically, the conversion between a preferred TM mode and a preferred TE mode between one end of the mode converter 210 and the other end is caused by a change in the stress field, which is related to a change in the distribution of stress structure components between one end of the mode converter 210 and the other end. The distribution of stress components can be variable in terms of the number of components, the proximity of the components to the mode converter 210, the height of the components, the width of the components, or the like.

[0020] In some embodiments, the stress structure includes islands symmetrically arranged on either side of the mode converter 210. In some embodiments, at a given location along the length of the mode converter 210, there are multiple islands on each of two opposing sides. The islands can be configured differently along the length, such that their number varies. In some embodiments, the islands at a given location along the length vary in height or width. These variations in island size, combined with the variations in their configuration along the length of the mode converter 210, help provide a nearly linear variation in refractive index along the length, making the mode converter 210 more efficient.

[0021] Certain aspects of the present disclosure relate to methods for fabricating a PIC device having a stress structure. The method may begin by providing a substrate. In some embodiments, the substrate is a BOX substrate 117. The PIC is formed by a process including etching a top layer 105 and depositing a capping layer 107 on the top layer 105. A metal interconnect structure 115 having electrical connections to the PIC may be formed on the capping layer 107.

[0022] In some embodiments, forming the stress structure includes etching and filling a hole. In some embodiments, the hole is formed in the top layer 105 such that the stress structure is embedded in the top layer 105. In some embodiments, the hole is formed in the capping layer 107. In some embodiments, the hole is formed in the interlayer dielectric layer 801 of the metal interconnect structure 115. In some embodiments, the hole formed in the interlayer dielectric layer 801 extends downward into the capping layer 107.

[0023] In some embodiments, the hole is refilled with the same type of material from which it was etched. In some embodiments, the hole is formed in silicon dioxide (SiO2) and refilled with silicon oxide (SiOx). In some embodiments, the hole is formed in silicon nitride (Si3N4) and refilled with silicon nitride (SixNy). In some embodiments, the hole is formed in a semiconductor and refilled with the semiconductor. Refilling with the same type of material can improve optical performance. Differences in deposition conditions between the original material and the replacement material, such as differences in deposition rate, can provide differences in the coefficients of thermal expansion of the original and replacement materials. In some embodiments, the replacement material differs from the original material in atomic ratios.

[0024] In other embodiments, the refill material has a different composition than the original material. Using a different composition helps provide the desired CTE difference from the surrounding material. This compositional difference can also help provide a stress structure with a rounded upper surface. If the refill material and the surrounding material have different polishing rates, chemical mechanical polishing (CMP) can be used to achieve the rounding of the upper surface. In some embodiments, forming the stress structure includes depositing a porous material. In some embodiments, forming the stress structure includes sol-gel technology. Sol-gel technology allows for the formation of materials with precisely controlled porosity and CTE.

[0025] In some embodiments, the stress structure is formed by ion implantation. In some embodiments, the ion implantation is followed by annealing. Ion implantation and annealing provide a stress structure that shares a composition and similar optical properties with the surrounding material, while having a different density or crystal structure. In some embodiments, ions are implanted into the top layer 105. In some embodiments, the ions are ions of silicon (Si) or the like. In some embodiments, ions are implanted into the capping layer 107. In some embodiments, the ions are ions of nitrogen (N), xenon (Xe), argon (Ar), or the like.

[0026] In some embodiments, the stressed structure is formed by laser annealing. Laser annealing is another method for forming a stressed structure that shares composition and similar optical properties with the surrounding material, while having a different CTE, density, or crystal structure. In some embodiments, laser annealing is applied to materials with a crystalline structure, such as the top layer 105. In some embodiments, laser annealing is applied to amorphous structures, such as the cap layer 107.

[0027] In some embodiments, the stress structure is provided by dummy metal in the metal interconnect structure 115. The dummy metal can be formed using the same process used to provide functional metal. Unlike conventional dummy metal structures used to prevent dishing during CMP, the position of the dummy metal, which serves as the stress structure, is determined with reference to the position of the optical device. In some embodiments, the dummy metal structures are arranged symmetrically with respect to the optical device. In some embodiments, the dummy metal structures include a row of islands that extend parallel to the optical transmission path of the optical device.

[0028] FIG1A shows a cross-sectional view of a PIC device 100. FIG1B shows a plan view of the PIC device 100. The PIC device 100 includes a waveguide 111 having a capping layer 107. The waveguide 111 is a rib-type waveguide and may be formed in a top layer 105 of an insulating layer substrate (BOX substrate) 117. The insulating layer substrate 117 includes a handle substrate 101, a buried oxide layer 103, and a top layer 105. The capping layer 107 is disposed on the insulating layer substrate 117, and a metal interconnect structure 115 may be disposed on the capping layer 107.

[0029] The stress structure 109A comprises a plurality of islands of material with intrinsic stress, which are embedded within the cladding layer 107 and exert stress on an optical propagation region (OPR) 113 associated with the waveguide 111. The stress changes the refractive index within the optical propagation region 113, particularly within the waveguide 111. The magnitude of the change may be sufficient to affect whether the waveguide 111 favors the TM mode or the TE mode.

[0030] The stress causes the refractive index in the waveguide 111 to change by at least about 5×10⁻¹⁵. In some embodiments, the refractive index change is at least about 2.5×10⁻¹⁵. Refractive index changes of these magnitudes may be sufficient to influence whether the waveguide 111 favors the TM mode or the TE mode. The refractive index change is anisotropic and can be achieved in a portion of the OPR 113 that comprises from about 5% to about 100% of the OPR 113 in a cross-section perpendicular to the light transmission direction 121 of the waveguide 111. In some embodiments, the stress structure 109A changes the pressure in the OPR by at least about 100 MPa. Pressures within this range can provide one of the aforementioned refractive index changes. The aforementioned ranges apply to any stress structure and optical device disclosed herein. The stress, strain, and refractive index changes involved in the present disclosure can be determined through mathematical modeling. The predictions of the mathematical model can be experimentally confirmed through techniques such as X-ray diffraction and Raman spectroscopy.

[0031] Waveguide 111 can have a width W1 ranging from about 1 μm to about 10 μm. In some embodiments, the islands of stress structure 109A have a width W2 ranging from about 1 μm to about 10 μm. In some embodiments, width W2 is less than width W1. In some embodiments, the islands of stress structure 109A have a spacing S1 (between rows 119) or a spacing S2 (within rows 119) ranging from about 1 μm to about 5 μm. In some embodiments, spacing S1 or spacing S2 is less than about 1 μm. These dimensions are suitable for generating localized stress that enhances the optical device while avoiding stress that causes warping or cracking.

[0032] In some embodiments, the islands of the stress structure 109A have the same composition as the capping layer 107. In some embodiments, the stress structure 109A has the composition of the capping layer 107 plus additional materials. In some embodiments, the stress structure 109A has the composition of the capping layer 107 but with differences in density or crystal structure. In some embodiments, the stress structure 109A has the same molecular composition as the capping layer 107, except for differences in atomic proportions. Alternatively, the islands of the stress structure 109A may have a completely different composition than the capping layer 107.

[0033] FIG2 shows a cross-sectional view of a PIC device 200 having a stress structure 109B according to another embodiment. While the island of stress structure 109A in FIG1A is positioned above waveguide 111, the island of stress structure 109B in FIG2 is lowered, so that a portion of stress structure 109B is coplanar (at the same height) with waveguide 111. Stress structure 109B can exert a greater force on waveguide 111 than stress structure 109A. On the other hand, stress structure 109A localized at or above waveguide 111 may be less likely to interfere with optical transmission.

[0034] FIG3 shows a cross-sectional view of a PIC device 300 having a stress structure 109C according to another embodiment. Stress structure 109C is similar to stress structure 109A of FIG1 , except that while stress structure 109A includes four rows of islands, two on each side of waveguide 111, stress structure 109C includes twelve rows of islands, six on each side of waveguide 111. For a symmetrical stress structure, there can be one to approximately ten rows of islands on each side of waveguide 111. In some embodiments, the stress structure is asymmetric relative to waveguide 111 or another optical device. Any of the illustrated stress structures can be made asymmetric by eliminating islands on one side of the optical device.

[0035] FIG4 illustrates a cross-sectional view of a PIC device 400 having a stress structure 109D according to another embodiment. Stress structure 109D is similar to stress structure 109B of FIG2 , except that the islands of stress structure 109D have rounded upper surfaces 401 in addition to rounded lower surfaces 403. Stress structure 109D may be completely embedded in capping layer 107, rather than having an upper surface adjacent to etch stop layer 405 at the bottom of metal interconnect structure 115.

[0036] FIG5 shows a cross-sectional view of a PIC device 500 having a stress structure 109E according to another embodiment. Stress structure 109E is similar to stress structure 109A of FIG1 , except that stress structure 109E comprises two wider islands arranged in two rows, one on each side of waveguide 111. The stress structures can be directly above, below, or to the sides of waveguide 111. When located to the sides, they can be spaced a distance D from waveguide 111. In some embodiments, distance D ranges from approximately 1 μm to approximately 20 μm. In some embodiments, distance D is approximately 1 μm or less. In some embodiments, the stress structure contacts waveguide 111 or other optical device. Direct contact can provide greater stress, but in some cases, direct contact can interfere with light transmission. In some embodiments, where the stress structure is above waveguide 111 or other optical device by a distance d, distance d ranges from approximately 0 μm to approximately 2 μm.

[0037] FIG6 shows a plan view of a PIC device 600 having a stress structure 109F according to another embodiment. Stress structure 109F illustrates the potential for variability in the positioning of individual islands within a group of islands comprising the stress structure. The islands of the stress structure can be spaced along the transmission direction 121 of the waveguide 111 to avoid excessive stress concentrations. The periodic spacing provides a generally uniform stress pattern, although oscillations in the stress pattern along the transmission direction 121 may be discernible. While periodic spacing is ideal to maintain uniform stress along the transmission direction 121, some uncertainty in the position of individual islands can be tolerated. In some embodiments, individual islands within a row of islands in the stress structure are permitted to deviate from the ideal periodic spacing by an amount less than or equal to approximately 25% of the island's width W2. This deviation can occur in any direction, for example, along or perpendicular to the transmission direction of the waveguide 111.

[0038] FIG7 shows a plan view of a PIC device 700 having a stress structure 109G according to another embodiment. The stress structure 109G comprises a row of islands embedded in the top layer 105. The islands of the stress structure 109G can have the same composition as the top layer 105, or they can have a completely different composition. In some embodiments, the stress structure 109G has the composition of the top layer 105 plus additional materials. In some embodiments, the stress structure 109G has the composition of the top layer 105, but with differences in density or crystal structure. In some embodiments, both the stress structure 109G and the top layer 105 are semiconductors.

[0039] FIG8 shows a cross-sectional view of a PIC device 800 having a stress structure 109H according to another embodiment. The stress structure 109H comprises an island embedded in an interlayer dielectric layer 801 of a metal interconnect structure 115. The stress structure 109H can be located directly above the waveguide 111. In some embodiments, the stress structure 109H comprises a composition of the interlayer dielectric layer 801.

[0040] FIG9 illustrates a cross-sectional view of a PIC device 900 having a stress structure 109I according to another embodiment. The stress structure 109I further includes a row of islands embedded in the interlayer dielectric layer 801. In some embodiments, the stress structure 109I is composed of dummy metal having the same composition as the conductive lines 901 of the metal interconnect structure 115. In some embodiments, the stress structure 109I has the composition of the interlayer dielectric layer 801 plus additional materials. In some embodiments, the stress structure 109I has the composition of the interlayer dielectric layer 801 but differs from the interlayer dielectric layer 801 in density or crystal structure.

[0041] 10 shows a cross-sectional view of a PIC device 1000 having a stress structure 109J according to another embodiment. The stress structure 109J includes a row of islands embedded in the interlayer dielectric layer 801. The islands of the stress structure 109J extend down into the cover layer 107, so that the stress structure 109J is also embedded in the cover layer 107.

[0042] FIG11 shows a cross-sectional view of a PIC device 1100 having a stress structure 109K according to another embodiment. The stress structure 109K includes a row of islands embedded in the interlayer dielectric layer 801. The islands of the stress structure 109K have rounded upper surfaces 1101, which may be produced by chemical mechanical polishing (CMP), and rounded lower surfaces 1103, which may be produced by a damascene process when etching relatively isotropically.

[0043] FIG12 shows a cross-sectional view of a PIC device 1200 having a stress structure 109L according to another embodiment. The stress structure 109L comprises a row of islands embedded in the interlayer dielectric layer 801 of the metal interconnect structure 115. The stress structure 109L is located in the same metallization layer 1201 as the conductive line 901, but is shorter than the conductive line 901 and has a different composition.

[0044] 13 shows a cross-sectional view of a PIC device 1300 having a stress structure 109M according to another embodiment. The stress structure 109M includes an island directly above and in direct contact with the top of the waveguide 111. The stress structure 109M may be embedded in both the interlayer dielectric layer 801 and the capping layer 107.

[0045] 14 shows a cross-sectional view of a PIC device 1400 having a stress structure 109N according to another embodiment. Stress structure 109N is similar to stress structure 109M of FIG. 13 but has a lower height.

[0046] FIG15A shows a cross-sectional view of a PIC device 1500 having a stress structure 109O according to another embodiment, and FIG15B shows a plan view thereof. PIC device 1500 includes a waveguide 1501. Waveguide 1501 is a strip-shaped type. Stress structure 109O has a higher coefficient of thermal expansion (CTE) than the surrounding material (cladding layer 107). A higher CTE means greater contraction when cooled from the manufacturing temperature. Consequently, the material surrounding the islands of stress structure 109O exerts tensile stress 1511 on the islands of stress structure 109O. Tensile stress 1511 is transmitted through cladding layer 107 and waveguide 1501, causing tensile stress 1509 to be applied to the sides of waveguide 1501. This tensile stress 1509 induces compressive stress 1507 at the top and bottom of waveguide 1501. The tensile stress 1509 on the sides of waveguide 1501 increases the refractive index in the horizontal direction, while the compressive stress 1507 at the top and bottom of the waveguide decreases the refractive index in the vertical direction. The overall effect is to make the waveguide 1501 a preferred TE mode.

[0047] FIG16A shows a cross-sectional view of a PIC device 1600 having a stress structure 109P according to another embodiment, and FIG16B shows a plan view thereof. PIC device 1600 includes a waveguide 1501. The stress structure 109P has a lower coefficient of thermal expansion (CTE) than the surrounding material (cladding layer 107). A lower CTE means less contraction when cooled from the manufacturing temperature. Consequently, the material surrounding the islands of stress structure 109P exerts compressive stress 1611 on the islands of stress structure 109P. This compressive stress 1611 is transmitted through the cladding layer 107 and waveguide 1501, causing compressive stress 1609 to be applied to the sides of waveguide 1501. This compressive stress 1609 induces tensile stress 1607 at the top and bottom of waveguide 1501. The compressive stress 1609 on the sides of waveguide 1501 reduces the refractive index in the horizontal direction, while the tensile stress 1607 at the top and bottom of the waveguide increases the refractive index in the vertical direction. The overall effect is to place waveguide 1501 in a preferred TM mode.

[0048] FIG17A shows a cross-sectional view of a PIC device 1700 having a stress structure 109Q according to another embodiment, and FIG17B shows a plan view thereof. PIC device 1700 includes a waveguide 111. The stress structure 109Q has a higher coefficient of thermal expansion (CTE) than the surrounding materials (the cover layer 107 and the interlayer dielectric layer 801). Consequently, the material surrounding the islands of stress structure 109Q exerts tensile stress 1711 on the islands of stress structure 109Q. This tensile stress 1711 is transmitted through the intermediate material, causing tensile stress 1709 to be applied to the sides of waveguide 111. Furthermore, compressive stress 1707 (shear stress) is generated within waveguide 111. The tensile stress 1709 on the sides of waveguide 111 increases the refractive index in the horizontal direction, while the compressive stress 1707 in the vertical direction decreases the refractive index in the vertical direction. The overall effect is to place waveguide 111 in a preferred TE mode.

[0049] FIG18A shows a cross-sectional view of a PIC device 1800 having a stress structure 109R according to another embodiment, and FIG18B shows a plan view thereof. PIC device 1500 includes a waveguide 111. The stress structure 109R has a higher coefficient of thermal expansion (CTE) than the surrounding materials (the cover layer 107 and the interlayer dielectric layer 801). Therefore, the material surrounding the islands of stress structure 109R exerts tensile stress 1811 on the islands of stress structure 109R. This tensile stress 1811 is transmitted through the intermediate material, causing tensile stress 1807 to be applied to the top of waveguide 111. Compressive stress 1809 (shear stress) is generated on the sides of waveguide 111. The compressive stress 1809 on the sides of waveguide 111 reduces the refractive index in the horizontal direction, while the tensile stress 1811 on the top of waveguide 111 increases the refractive index in the vertical direction. The overall effect is to place waveguide 111 in a preferred TM mode.

[0050] FIG19A shows a cross-sectional view of a PIC device 1900 having a stress structure 109S according to another embodiment, and FIG19B shows a plan view thereof. PIC device 1900 includes a photodiode 1901. Photodiode 1901 may include a germanium structure 1903 located within a portion of top layer 105, having a waveguide-like structure. Stress structure 109S includes islands of material under tensile stress 1911. Tensile stress 1911 is transmitted through capping layer 107 and top layer 105, causing tensile stress 1909 to be applied to the sides of germanium structure 1903. Furthermore, compressive stress 1907 may be generated in the germanium structure 1903 in a perpendicular direction. The overall effect is to alter the bandgap energy of germanium structure 1903, thereby changing the absorption spectrum of photodiode 1901.

[0051] FIG20A shows a cross-sectional view of a PIC device 2000 having a stress structure 109T according to another embodiment, and FIG20B shows a plan view thereof. PIC device 2000 includes a photodiode 1901. Stress structure 109T comprises islands of material under tensile stress 2011. The tensile stress 2011 is transmitted through the intermediate material, causing tensile stress 2009 to be applied to the sides of the germanium structure 1903. Furthermore, compressive stress 2007 may be generated in the germanium structure 1903 in a perpendicular direction. The overall effect is to alter the bandgap energy of the germanium structure 1903, thereby changing the absorption spectrum of the photodiode 1901. This movement may be different from the movement that occurs in the PIC device 1900 shown in FIG19A and FIG19B.

[0052] Figures 21A to 21C show a series of cross-sectional views of a PIC device 2100 including a mode converter 2103, and Figure 21D shows a plan view thereof. The mode converter 2103 comprises a waveguide 2105 and a stress structure 109U, which comprises two islands located on opposite sides of the waveguide 2105. The two islands of the stress structure 109U provide tensile stress 2101. The width of the stress structure 109U gradually narrows along the length of the waveguide 2105, causing the stress applied to the waveguide 2105 to vary along its length. At the end with the highest stress, the waveguide 2105 favors the TM mode. At the end with the lowest stress, the waveguide 2105 favors the TE mode.

[0053] Figure 22 provides a schematic diagram showing how the stress generated by an exemplary stress structure affects the refractive index of the TE and TM modes in an exemplary waveguide. When the stress increases from 100 MPa to 500 MPa, the TM mode refractive index increases by approximately 5 x 10⁻¹⁴, while the TE mode refractive index decreases by approximately 3.5 x 10⁻¹⁴. At 100 MPa, the TE mode refractive index is greater than the TM mode refractive index, indicating that the device favors the TE mode. At 500 MPa, the TM mode refractive index is greater than the TE mode refractive index, indicating that the device favors the TM mode.

[0054] Figure 23A shows a cross-sectional view of a PIC device 2300, which includes a mode converter 2301, and Figure 23B shows a plan view thereof. Mode converter 2301 comprises a waveguide 2105 and a stress structure 109V. Stress structure 109V includes eight rows of islands, two on each side of waveguide 2105. The lengths of the rows vary, with the rows closest to waveguide 2105 being the shortest. Variations in the number of islands and their distances from the waveguide 2105 along the length of the waveguide 2105 result in conversion between a preferred TE mode and a preferred TM mode along the length of the waveguide 2105.

[0055] FIG24A shows a cross-sectional view of a PIC device 2400 including a mode converter 2401, and FIG24B shows a plan view thereof. Mode converter 2401 includes a waveguide 2105 and a stress structure 109W. The stress structure 109W includes eight rows of islands, two on each side of the waveguide 2105. The lengths of the rows vary, with the rows furthest from the waveguide 2105 being the shortest. This results in the number of islands on the sides of the waveguide 2105 varying along its length. This variation in the number of islands enables conversion between a preferred TE mode and a preferred TM mode.

[0056] FIG25 shows a cross-sectional view of a PIC device 2500 including a mode converter 2501 having a stress structure 109X. The stress structure 109X can have an island layout similar to the stress structure 109V shown in FIG23B or a layout similar to the stress structure 109W shown in FIG24B. The stress structure 109X differs in that the islands of the stress structure 109X have different depths, with the islands closest to the waveguide 2105 being the deepest.

[0057] FIG26 shows a cross-sectional view of a PIC device 2600 including a mode converter 2601 having a stress structure 109Y. Stress structure 109Y can have an island layout similar to stress structure 109V, as shown in FIG23B , or a layout similar to stress structure 109W, as shown in FIG24B . Stress structure 109Y differs in that the islands of stress structure 109Y have varying depths, with deeper islands farther from the waveguide 2105. For a given application, the stress structure 109V of FIG23A-23B , the stress structure 109W of FIG24A-24B , or a combination of these stress structures with features of stress structure 109X of FIG25 or stress structure 109Y of FIG26 may provide the most efficient mode converter. Computer simulation and experimental confirmation can determine which is optimal.

[0058] Figures 27 and 28 provide additional options for implementing a mode converter using stress variations along the length of a waveguide. Figure 27 shows a cross-sectional view of a PIC device 2700 including a mode converter 2701 having a stress structure 109Z. The stress structure 109Z includes islands located at varying distances from the waveguide 2105 and embedded at varying depths in the cladding layer 107. The number and / or location of these islands can be varied along the length of the waveguide 2105 to achieve conversion between a preferred TE mode and a preferred TM mode.

[0059] FIG28 shows a cross-sectional view of a PIC device 2800 including a mode converter 2801 having a stress structure 109AA. The stress structure 109AA includes a stepped structure 2803. As shown in the cross-section, the steps of the stepped structure 2803 may be wider at the top or wider at the bottom. The number, length, or distance of the steps from the waveguide 2105 can be varied to achieve conversion between a preferred TE mode and a preferred TM mode.

[0060] FIG29A shows a cross-sectional view, and FIG29B shows a plan view, of an IC device 2900 including a PiN modulator 2901 modified by a stress structure 109BB. PiN modulator 2901 includes a waveguide 2903 located between a P-type doped region 2906 and an N-type doped region 2905 in a semiconductor top layer 105. Contact pads 2909 are connected to the P-type doped region 2906 and the N-type doped region 2905 via conductive lines 2907, allowing for control of the voltage between the P-type doped region 2906 and the N-type doped region 2905. Controlling the voltage can control the amplitude and phase of light passing through waveguide 2903. Stress structure 109BB modifies the relationship between voltage and the amplitude and phase of transmitted light, providing additional degrees of freedom in the design of PiN modulator 2901.

[0061] FIG30A shows a cross-sectional view and FIG30B shows a plan view of an IC device 3000 including a ring resonator 3001 modified by a stress structure 109CC. Ring resonator 3001 includes a closed-loop waveguide 3005 optically coupled to a straight waveguide 3003. The coupling wavelength of ring resonator 3001 is modulated by stress structure 109CC. IC device 3000 may include multiple ring resonators 3001, all similar except for differences in stress structure 109CC. These differences can be exploited to condition, filter, convert, or otherwise manipulate optical signals across a range of wavelengths.

[0062] FIG31A shows a cross-sectional view, and FIG31B shows a plan view, of an IC device 3100. The IC device 3100 includes a plurality of electro-absorption modulators 3101A to 3101D modified by stress structures 109DA to 109DD. Each electro-absorption modulator 3101A to 3101D includes a waveguide 3103 and a stack 3109 located above the waveguide 3103. The stack 3109 may include a quantum well formed by alternating layers of a first semiconductor 3105 and a second semiconductor 3107. At least one layer in the stack 3109 may be configured as an electrode. The absorption spectra of the electro-absorption modulators 3101A to 3101D are modulated by the stress structures 109DA to 109DD. The differences between the stress structures 109DA to 109DD result in each electro-absorption modulator 3101A to 3101D having a different absorption spectrum.

[0063] Figures 32 through 51 provide a series of cross-sectional views 3200 through 5100 illustrating a method for forming a PIC device having a stress structure according to the present disclosure. While Figures 32 through 51 are described with reference to various embodiments of the method, it should be understood that the structures illustrated in Figures 32 through 51 are not limited to the method and may exist independently of the method. Figures 32 through 51 are described as a series of steps. In other embodiments, the order of these steps may vary. While Figures 32 through 51 illustrate and describe a particular set of steps, in other embodiments, some steps may be omitted. Furthermore, other embodiments may include steps not illustrated and / or described.

[0064] As shown in cross-sectional view 3200 in FIG32 , the method may begin by providing a BOX substrate 117. The BOX substrate 117 includes a handle substrate 101, an oxide layer 103, and a top layer 105. The handle substrate 101 may be made of materials such as glass, ceramic, sapphire, or a semiconductor. The semiconductor may be silicon (Si), a III-V semiconductor or other binary semiconductor (e.g., GaAs), a ternary semiconductor (e.g., AlGaAs), or a higher-order semiconductor. The semiconductor may be doped or undoped. The oxide layer 103 may be, for example, silicon dioxide (SiO 2 ) or the like. The oxide layer 103 may serve as a capping layer for optical devices formed in the top layer 105. In some embodiments, the thickness of the oxide layer 103 ranges from approximately 0.5 μm to approximately 4 μm. The top layer 105 may include an optical material such as silicon (Si), silicon nitride (Si 3 N 4 ), lithium niobate (LiNbO 3 ), indium phosphide (InP), or the like. The top layer 105 has a higher refractive index than the oxide layer 103. In some embodiments, the top layer 105 is silicon. The silicon can be doped or undoped. In some embodiments, the thickness of the top layer 105 is in the range of about 100 nm to about 1.5 μm.

[0065] As shown in cross-sectional view 3300 of FIG33 , a mask 3301 can be formed and used to pattern the top layer 105 to form various optical structures, including, for example, waveguide 2903, waveguide 111, and the like. Mask 3301 and other masks used in this process can be photoresist or hard masks patterned using photoresist or the like. The hard mask can be, for example, silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxynitride (SiON), aluminum nitride (AlN), the like, or any other suitable material. Mask 3301 and other masks used in this process can be patterned using photolithography, electron beam lithography, the like, or any other suitable method.

[0066] As shown in cross-sectional view 3400 in FIG34 , a mask 3401 can be patterned and used to define the location of a stress structure 109G in the top layer 105. In some embodiments, the stress structure 109G is formed by etching and refilling exposed areas of the top layer 105. In some embodiments, the top layer 105 is a semiconductor, the refill process is an epitaxial growth process, and the stress structure 109G comprises a semiconductor. The semiconductor can be silicon (Si), silicon germanium (SiGe), or any other semiconductor that can be formed at elevated temperatures and has a coefficient of thermal expansion (CTE) mismatch with the top layer 105. In some embodiments, the refill process is a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. Examples of materials that may be deposited include amorphous semiconductors such as polysilicon, dielectrics, metals, or combinations thereof. The dielectric can be a low-k dielectric, silicon dioxide (SiO 2 ), a high-k dielectric, or the like. In some embodiments, the refill process utilizes a sol-gel technique or a similar technique. In some embodiments, the refill material is porous. In some embodiments, the top layer 105 is a dielectric optical material, such as silicon nitride (Si 3 N 4 ). The refill material has the same molecular composition as the dielectric optical material, but with a different atomic ratio, such as silicon nitride (Si x N y ).

[0067] In some embodiments, the stress structure 109G is formed by treating the exposed portion of the top layer 105 so that the stress structure 109G comprises the composition of the top layer 105 with appropriate modifications. In some embodiments, the treatment is ion implantation. In some embodiments, Si++ ions or similar ions are implanted. The implantation process may be followed by an annealing step, for example, at approximately 120°C for approximately 4 hours. In some embodiments, the treatment step is laser annealing. Ion implantation or laser annealing can alter the density and / or crystal structure of the optical material.

[0068] 35 , a mask 3501 may be formed and etched to further pattern the top layer 105. This second stage of processing may extend deeper into the top layer to form structures such as waveguide 1501, which may be a ribbon type.

[0069] As shown in cross-sectional view 3600 in FIG36 , capping layer 107 is deposited on patterned top layer 105. In some embodiments, capping layer 107 is an oxide. In some embodiments, capping layer 107 has the same composition as oxide layer 103. More generally, capping layer 107 can be silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), hafnium oxide (HfO 2), zirconium oxide (ZrO 2), aluminum oxide (Al 2 O 3), the like, or any other suitable capping layer material. Capping layer 107 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), the like, or any other suitable process. A planarization process can be performed after deposition of the capping layer. A second capping layer material (not shown) can be deposited to facilitate planarization. For example, borophosphosilicate glass (BPSG) or the like can be used to fill low spots on the silicon dioxide (SiO 2) capping layer. This second capping layer material is typically located outside the optical propagation region of the optical device but can be a source of stress noise.

[0070] As shown in cross-sectional view 3700 in FIG37 , contact plugs 3701 can be formed in cover layer 107 to provide electrical contact with the optical device. Contact plugs 3701 can be formed by etching a hole and filling it with a conductive material. The conductive material can be a metal or some other suitable type of material. The metal can be copper (Cu), silver (Ag), gold (Au), tungsten (W), cobalt (Co), aluminum (Al), the like, alloys thereof, or any other suitable metal. The conductive material can be deposited by CVD, PVD, electroplating, electroless plating, similar methods, or any other suitable process. Deeper contact plugs 3703 can be formed to contact handle substrate 101 or to provide electrical connection to structures subsequently formed on the backside of insulating layer substrate 117. Dummy versions of contact plugs 3703 can be used to provide stress structures.

[0071] As shown in cross-sectional view 3800 in FIG38 , a mask 3801 can be patterned and used to form stress structures 109A or the like at selected locations on the capping layer 107. In some embodiments, the stress structures 109A are formed by etching and refilling exposed areas of the capping layer 107. In some embodiments, the refill material has the same composition as the capping layer 107 but is deposited under different conditions, resulting in a different coefficient of thermal expansion (CTE) for the stress structures 109A than for the capping layer 107. In some embodiments, the refill material has the same atomic composition as the capping layer 107, but has a different atomic ratio to help provide the CTE difference. For example, both the capping layer 107 and the stress structures 109A can be Si x N y , Al x O y , Zr x Hf y O z , or the like. The refill process can be a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. In some embodiments, the refill process uses sol-gel technology or the like. In some embodiments, the refill material is porous.

[0072] In some embodiments, the stress structure 109A is formed by treating the exposed portion of the capping layer 107 so that the stress structure 109A comprises a suitably modified composition of the capping layer 107. In some embodiments, the treatment process is ion implantation. Examples of ions that may be suitable for implanting the capping layer 107 to alter the thermal expansion coefficient of the implanted region include xenon (Xe), argon (Ar), and nitrogen (N) plasma. The implantation process may be followed by an annealing step, for example, at 1000°C for approximately four hours. In some embodiments, the treatment process is laser annealing.

[0073] As shown in cross-sectional view 3900 of FIG. 39 , an etch stop layer 405 and an interlayer dielectric layer 801 may be formed on the capping layer 107. The etch stop layer 405 may be, for example, silicon nitride (Si 3 N 4 ), silicon carbide (SiC), silicon oxynitride (SiON), aluminum nitride (AlN), the like, or any other suitable material. The interlayer dielectric layer 801 may be silicon dioxide (SiO 2 ), a low-k dielectric material, the like, or any other suitable material. The interlayer dielectric layer 801 may be deposited by CVD, PVD, the like, or any other suitable process.

[0074] As shown in FIG40 , a cross-sectional view 4000 is formed and used to etch trenches 4003 and holes 4005 through the interlayer dielectric layer 801. As shown in FIG41 , a cross-sectional view 4100 is formed, and a metal 4101 is deposited to fill the trenches 4003 and holes 4005. The metal 4101 can be copper (Cu), silver (Ag), gold (Au), tungsten (W), cobalt (Co), aluminum (Al), or the like, alloys thereof, or any other suitable metal. The metal 4101 can be deposited by CVD, PVD, electroplating, electroless plating, the like, or any other suitable process.

[0075] As shown in cross-sectional view 4200 of FIG42 , a planarization process may be performed to remove metal 4101 deposited outside trench 4003 and hole 4005. The metal 4101 remaining in trench 4003 provides conductive line 901. The metal 4101 remaining in trench 4003 provides stress structure 109I. Conductive line 901 and interlayer dielectric layer 801 provide first metallization layer 4201. Stress structure 109I is a dummy metal structure within first metallization layer 4201. First metallization layer 4201 may include other dummy metal structures (not shown). These other dummy metal structures may not enhance any optical device.

[0076] As shown in cross-sectional view 4300 in FIG43 , a mask 4301 can be formed and used to etch a hole 4303 through interlayer dielectric layer 801. In some embodiments, hole 4303 extends into capping layer 107. As shown in cross-sectional view 4400 in FIG44 , mask 4301 can be stripped and material 4401 can be deposited to fill hole 4303. Material 4401 can be a dielectric material, a semiconductor, or a metal. In some embodiments, material 4401 is a dielectric material. In some embodiments, material 4401 has the same composition as interlayer dielectric layer 801. In some embodiments, material 4401 has the same composition as capping layer 107. Material 4401 can be deposited by CVD, PVD, electroplating, electroless plating, similar methods, or any other suitable process. In some embodiments, material 4401 is porous. In some embodiments, material 4401 is deposited using sol-gel techniques or similar methods.

[0077] As shown in cross-sectional view 4500 in FIG45 , a planarization process may be performed to remove material 4401 deposited outside of hole 4303. The remaining portion of material 4401 provides a stress structure 109J or other stress structure embedded in interlayer dielectric layer 801 or capping layer 107. The planarization process may be chemical mechanical polishing (CMP), a similar method, or any other suitable process. The planarization process may result in a rounded top portion of stress structure 109J.

[0078] As shown in the cross-sectional view 4600 of FIG46 , a via layer 4605 and additional metallization layers 4607 may be formed to complete the metal interconnect structure 115. The number of metallization layers 4607 may be greater or less than that shown. The via layer 4605 and additional metallization layers 4607 may be formed using a damascene process, a dual damascene process, the like, or any other suitable method.

[0079] 47 , an adhesive layer 4705 may be formed on the metal interconnect structure 115. The adhesive layer 4705 may include a passivation layer 4701, a passivation layer 4703, contact pads 2909, similar structures, or other suitable insulating, protective, and adhesive structures.

[0080] As shown in cross-sectional view 4800 of FIG48 , the BOX substrate 117 can be flipped over and thinned from the back side 4801. The thinning process can remove part or all of the handle substrate 101. Optionally, the front side 4803 of the BOX substrate 117 can be attached to a carrier substrate (not shown) before thinning.

[0081] As shown in cross-sectional view 4900 in FIG49 , substrate 101 can be processed to form through-substrate vias 4901 for coupling to deeper contact plugs 3703 and, in turn, to metal interconnect structures 115. As shown in cross-sectional view 5000 in FIG50 , metal interconnect structures 5001 and adhesive layer 5003 can be formed on backside 4801. As shown in cross-sectional view 5100 in FIG51 , BOX substrate 117 can then be bonded to a second substrate 5101. Second substrate 5101 can be a carrier substrate or another photonic or electronic integrated circuit device.

[0082] FIG52 presents a flow chart of a process 5200 for forming a PIC device according to the present disclosure. While process 5200 of FIG52 is illustrated and described herein as a series of acts or events, it should be understood that the order of these acts or events is not to be construed in a limiting manner. For example, certain acts may occur in a different order and / or concurrently with other acts or events than shown and / or described herein. Furthermore, not all illustrated acts are required to implement one or more aspects or embodiments described herein, and one or more acts depicted herein may be performed in one or more separate acts and / or stages.

[0083] Process 5200 may begin with step 5201, where a BOX substrate is provided. The BOX substrate comprises a handle substrate, an oxide layer, and a top layer. The top layer has a thickness and material suitable for waveguides and other optical devices. The cross-sectional view 3200 of FIG. 32 illustrates an example of this type of substrate. Alternatively, another type of substrate may be used.

[0084] Process 5200 may continue with step 5203, where an optical device is formed in the top layer. Forming the optical device in the top layer may include forming a mask, dry etching, wet etching, deposition, ion implantation, similar processes, or other suitable processes. Examples of optical devices that may be formed include waveguides, splitters, multiplexers, filters, modulators (e.g., phase shifters, PiN modulators, or electro-absorption modulators), sensors, switches (e.g., Mach-Zehnder interferometers), amplifiers, edge couplers, grating couplers, ring resonators, laser diodes, light-emitting diodes, photodetectors, and the like. Examples of such processes are provided in cross-sectional view 3300 of FIG. 33 and cross-sectional view 3500 of FIG. 35 .

[0085] Step 5205 is an optional step of forming embedded stress structures in the top layer. An example is provided in cross-sectional view 3400 of FIG. 34 . In some embodiments, these stress structures are formed by etching and filling holes in the top layer. In some embodiments, the stress structures are formed by locally processing the top layer.

[0086] Step 5207 is depositing a capping layer on the top layer. An example is provided in cross-sectional view 3600 of FIG. 36. Step 5209 is forming contact plugs in the capping layer to make electrical connections to the optical device. An example is provided in cross-sectional view 3700 of FIG. 37.

[0087] Step 5211 is an optional step of forming embedded stress structures in the cover layer. An example is provided in cross-sectional view 3800 of FIG. 38 . In some embodiments, these stress structures are formed by etching and filling holes in the cover layer. In some embodiments, the stress structures are formed by locally processing the cover layer.

[0088] Step 5213 is to form a first metallization layer on the capping layer. The cross-sectional views 3900-4200 of Figures 39 to 42 provide an example. In some embodiments, the location and shape of the dummy metal structures in the first metallization layer are designed to provide stress structures. Dummy metal in other metallization layers above the first metallization layer can also be used to provide or contribute to stress structures.

[0089] The first metallization layer includes an interlayer dielectric layer. Step 5215 is an optional step of forming embedded stress structures in the interlayer dielectric layer. Cross-sectional views 4300-4500 of Figures 43 to 45 provide an example. In some embodiments, these stress structures are formed by etching and filling holes in the interlayer dielectric layer. Such stress structures can extend into the cover layer. In some embodiments, the stress structures are formed in the interlayer dielectric layer by locally treating the interlayer dielectric layer. The stress structures can also be formed in the interlayer dielectric layer above the first metallization layer.

[0090] Step 5217 is an optional step of forming additional metallization layers and via layers to complete the formation of the metal interconnect structure. An example is provided in cross-sectional view 4600 of FIG. 46. Step 5219 is an optional step of forming an adhesive layer on the metal interconnect structure. An example is provided in cross-sectional view 4700 of FIG. 47. Step 5221 is an optional step of polishing or grinding to thin or remove the processed substrate. An example is provided in cross-sectional view 4800 of FIG. 48. Step 5223 is an optional step of forming through-substrate vias. An example is provided in cross-sectional view 4900 of FIG. 49. The through-substrate vias can optionally be used to provide a stress structure.

[0091] Step 5225 is an optional step of forming a metal interconnect structure on the back side. An example is provided in cross-sectional view 5000 of FIG. 50 . Step 5227 is an optional step of bonding to a carrier substrate or another integrated circuit device via the back side. An example is provided in cross-sectional view 5100 of FIG. 51 .

[0092] FIG53 presents a flow chart of a design process 5300 that can be used to design a PIC device according to the present disclosure. While process 5300 of FIG53 is illustrated and described herein as a series of steps or events, it should be understood that the illustrated order of these steps or events should not be construed as limiting. For example, certain steps may occur in a different order and / or concurrently with other steps or events illustrated and / or described herein. Furthermore, not all illustrated steps are required to implement one or more aspects or embodiments described herein, and one or more steps depicted herein may be performed in one or more separate steps and / or phases.

[0093] Design process 5300 may begin at step 5301 by collecting data on stress effects in the PIC. The focus may be on a specific optical device or group of devices in the PIC. This data may include strain measurements of the current design using X-ray diffraction, Raman spectroscopy, or similar techniques. Additional data may include the coefficient of thermal expansion (CTE), manufacturing temperature, the relationship between stress and strain, and the relationship between stress and refractive index.

[0094] Step 5303 is to build a mathematical model and perform computer simulations to represent the measured stresses. The model can be three-dimensional, although two-dimensional modeling may be sufficient. The model is adjusted until it reasonably matches the data.

[0095] Step 5305 is identifying enhancements to the optical device that can be achieved through stress structures. In some embodiments, this means identifying optical devices that are being adversely affected by unintended stresses. In some embodiments, this means identifying optical devices that can be tuned using stress.

[0096] Step 5307 proposes a stress structure to provide reinforcement. This disclosure provides numerous options for the location, shape, and composition of the stress structure. Step 5309 places the proposed structure into the model to determine whether it provides the desired reinforcement. In some embodiments, step 5309 includes determining whether the proposed stress structure offsets the unintended stresses. In some embodiments, step 5309 includes determining whether the proposed stress structure provides the desired accommodation. If the proposed stress structure does not provide the desired reinforcement, the proposed stress structure is modified and the simulation is repeated until satisfactory results are achieved.

[0097] Step 5311 is to experimentally determine whether the proposed stress structure provides the desired reinforcement. If the desired reinforcement is not achieved, the model can be updated to match the data and steps 5309 to 5311 can be repeated until the desired result is achieved.

[0098] Certain aspects of the present disclosure relate to a photonic integrated circuit device comprising a BOX substrate, a cover layer overlying the BOX substrate, and a metal interconnect structure overlying the cover layer. The PIC includes an optical device, wherein the top layer of the BOX substrate and the cover layer provide an optical propagation region. The stress structure is shaped and positioned to influence the stress field in the optical propagation region, thereby enhancing the optical device. In some embodiments, the stress structure is provided as a plurality of islands of material, each island having internal stress. In some embodiments, the internal stress is generated due to a mismatch in the coefficient of thermal expansion (CTE) with the surrounding material. In some embodiments, the internal stress is the result of ion implantation. In some embodiments, the islands are arranged symmetrically in two or more rows around the optical device. In some embodiments, the optical device defines a light transmission path, and the islands form a row of structures parallel to the light transmission path.

[0099] In some embodiments, the stress structure is embedded within a capping layer. In some embodiments, the stress structure is embedded within a top layer of a BOX substrate. In some embodiments, the stress structure is embedded within a metal interconnect structure. In some embodiments, the stress structure is provided by dummy metal within the metal interconnect structure. In some embodiments, the stress structure comprises the composition of the adjacent material and has a different density than the adjacent material. In some embodiments, the stress structure has the same composition as the adjacent material except for differences in atomic proportions.

[0100] In some embodiments, the optical device is a mode converter, and the stress structure causes a shift in the waveguide length along the mode converter from a preferred TM mode to a preferred TE mode. In some embodiments, the optical device is a photodiode, and the stress structure changes the absorption spectrum of the photodiode. In some embodiments, the optical device is a waveguide, and the stress structure affects whether the waveguide favors the TM mode or the TE mode. In some embodiments, the optical device is a PiN modulator comprising a waveguide, and the stress structure affects whether the waveguide favors the TM mode or the TE mode at a specific voltage. In some embodiments, the optical device is a ring resonator, and the stress structure affects the coupling wavelength of the ring resonator. In some embodiments, the optical device is an electroabsorption modulator, and the stress structure changes the relationship between the applied voltage and the absorption spectrum of the electroabsorption modulator.

[0101] Certain aspects of the present disclosure relate to a device including a photodiode (PIC). The PIC includes an optical device positioned within an optical transmission region. The optical transmission region includes an optical material and a cover layer. The optical device defines a light transmission path through the optical transmission region. A stress structure applies stress to the optical transmission region. The stress varies periodically along the light transmission path.

[0102] Certain aspects of the present disclosure relate to a method comprising providing a BOX substrate having a handle substrate, a buried oxide layer, and a top layer. A PIC comprising an optical device is formed by a process comprising etching the top layer and, after etching, depositing a capping layer on the top layer. A stress structure is formed at a first temperature. After cooling, the stress structure applies stress to the optical device. In some embodiments, forming the stress structure comprises ion implantation. In some embodiments, forming the stress structure comprises laser annealing. In some embodiments, forming the stress structure comprises depositing a porous material. In some embodiments, forming the stress structure comprises etching holes, filling the holes, and chemical mechanical polishing, wherein the chemical mechanical polishing rounds an upper surface of the stress structure. In some embodiments, a metal interconnect structure comprising a metallization layer is formed on the capping layer, and the metal interconnect structure comprises dummy metal providing the stress structure.

[0103] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that the aforementioned equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0104] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800: PIC device 101: Processing the substrate 103:Buried oxide layer 105: Top floor 107: Covering layer 109A, 109AA, 109B, 109BB, 109C, 109CC, 109D, 109DA, 109DB, 109DC, 109DD, 109E, 109F, 109G, 109H, 109I, 109J, 109K, 109L, 109M, 109N, 109O, 109P, 109Q, 109R, 109S, 109T, 109U, 109V, 109W, 109X, 109Y, 109Z: stress structure 11, 111, 1501, 2105, 2903, 3103: waveguide 113: Optical propagation area 115, 5001: Metal interconnect structure 117:BOX base / insulation layer base 119: OK 120, 1201: Metallization layer 121: Optical transmission direction 1509, 1511, 1607, 1709, 1711, 1807, 1811, 1909, 1911, 2009, 2011, 2101: Tensile stress 1507, 1609, 1611, 1707, 1809, 1907, 2007: compressive stress 190, 1901: Photodiode 1903: Germanium structure 210, 2103, 2301, 2401, 2501, 2601, 2701, 2801: Mode converter 2803: Ladder structure 2900, 3000, 3100: IC devices 290, 2901: PiN regulator 2906: P-type doped region 2905: N-type doped region 2909:Contact pad 3001: Ring Resonator 3005: Closed-loop waveguide 3003:Straight waveguide 300: Ring resonator 310, 3101A, 3101B, 3101C, 3101D: Electroabsorption Regulators 3109: Stack 3105:First Semiconductor 3107: Second Semiconductor 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900, 5000, 5100: Cross-section 3301, 3401, 3501, 3801, 4001, 4301: screen 3701, 3703: Contact plug 4003: Ditch 4005, 4303: hole 401, 1101: circular upper surface 403, 1103: Circular lower surface 405: Etching stop layer 4101:Metal 4201: First metallization layer 4401: Materials 4605:Through hole layer 4607:Metalization layer 4705, 5003: Adhesive layer 4701, 4703: passivation layer 4801: Dorsal 4803:Front 4901:Through hole 5101: Second base 5200:Process 5201, 5203, 5205, 5207, 5209, 5211, 5213, 5215, 5217, 5219, 5221, 5223, 5225, 5227, 5301, 5303, 5305, 5307, 5309, 5311: Steps 5300: Design Process 530: Behavior 801: interlayer dielectric layer 901, 2907: Wire D, d: distance S1, S2: Spacing W 1: Width W 2: Width

Claims

1. A photonic integrated circuit device, comprising: An embedded oxide substrate includes a substrate, a top layer, and an embedded oxide layer located between the substrate and the top layer; A cover layer, located above the top layer; A metallic interconnect structure disposed above the cover layer; a photonic integrated circuit including an optical device located within an optical propagation region, wherein the optical propagation region includes the top layer and the cover layer; and a stress structure comprising a plurality of islands of material with internal stress, wherein the stress structure influences the stress field in the optical propagation region to enhance the optical device.

2. The photonic integrated circuit device as claimed in claim 1, wherein the stress structure is embedded within the cover layer.

3. The photonic integrated circuit device as claimed in claim 1, wherein the stress structure comprises a composition of adjacent materials and has a density different from that of the adjacent materials.

4. The photonic integrated circuit device as claimed in claim 1, wherein the stress structure is embedded in the top layer.

5. The photonic integrated circuit device as claimed in claim 1, wherein the stress structure is provided by a dummy metal within the metal interconnect structure.

6. The photonic integrated circuit device as claimed in claim 1, wherein the islands are arranged symmetrically around the optical device in two or more rows.

7. The photonic integrated circuit device as claimed in claim 1, wherein the optical device includes an optical transmission path, and the islands are arranged in rows and parallel to the optical transmission path.

8. A photonic integrated circuit device, comprising: A photonic integrated circuit includes an optical device located within an optical propagation region, wherein the optical propagation region includes an optical material and a capping layer, and the optical device includes a light transmission path passing through the optical propagation region; and a stress structure that applies stress to the optical propagation region, the stress varying periodically along the light transmission path.

9. A method for forming a photonic integrated circuit device, comprising: A buried oxide substrate is provided, including a substrate, a buried oxide layer, and a top layer; a photonic integrated circuit is formed by means of a process including etching the top layer and depositing a capping layer on the top layer after etching, wherein the photonic integrated circuit includes an optical device; and a stress structure is formed at a first temperature, wherein the stress structure applies stress to the optical device after cooling.

10. The method of claim 9, wherein forming the stress structure includes etching holes, filling the holes, and chemical mechanical polishing, wherein the chemical mechanical polishing rounds the upper surface of the stress structure.

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