Semiconductor device and method for fabricating the same

Abstract

This invention discloses a method for manufacturing a semiconductor device, which mainly involves first providing a first wafer and a second wafer, then performing a first dicing process to divide the first wafer into a plurality of first dies, bonding the first dies to a second wafer, forming a first encapsulant layer around the first dies, forming first protrusions on the first dies, performing a second dicing process to divide the second wafer into a plurality of second dies, and then bonding the first dies to a third wafer.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a stacked structure by bonding a plurality of grains. [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the stacking density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in stacking density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages utilizing smaller areas compared to previous packages. Some smaller types of semiconductor component packages include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated chips (3DIC), wafer-level packages (WLP), and package-on-package (PoP) devices, etc. 3D integrated chips offer increased stacking density and other advantages, such as faster speeds and higher bandwidth, due to the reduced length of interconnects between stacked chips. However, many challenges remain to be addressed for 3D integrated wafer technology. [Summary of the Invention]

[0003] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly involves first providing a first wafer and a second wafer, then performing a first dicing process to divide the first wafer into a plurality of first dies, bonding the first dies to a second wafer, forming a first encapsulant layer around the first dies, forming first protrusions on the first dies, performing a second dicing process to divide the second wafer into a plurality of second dies, and then bonding the first dies to a third wafer.

[0004] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a first die bonded to a substrate, a second die disposed on the first die, a third die disposed on the second die, a fourth die disposed on the third die, and an encapsulant layer surrounding the first die, the second die, and the third die.

Implementation Method

[0006] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0007] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiments. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0008] Generally, terms can be understood at least in part according to their usage in context. For example, the term “one or more” (at least in part according to context) as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a plural combination of features, structures, or characteristics. Similarly, terms such as “a,” “an,” or “the” can again be understood to express a singular usage or convey a plural usage, at least in part according to context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and can conversely allow for the presence of additional factors that are not necessarily explicitly described, at least in part according to context.

[0009] It should be readily understood that the meanings of “on top of,” “above,” and “above” in the disclosure of this case should be interpreted in the broadest sense, such that “on top of” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers between them, and that “on top of” or “above” not only means being on or above something, but also includes the meaning of not having intermediate features or layers (i.e., being directly on something).

[0010] Furthermore, for ease of description, as illustrated in the figures, spatial relative terms such as “below,” “under,” “lower,” “above,” and “higher” may be used to describe the relationship (one or more) of one element or feature to another. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the element in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein may be interpreted accordingly.

[0011] As used herein, the term "substrate" refers to the material on which a layer of material is subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0012] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A single layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0013] Please refer to Figures 1 to 11, which are schematic diagrams of a method for fabricating semiconductor devices according to an embodiment of the present invention. As shown in Figure 1, a first wafer, such as wafer 12, and a second wafer, such as wafer 14, made of semiconductor materials are first provided. Each wafer 12 and 14 includes a substrate 16 made of semiconductor materials, and each substrate 16 can be selected from semiconductor substrates such as silicon substrates, epitaxial silicon substrates, silicon carbide substrates, or even substrates made of silicon-on-insulator (SOI). These material selections are all within the scope of the present invention. In this embodiment, each wafer 12 and 14 can be used in subsequent processes to fabricate various devices such as medium-voltage devices, high-voltage devices, pixel circuits, low-voltage devices of low-voltage drive circuits, and / or graphics processing units (GPUs).

[0014] Then, a front-end of line (FEOL) process and a back-end of line (BEOL) process are performed on wafers 12 and 14 respectively. In this embodiment, the front-end process may include fabricating, depending on the process or product, metal oxide semiconductor (MOS) transistors, oxide field-effect semiconductor (OS FETs), fin field-effect transistors (FinFETs), or other active and / or passive components on wafers 12 and 14. The back-end process may form metal interconnect structures, such as inter-metal dielectric layers 18 and metal interconnects 20, on these active and / or passive components. Taking the fabrication of metal-oxide-semiconductor transistors as an example, the front-end process may include forming a substrate with a gate structure on the substrate, sidewalls (not shown) disposed on the sidewalls of the gate structure, and source / drain regions disposed on both sides of the sidewalls. The gate structure may contain polysilicon or metal materials, the sidewalls may contain dielectric materials such as silicon oxide or silicon nitride, and the source / drain regions may contain different dopants depending on the conductivity type of the transistor, such as P-type dopants or N-type dopants.

[0015] Next, an interlayer dielectric layer can be formed on the substrate and cover metal-oxide-semiconductor transistors or other active components. Then, contact plugs and metal interconnects in the subsequent process are formed to form a plurality of contact plugs in the interlayer dielectric layer to connect the source / drain regions and the gate structure. The interlayer dielectric layer 18 is disposed on the interlayer dielectric layer and the metal interconnects 20 are disposed in the interlayer dielectric layer and connected to the contact plugs. The metal interconnects 20 on the topmost layer of the front side of each wafer 12 and 14 can also serve as the contact point of the direct bond interconnect (DBI), which can be docked with the direct bond interconnects of another wafer in the subsequent process. In this embodiment, the interlayer dielectric layer and the intermetal dielectric layer 18 may contain oxides such as, but not limited to, tetraethyl orthosilicate (TES). The contact plugs, metal interconnects 20, or direct bonding interconnects may contain aluminum, chromium, copper, tantalum, molybdenum, tungsten, or combinations thereof, but are not limited thereto.

[0016] It should be noted that in this embodiment, the substrate 16 of the wafer 12 is preferably provided with through-silicon vias (TSVs) 22 to connect the active components and / or passive components on the substrate 16, while the substrate 16 of the wafer 14 is preferably not provided with through-silicon vias to connect the components on the substrate.

[0017] Subsequently, as shown in Figure 2, a selective grinding process can be performed first to remove a portion of the substrate 16 of the wafer 12 from the back side of the wafer 12 to reduce its thickness. Then, a dicing process is performed to divide the wafer 14 into a plurality of first dies, such as dies 24, and the dies 24 are bonded to the wafer 12. According to an embodiment of the present invention, a hybrid bonding process can be performed to dock the dies 24 with the wafer 14. During the bonding process, each die 24 can be flipped so that the front side of the die 24 or the side exposing the metal interconnects 20 or the side directly bonding the interconnects faces the front side of the wafer 12 or the side exposing the metal interconnects 20. Then, the dies 24 are directly bonded to the metal interconnects 20 of the wafer 12 by means of, for example, heating, thereby forming a first stacked structure 26.

[0018] Next, as shown in Figure 3, an encapsulating layer 28 is formed on the wafer 12 and surrounds the die 24. A grinding process is then performed to remove a portion of the encapsulating layer 28, making the top surface of the remaining encapsulating layer 28 flush with the top surface of the die 24. The height of the encapsulating layer 28 in this stage is preferably between 700-800 micrometers or, most preferably, about 750 micrometers. According to one embodiment of the present invention, the encapsulating layer 28 may be an organic or inorganic thin film material such as oxide or fluorinated silicate glass (FSG). Furthermore, the encapsulating layer 28 may also contain polymer materials such as thermosetting polymers, thermoplastic polymers, or mixtures thereof. More specifically, polymeric materials may include plastic materials, epoxy resins, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethyl methacrylate (PMMA), polymeric components doped with specific fillers, or combinations thereof.

[0019] As shown in Figure 4, another polishing process is then performed to remove part of the die 24 and part of the encapsulant layer 28, reducing its height to approximately 3-5 micrometers. A contact pad process is then performed to form a redistribution layer (RDL) 30 and contact pads 32 on the upper surface of the die 24 or stacked structure 26. Then, bumps 34, such as micro bumps or solder balls, are formed on the contact pads 32. In this embodiment, the redistribution layer 30, contact pads 32, and bumps 34 may contain aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or alloys thereof, and are not limited thereto.

[0020] Next, as shown in Figure 5, a dicing process is performed to divide the stacked structure 26 or wafer 12 and the encapsulating layer 28 thereon into a plurality of second dies such as dies 36, and then the diced dies 36 are bonded to a third wafer such as wafer 38.

[0021] As shown in Figure 1, wafer 38 includes a substrate 16 made of semiconductor material, and various devices can also be formed on the substrate surface on wafer 38 according to the front-end process and the back-end process. The front-end process can fabricate, for example, metal oxide semiconductor (MOS) transistors, oxide field-effect semiconductor (OS FET), fin structure transistors (FinFET) or other active and / or passive devices on the wafer, while the back-end process can form metal interconnect structures such as inter-metal dielectric layer 18 and metal interconnect 20 on these active and / or passive devices.

[0022] According to an embodiment of the present invention, after the wafer 12 is cut using the aforementioned cutting process, the die 36 or the stacked structure 26 can be flipped so that the front side of the die 24 or the side exposing the protrusion 34 faces the front side of the wafer 38 or the side exposing the metal interconnect 20. Then, the stacked structure 26 and the wafer 38 are directly joined by means of, for example, heating to form a stacked structure 40.

[0023] Subsequently, as shown in Figure 6, an encapsulant layer 28 is formed around the grains 24 and 36, and a grinding process is performed to remove part of the encapsulant layer 28 so that the top surface of the remaining encapsulant layer 28 is flush with the top surface of the grains 36.

[0024] Then, as shown in Figure 7, the stacked structure 40 is first flipped, and a selective polishing process is performed to remove part of the substrate 16 of the wafer 38 to reduce its thickness. As shown in Figure 4, a contact pad process is performed to form a redistribution layer (RDL) 30 and contact pads 32 on one side of the wafer 38 or the first stacked structure 18, as shown on the upper surface. Then, bumps 34, such as micro bumps or solder balls, are formed on the contact pads 32. As described above, the redistribution layer 30, contact pads 32, and bumps 34 may contain aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), or alloys thereof, and are not limited thereto.

[0025] As shown in Figure 8, a dicing process is then performed to separate the stacked structure 40 or wafer 38 and the underlying encapsulant layer 28 into a plurality of third dies, such as dies 46, and the diced dies 46 are then bonded to a fourth wafer, such as wafer 48. It is worth noting that the width of the dies 46 formed in this stage after the above dicing process is preferably greater than that of dies 24 and dies 36, wherein the width of dies 36 is greater than that of dies 24.

[0026] As shown in Figure 5, wafer 48 includes a substrate 16 made of semiconductor material, and various devices can also be formed on the substrate surface on wafer 48 according to the front-end process and the back-end process. The front-end process can fabricate such as metal oxide semiconductor (MOS) transistors, oxide field-effect semiconductor (OS FET), fin structure transistors (FinFET) or other active devices and / or passive devices on the wafer, while the back-end process can form metal interconnect structures such as inter-metal dielectric layer 18 and metal interconnect 20 on these active devices and / or passive devices.

[0027] According to an embodiment of the present invention, after the wafer 38 is cut using the aforementioned cutting process, the die 46 or the stacked structure 40 can be flipped so that the front side of the die 46 or the side exposing the protrusion 34 faces the front side of the wafer 48. Then, the stacked structure 40 and the wafer 48 can be directly joined by means of, for example, heating to form the stacked structure 50.

[0028] Then, as shown in Figure 9, an encapsulant layer 28 is formed around the die 24, die 36, and die 46, and a grinding process is performed to remove part of the encapsulant layer 28 so that the top surface of the remaining encapsulant layer 28 is flush with the top surface of the die 36. Then the stacked structure 50 can be flipped, and a grinding process is performed to remove part of the substrate 16 of the wafer 48 to slightly reduce its thickness.

[0029] Then, as shown in Figure 10, the stacked structure 50 is flipped over, and a selective grinding process is performed to remove part of the die 36 and part of the encapsulant layer 28 and expose the silicon through-hole 22 in the die 36. Then, solder balls 54 are formed on the die 36 to connect the silicon through-hole 22.

[0030] As shown in Figure 11, the stacked structure 50 is then flipped again, and a dicing process is performed to separate the wafer 48 and the encapsulating layer 28 into a plurality of fourth dies, such as dies 52. The separated stacked structure 50 can then be connected to another substrate 56 or one side of a substrate, such as the upper surface, via an underfill layer 60, and a plurality of solder balls 58 are formed on the lower surface of the substrate 56. This completes the fabrication of a semiconductor device according to the present invention. It should be noted that although Figure 1 facilitates the formation of silicon through-hole vias 22 within the substrate 16 of the wafer 12, this sequence is not limited. According to other embodiments of the present invention, the formation of silicon through-hole vias 22 can be moved to before dicing after the plurality of dies have been stacked. For example, in Figure 1, wafers 12 and 14 without silicon through-holes in the substrate 16 can be provided first. Then, multi-layer die stacking is performed according to the process described in Figures 2 to 10. In Figure 10, the stacked structure 50 is flipped to form silicon through-holes 22 in the die 36 and solder balls 54 are connected to the silicon through-holes 22 on the die 36. This variation is also within the scope of the present invention.

[0031] Please continue to refer to Figure 11, which discloses a schematic diagram of the structure of a semiconductor device according to one embodiment of the present invention. As shown in Figure 11, the semiconductor device mainly includes four sets of dies, including a die 36 bonded to a substrate 56, a die 24 disposed on the die 36, a die 46 disposed on the die 24, a die 52 disposed on the die 46, and an encapsulant layer 28 surrounding the dies 36, 24, 46, and 52. In addition, the semiconductor device also includes protrusions 34 disposed between the die 24 and the die 46, and between the die 46 and the die 52, and solder balls 54 disposed between the bottommost die 36 and the substrate 56. In this embodiment, the dies preferably have different widths. For example, the width of the bottommost die 36 is preferably greater than the width of the die 24 above it, the width of the die 24 is smaller than the width of the die 46 above it, and the width of the die 46 is smaller than the width of the die 52. In other words, the second-layer grain 24 from the bottom up, or the grain 24 initially formed by cutting wafer 14, has the smallest width; the bottom-layer grain 36, or the grain 36 formed by cutting wafer 12 in Figure 5, has the second width or a width between grain 24 and grain 46; the third-layer grain 46 from the bottom up has the third width or a width between grain 36 and grain 52; and the top-layer grain 52 has the largest width.

[0032] In summary, this invention mainly discloses a wafer-to-wafer stacking technology for high bandwidth memory (HBM). The main process involves first performing a first dicing process to divide a first wafer into a plurality of first dies, then bonding these first dies to a second wafer, forming a first encapsulant layer surrounding the first dies, and forming first protrusions on the first dies. A second dicing process is then performed to divide the second wafer into a plurality of second dies, and finally bonding these first dies to a third wafer. Subsequently, the stacking die steps described above can be repeated to increase the required number of stacked structures according to process or product requirements.

[0033] According to one embodiment of the invention, the bonding methods between wafers and between stacked structures may include, but are not limited to, hybrid bonding processes, microbump bonding processes, or gold bump processes. The present invention can stack multiple wafers and then perform wafer probe testing (CP test) and repair steps via redistribution layers (RDLs), contact pads, and bumps on the stacked structure. This saves cycle time and cost compared to the conventional technique of performing probe testing first and then stacking wafers. The above description is only a preferred embodiment of the present invention. All equivalent variations and modifications made within the scope of the claims of the present invention should be considered within the scope of the present invention. [Simplified Explanation of the Diagram]

[0005] Figures 1 to 11 are schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that it comprises: performing a first dicing process to divide a first wafer into a plurality of first dies; bonding the first dies to a second wafer; forming a first encapsulant layer surrounding the first dies; forming first protrusions on the first dies; performing a second dicing process to divide the second wafer into a plurality of second dies; and bonding the first dies to a third wafer.

2. The method as described in claim 1, further comprising: forming a second encapsulating layer surrounding the first and second dies; forming a second protrusion on the third wafer; performing a third dicing process to divide the third wafer into a plurality of third dies; bonding the third dies to a fourth wafer; forming a third encapsulating layer surrounding the first, second, and third dies; forming solder balls on the second dies; and performing a fourth dicing process to divide the fourth wafer into a plurality of fourth dies.

3. The method as described in claim 2 further includes grinding the third wafer before forming the second protrusions.

4. The method as described in claim 2 further includes grinding the second grains and the third encapsulating layer before forming the solder ball.

5. The method as described in claim 1 further includes grinding the first grains and the first sealant layer before forming the first protrusion.

6. The method as described in claim 1, wherein the width of each of the first grains is smaller than the width of each of the second grains.

7. The method as described in claim 2, wherein the width of each of the first grains is smaller than the width of each of the third grains.

8. The method as described in claim 2, wherein the width of each of the third grains is smaller than the width of each of the fourth grains.

9. A semiconductor device, characterized in that it comprises: a first die bonded to a substrate; a second die disposed on the first die; a third die disposed on the second die; a fourth die disposed on the third die; and an encapsulating layer surrounding the first die, the second die, and the third die, wherein the top surface of the encapsulating layer is lower than the fourth die.

10. The semiconductor element as described in claim 9 further includes solder balls disposed between the first die and the substrate.

11. The semiconductor device as described in claim 9 further comprises: a first protrusion disposed between the second die and the third die; and a second protrusion disposed between the third die and the fourth die.

12. The semiconductor element as described in claim 9, wherein the second grain width is smaller than the first grain width.

13. The semiconductor element as described in claim 9, wherein the first grain width is smaller than the third grain width.

14. The semiconductor element as described in claim 9, wherein the width of the third die is smaller than the width of the fourth die.

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