Carbon replenishment of silicon-containing materials to reduce thickness loss

Abstract

An exemplary method of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The method may include contacting the structure with the etchant precursor. Contact with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. A method may also include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. The method may include contacting the structure with the carbon-containing precursor. Contact with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 669,136, filed on July 9, 2024, entitled “CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS TO REDUCE THICKNESS LOSS,” and U.S. Provisional Application No. 63 / 542,109, filed on October 3, 2023, entitled “NATIVE OXIDE REMOVAL AND CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIALS,” the entire disclosure of each of which is incorporated herein by reference for all purposes.

[0002] The present technology relates to methods and systems for semiconductor processing. More specifically, the present technology relates to systems and methods for replenishing carbon in silicon-containing materials after etching operations to prevent thickness loss of the silicon-containing materials during subsequent operations. Prior Art

[0003] Integrated circuits may be fabricated through processes that create complex patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing materials. As device sizes continue to decrease, film properties can significantly impact device performance. The materials used to form the material layers can affect the operating characteristics of the resulting device. As material thickness continues to decrease, the properties of the deposited films can significantly impact device performance.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality components and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary method of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The method may include contacting the structure with the etchant precursor. Contacting the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The method may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the carbon-containing precursor. Contacting the carbon-containing precursor may replenish carbon in the first silicon-containing material.

[0006] In some embodiments, the second silicon-containing material may be or include a silicon-and-oxygen material or a silicon-and-germanium material. The first silicon-containing material may be or include a silicon-and-carbon material. The etchant precursor may be or include a halogen-containing precursor. Contacting the structure with the carbon-containing precursor may increase the carbon content of the first silicon-containing material by greater than or approximately 0.1 atomic %. The carbon-containing precursor may be or include hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH 3-O-Si-(CH 3) 3), dimethyldimethoxysilane (DMDCS) ((CH 3) 2-Si-(OCH 3) 2), methyltrimethoxysilane (MTMS) ((CH 3-O) 3-Si-CH 3), phenyltrimethoxysilane (PTMOS) (C 6H 5-Si-(OCH 3) 3), phenyldimethylchlorosilane (PDMCS) (C 6H 5-Si(Cl)-(CH 3) 2), dimethylaminotrimethylsilane (DMATMS) ((CH 3) 2-N-Si-(CH 3) 3), or bis(dimethylamino)dimethylsilane (BDMADMS). The method may include exposing the structure to ultraviolet (UV) radiation while or after contacting the structure with the carbon-containing precursor. Contacting the structure with the carbon-containing precursor and exposing the structure to UV radiation may be performed simultaneously. The method may include providing a cleaning agent to a processing region of a semiconductor processing chamber after contacting the structure with the carbon-containing precursor. The method may include contacting the structure with the cleaning agent. Contact with the cleaning agent can remove residue from the structure.The temperature in the semiconductor processing chamber can be less than or about 500°C.

[0007] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include providing a first etchant precursor to a processing region of a semiconductor processing chamber, wherein a structure is disposed within the processing region. The structure may include alternating layers of a first silicon-containing material and a silicon-and-germanium-containing material. The structure may include a second silicon-containing material overlying and extending into one or more recesses defined by the alternating layers of the first silicon-containing material and the silicon-and-germanium-containing material. The method may include contacting the structure with the first etchant precursor. Contact with the first etchant precursor may etch through the alternating layers of the first silicon-containing material and the silicon-and-germanium-containing material. The method may include providing a first carbon-containing precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the first carbon-containing precursor. Contact with the first carbon-containing precursor may replenish carbon in the second silicon-containing material. The method may include providing a first cleaning agent to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the first cleaning agent. Contact with the first cleaning agent may remove a first residue from the structure. The method may include providing a second etchant precursor to a processing region of a semiconductor processing chamber. The method may include contacting a structure with the second etchant precursor. The contacting may etch a portion of a silicon-and-germanium-containing material. The method may include providing a silicon-and-germanium-containing precursor to the processing region. The method may include contacting the structure with the silicon-and-germanium-containing precursor. The contacting may deposit a third silicon-and-germanium-containing material on the structure. The third silicon-and-germanium-containing material may extend into a recess defined by the etched portion of the silicon-and-germanium-containing material. The method may include providing a third etchant precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the third etchant precursor. The contacting may etch a portion of the third silicon-and-germanium-containing material. After the contacting, remaining third silicon-and-germanium-containing material may extend into the recess defined by the etched portion of the silicon-and-germanium-containing material. The method may include providing a second carbon-and-carbon-containing precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the second carbon-and-carbon-containing precursor. Contact with a second carbon-containing precursor may replenish carbon in the third silicon-containing material. The method may include providing a second cleaning agent to a processing region of a semiconductor processing chamber. The method may include contacting the structure with the second cleaning agent. Contact with the second cleaning agent may remove a second residue from the structure. The method may include providing a fourth etchant precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the fourth etchant precursor. Contact with the fourth etchant precursor may remove dummy oxide material from the structure. The method may include providing a third carbon-containing precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the third carbon-containing precursor. Contact with the third carbon-containing precursor may replenish carbon in the second silicon-containing material. The method may include providing a fifth etchant precursor to the processing region of the semiconductor processing chamber. The method may include contacting the structure with the fifth etchant precursor. Contact with the fifth etchant precursor may remove silicon- and germanium-containing material from the structure. The method may include providing the fourth carbon-containing precursor to the processing region of the semiconductor processing chamber. The method can include contacting the structure with a fourth carbon-containing precursor.Contact with the fourth carbon-containing precursor may replenish carbon in the second silicon-containing material, the third silicon-containing material, or both.

[0008] In some embodiments, one or more of the first carbon-containing precursor, the second carbon-containing precursor, the third carbon-containing precursor, and the fourth carbon-containing precursor may be the same carbon-containing precursor. The second silicon-containing material, the third silicon-containing material, or both may be characterized by a dielectric constant of less than or approximately 7.5. Contacting the structure with the first carbon-containing precursor, the second carbon-containing precursor, the third carbon-containing precursor, or the fourth carbon-containing precursor may prevent thickness loss of the second silicon-containing material, the third silicon-containing material, or both during subsequent operations. One or more of the first etchant precursor, the second etchant precursor, the third etchant precursor, or the fourth etchant precursor may be or include a hydrogen-containing precursor, a nitrogen-containing precursor, a helium-containing precursor, a halogen-containing precursor, or an oxygen-containing precursor. The method may include depositing an epitaxial material on the structure before contacting the structure with the fourth etchant precursor.

[0009] Some embodiments of the present technology may encompass a semiconductor processing system. The system may include a first semiconductor processing chamber. The first semiconductor processing chamber may be configured to flow an etchant precursor to a processing region of the first semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The first semiconductor processing chamber may be configured to contact the structure with the etchant precursor. Contact with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The system may include a second semiconductor processing chamber on the same mainframe as the first semiconductor processing chamber. The second semiconductor processing chamber may be configured to flow a carbon-containing precursor to the processing region of the second semiconductor processing chamber. The second semiconductor processing chamber may be configured to contact the structure with the carbon-containing precursor. Contact with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

[0010] In some embodiments, a system may include a third semiconductor processing chamber on the same mainframe as the first and second semiconductor processing chambers. The third semiconductor processing chamber may be configured to flow a cleaning agent into a processing region of the third semiconductor processing chamber. The third semiconductor processing chamber may be configured to contact a structure with the cleaning agent. Contact with the cleaning agent may remove residue from the structure. The system may include a fourth semiconductor processing chamber on the same mainframe as the first, second, and third semiconductor processing chambers. The fourth semiconductor processing chamber may be configured to flow one or more deposition gases into a processing region of the fourth semiconductor processing chamber. The fourth semiconductor processing chamber may be configured to contact a structure with the one or more deposition gases. Contact with the one or more deposition gases may deposit an epitaxial material on the structure. The system may include one or more pre-treatment semiconductor processing chambers on the same mainframe as the first and second semiconductor processing chambers. The one or more pre-processing semiconductor processing chambers may be configured to etch a portion of the first silicon-containing material and the silicon and germanium-containing material, deposit a second silicon-containing material on the structure, and / or etch a portion of the second silicon-containing material.

[0011] This technology can provide several benefits over conventional systems and techniques. For example, embodiments of the present technology can increase the carbon concentration in a material that has already been depleted of carbon, which can increase resistance to subsequent etching operations (such as thermal, dry pre-cleaning). The increased resistance can allow subsequent operations to be performed on the structure, reducing or eliminating the removal of process material due to the increased carbon concentration. These and other embodiments, along with many of their advantages and features, are described in greater detail in conjunction with the following description and accompanying figures. Simple diagram description

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and drawings.

[0013] FIG. 1 illustrates a top plan view of an exemplary processing system in accordance with some embodiments of the present technology.

[0014] FIG. 2 illustrates a schematic cross-sectional view of an illustrative plasma deposition system in accordance with some embodiments of the present technology.

[0015] FIG. 3 illustrates operations in a semiconductor processing method, in accordance with some embodiments of the present technology.

[0016] 4A-4C illustrate cross-sectional views of processed structures according to some embodiments of the present technology.

[0017] FIG. 5 illustrates operations in a semiconductor processing method, in accordance with some embodiments of the present technology.

[0018] 6A-6I illustrate cross-sectional views of processed structures according to some embodiments of the present technology.

[0019] Several figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and are not to scale unless specifically noted as being to scale. Furthermore, as schematic diagrams, the figures are provided to aid understanding and may not include all aspects or information as compared to actual representations, and may include exaggerated material for illustrative purposes.

[0020] In the drawings, similar components and / or features may have the same reference number. Additionally, components of the same type may be distinguished by following the reference number with a letter that distinguishes between the similar components. If only the first reference number is used in this specification, the description applies to any similar component with the same first reference number, regardless of the letter. Implementation Method

[0021] As semiconductor device sizes continue to decrease, the constituent films included within the structures can impact device performance and the fabrication of other materials included within the devices. Furthermore, as demand increases, throughput and queue times become a concern. Consequently, there is a need for high-quality materials and structures that can be formed quickly and efficiently. However, in processes for forming conformal low-k silicon-containing materials, such as in gate-all-around (GAA) applications, high conformality and low k can result in poor resistance during subsequent etching operations. Due to carbon depletion in the silicon-containing material during trimming and other removal operations, the silicon-containing material may be completely removed during etching operations, such as cleaning operations using wet etchants.

[0022] To further increase conformality and lower the dielectric constant, conventional techniques can modify deposition precursors and deposit alternative materials, such as those containing silicon, oxygen, and carbon. While these techniques can be effective in depositing high-quality materials, they can be easily removed completely during subsequent operations due to their poor resistance to some etchants.

[0023] This technology overcomes these issues by intermittently processing silicon-containing materials with high conformality and low dielectric constant. After certain etching or ashing operations (such as spacer trimming, dummy gate removal, and / or channel release in GAA processing), the remaining silicon-containing material can be treated with a carbon-containing precursor during a carbon replenishment process and / or ultraviolet (UV) irradiation. This treatment returns depleted carbon to the silicon-containing material, thereby increasing the material's resistance to subsequent wet etching operations.

[0024] While the remainder of the disclosure will generally identify specific processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other operations and etching processes, such as may occur in the described chamber or any other chamber. Thus, the present technology should not be considered as limited to use with these specific deposition processes or a single chamber. Before describing additional variations and adjustments to this system according to embodiments of the present technology, the present disclosure will discuss a set of possible chambers that may be used to perform processes according to embodiments of the present technology.

[0025] FIG1 illustrates a top plan view of one embodiment of a processing system 100 including deposition, etching, baking, and curing chambers, according to an embodiment. In the figure, a pair of front-opening pods 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low-pressure holding area 106 before being placed into one of semiconductor processing chambers 108a-f, which are positioned in series sections 109a-c. A second robot 110 can be used to transport substrate wafers from the holding area 106 to the semiconductor processing chambers 108a-f and back. Each semiconductor processing chamber 108a-f can be equipped to perform a number of substrate processing operations, including forming stacks of semiconductor materials as described herein, in addition to plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, or other substrate processes including annealing, ashing, etc.

[0026] Semiconductor processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric or other films on substrates. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a stack of alternating dielectric films on a substrate. Any one or more of the processes described may be performed in a chamber separate from the fabrication system illustrated in various embodiments. It will be appreciated that additional configurations of chambers for depositing, etching, annealing, and curing dielectric films are contemplated by system 100.

[0027] FIG2 illustrates a schematic cross-sectional view of an exemplary plasma system 200 according to some embodiments of the present technology. The plasma system 200 may depict a pair of processing chambers 108 that may be adapted within one or more of the tandem sections 109 described above and may include panels or other components or assemblies according to embodiments of the present technology. The plasma system 200 may generally include a chamber body 202 having sidewalls 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0028] For example, processing region 220B (components of which may also be included in processing region 220A) may include a susceptor 228 disposed within the processing region through a channel 222 formed in a bottom wall 216 of the plasma system 200. The susceptor 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the susceptor (e.g., a body portion). The susceptor 228 may include heating elements 232, such as resistive heating elements, that can heat and control the substrate temperature to a desired processing temperature. The susceptor 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0029] The body of the pedestal 228 can be coupled to the rod 226 via a flange 233. The rod 226 can electrically couple the pedestal 228 to the power outlet or power box 203. The power box 203 can include a drive system that controls the height and movement of the pedestal 228 within the processing region 220B. The rod 226 can also include an electrical power interface to provide electrical power to the pedestal 228. The power box 203 can also include an interface for electrical power and a temperature indicator, such as a thermocouple interface. The rod 226 can include a base assembly 238 adapted to be removably coupled to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 can be a shoulder adapted to serve as a mechanical stop or platform configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0030] The rod 230 can be included through a channel 224 formed in the bottom wall 216 of the processing region 220B and can be used to position substrate lift pins 261 provided through the body of the pedestal 228. The substrate lift pins 261 can selectively separate the substrate 229 from the pedestal to facilitate exchange of the substrate 229 with a robot used to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0031] The chamber lid 204 can be coupled to the top of the chamber body 202. The lid 204 can house one or more precursor distribution systems 208 coupled thereto. The precursor distribution system 208 can include a precursor inlet channel 240 that delivers reactants and cleaning precursors through a gas delivery assembly 218 into the processing region 220B. The gas delivery assembly 218 can include a gas box 248 having a baffle plate 244 disposed between a faceplate 246. A radio frequency (RF) source 265 can be coupled to the gas delivery assembly 218. The RF source can power the gas delivery assembly 218 to facilitate the generation of a plasma region between the faceplate 246 and the pedestal 228 of the gas delivery assembly 218. The plasma region can be the processing region of the chamber. In some embodiments, the RF source can be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. Dielectric isolators 258 may be provided between the lid 204 and the gas delivery assembly 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 may be provided on the perimeter of the base 228 where it engages the base 228.

[0032] Optional cooling channels 247 may be formed in the gas box 248 of the gas distribution system 208 to cool the gas box 248 during operation. A heat transfer fluid (such as water, glycol, gas, or the like) may be circulated through the cooling channels 247 so that the gas box 248 can be maintained at a predefined temperature. A liner assembly 227 may be positioned proximate to the sidewalls 201, 212 of the chamber body 202 in the processing region 220B to prevent the sidewalls 201, 212 from being exposed to the processing environment within the processing region 220B. The liner assembly 227 may include a circumferential pumping cavity 225 that may be coupled to a pumping system 264 configured to exhaust gases and byproducts from the processing region 220B and control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas to flow from the processing region 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200 .

[0033] FIG3 illustrates exemplary operations in a semiconductor processing method 300 according to some embodiments of the present technology. The method can be performed in various processing chambers, including the system 200 described above. Method 300 may include one or more operations prior to initiating the method operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations, as indicated in the figure, which may or may not be specifically associated with methods according to the present technology. For example, many operations are described to provide a broader scope of semiconductor processes, but these operations are not critical to the technology or may be performed using alternative methodologies, as discussed further below.

[0034] Method 300 may involve optional operations for developing a semiconductor structure, including specific manufacturing operations. While in some embodiments, method 300 may be performed on a base structure, in some embodiments, the method may be performed after other materials have been formed or removed. For example, any number of deposition, masking, or removal operations may be performed to produce any transistor, memory, or other structural configuration on the substrate or structure. The substrate or structure may be disposed on a substrate support, which may be positioned within a processing region of a semiconductor processing chamber. The operations may be performed in the same chamber in which the configurations of method 300 are performed, and one or more operations may be performed in one or more chambers on a platform similar to the chamber in which the operations of method 300 are performed, or on another platform. Method 300 describes the operations schematically illustrated in Figures 4A through 4C, and descriptions of these operations will be incorporated into the description of the operations of method 300. It will be understood that Figures 4A through 4C are only partial schematic representations, and that the substrate may contain any number of transistor segments having the configurations shown.

[0035] As shown in FIG. 4A , structure 400 may include substrate 405. Substrate 405 may be made of or contain silicon or some other semiconductor substrate material. One or more material layers may be formed over substrate 405. The material layers may include, for example, a first layer of material 410. The first layer of material 410 may be, for example, a first silicon-containing material or an oxygen-containing material. In one embodiment, although not shown, the first layer of material 410 may include both the first silicon-containing material and the oxygen-containing material. The material layers may also include a second silicon-containing material 415. The second silicon-containing material 415 may be, for example, a silicon-and-oxygen-containing material, a silicon-and-nitrogen-containing material, or a silicon-oxygen-and-carbon-containing material. In one embodiment, the second silicon-containing material 415 may be characterized by a dielectric constant of less than or approximately 5.0.

[0036] At operation 305, method 300 may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber. At operation 310, method 300 may include contacting a substrate with an etchant precursor, which may be used to remove carbon-containing materials (e.g., carbon-containing spin-on materials) from substrate 405. For example, the etchant precursor may include a hydrogen-containing precursor, a nitrogen-containing precursor, an oxygen-containing precursor, a helium-containing precursor, a halogen-containing precursor, or any other conventional semiconductor precursor for removing silicon-containing materials and / or oxygen-containing materials. In one example, the one or more etchant precursors may include diatomic hydrogen (H2) and diatomic nitrogen (N2). The halogen-containing precursor may include, for example, a fluorine-containing precursor, a chlorine-containing precursor, or any other conventional semiconductor precursor for removing oxygen-containing materials (such as silicon- and oxygen-containing materials). In one example, the halogen-containing precursor may include dilute hydrofluoric acid (dHF) or any other wet halogen-containing etchant. In another example, the halogen-containing precursor may include diatomic fluorine (F2), nitrogen trifluoride (NF3), nitrogen trichloride (NCl3), boron trichloride (BCl3), or any other dry halogen-containing etchant. Other non-halogen-containing precursors, such as ammonia (NH3) or an inert gas, may also be provided with the etchant precursor. In one embodiment, method 300 may include forming a plasma of one or more etchant precursors to enhance bombardment and removal of silicon-containing materials and / or oxygen-containing materials.

[0037] The plasma effluent of the etchant precursor may be generated at a plasma power of less than or about 5000 W, and may be generated at a plasma power of less than or about 4500 W, less than or about 4000 W, less than or about 3500 W, less than or about 3000 W, less than or about 2750 W, less than or about 2500 W, less than or about 2250 W, less than or about 2000 W, less than or about 1750 W, less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less. While a plasma of the etchant precursor may be generated in some embodiments, other embodiments may include a thermal process that does not include generating a plasma of a halogen-containing precursor.

[0038] As shown in FIG. 4B , the contacting at operation 310 may etch at least a portion of the first layer of material 410 from substrate 405. Second silicon-containing material 415 may not be etched by the contacting at operation 410, but carbon depletion may occur at an upper portion and / or exposed portion of second silicon-containing material 415, such as on exposed sidewalls of second silicon-containing material 415. Thus, when the first layer of material 410 is etched from substrate 405 at operation 310, carbon may be depleted from a portion of second silicon-containing material 415, resulting in a carbon-depleted portion of second silicon-containing material 420. Prior to operation 310, the exposed surface of the second silicon-containing material 415 may be characterized by a carbon concentration greater than or about 5 atomic percent, such as greater than or about 6 atomic percent, greater than or about 7 atomic percent, greater than or about 8 atomic percent, greater than or about 9 atomic percent, greater than or about 10 atomic percent, greater than or about 11 atomic percent, greater than or about 12 atomic percent, greater than or about 13 atomic percent, greater than or about 14 atomic percent, greater than or about 15 atomic percent, greater than or about 16 atomic percent, greater than or about 17 atomic percent, greater than or about 18 atomic percent, greater than or about 19 atomic percent, greater than or about 20 atomic percent, greater than or about 21 atomic percent, greater than or about 22 atomic percent, greater than or about 23 atomic percent, greater than or about 24 atomic percent, greater than or about 25 atomic percent, or greater, as measured using X-ray photoelectron spectroscopy (XPS). During operation 310, carbon may be removed at a faster rate than other elements in the second silicon-containing material 415, such as silicon, oxygen, and other elements. Carbon may be outgassed during etching of the first layer of material 410. After operation 310, the second silicon-containing material 415 may be characterized by a carbon concentration of less than or about 15 atomic%, such as less than or about 14 atomic%, less than or about 13 atomic%, less than or about 12 atomic%, less than or about 11 atomic%, less than or about 10 atomic%, or less, which may be measured using XPS. In one embodiment, operation 310 may reduce the carbon concentration in the second silicon-containing material 415 (such as at the surface) by greater than or about 0.1 atomic%, greater than or about 0.5 atomic%, greater than or about 1 atomic%, greater than or about 1.5 atomic%, greater than or about 2 atomic%, greater than or about 2.5 atomic%, greater than or about 3 atomic%, greater than or about 4 atomic%, greater than or about 5 atomic%, greater than or about 7 atomic%, greater than or about 8 atomic%, greater than or about 9 atomic%, greater than or about 10 atomic%, or more. If untreated, the carbon-depleted portion of the second silicon-containing material 420 would be susceptible to damage and / or removal during subsequent operations, such as subsequent etching operations, such as thermal or dry pre-cleaning. Therefore, method 300 and the present technology may perform a carbon treatment to replenish the carbon in the carbon-depleted portion of the second silicon-containing material 420. The carbon treatment may repair the carbon-depleted portion of the second silicon-containing material 420 to increase resistance to subsequent etching operations, such as thermal or dry pre-cleaning.

[0039] To perform carbon processing, method 300 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber at operation 315. The carbon-containing precursor may be any precursor that includes carbon and may also include silicon and / or oxygen. In one embodiment, the carbon-containing precursor may be or include hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-O-Si-(CH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3-O)3-Si-CH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si(Cl)-(CH3)2), dimethylaminotrimethylsilane (DMATMS). ((CH 3) 2-N-Si-(CH 3) 3), or bis(dimethylamino)dimethylsilane (BDMADMS), and any other carbon-containing precursors that may be used in semiconductor processing. The precursors may or may not include the delivery of additional precursors, such as one or more carrier gases, to assist in the flow of the carbon-containing precursors. The carrier gas may include helium, argon, or diatomic nitrogen.

[0040] In one embodiment, method 300 may include generating a plasma of a carbon-containing precursor. The plasma effluent of the carbon-containing precursor may be generated at a plasma power of less than or about 3000 W, and may be generated at a plasma power of less than or about 2750 W, less than or about 2500 W, less than or about 2250 W, less than or about 2000 W, less than or about 1750 W, less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less. While in some embodiments a plasma of a carbon-containing precursor may be generated, other embodiments may include a thermal process that does not include generating a plasma of a carbon-containing precursor.

[0041] At operation 320, method 300 may include contacting the substrate with a carbon-containing precursor. Contacting the carbon-containing precursor may replenish carbon in the carbon-depleted portion of the second silicon-containing material 420. As shown in FIG. 4C , contacting may return the carbon-depleted portion of the second silicon-containing material 420 to a state similar to or identical to the second silicon-containing material 415. However, it is contemplated that contacting at operation 320 may not fully restore the carbon in the carbon-depleted portion of the second silicon-containing material 420. In one embodiment, contacting the second silicon-containing material 415 with the carbon-containing precursor at operation 320 may increase the carbon concentration at the exposed surface of the second silicon-containing material 415 by greater than or about 0.1 atomic %, such as greater than or about 0.5 atomic %, greater than or about 1 atomic %, greater than or about 1.5 atomic %, greater than or about 2 atomic %, greater than or about 2.5 atomic %, greater than or about 3 atomic %, greater than or about 4 atomic %, greater than or about 5 atomic %, greater than or about 7 atomic %, greater than or about 8 atomic %, greater than or about 9 atomic %, greater than or about 10 atomic %, or greater, which may be measured using XPS. In one embodiment, the increase in carbon concentration may involve the surface of the second silicon-containing material 415, but it is contemplated that the increase may also penetrate a portion of the second silicon-containing material 415.

[0042] At optional operation 325, method 300 may include exposing substrate 405 to ultraviolet (UV) radiation. The UV radiation source may be, for example, a UV lamp. The UV radiation source may be located outside the semiconductor processing chamber, and the semiconductor processing chamber may have a quartz window through which the UV radiation is transmitted. Structure 400 may be located in an inert gas environment, such as, for example, helium, argon, or diatomic nitrogen. The processing semiconductor chamber may include a microwave source to heat second silicon-containing material 415 prior to or concurrently with exposing the silicon-containing material to the UV radiation. In one embodiment, the UV radiation exposure may be performed using a plasma to simulate the UV radiation wavelength. The plasma may be formed by coupling RF power to a process gas, such as, for example, helium, argon, molecular oxygen, or diatomic oxygen. Exposure of the second silicon-containing material 415 to UV radiation may break Si—H and / or Si—OH bonds in the material, thereby allowing the formation of Si—CH 2 —CH 2 —Si(CH 3 ) 3 and / or Si—O—Si(CH 3 ) 3 bonds, thereby increasing the carbon concentration.

[0043] During operation 325, UV radiation conditions can be tailored to treat the second silicon-containing material 415. For example, the UV radiation power can be characterized as being between approximately 100 W / m² and approximately 2000 W / m². At UV radiation powers less than 100 W / m², the UV radiation may be insufficient to modify the material. At UV radiation powers greater than 2000 W / m², the UV radiation may damage the material or structure. Furthermore, the UV wavelength can be characterized as being between approximately 100 nm and approximately 400 nm. UV wavelengths below 100 nm may require specialized light sources that may not be commonly available. UV wavelengths above 400 nm, such as visible light, may not have sufficient energy to modify the bonds discussed previously.

[0044] In one embodiment, contacting the second silicon-containing material 415 with the carbon-containing precursor and exposing the substrate to ultraviolet (UV) radiation can be performed simultaneously. Specifically, operations 320 and 325 can be performed simultaneously to process the second silicon-containing material 415. However, it is contemplated that the operations can be performed sequentially in some embodiments.

[0045] At optional operation 330, after the contacting at operation 320 and / or the exposure to UV radiation at optional operation 325, method 300 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant and may be, for example, a fluorine-containing cleaner. In one embodiment, the fluorine-containing cleaner may be or include diluted hydrofluoric acid. The cleaning agent may also be a cleaning plasma, such as a halogen-containing plasma, a hydrogen-containing plasma, a nitrogen-containing plasma, a helium-containing plasma, or an oxygen-containing plasma. At optional operation 335, method 300 may include contacting substrate 405 with the cleaning agent. Contact with the cleaning agent may remove residues from substrate 405, such as native oxide or other residues from previous operations in method 300.

[0046] The operations of method 300 may be repeated for a second cycle and may be repeated for any number of cycles. Operations 505 to 540 of the second cycle or any subsequent cycle of method 300 may be similar to operations 305 to 330 previously discussed with respect to the first cycle of method 300 and may include any features or characteristics of such operations.

[0047] FIG5 illustrates exemplary operations in a semiconductor processing method 500 according to some embodiments of the present technology. The method can be performed in various processing chambers, including the system 200 described above. Method 500 may include one or more operations prior to initiating the method operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations, as indicated in the figure, which may or may not be specifically associated with the method according to the present technology. For example, many operations are described to provide a broader scope of semiconductor processes, but these operations are not critical to the technology or may be performed using alternative methodologies, as discussed further below.

[0048] Method 500 may involve optional operations for developing a semiconductor structure, including specific manufacturing operations. While in some embodiments, method 500 may be performed on a base structure, in some embodiments, the method may be performed after other materials have been formed or removed. For example, any number of deposition, masking, or removal operations may be performed to produce any transistor, memory, or other structural features on the substrate. The substrate may be positioned on a substrate support, which may be positioned within a processing region of a semiconductor processing chamber. The operations may be performed in the same chamber in which the aspects of method 500 are performed, and one or more operations may be performed in one or more chambers on a platform similar to the chamber in which the operations of method 500 are performed, or on another platform. Method 500 describes the operations schematically illustrated in Figures 6A through 6I , and descriptions of these operations will be incorporated into the description of the operations of method 500. It will be understood that Figures 6A through 6I are only partial schematic representations, and that the substrate may contain any number of transistor segments having the aspects shown in the figures.

[0049] As shown in FIG. 6A , structure 600 may include a substrate 605. Substrate 605 may be made of or contain silicon or some other semiconductor substrate material. One or more material layers may be formed over substrate 605. For example, alternating material layers may be deposited over substrate 605. The alternating material layers may include, for example, a layer of silicon-containing material 610 (such as silicon) and a layer of silicon and germanium-containing material 615 (such as silicon-germanium). Dummy gates 625, which may be replaced with metal in subsequent operations, may be deposited over the alternating layers of silicon-containing material 610 and silicon and germanium-containing material 615. Dummy gates 625 may be any suitable material, such as a silicon-containing material (e.g., silicon or polysilicon), an oxygen-containing material, or a metal-containing material (e.g., titanium-containing material), and may be separated from the alternating material layers by a layer of silicon-containing material 620 (such as silicon oxide or silicon nitride). Similarly, a layer of silicon-containing material 630 (such as silicon oxide or silicon nitride) may be formed over the dummy gate 625.

[0050] The gate spacer 635 can be formed on the substrate 605 overlying the previously described materials. The gate spacer 635 can be a silicon-containing material, such as a low-k material that can include silicon, oxygen, carbon, nitrogen, or a combination thereof. For example, the gate spacer 635 can be a silicon-and-oxygen material or a silicon-oxygen-and-carbon material. These conformal silicon-containing materials (such as silicon-and-oxygen materials or silicon-oxygen-and-carbon materials) exhibit lower dielectric constants compared to other conformal materials, making them useful in GAA applications. The silicon-containing material of the gate spacer 635 can be characterized by a dielectric constant less than or approximately 7.5, such as less than or approximately 7.0, less than or approximately 6.5, less than or approximately 6.0, less than or approximately 5.5, less than or approximately 5.0, or less. Furthermore, the silicon-containing material of the gate spacer 635 can have a conformality greater than or approximately 90%. However, as discussed below, subsequent GAA processing may utilize wet etchants, and these silicon-containing materials may be less resistant to these wet etchants or cleaners. This poor resistance poses a challenge to the use of these low-k conformal materials. During method 500, individual materials may be removed relative to other materials in structure 600. However, this removal operation may deplete one or more components, such as carbon, in the material to be maintained. A replenishment process may be performed to increase the concentration of one or more components, such as carbon, in the material to be maintained. This replenishment process can prevent thickness loss during subsequent operations.

[0051] At optional operation 505, method 500 may include pre-processing operations to prepare substrate 605 for further processing. For example, optional operation 505 may include operations for developing the GAA structure shown in FIG. 6A . Such operations may include, but are not limited to, depositing blanket films of silicon-containing material 610 and silicon and germanium-containing material 615. Operations may also include forming a layer of silicon-containing material 620, a dummy gate 625, and a layer of silicon-containing material 630. After forming silicon-containing material 630, gate spacers 635 may be formed over all layers.

[0052] At operation 510, method 500 may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber. For example, the etchant precursors may include a hydrogen-containing precursor, a nitrogen-containing precursor, an oxygen-containing precursor, a helium-containing precursor, a halogen-containing precursor, or any other conventional semiconductor precursor used to remove silicon-containing materials. In one example, the one or more etchant precursors may include a fluorine-containing precursor, a chlorine-containing precursor, an oxygen-containing precursor, and / or an inert gas. The inert gas may be or include argon, helium, neon, xenon, or any other rare and inert material used or useful in semiconductor processing. In one embodiment, method 500 may include forming a plasma of the one or more etchant precursors to enhance bombardment and removal of materials such as gate spacers 635, silicon-containing material 610, and silicon and germanium-containing material 615.

[0053] At operation 515, method 500 may include contacting substrate 605 with one or more etchant precursors. Method 500 may include etching a portion of the silicon-containing material (referred to as gate spacer 635) from substrate 605, as well as etching a cavity through silicon-containing material 610 and silicon-and-germanium-containing material 615. As shown in FIG. 6B , one or more etchant precursors may contact substrate 605 and remove a portion of gate spacer 635, silicon-containing material 610, and silicon-and-germanium-containing material 615. The etch may leave a portion of the silicon-containing material of gate spacer 635, such as a portion extending above the uppermost silicon-containing material 610 or silicon-and-germanium-containing material 615 of the alternating material layers. In one embodiment, operation 515 may be reactive ion etching (RIE) of the source and drain cavities in a GAA process.

[0054] After etching at operation 515, carbon may be depleted from the exposed portions of the silicon-containing material of the gate spacer 635. Thus, performing a carbon replenishment operation after operation 515 can prevent thickness loss of the gate spacer 635 during subsequent operations. In some embodiments, a pre-clean may be performed before the carbon replenishment operation to remove one or more residues from the gate spacer 635 that may limit the effectiveness of the carbon replenishment operation. At operation 520, method 500 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. Operation 520 may be similar to operation 315 discussed previously and may include any features or characteristics of that operation. At operation 525, method 500 may include contacting the substrate with the carbon-containing precursor. The contacting at operation 525 may replenish carbon in the gate spacer 635. Operation 525 may be similar to operation 320 discussed previously and may include any features or characteristics of that operation. In some embodiments, a pre-clean may be performed before operation 515 to remove one or more residues from the gate spacer 635 that may limit the effectiveness of the carbon replenishment operation.

[0055] Similar to method 300, method 500 may include exposing substrate 605 to UV radiation at optional operation 530. Optional operation 530 may be similar to operation 325 previously discussed and may include any features or characteristics of that operation.

[0056] At optional operation 535, method 500 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant and may be, for example, a fluorine-containing cleaning agent. In one embodiment, the fluorine-containing cleaning agent may be or include diluted hydrofluoric acid (dHF). The cleaning agent may also be a dry etchant, such as a fluorine-containing precursor, which may or may not be plasma-enhanced. At optional operation 540, method 500 may include contacting substrate 605 with the cleaning agent. After contacting at operation 525, the cleaning agent may be provided to clean structure 600, which may leave residue on one or more materials present on the substrate, such as oxygen-containing materials. Without performing carbon replenishment, carbon-depleted materials (such as gate spacers 635) may be etched at optional operation 535. However, after carbon replenishment, gate spacers 635 may be more resistant to cleaning at optional operations 535-540 and may not suffer thickness loss during cleaning.

[0057] At optional operation 545, method 500 may include performing a post-cleaning operation. For example, as shown in FIG. 6C , the layer of silicon-and-germanium-containing material 615 may be recessed relative to the layer of silicon-containing material 610. Furthermore, as shown in FIG. 6D , an internal spacer 640 may be deposited. The internal spacer 640 may be similar to the gate spacer 635 discussed previously and may include any of the features or characteristics of the gate spacer.

[0058] After performing the post-clean operation at optional operation 545, the operations of method 500 may be repeated for a second iteration. Operations 505 through 540 of the second iteration of method 500 may be similar to operations 505 through 540 previously discussed with respect to the first iteration of method 500 and may include any features or characteristics of such operations. First, any pre-treatment operations may be performed at optional operation 505 of the second iteration of method 500. At operation 510 of the second iteration of method 500, one or more etchant precursors may be provided to the processing region of the semiconductor processing chamber. For example, the one or more etchant precursors may include a fluorine-containing precursor, a chlorine-containing precursor, an oxygen-containing precursor, and / or an inert gas. In one embodiment, the second iteration of method 500 may include forming a plasma of the one or more etchant precursors to enhance the bombardment and removal of materials, such as internal spacers 640.

[0059] At operation 515 of the second iteration of method 500, substrate 605 may be contacted with one or more etchant precursors. Method 500 may include etching a portion of the silicon-containing material, referred to as internal spacer 640, from substrate 605. As shown in FIG. 6E , the one or more etchant precursors may contact substrate 605 and remove a portion of internal spacer 640. The etching may leave behind a portion of internal spacer 640, such as a portion extending into a recess defined by the alternating material layers of silicon-containing material 610 and silicon and germanium-containing material 615. In one embodiment, operation 515 of the second iteration of method 500 may be internal spacer RIE in GAA processing.

[0060] The etching at operation 515 of the second iteration of method 500 may deplete carbon from the exposed portions of the inner spacer 640 and / or gate spacer 635. Conversely, the oxygen concentration in the silicon-containing material of the inner spacer 640 may increase during the contacting at operation 525 of the second iteration of method 500. This may be due to the interaction between one or more etchant precursors (such as oxygen-containing precursors) and / or etch byproducts and the silicon-containing material of the inner spacer 640. To maintain the spacer 435 during subsequent operations (such as in GAA processing), it may be desirable or necessary to replenish the carbon in the inner spacer 640. Thus, a carbon replenishment process may be performed as discussed further below. However, the presence of any oxygen-containing material may also undesirably react with the carbon-containing precursor during the carbon replenishment process.

[0061] Similar to the increase in oxygen concentration in the silicon-containing material of inner spacer 640 during operation 525 of the second iteration of method 500, a portion of the layer of silicon-containing material 610 may also be oxidized when an oxygen-containing precursor or oxygen-containing byproduct is present. The oxidation of silicon-containing material 610 may form oxygen-containing material 644 on silicon-containing material 610. Additionally or alternatively, after etching a portion of the silicon-containing material (referred to as inner spacer 640) from substrate 605, substrate 605 may be moved to another processing area of ​​another semiconductor processing chamber. However, it is also contemplated that substrate 605 may remain in the same processing area of ​​the same semiconductor processing chamber. Regardless, as shown in FIG. 6E , after etching a portion of inner spacer 640, oxygen-containing material 644 (which may be referred to as a native oxide or surface oxide) may be present on silicon-containing material 610. Oxygen-containing material 644 may be an oxidized portion of silicon-containing material 610 that may be formed due to interaction with an etchant precursor and / or etch byproducts. Additionally or alternatively, oxygen-containing material 644 may be an oxidized portion of silicon-containing material 610 that may be formed due to exposure to ambient conditions. If untreated, carbon from a carbon replenishment process, as discussed further below, may combine with oxygen in oxygen-containing material 644, which may increase surface variability for subsequent GAA processing, such as during epitaxial growth operations. Thus, method 500 may include providing a halogen-containing precursor to a processing region of a semiconductor processing chamber for the purpose of removing oxygen-containing material 644.

[0062] The halogen-containing precursor may include, for example, a fluorine-containing precursor, a chlorine-containing precursor, or any other conventional semiconductor precursor used to remove oxygen-containing materials (such as silicon- and oxygen-containing materials). In one example, the halogen-containing precursor may include diluted hydrofluoric acid (dHF) or any other wet halogen-containing etchant. In another example, the halogen-containing precursor may include diatomic fluorine (F), nitrogen trifluoride (NF), nitrogen trichloride (NCl), boron trichloride (BCl), or any other dry halogen-containing etchant. Other non-halogen-containing precursors, such as ammonia (NH) or an inert gas, may also be provided along with the halogen-containing precursor. In one embodiment, a plasma of the halogen-containing precursor may be formed to enhance bombardment and removal of the oxygen-containing material 644.

[0063] The plasma effluent of the halogen-containing precursor may be generated at a plasma power of less than or about 5000 W, and may be generated at a plasma power of less than or about 4500 W, less than or about 4000 W, less than or about 3500 W, less than or about 3000 W, less than or about 2750 W, less than or about 2500 W, less than or about 2250 W, less than or about 2000 W, less than or about 1750 W, less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less. While a plasma containing a halogen-containing precursor may be generated in some embodiments, other embodiments may include a thermal process that does not include generating a plasma containing a halogen-containing precursor.

[0064] The method may include contacting the substrate 605 with a halogen-containing precursor. Contacting the substrate 605 and the oxygen-containing material 644 with the halogen-containing precursor may introduce the halogen material into the oxygen-containing material 644 of the silicon-containing material 610. Introducing and contacting the halogen material may etch a portion of the layer of silicon-containing material 610, such as the oxygen-containing material 644, from the substrate 605. The halogen-containing material may be provided in a liquid phase or a vapor phase, which may allow the halogen-containing precursor to fully contact the oxygen-containing material 644 of the silicon-containing material 610.

[0065] As discussed further below, contacting the oxygen-containing material 644 of the silicon-containing material 610 with a halogen-containing precursor or its plasma effluent can reduce the variability of the structure 600 after a subsequent carbon replenishment process may be performed. As previously discussed, without removing any oxygen-containing material 644, the carbon from the carbon replenishment process can combine with oxygen in the oxygen-containing material 440. The formation of CO bonds can increase surface variability during subsequent GAA processes, such as during epitaxial growth operations. Conversely, contacting can remove hydroxyl (-OH) bonds from the surface of the layer of silicon-containing material 644. Thus, contacting can remove surface caps that may be susceptible to carbon bonding during the carbon replenishment process.

[0066] The contacting may remove a portion of the oxygen-containing material 644 and / or the silicon-containing material 610. In embodiments, to ensure removal of the oxygen-containing material 644, the thickness of the removed portion of the layer of oxygen-containing material and / or silicon-containing material 641 may be greater than or about 10 Å, and may be greater than or about 15 Å, greater than or about 20 Å, greater than or about 25 Å, greater than or about 30 Å, greater than or about 35 Å, greater than or about 40 Å, greater than or about 45 Å, greater than or about 50 Å, greater than or about 55 Å, greater than or about 60 Å, or greater.

[0067] As previously discussed, the etching at operation 515 of the second iteration of method 500 may deplete carbon from exposed portions of the inner spacer 640 and / or gate spacer 635. Thus, performing a second carbon replenishment operation after operation 515 of the second iteration of method 500 may prevent thickness loss of the inner spacer 640 and / or gate spacer 635 during subsequent operations. At operation 520 of the second iteration of method 500, method 500 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. Operation 520 of the second iteration of method 500 may be similar to operation 520 of the first iteration of method 500 and / or operation 315 discussed previously and may include any features or characteristics of such operations. At operation 525 of the second iteration of method 500, method 500 may include contacting the substrate with the carbon-containing precursor. The contacting at operation 525 may replenish carbon in the inner spacer 640 and / or gate spacer 635. Operation 525 of the second iteration of method 500 may be similar to operation 525 of the first iteration of method 500 and / or operation 320 discussed previously and may include any features or characteristics of such operations. In one embodiment, a pre-clean may be performed prior to operation 520 of the second iteration of method 500 to remove one or more residues from the inner spacer 640 and / or the gate spacer 635 that may limit the effectiveness of the carbon replenishment operation.

[0068] Similar to the first iteration of method 500 and method 300, the second iteration of method 500 may include exposing substrate 605 to UV radiation at optional operation 530. Optional operation 530 of the second iteration of method 500 may be similar to operation 525 of the first iteration of method 500 and / or operation 325 discussed previously and may include any features or characteristics of such operations.

[0069] At optional operation 535, the second iteration of method 500 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant and may be, for example, a fluorine-containing cleaning agent. In one embodiment, the fluorine-containing cleaning agent may be or include dHF. The cleaning agent may also be a dry etchant, such as a fluorine-containing precursor that may or may not be plasma-enhanced. Operation 535 of the second iteration of method 500 may be similar to operation 535 of the first iteration of method 500 and may include any features or characteristics of such operation. At optional operation 540, the second iteration of method 500 may include contacting substrate 605 with the cleaning agent. Following the contacting at operation 525, the cleaning agent may be provided to clean structure 600, which may leave residue on one or more materials present on the substrate, such as oxygen-containing materials. Operation 540 of the second iteration of method 500 may be similar to operation 540 of the first iteration of method 500 and may include any features or characteristics of such operation. Without performing carbon replenishment, carbon-depleted materials, such as the inner spacers 640 and / or the gate spacers 635, may be etched at optional operation 535. However, the inner spacers 640 and / or the gate spacers 635 after carbon replenishment may be more resistant to cleaning at optional operations 535-540 and may not suffer thickness loss during cleaning.

[0070] At optional operation 545, method 500 may include performing a post-cleaning operation. For example, as shown in FIG. 6F , at optional operation 545 of the second iteration of method 500, epitaxial material 645 may be deposited on substrate 605. Furthermore, at optional operation 545 of the second iteration of method 500, interlayer dielectric material 650 may be formed over epitaxial material 645. Interlayer dielectric material 650 may be used to separate individual gates of the GAA structure.

[0071] The deposition of epitaxial material 645 may include an additional carbon replenishment operation. For example, in conventional deposition of epitaxial materials, one skilled in the art will recognize a process flow for depositing a P epitaxial hard mask material, patterning the hard mask material (possibly with additional mask material and subsequent removal of the additional mask), epitaxial growth, and stripping or removal of the hard mask material. Similarly, one skilled in the art will recognize a similar process flow for N epitaxial deposition. For example, one skilled in the art will recognize a process flow for depositing an N epitaxial hard mask material, patterning the hard mask material (possibly with additional mask material and subsequent removal of the additional mask), epitaxial growth, and stripping or removal of the hard mask material.

[0072] Although not shown in the figures, one skilled in the art will appreciate the possibility of replenishing carbon after patterning the hard mask material for both P-Epitaxial formation and N-Epitaxial formation, and stripping any remaining hard mask material after forming the epitaxial material 645. Thus, the present technique may include one or more carbon replenishment operations, such as operations 520-530 of method 500 or method 300, prior to any subsequent cleaning or etching operations. The carbon replenishment operation may reintroduce carbon to any exposed carbon-containing material, such as the inner spacer 640, which may be carbon-depleted when the hard mask material is patterned for both P-Epitaxial formation and N-Epitaxial formation, and any remaining hard mask material is stripped after forming the epitaxial material 645.

[0073] After performing a post-clean operation at optional operation 545, the operations of method 500 may repeat for a third iteration. Operations 505 through 540 of the third iteration of method 500 may be similar to operations 505 through 540 previously discussed with respect to the first and / or second iterations of method 500 and may include any features or characteristics of such operations. First, any pre-treatment operations may be performed at optional operation 505 of the third iteration of method 500. At operation 510 of the third iteration of method 500, one or more etchant precursors may be provided to a processing region of a semiconductor processing chamber. For example, the one or more etchant precursors may include a fluorine-containing precursor, a chlorine-containing precursor, an oxygen-containing precursor, and / or an inert gas. In one embodiment, the third iteration of method 500 may include forming a plasma of the one or more etchant precursors to enhance the bombardment and removal of materials (such as silicon-containing material 630 and / or dummy gate 625).

[0074] At operation 515 of the third iteration of method 500, substrate 605 may be contacted with one or more etchant precursors. The third iteration of method 500 may include etching a portion of silicon-containing material 630 and dummy gate 625 from substrate 605. As shown in FIG. 6G , one or more etchant precursors may contact substrate 605 and remove a portion of silicon-containing material 630 and dummy gate 625. The etching may completely remove silicon-containing material 630 and dummy gate 625. Alternatively, some remnants of silicon-containing material 630 and / or dummy gate 625 may remain on gate spacers 635 and / or silicon-containing material 620. In one embodiment, operation 515 of the third iteration of method 500 may be polysilicon pull in GAA processing.

[0075] The etching at operation 515 of the third iteration of method 500 may deplete carbon from the exposed portions of gate spacer 635. Thus, performing a third carbon replenishment operation after operation 515 of the third iteration of method 500 may prevent thickness loss of gate spacer 635 during subsequent operations. At operation 520 of the third iteration of method 500, method 500 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. Operation 520 of the third iteration of method 500 may be similar to operation 520 of the first iteration of method 500, operation 520 of the second iteration of method 500, and / or operation 315 discussed previously and may include any features or characteristics of such operations. At operation 525 of the third iteration of method 500, method 500 may include contacting substrate 605 with the carbon-containing precursor. The contacting at operation 525 may replenish carbon in gate spacer 635. Operation 525 of the third iteration of method 500 may be similar to operation 525 of the first iteration of method 500, operation 525 of the second iteration of method 500, and / or operation 320 discussed previously and may include any features or characteristics of such operations. In one embodiment, a pre-clean may be performed prior to operation 520 of the third iteration of method 500 to remove one or more residues from the gate spacers 635 that may limit the effectiveness of the carbon replenishment operation.

[0076] Similar to the first and second iterations of method 500 and method 300, the third iteration of method 500 may include exposing substrate 605 to UV radiation at optional operation 530. Optional operation 530 of the third iteration of method 500 may be similar to operation 525 of the first iteration of method 500, the second iteration of method 500, and / or operation 325 discussed previously and may include any features or characteristics of such operations.

[0077] At optional operation 535, the third iteration of method 500 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant and may be, for example, a fluorine-containing cleaning agent. In one embodiment, the fluorine-containing cleaning agent may be or include dHF. The cleaning agent may also be a dry etchant, such as a fluorine-containing precursor that may or may not be plasma-enhanced. Operation 535 of the third iteration of method 500 may be similar to operation 535 of the first iteration of method 500 and / or operation 535 of the second iteration of method 500 and may include any features or characteristics of such operations. At optional operation 540, the third iteration of method 500 may include contacting substrate 605 with the cleaning agent. Following the contacting at operation 525, the cleaning agent may be provided to clean structure 600, which may leave residue on one or more materials present on substrate 605, such as oxygen-containing materials. Operation 540 of the third iteration of method 500 may be similar to operation 540 of the first iteration of method 500 and / or operation 540 of the second iteration of method 500 and may include any features or characteristics of such operations. Without performing carbon replenishment, carbon-depleted material (such as gate spacers 635) may be etched at optional operation 535. However, gate spacers 635 after carbon replenishment may be more resistant to cleaning at optional operations 535-540 and may not suffer thickness loss during cleaning.

[0078] A third iteration of method 500 may include performing a post-cleaning operation at optional operation 545 .

[0079] At operation 515 of the fourth iteration of method 500, substrate 605 may be contacted with one or more etchant precursors. The fourth iteration of method 500 may include etching silicon-containing material 620 from substrate 605. As shown in FIG. 6H , the one or more etchant precursors may contact substrate 605 and remove a portion of silicon-containing material 620. The etching may completely remove silicon-containing material 620. Alternatively, some remnants of silicon-containing material 620 may remain on gate spacers 635. In one embodiment, operation 515 of the fourth iteration of method 500 may be dummy oxide removal in GAA processing.

[0080] The etching at operation 515 of the fourth iteration of method 500 may deplete carbon from exposed portions of gate spacers 635 and / or inner spacers 640. Thus, performing a third carbon replenishment operation after operation 515 of the fourth iteration of method 500 may prevent thickness loss of gate spacers 635 and / or inner spacers 640 during subsequent operations. At operation 520 of the fourth iteration of method 500, method 500 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. Operation 520 of the fourth iteration of method 500 may be similar to operations 520 of the first, second, and / or third iterations of method 500 and / or operation 315 discussed previously and may include any features or characteristics of such operations. At operation 525 of the fourth iteration of method 500, method 500 may include contacting substrate 605 with the carbon-containing precursor. The contacting at operation 525 may replenish carbon in gate spacers 635 and / or inner spacers 640. Operation 525 of the fourth iteration of method 500 may be similar to operation 525 of the first, second, and / or third iterations of method 500 and / or operation 320 discussed previously and may include any features or characteristics of such operations. In one embodiment, a pre-clean may be performed prior to operation 520 of the fourth iteration of method 500 to remove one or more residues from the gate spacers 635 that may limit the effectiveness of the carbon replenishment operation.

[0081] Similar to the first, second, and / or third iterations of method 500 and method 300, the fourth iteration of method 500 may include exposing substrate 605 to UV radiation at optional operation 530. Optional operation 530 of the fourth iteration of method 500 may be similar to operation 525 of the first, second, and / or third iterations of method 500 and / or operation 325 discussed previously and may include any features or characteristics of such operations.

[0082] At optional operation 535, the fourth iteration of method 500 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant, and may be, for example, a fluorine-containing cleaning agent. In one embodiment, the fluorine-containing cleaning agent may be or include dHF. The cleaning agent may also be a dry etchant, such as a fluorine-containing precursor that may or may not be plasma-enhanced. Operation 535 of the fourth iteration of method 500 may be similar to operation 535 of the first, second, and / or third iterations of method 500 and may include any features or characteristics of such operations. At optional operation 540, the fourth iteration of method 500 may include contacting substrate 605 with the cleaning agent. Following the contacting at operation 525, the cleaning agent may be provided to clean structure 600, which may leave residue on one or more materials present on substrate 605, such as oxygen-containing materials. Operation 540 of the fourth iteration of method 500 may be similar to operation 540 of the first, second, and / or third iterations of method 500 and may include any features or characteristics of such operations. Without performing carbon replenishment, carbon-depleted materials, such as the gate spacers 635 and / or the inner spacers 640, may be etched at optional operation 535. However, the gate spacers 635 and / or the inner spacers 640 after carbon replenishment may be more resistant to cleaning at optional operations 535-540 and may not suffer thickness loss during cleaning.

[0083] A fourth iteration of method 500 may include performing a post-cleaning operation at optional operation 545 .

[0084] The operations of method 500 may be repeated for a fifth iteration. Operations 505 through 540 of the fifth iteration of method 500 may be similar to operations 505 through 540 previously discussed with respect to the first, second, and / or third iterations of method 500 and may include any features or characteristics of such operations. First, any pre-processing operations may be performed at optional operation 505 of the third iteration of method 500. At operation 510 of the fifth iteration of method 500, one or more etchant precursors may be provided to the processing region of the semiconductor processing chamber. For example, the one or more etchant precursors may include a fluorine-containing precursor, a chlorine-containing precursor, an oxygen-containing precursor, and / or an inert gas. In one embodiment, the fifth iteration of method 500 may include forming a plasma of the one or more etchant precursors to enhance the bombardment and removal of materials, such as the alternating layers of silicon- and germanium-containing material 615.

[0085] At operation 515 of the fifth iteration of method 500, substrate 605 may be contacted with one or more etchant precursors. Method 500 may include etching a portion of the alternating layers of silicon-and-germanium-containing material 615 from substrate 605. As shown in FIG. 6I , the one or more etchant precursors may contact substrate 605 and remove a portion of the alternating layers of silicon-and-germanium-containing material 615. The etching may completely remove the alternating layers of silicon-and-germanium-containing material 615. Alternatively, some remnants of the alternating layers of silicon-and-germanium-containing material 615 may remain on gate spacers 635. In one embodiment, operation 515 of the fifth iteration of method 500 may be a channel release in a GAA process.

[0086] The etching at operation 515 of the fifth iteration of method 500 may deplete carbon from exposed portions of gate spacers 635 and / or inner spacers 640. Thus, performing a fifth carbon replenishment operation after operation 515 of the fifth iteration of method 500 may prevent thickness loss of gate spacers 635 and / or inner spacers 640 during subsequent operations. At operation 520 of the fifth iteration of method 500, method 500 may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. Operation 520 of the fifth iteration of method 500 may be similar to operations 520 of the first, second, third, and / or fourth iterations of method 500 and / or operation 315 discussed previously and may include any features or characteristics of such operations. At operation 525 of the fifth iteration of method 500, method 500 may include contacting substrate 605 with the carbon-containing precursor. The contacting at operation 525 may replenish carbon in gate spacers 635 and / or inner spacers 640. Operation 525 of the fifth iteration of method 500 may be similar to operation 525 of the first, second, third, and / or fourth iterations of method 500 and / or operation 320 discussed previously and may include any features or characteristics of such operations. In one embodiment, a pre-clean may be performed prior to operation 520 of the fifth iteration of method 500 to remove one or more residues from the gate spacers 635 that may limit the effectiveness of the carbon replenishment operation.

[0087] Similar to the first, second, third, and / or fourth iterations of method 500 and method 300, the fifth iteration of method 500 may include exposing substrate 605 to UV radiation at optional operation 530. Optional operation 530 of the fifth iteration of method 500 may be similar to operation 525 of the first, second, third, and / or fourth iterations of method 500 and / or operation 325 discussed previously and may include any features or characteristics of such operations.

[0088] At optional operation 535, the fifth iteration of method 500 may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The cleaning agent may be any wet etchant, and may be, for example, a fluorine-containing cleaning agent. In one embodiment, the fluorine-containing cleaning agent may be or include dHF. The cleaning agent may also be a dry etchant, such as a fluorine-containing precursor, which may or may not be plasma-enhanced. Operation 535 of the fifth iteration of method 500 may be similar to operation 535 of the first, second, third, and / or fourth iterations of method 500 and may include any features or characteristics of such operations. At optional operation 540, the fifth iteration of method 500 may include contacting substrate 605 with the cleaning agent. Following the contacting at operation 525, the cleaning agent may be provided to clean structure 600, which may leave residue on one or more materials present on substrate 605, such as oxygen-containing materials. Operation 540 of the fifth iteration of method 500 may be similar to operation 540 of the first, second, third, and / or fourth iterations of method 500 and may include any features or characteristics of such operations. Without performing carbon replenishment, carbon-depleted materials, such as the gate spacers 635 and / or the inner spacers 640, may be etched at optional operation 535. However, the gate spacers 635 and / or the inner spacers 640 after carbon replenishment may be more resistant to cleaning at optional operations 535-540 and may not suffer thickness loss during cleaning.

[0089] A fifth iteration of method 500 may include performing a post-cleaning operation at optional operation 545 .

[0090] Subsequent contact application processing may include an additional carbon replenishment operation. In conventional contact application processing, those skilled in the art will recognize that the process flow may include multiple etching operations, such as material removal or hard mask patterning / stripping, which may deplete carbon from the low-k dielectric material. Therefore, carbon replenishment is performed during the contact application process, such as operations 520-530 of method 500 or method 300.

[0091] For example, conventional contact application processes may include an etching operation to open holes or features in which contacts may be formed. Following this etching, a cleaning operation may be performed. However, carbon may be depleted from exposed materials, such as low-k dielectric materials containing carbon. If untreated, the cleaning operation may result in a loss of thickness of the carbon-depleted low-k dielectric material. Thus, the present technology may include a carbon replenishment operation after the etching operation to open holes or features in which contacts may be formed and before the cleaning operation.

[0092] After the cleaning operation, PMOS patterning can be performed to allow for subsequent P+ implantation. In conventional contact application processes, another cleaning operation can follow the PMOS patterning, which can again result in a loss of thickness of the carbon-depleted material. Thus, the present technique can include a carbon replenishment operation after the PMOS patterning and before the cleaning operation.

[0093] After the P+ implant, the hard mask used for PMOS patterning can be stripped and another cleaning operation can be performed. Again, this cleaning operation can result in a loss of thickness of the carbon-depleted material. However, the present technique may include a carbon replenishment operation after stripping the hard mask used for PMOS patterning and before the cleaning operation.

[0094] After removing the hard mask used for PMOS patterning, a liner material (such as a low-k dielectric constant material) can be deposited in the holes or features where contacts can be formed. An etch can be performed to remove a portion of the liner material. A cleaning operation that removes a portion of the liner material after etching can result in a loss of thickness of the carbon-depleted material. Similarly, the present technique can include a carbon replenishment operation after removing a portion of the liner material and before the cleaning operation.

[0095] The present technique may also include a carbon replenishment operation prior to forming the contact metallization. In one embodiment, the cleaning operation after removing a portion of the liner may be a wet clean, which may deplete carbon from other areas of the substrate. The cleaning operation before forming the contact metallization may be a dry clean, which may result in a loss of thickness of material that may be carbon-depleted after the wet clean. Thus, the present technique may include a carbon replenishment operation after the wet clean performed after removing a portion of the liner material.

[0096] Process conditions can affect the operations performed in method 300. Each of the operations of method 300 can be performed at a constant temperature in some embodiments, while in some embodiments the temperature can be adjusted during different operations. In some embodiments of the present technology, method 300 can be performed at a substrate, susceptor, and / or chamber temperature of less than or about 500°C due to thermal budget issues, and can be performed at a temperature of less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, less than or about 325°C, less than or about 300°C, less than or about 275°C, less than or about 250°C, less than or about 225°C, less than or about 200°C, or less. The temperature can also be maintained within these ranges, within smaller ranges encompassed by these ranges, or at any temperature between any of these ranges. Forming the material at an increased temperature can increase the amount of carbon in the silicon-containing material introduced into the spacers 435 at operation 335 and thereby improve resistance to wet etchants. Thus, in some embodiments, the temperature can be maintained between greater than or about 10° C., and can be maintained at greater than or about 25° C., greater than or about 50° C., greater than or about 75° C., greater than or about 100° C., greater than or about 125° C., greater than or about 150° C., greater than or about 175° C., greater than or about 200° C., greater than or about 225° C., greater than or about 250° C., greater than or about 275° C., greater than or about 300° C., greater than or about 325° C., greater than or about 350° C., or higher.

[0097] The pressure within the semiconductor processing chamber can also affect the operations performed. In one embodiment, the pressure can be maintained at less than about 40 Torr. Thus, the pressure can be maintained at less than or about 35 Torr, less than or about 30 Torr, less than or about 25 Torr, less than or about 20 Torr, less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 4 Torr, less than or about 2 Torr, less than or about 1 Torr, or less. The pressure can also be maintained within these ranges, within smaller ranges encompassed by these ranges, or at any pressure between any of these ranges.

[0098] In conventional embodiments, the remaining silicon-containing material with a reduced carbon concentration at the exposed surface of the silicon-containing material may be less resistant to cleaning agents, such as fluorine-containing substances. In such conventional embodiments, the silicon-containing material may be completely removed, which may damage or destroy the structure. By treating the silicon-containing material with a carbon-containing precursor and / or exposing the silicon-containing material to UV radiation, carbon can be added to the silicon-containing material. The increased carbon concentration can increase the silicon-containing material's resistance to cleaning agents and other etchants used during processing. While conventional embodiments may immediately begin etching the silicon-containing material when exposed to cleaning agents and other wet etchants, the present technology can prevent any etching that occurs after exposures of greater than or about 5 seconds, such as greater than or about 10 seconds, greater than or about 15 seconds, greater than or about 20 seconds, greater than or about 25 seconds, greater than or about 30 seconds, greater than or about 35 seconds, greater than or about 40 seconds, or longer.

[0099] In one embodiment, operations 305 through 335 of method 300 and operations 505 through 555 of method 500 (including multiple iterations) can be performed on a single host or processing system (such as processing system 100 shown in FIG. 1 ). Thus, the operations of methods 300 and 500 can be performed without breaking vacuum and without exposure to ambient conditions. By maintaining vacuum, queue times can be reduced and throughput can be increased. However, it is also contemplated that vacuum can be broken between operations, such as, for example, between operations 310 and 315 or between operations 515 and 520. For example, vacuum can be broken when operations 310 or 515 include a wet etch operation using dHF.

[0100] As previously discussed, a processing system (such as processing system 100) can be configured to perform some or all of operations 305 through 335 of method 300 and operations 505 through 555 of method 500, as previously discussed. For example, one embodiment of a processing system (also referred to as a cluster tool) may include a first semiconductor processing chamber configured to perform operations 305 and 310 (or operations 510 and 515) to etch a portion of a material layer. After etching the portion of the material layer, substrate 405 may be transferred to a second semiconductor processing chamber. The second semiconductor processing chamber may be located on the same mainframe as the first semiconductor processing chamber. Thus, a vacuum may be maintained during transfer between the first and second semiconductor processing chambers. The second semiconductor processing chamber may perform operations 315 and 320 (or operations 520 and 525) to introduce carbon depleted during an earlier etching process.

[0101] Another embodiment of a processing system or cluster tool may include a third semiconductor processing chamber capable of performing operations 330 and 335 (or operations 535-545) after performing operation 325 (or operation 530) in the second semiconductor processing chamber. In addition to the first and second semiconductor processing chambers discussed previously, yet another embodiment of a processing system or cluster tool may include one or more pre-processing semiconductor processing chambers capable of performing operations prior to method 300 or method 500. For example, the additional one or more pre-processing semiconductor processing chambers may include a single chamber operable to perform operation 505. Yet another embodiment of a processing system or cluster tool may include each of the previously discussed semiconductor processing chambers operable to perform all of operations 305-335 or operations 505-545. While it is contemplated that any number of operations may be combined in a single semiconductor processing chamber, each operation may also be performed in a separate semiconductor processing chamber.

[0102] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0103] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Furthermore, several well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be considered to limit the scope of the technology.

[0104] Where a range of values ​​is provided, it will be understood that, unless the context clearly dictates otherwise, each intervening value to the nearest fraction of the unit of the lower limit between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated value or intervening value not stated in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in that range, and each range where either, neither, or both limits are included in the smaller range is also encompassed within the technology, subject to any specifically excluded limits in the stated range. Where a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0105] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, and reference to "the material" includes reference to one or more materials and equivalents thereof known to those skilled in the art, and so forth.

[0106] In addition, when used in this specification and the following claims, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including" are intended to specify the presence of the stated features, integers, components, or operations, but such words do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

[0107] 100:Processing system 102: Front-opening wafer transfer box 104:Robotic Arm 106: Low pressure holding area 108a: semiconductor processing chamber 108b: semiconductor processing chamber 108c: Semiconductor processing chamber 108d: Semiconductor processing chamber 108e: Semiconductor processing chamber 108f: Semiconductor processing chamber 109a: Serial segment 109b: Serial segment 109c: Serial segment 110: Second robotic arm 200: Plasma system 201:Inner side wall 202: Chamber body 203: Power Box 204: Chamber cover 206: Shielding Ring 208:Gas Distribution System 212: Sidewall 216:Bottom wall 218: Gas delivery assembly 220A: Processing area 220B: Processing area 222: Channel 224: Channel 225: Circumferential pumping cavity 226: Rod 227: Gasket assembly 228: Base 229:Substrate 230: Stick 231: Discharge Port 232: Heating element 233: flange 235:Circular Ring 238: Base component 240: Precursor entrance channel 244:Blocking plate 246: Panel 247: Cooling channel 248: Air box 258: Dielectric Isolator 260: substrate transfer port 261: Substrate lifting pin 264: Pumping System 265: Radio Frequency (RF) Source 300: Method 305: Operation 310: Operation 315: Operation 320: Operation 325: Operation 330: Operation 335: Operation 400:Structure 405:Substrate 410: Materials 415: Second silicon-containing material 420: Second silicon-containing material 500:Method 505: Operation 510: Operation 515: Operation 520: Operation 525: Operation 530: Operation 535: Operation 540: Operation 545: Operation 600:Structure 605:Substrate 610: Silicon-containing materials 615: Silicon and germanium containing materials 620: Silicon-containing materials 625:Dummy gate 630: Silicon-containing materials 635: Gate spacer 640: Internal spacer 644: Oxygen-containing materials 645: Epitaxial Materials 650: Interlayer dielectric material

[0108] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A semiconductor processing method comprising the steps of: providing an etchant precursor to a processing region of a semiconductor processing chamber, wherein a structure is disposed in the processing region, wherein the structure comprises a first silicon-containing material, and wherein the structure comprises a second silicon-containing material, an oxygen-containing material, or both; contacting the structure with the etchant precursor, wherein the contact with the etchant precursor etches at least a portion of the second silicon-containing material or the oxygen-containing material from the structure; providing a carbon-containing precursor to the processing region of the semiconductor processing chamber; and contacting the structure with the carbon-containing precursor, wherein the contact with the carbon-containing precursor replenishes carbon in the first silicon-containing material and reduces thickness loss of the first silicon-containing material during subsequent operations.

2. The semiconductor processing method as claimed in claim 1, wherein the second silicon-containing material comprises a silicon- and oxygen-containing material or a silicon- and germanium-containing material.

3. The semiconductor processing method as described in claim 1, wherein the first silicon-containing material comprises a silicon- and carbon-containing material.

4. The semiconductor processing method as claimed in claim 1, wherein the etchant precursor comprises a halogen-containing precursor.

5. The semiconductor processing method as claimed in claim 1, wherein contacting the structure with the carbon-containing precursor increases the carbon content in the first silicon-containing material by more than or about 0.1 atoms.

6. The semiconductor processing method as described in claim 1, wherein the carbon-containing precursor comprises hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-O-Si-(CH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3-O)3-Si-CH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si(Cl)-(CH3)2), and dimethylaminotrimethylsilane (DMATMS). ((CH3)2-N-Si-(CH3)3), or bis(dimethylamino)dimethylsilane (BDMADMS).

7. The semiconductor processing method as described in claim 1 further comprises the step of: exposing the structure to ultraviolet (UV) radiation while contacting the structure with the carbon-containing precursor or after contacting the structure with the carbon-containing precursor.

8. The semiconductor processing method as claimed in claim 7, wherein contacting the structure with the carbon-containing precursor and exposing the structure to ultraviolet (UV) radiation are performed simultaneously.

9. The semiconductor processing method as claimed in claim 1, further comprising the steps of: after contacting the structure with the carbon-containing precursor, providing a cleaning agent to the processing area of ​​the semiconductor processing chamber; and contacting the structure with the cleaning agent, wherein the contact with the cleaning agent removes a residue from the structure.

10. The semiconductor processing method as claimed in claim 1, wherein a temperature in the semiconductor processing chamber is less than or about 500°C.

11. A semiconductor processing method comprising the steps of: providing a first etchant precursor to a processing region of a semiconductor processing chamber, wherein a structure is disposed in the processing region, wherein the structure includes an alternating layer of a first silicon-containing material and an alternating layer of silicon and germanium-containing materials, and wherein the structure includes a second silicon-containing material covering and extending into one or more recesses defined by the alternating layers of the first silicon-containing material and the alternating layers of the silicon and germanium-containing materials; contacting the structure with the first etchant precursor, wherein the contact with the first etchant precursor etches through the alternating layers of the first silicon-containing material and the alternating layers of the silicon and germanium-containing materials; providing a first carbon-containing precursor to the processing region of the semiconductor processing chamber; contacting the structure with the first carbon-containing precursor, wherein the contact with the first carbon-containing precursor replenishes carbon in the second silicon-containing material; and providing a first cleaning agent to the processing region of the semiconductor processing chamber. The structure is brought into contact with the first cleaning agent, wherein the contact with the first cleaning agent removes a first residue from the structure; a second etchant precursor is provided to the processing area of ​​the semiconductor processing chamber; the structure is brought into contact with the second etchant precursor, wherein the contact etches a portion of the silicon and germanium-containing material; a silicon-containing precursor is provided to the processing area; the structure is brought into contact with the silicon-containing precursor, wherein the contact deposits a third silicon-containing material on the structure, and wherein the third silicon-containing material extends into a recess defined by an etched portion of the silicon and germanium-containing material; a third etchant precursor is provided to the processing area of ​​the semiconductor processing chamber; the structure is brought into contact with the third etchant precursor, wherein the contact etches a portion of the third silicon-containing material, and wherein after the contact, the remaining third silicon-containing material extends into the recess defined by the etched portion of the silicon and germanium-containing material; A second carbon-containing precursor is provided to the processing region of the semiconductor processing chamber; the structure is brought into contact with the second carbon-containing precursor, wherein the contact with the second carbon-containing precursor replenishes carbon in the third silicon-containing material; a second cleaning agent is provided to the processing region of the semiconductor processing chamber; the structure is brought into contact with the second cleaning agent, wherein the contact with the second cleaning agent removes a second residue from the structure; a fourth etchant precursor is provided to the processing region of the semiconductor processing chamber; the structure is brought into contact with the fourth etchant precursor, wherein the contact with the fourth etchant precursor removes a dummy oxide material from the structure; a third carbon-containing precursor is provided to the processing region of the semiconductor processing chamber; the structure is brought into contact with the third carbon-containing precursor, wherein the contact with the third carbon-containing precursor replenishes carbon in the second silicon-containing material; a fifth etchant precursor is provided to the processing region of the semiconductor processing chamber; The structure is brought into contact with the fifth etchant precursor, wherein the contact with the fifth etchant precursor removes the silicon and germanium-containing material from the structure;A fourth carbon-containing precursor is provided to the processing region of the semiconductor processing chamber; and the structure is brought into contact with the fourth carbon-containing precursor, wherein the contact with the fourth carbon-containing precursor replenishes the carbon in the second silicon-containing material, the third silicon-containing material, or both, wherein the contact of the structure with the first carbon-containing precursor, the second carbon-containing precursor, the third carbon-containing precursor, or the fourth carbon-containing precursor reduces thickness loss of the second silicon-containing material, the third silicon-containing material, or both during subsequent operations.

12. The semiconductor processing method as claimed in claim 11, wherein one or more of the first carbon-containing precursor, the second carbon-containing precursor, the third carbon-containing precursor, and the fourth carbon-containing precursor are the same carbon-containing precursor.

13. The semiconductor processing method as claimed in claim 11, wherein the second silicon-containing material, the third silicon-containing material, or both are characterized by a dielectric constant of less than or about 7.

5.

14. The semiconductor processing method as claimed in claim 11, wherein one or more of the first etchant precursor, the second etchant precursor, the third etchant precursor, or the fourth etchant precursor comprises a hydrogen-containing precursor, a nitrogen-containing precursor, a helium-containing precursor, a halogen-containing precursor, or an oxygen-containing precursor.

15. The semiconductor processing method as claimed in claim 11 further comprises the step of: depositing an epitaxial material on the structure before contacting the structure with the fourth etchant precursor.

16. A semiconductor processing system comprising: a first semiconductor processing chamber, wherein the first semiconductor processing chamber is configured to: allow an etchant precursor to flow into a processing region of the first semiconductor processing chamber, wherein a structure is disposed in the processing region, wherein the structure includes a first silicon-containing material, and wherein the structure includes a second silicon-containing material, an oxygen-containing material, or both; and contact the structure with the etchant precursor, wherein the contact with the etchant precursor etches at least a portion of the second silicon-containing material or the oxygen-containing material from the structure; and a second semiconductor processing chamber, on the same host as the first semiconductor processing chamber, wherein the second semiconductor processing chamber is configured to: allow a carbon-containing precursor to flow into a processing region of the second semiconductor processing chamber; and contact the structure with the carbon-containing precursor, wherein the contact with the carbon-containing precursor replenishes carbon in the first silicon-containing material and reduces thickness loss of the first silicon-containing material during subsequent operations.

17. The semiconductor processing system of claim 16, further comprising: a third semiconductor processing chamber on the same host as the first semiconductor processing chamber and the second semiconductor processing chamber, wherein the third semiconductor processing chamber is configured to: allow a cleaning agent to flow into a processing area of ​​the third semiconductor processing chamber; and bring the structure into contact with the cleaning agent, wherein contact with the cleaning agent removes a residue from the structure.

18. The semiconductor processing system of claim 17, further comprising: a fourth semiconductor processing chamber on the same host as the first semiconductor processing chamber, the second semiconductor processing chamber, and the third semiconductor processing chamber, wherein the fourth semiconductor processing chamber is configured to: allow one or more deposition gases to flow into a processing area of ​​the fourth semiconductor processing chamber; and contact the structure with the one or more deposition gases, wherein an epitaxial material is deposited on the structure in contact with the one or more deposition gases.

19. The semiconductor processing system of claim 16, further comprising: one or more pre-processing semiconductor processing chambers on the same host as the first semiconductor processing chamber and the second semiconductor processing chamber, wherein the one or more pre-processing semiconductor processing chambers are configured to: etch the first silicon-containing material and a portion of a silicon- and germanium-containing material; deposit the second silicon-containing material on the structure; and / or etch a portion of the second silicon-containing material.

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