Method of forming hardmasks and method of using hardmasks

Abstract

Thicker hard masks are typically required to etch deeper capacitor vias in DRAM structures. Instead of increasing the hard mask thickness, the hard mask can be formed with increased etch selectivity relative to the underlying semiconductor structure. For example, a boron-based hard mask comprising a relatively high percentage of boron (e.g., greater than 90%) can be formed. The etch selectivity of the hard mask can be improved by performing an ion implantation process using different types of ions. Ion implantation can occur before or after the patterned openings of the DRAM capacitor vias in the hard mask. Some designs also tilt the semiconductor substrate relative to the ion implantation process and rotate the substrate to provide greater ion penetration throughout the entire depth of the openings in the hard mask.

Description

Technical Field

[0001] This application claims the benefit of and priority to U.S. non-provisional application No. 18 / 495,493, filed on October 26, 2023, and entitled “IMPROVED SELECTIVITY OF BORON HARD MASKS USING ION IMPLANT,” the entire contents of which are incorporated herein by reference for all purposes.

[0002] The present disclosure generally describes a boron hard mask for etching dynamic random access memory (DRAM) features. More specifically, the present disclosure describes the use of ion implantation in the boron hard mask to improve the selectivity of the hard mask. Prior Art

[0003] Integrated circuits may be fabricated using processes that create complex patterns of material layers on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing materials. Material properties can influence how devices operate and also affect how films are removed relative to one another. Deposition processes produce films with certain properties. Many of the resulting films require additional processing to adjust or enhance the film's material properties to provide desired properties.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality components and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] In some embodiments, a method of forming a hard mask may include, in a first semiconductor processing chamber: delivering a boron-containing precursor to a processing region of the semiconductor processing chamber; forming a plasma of the precursor within the processing region of the first semiconductor processing chamber; and forming a boron-based hard mask on a substrate disposed within the processing region of the first semiconductor processing chamber. The method may also include, in a second semiconductor processing chamber: implanting the boron-based hard mask using ions.

[0006] In some embodiments, a method may also include forming a dynamic random access memory (DRAM) structure comprising a plurality of alternating layers of oxide and nitride materials. The method may additionally include forming a boron-based hard mask over the DRAM structure, wherein the boron-based hard mask may comprise at least 90% boron. The method may additionally include ion implanting the boron-based hard mask. The method may further include opening the boron-based hard mask using a pattern of a plurality of capacitor holes to be formed in the DRAM structure. The method may also include performing an etch to form the plurality of capacitor holes in the DRAM structure through the openings in the boron-based hard mask, wherein ion implanting the boron-based hard mask increases the etch selectivity of the DRAM structure relative to the boron-based hard mask.

[0007] In some embodiments, a method may include forming a boron-based hard mask over a semiconductor structure. The method may also include opening the boron-based hard mask using a pattern of a plurality of apertures to be formed in the semiconductor structure. The method may additionally include tilting a substrate support in a semiconductor processing chamber to tilt the semiconductor structure relative to an ion implantation process. The method may further include implanting the boron-based hard mask with ions using the ion implantation process, wherein tilting the substrate implants ions at an angle into vertical sidewalls of the plurality of openings in the boron-based hard mask.

[0008] In any embodiment, any or all of the following features may be implemented in any combination and are not limited to: In a first semiconductor processing chamber, a dopant-containing precursor may be delivered to a processing region of the first semiconductor processing chamber along with a boron-containing precursor, and a dopant concentration within a boron-based hard mask may be maintained at less than or approximately 10 atomic %. The dopant-containing precursor may include silicon. Ions may be implanted using a high ion beam current to implant ions into the boron-based hard mask. The ions may include indium ions, helium ions, and / or neon ions. Implanting the boron-based hard mask with ions may increase the etch selectivity of the DRAM structure relative to the boron-based hard mask by at least 10%. The ions may be implanted into the boron-based hard mask to a depth greater than approximately 50% of the thickness of the boron-based hard mask, and the boron-based hard mask may have a thickness of at least 3000 Å. The boron-based hard mask may be ion-implanted before opening the boron-based hard mask. The boron-based hard mask may be annealed before opening the boron-based hard mask. Ions may be implanted into the boron-based hard mask before the boron-based hard mask is opened. The ions may be implanted into the boron-based hard mask to a depth greater than approximately 80% of the thickness of the boron-based hard mask. The boron-based hard mask may be annealed after the boron-based hard mask is opened. Etching may be performed to form a plurality of holes in the semiconductor structure through the openings in the boron-based hard mask, wherein utilizing the ion-implanted boron-based hard mask may increase an etch selectivity of the semiconductor structure relative to the boron-based hard mask by at least 10%. The plurality of holes may have a critical dimension of at least 15:1. The plurality of holes may have a depth of at least 300 nm. The etch selectivity may be increased by at least 15%. Simple diagram description

[0009] A further understanding of the nature and advantages of the various embodiments may be realized by referring to the remaining portions of the specification and the drawings, in which the same reference numerals are used in several figures to represent similar components. In some cases, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When a reference numeral is cited without specifying the existing sub-label, it is intended to refer to all such multiple similar components.

[0010] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber according to some embodiments.

[0011] FIG. 2 illustrates a portion of a DRAM structure during fabrication, according to some embodiments.

[0012] FIG. 3 illustrates a flow chart of a method for forming a hard mask using ion implantation according to some embodiments.

[0013] FIG. 4 illustrates a flow chart of a method for forming a hard mask according to some embodiments.

[0014] FIG. 5A illustrates a structure having a hard mask that has been opened prior to performing an ion implantation process, in accordance with some embodiments.

[0015] FIG. 5B illustrates the structure after an ion implantation process, according to some embodiments.

[0016] FIG. 6 illustrates a structure in which an ion implantation process is performed at an angle, according to some embodiments.

[0017] FIG. 7 illustrates a cross-sectional view of a hard mask when ion implantation is performed at an angle, according to some embodiments.

[0018] FIG. 8 illustrates a table listing several different types of processing conditions utilizing an ion implant recipe used in an ion implantation process, according to some embodiments. Implementation Method

[0019] During semiconductor manufacturing, various deposition and etching operations can be used to create structures on a substrate. Masking materials can be used to allow at least partial etching of materials to create features across the substrate. As device sizes continue to shrink, improved selectivity between materials can facilitate structure formation, and utilizing improved hard masks can facilitate manufacturing. For example, future DRAM nodes may require taller capacitor structures, which may involve forming deeper trenches in the substrate. Conventional hard masks may reach selectivity limits relative to the underlying silicon material. Consequently, many semiconductor manufacturing processes are utilizing thicker hard mask films for larger vertical device structures or are attempting to develop mask materials characterized by increased hardness. However, thicker hard mask films can pose patterning challenges, which in turn can affect uniformity of transfer into the underlying structures. Thicker hard masks also inherently increase the depth of the etch performed on the underlying device material, making it difficult to maintain a high aspect ratio.

[0020] The present technology can overcome these limitations by forming a hard mask with increased etch selectivity relative to the underlying semiconductor structure. For example, a boron-based hard mask can be formed that includes a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hard mask can be improved by performing an ion implantation process using different types of ions. The ion implantation can occur before or after the hard mask is opened with the pattern of DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implantation process and rotate the substrate to provide greater ion penetration throughout the depth of the opening in the hard mask. It will be understood that because the described technology can be used to improve a number of film formation processes and is applicable to a variety of processing chambers and operations, the present technology is not intended to be limited to the specific films and processes discussed. Specifically, a boron-based hard mask is used herein as an example, but this is not meant to be limiting. The same techniques for implanting ions in the hard mask can also be used with any other type of hard mask material or composition. Thus, the boron-based hard masks described throughout this disclosure can be substituted with any other type of hard mask without limitation.

[0021] After describing the general aspects of a chamber in which the plasma processing operations discussed below can be performed according to some embodiments of the present technology, the specific methodology can be discussed. It will be understood that because the described techniques can be used to improve a number of film formation processes and can be applied to a variety of processing chambers and operations, the present technology is not intended to be limited to the specific films, chambers, or processes discussed.

[0022] FIG1 illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments. The diagram may provide an overview of a system that incorporates one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of chamber 100 or the methods performed therein may be described further below. Chamber 100 may be used to form film layers, etch material layers, form other material layers, or a combination thereof, but it should be understood that deposition and etching methods may be similarly performed in any chamber in which deposition and etching processes may occur. Processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within chamber body 102, and a lid assembly 106 coupled to chamber body 102 and enclosing substrate support 104 in a processing volume 120. A substrate 103 may be provided to processing volume 120 through an opening 126, which may be sealed for processing using a conventional slit valve or door. During processing, substrate 103 may rest on surface 105 of the substrate support. In some embodiments, the substrate support 104 may be rotatable along a vertical axis, where the shaft 144 of the substrate support 104 may be located, or may be fixed. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0023] The gas distributor 112 can define an aperture 118 for distributing the process precursor into the processing volume 120. The gas distributor 112 can be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that can be coupled to the processing chamber. In some embodiments, the first power source 142 can be an RF power supply.

[0024] The gas distributor 112 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 can also be formed from both conductive and non-conductive components. For example, the main body of the gas distributor 112 can be conductive, while the faceplate of the gas distributor 112 can be non-conductive. The gas distributor 112 can be powered, such as by a first power source 142 as shown in FIG. 1 , or in some embodiments, the gas distributor 112 can be coupled to ground.

[0025] A first electrode 122 may be coupled to the substrate support 104. The first electrode 122 may be embedded within the substrate support 104 or coupled to a surface of the substrate support 104. The first electrode 122 may be a plate, a porous plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The first electrode 122 may be a tuning electrode and may be coupled to a tuning circuit 136 via, for example, a conduit 146 (e.g., a cable having a selected resistance (e.g., 50 ohms)) disposed within a shaft 144 of the substrate support 104. The tuning circuit 136 may include an electronic sensor 138 and an electronic controller 140, which may be a variable capacitor. The electronic sensor 138 may be a voltage or current sensor and may be coupled to the electronic controller 140 to provide further control over the plasma conditions in the processing volume 120.

[0026] A second electrode 124 (which may be a bias electrode and / or an electrostatic clamping electrode) may be coupled to the substrate support 104. The second electrode may be coupled to a second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature, which may be between approximately 25°C and approximately 800°C or greater.

[0027] The lid assembly 106 and substrate support 104 of FIG. 1 can be used with any processing chamber used for plasma or thermal processing. In operation, the processing chamber 100 can provide real-time control of plasma conditions in the processing volume 120, such as via a controller 101 that can be contained within the processor 107. A substrate 103 can be positioned on the substrate support 104, and process gases can be flowed through the lid assembly 106 using an inlet 114 according to any desired flow schedule. Gases can exit the processing chamber 100 through an outlet 152. Electrical power can be coupled to the gas distributor 112 to establish the plasma in the processing volume 120. In some embodiments, the substrate can be electrically biased using a second electrode 124.

[0028] After energizing the plasma in the processing volume 120, a potential difference can be established between the plasma and the first electrode 122. The electronic controller 140 can then be used to adjust the flow properties of the ground path represented by the tuning circuit 136. Set points can be delivered to the tuning circuit 136 to provide independent control of the deposition rate and the uniformity of the plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, the electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0029] The tuning circuit 136 may have a variable impedance that can be adjusted using the electronic controller 140. If the electronic controller 140 is a variable capacitor, the capacitance range of each variable capacitor may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Thus, when the capacitance of the electronic controller 140 is at its minimum or maximum value, the impedance of the tuning circuit 136 may be high, resulting in a plasma shape with minimal airspace or lateral coverage above the substrate support. When the capacitance of the electronic controller 140 approaches a value that minimizes the impedance of the tuning circuit 136, the airspace coverage of the plasma may increase to a maximum value, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the electronic controller 140 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the airspace coverage of the substrate support may decrease.

[0030] Electronic sensors 138 can be used to tune the closed-loop tuning circuit 136. Depending on the type of sensor used, a current or voltage setpoint can be installed in each sensor, and the sensor can be equipped with control software that determines adjustments to the electronic controller 140 to minimize deviations from the setpoint. Thus, the plasma shape can be selected and dynamically controlled during processing. It will be understood that while the above discussion is based on the electronic controller 140, which can be a variable capacitor, any electronic component with adjustable characteristics can be used to provide adjustable impedance to the tuning circuit 136.

[0031] FIG2 illustrates a portion of a DRAM structure 200 during fabrication, according to some embodiments. The DRAM structure may include a capacitor hole 214. Note that, to clearly illustrate capacitor hole 214, this DRAM structure 200 represents only a portion of the overall structure. In practice, DRAM structure 200 may include many additional layers, through which capacitor hole 214 is formed. Thus, DRAM structure 200 should be interpreted as including additional layers, not shown, as appropriate, in addition to the layers explicitly shown between the layers in FIG2 .

[0032] DRAM structure 200 may represent a state of a DRAM structure during the manufacturing process, rather than a completed DRAM structure. For example, DRAM structure 200 may represent a mold formed from multiple layers in which capacitor hole 214 is formed. After forming capacitors in capacitor hole 214, some of the layers shown in DRAM structure 200 may be removed, and the resulting voids may be filled with other materials to form the final DRAM structure for use in a memory array.

[0033] DRAM structure 200 may include a metal layer 202 formed from tungsten or other similar conductive materials. Metal layer 202 may represent control lines in a memory array, such as voltage reference lines or select lines. A silicon nitride layer 204 may be formed on top of metal layer 202. Next, multiple layers of oxide and nitride materials may be deposited to form the main body of the mold. For example, nitride layer 208 may include silicon nitride or silicon nitride carbon (SiCN) formed as a relatively thin layer in the main body of the mold. This nitride layer 208 may remain after other materials in the mold are removed. Subsequently, after the mold material is removed and new material fills the resulting void, nitride layer 208 may mechanically hold the capacitor structure in place.

[0034] An oxide layer may be formed throughout the mold body between nitride layers 208. In some embodiments, a single oxide material, such as tetraethylorthosilicate (TEOS) or silicon dioxide, may be used to form the bulk of the mold material. In other embodiments, multiple oxide materials may be used to avoid excessive tapering when etching capacitor holes 214 through the mold. For example, some embodiments may include one or more TEOS layers 210 in the upper portion of the mold, while using one or more layers of borophosphosilicate glass (BPSG) 206 in the lower portion of the mold. The oxide material (e.g., TEOS) used in the upper portion of the mold may be etched at a first rate during the etching process, while the oxide material (e.g., BPSG) used in the lower portion of the mold may be etched at a second rate during the etching process. The second rate may be faster than the first rate, causing the oxide material used in the lower portion of the mold to etch faster to avoid tapering of capacitor holes 214. Note that some technology nodes may place the top nitride layer 208 - 2 directly under the hard mask 212 , while other technology nodes may interpose an oxide layer 210 - 2 between the top nitride layer 208 - 2 and the hard mask 212 .

[0035] Any etching process can be used to form the capacitor holes 214 through the oxide layers 210, 206 and the nitride layer 208. After the etching process is completed and the capacitor holes 214 are formed, the oxide layers 210, 206 can be removed via a second etching process that is selective to these particular oxide materials. To form the capacitor holes 214, a hard mask 214 can be formed on top of the mold and patterned to form a pattern with openings that define the capacitor holes 214. Subsequently, the pattern in the hard mask 212 can be selectively exposed through an etching process to expose the remaining layers of the mold, forming the capacitor holes 214 through the depth of the mold.

[0036] The hard mask 212 can be formed as an amorphous boron (aB) hard mask using the process described above for depositing a hard mask on a substrate. Therefore, the hard mask 212 may be referred to as a boron-containing hard mask or a boron-containing material, which should be understood to refer to a hard mask layer composed primarily of boron. In some embodiments, the aB hard mask may be doped with silicon to form an aB(Si) hard mask. When boron is doped with a material such as silicon, the boron-containing material may include greater than approximately 90% boron compared to the doping material (e.g., silicon). Some embodiments can form an aB(Si) hard mask with greater than approximately 95% boron, greater than approximately 96% boron, greater than approximately 97% boron, greater than approximately 98% boron, or substantially 100% boron (i.e., formed primarily from a boron precursor, excluding trace amounts of material that may be unintentionally included during the deposition process). Some embodiments may also use a metal boride mask, where the boron hard mask is doped with various metals using the process described above. For example, many different hard mask films can be used to pattern DRAM structures to etch capacitor holes, and the ion implantation process described below can be used with any hard mask. However, aB and aB(Si) hard masks may be of particular interest in some applications.

[0037] With each subsequent DRAM technology node, the diameter of the capacitor holes 214 in the DRAM array may become increasingly smaller. To maintain capacitance, the depth of the capacitor holes 214 may need to increase accordingly. This requires the process used to fabricate the DRAM structure to be capable of etching deeper holes compared to each earlier node. Typically, this will require increasing the thickness of the hard mask 212. For example, etching deeper holes 214 generally uses a longer etch process, which requires a thicker hard mask 212 to withstand the longer etch process. However, increasing the thickness of the hard mask 212 increases the total combined thickness of the hard mask 212 and the holes 214, resulting in a higher aspect ratio and poorer critical dimension uniformity (CDU) of the holes 214.

[0038] It has been discovered that some newer technology nodes have increased the depth and / or reduced the diameter of capacitor holes 214 beyond what existing hardmask 212 designs can accommodate. Specifically, the increased thickness of hardmask 212 required to etch capacitor holes 214 deep enough for new technology nodes results in poor CDU across the capacitor array. Thus, the embodiments described herein overcome this technical issue by modifying hardmask 212 to increase the etch selectivity (ES) over existing hardmask compositions composed primarily of boron. Specifically, as the etch selectivity of hardmask 212 is increased, the thickness of hardmask 212 can be maintained while increasing the depth of capacitor holes 214. Because hardmask 212 is more resistant to the etching process than other materials in the mold, capacitor holes 214 can be etched deeper without increasing the thickness of hardmask 212.

[0039] For example, creating taller capacitor holes 214 can begin by forming a taller capacitor mold beneath hard mask 212 using the material shown in FIG. 2 . Subsequently, the taller capacitor mold can result in deeper holes etched compared to earlier technology nodes. Instead of proportionally increasing the thickness of hard mask 212 (which in practice results in poor CDU), these embodiments introduce a hard mask with higher etch selectivity to maintain the thickness of hard mask 212 while still managing the CDU of capacitor holes 214. For example, a hard mask composed of greater than approximately 90% amorphous boron can have insufficient etch selectivity toward capacitor mold materials. When compared to existing boron hard masks, the techniques described herein can increase the etch selectivity of hard mask 212 relative to other mold materials by 10% or more. Specifically, some embodiments can improve the composition of hard mask 212 by implanting it with metal ions. The hard mask can be modified using several techniques, each of which is described in detail below.

[0040] There are many technical advantages to using ion implantation compared to other previous techniques. For example, ion implantation can be directly contrasted with the deposition of metal-containing hard mask films. Direct deposition of metal-containing films requires the development of a new set of deposition, etch, and stripping chemistries, which is challenging and time-consuming. Ion implantation has proven to be a much faster and more versatile tool for evaluating doping chemistries for many different elements in films. This allows new hard masks to be developed, tested, and implemented in production very quickly. As described above, ion implantation also increases the etch selectivity of the hard mask, allowing the hard mask thickness to be maintained or even reduced, depending on the application. Ion implantation is also well-suited for providing manufacturing solution recipes for multiple chamber types. For example, the initial boron-containing hard mask can be deposited in one chamber, and the ion implantation can be performed in another. These chambers can be part of the same integrated processing tool or platform, allowing substrates to be transferred between chambers while maintaining processing pressures and / or without exposure to the environment outside the tool or platform. These chambers can also be part of separate tools or platforms.

[0041] FIG3 shows a flow chart of a method 300 for forming a hard mask using ion implantation according to some embodiments. The method may include depositing a hard mask (302). The hard mask may be formed on top of a DRAM structure (such as the structure shown in FIG2 above) on a substrate. The substrate may be or include any number of layers on which materials may be deposited. The substrate may be or include silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any combination of such materials, which may be the substrate itself or formed on the substrate. In some embodiments, optional processing operations (e.g., pretreatment) may be performed to prepare the surface of the substrate for deposition. For example, pretreatment may be performed to provide certain ligand terminals on the surface of the substrate, which may promote nucleation of the film to be deposited. For example, hydrogen, oxygen, carbon, nitrogen, or other molecular terminals (including any combination of such atoms or radicals) may be adsorbed, reacted, or formed on the surface of the substrate. Additionally, material removal operations may be performed, such as reducing native oxides or etching materials, or any other operations that may prepare one or more exposed surfaces of the substrate for deposition.

[0042] The hard mask may be a boron or amorphous boron hard mask. The boron hard mask may be doped with silicon or other materials as described above, or may be substantially undoped. The hard mask may be formed in any deposition chamber, such as a dielectric deposition chamber. The hard mask may be deposited to varying thicknesses between approximately 1000 Å and approximately 5000 Å. For example, depending on the depth of the capacitor hole, the hard mask may be between approximately 1000 Å and approximately 2000 Å, between approximately 2000 Å and approximately 3000 Å, between approximately 3000 Å and approximately 4000 Å, between approximately 4000 Å and approximately 5000 Å, or greater than approximately 5000 Å. The hard mask thickness may also be within any range within the ranges described above (e.g., between approximately 3500 Å and approximately 4500 Å). The thickness of the hard mask can also be any single value contained in the range described above (eg, approximately 3500 Å).

[0043] One or more precursors may be delivered to a processing region of a chamber. For example, the film being deposited may be a mask film for semiconductor processing. Deposition precursors may include any number of mask precursors, including one or more boron-containing precursors. The precursors may be flowed together or separately. For example, in exemplary embodiments in which a boron-containing film may be formed, at least one boron-containing precursor may be delivered to a processing region of a processing chamber. Plasma-enhanced deposition may be performed in some embodiments of the present technology, which may promote material reaction and deposition. For example, a plasma may be formed from a boron-containing precursor, and a boron-containing material may be deposited as appropriate.

[0044] Boron-containing hard masks can be characterized by relatively high hardness, which can improve etch selectivity. However, to further improve etch selectivity toward underlying silicon-containing materials (such as silicon oxide or silicon nitride layers that may be present in DRAM structures), the present technology can incorporate one or more dopant materials, which may include one or more metals. Thus, some embodiments may include additionally providing a dopant-containing precursor, provided along with other deposition precursors. As explained above, the delivered precursors may all be used to form a plasma within a processing region of a semiconductor processing chamber, and thus the sequence of operations may include operations occurring in different orders (including simultaneously). For example, a material including a dopant within a deposited boron hard mask may be deposited on a substrate. In some embodiments, by integrating a dopant-containing precursor, etch selectivity can be increased while producing a film with controlled hardness and transparency.

[0045] Depending on the precursors used, the flow rate of the dopant precursor can be used to control the integration of the dopant. For example, while other deposition precursors may have flow rates of hundreds of sccm or greater, the dopant precursor may flow at a flow rate of less than or about 250 sccm, and may be delivered at a flow rate of less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm, less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 25 sccm, less than or about 20 sccm, less than or about 15 sccm, less than or about 10 sccm, less than or about 5 sccm, or less.

[0046] With respect to boron-containing precursors, the present technology can utilize any number of precursors. For example, the boron-containing material can include a borane, such as borane, diborane, or other multi-center bonded boron materials, as well as any other boron-containing material that can be used to generate a boron-containing material. The boron integration in the resulting hard mask can be based on any percentage; however, most hard masks described herein will include a relatively high boron content relative to any additional dopants. For example, a boron hard mask can include greater than or about 40% boron, a boron hard mask can include greater than or about 50% boron, a boron hard mask can include greater than or about 60% boron, a boron hard mask can include greater than or about 70% boron, greater than or about 75% boron, greater than or about 80% boron, greater than or about 85% boron, greater than or about 90% boron, greater than or about 95% boron, greater than or about 97% boron, greater than or about 98% boron, or greater, including films that are substantially or essentially boron, less than the amount of dopant within the film. While trace amounts of materials exposed to the atmosphere or other process environment may be integrated within the film, it will be understood that the film may still be substantially boron-based in nature.

[0047] The dopant precursor can include any precursor, including any metal or transition metal that can be delivered to the processing region in a stable form. Some embodiments may use silicon as a precursor to form a silicon-doped boron hard mask. For example, an amorphous boron hard mask can be doped with silicon to form an aB(Si) hard mask. One or more dopants may be included in any amount or concentration and may be individually or collectively included in the deposited film at greater than or about 1 atomic %, and in some embodiments, greater than or about 2 atomic %, greater than or about 3 atomic %, greater than or about 4 atomic %, greater than or about 5 atomic %, greater than or about 6 atomic %, greater than or about 7 atomic %, greater than or about 8 atomic %, greater than or about 9 atomic %, greater than or about 10 atomic %, greater than or about 11 atomic %, greater than or about 12 atomic %, greater than or about 13 atomic %, greater than or about 14 atomic %, greater than or about 15 atomic %, greater than or about 16 atomic %, greater than or about 17 atomic %, greater than or about 18 atomic %, greater than or about 19 atomic %, greater than or about 20 atomic %, or greater.

[0048] The temperature of the substrate can additionally affect deposition. For example, in some embodiments, during deposition, the substrate can be maintained at a temperature greater than or about 300° C., and can be maintained at a temperature greater than or about 325° C., greater than or about 350° C., greater than or about 375° C., greater than or about 400° C., greater than or about 425° C., greater than or about 450° C., greater than or about 475° C., greater than or about 500° C., greater than or about 525° C., greater than or about 550° C., greater than or about 575° C., greater than or about 600° C., or higher.

[0049] As mentioned above, the present technology can increase the selectivity of hard mask films while limiting hardness loss. For example, the film hardness of the boron-containing material according to some embodiments is maintained at greater than or about 20 GPa, and can be maintained at greater than or about 22 GPa, greater than or about 24 GPa, greater than or about 26 GPa, greater than or about 28 GPa, greater than or about 30 GPa, greater than or about 32 GPa, greater than or about 34 GPa, greater than or about 36 GPa, greater than or about 38 GPa, greater than or about 40 GPa, greater than or about 42 GPa, greater than or about 44 GPa, or greater, despite the integration of some metal materials that can reduce the film hardness.

[0050] The method may also include implanting ions into the hard mask (304). The ions may be implanted in a chamber separate from the chamber in which the hard mask is deposited. For example, some embodiments may use a high current (AC) ion implantation chamber that delivers a high ion beam current to implant ions into the hard mask layer. For example, the ion implantation chamber may be part of a separate platform or tool from the deposition chamber used to form the hard mask, or may be part of the same platform.

[0051] In some embodiments, the materials used for ion implantation may be limited to metal ions such as aluminum (Al), gallium (Ga), indium (In), tin (Sn), lanthanum (La), and / or other similar metals. Some embodiments may utilize additional metals such as molybdenum (Mo), ruthenium (Ru), tungsten (W), rhenium (Re), osmium (Os), and / or other similar metals or transition metals. Other embodiments need not be limited to metal ions and may additionally or alternatively utilize non-metal ions. For example, some embodiments may utilize additional boron (B) or silicon (Si) ions for implanting the hard mask. Other embodiments may utilize ions other than metal ions.

[0052] The ions may be implanted at elevated temperatures or at room temperature. The ions may be implanted at temperatures ranging from about 150° C. to about 550° C. For example, the ion implantation process may be performed at temperatures between about 25° C. and about 150° C., between about 150° C. and about 200° C., between about 200° C. and about 250° C., between about 250° C. and about 300° C., between about 300° C. and about 350° C., between about 350° C. and about 400° C., between about 400° C. and about 450° C., between about 450° C. and about 500° C., between about 500° C. and about 550° C., and at temperatures greater than or equal to about 550° C., depending on the type of ions being implanted and / or the specific ion implantation process used.

[0053] As described below, the depth of ion penetration into the hard mask can vary depending on the process used and the ion species used. In some embodiments, the ion implantation depth can be greater than about 80% of the thickness of the hard mask. For example, the ion implantation depth can be greater than or between about 50% and about 60%, greater than or between about 60% and about 70%, greater than or between about 70% and about 80%, greater than or between about 80% and about 90%, or greater than or between about 90% and about 100%.

[0054] The method may optionally include performing an annealing process (306) on the hard mask after implanting the hard mask with ions. The annealing process may be used to activate the deposited metal, allowing the metal to bond to the matrix of the hard mask or repair any damage caused by the ion implantation. Optionally, the steps of forming the hard mask (302), implanting ions in the hard mask (304), and / or annealing the hard mask (306) may be repeated to increase the thickness of the hard mask. For example, to achieve a greater ion penetration depth in the hard mask, a thin layer of hard mask (e.g., less than about 1000 Å, less than about 2000 Å, etc.) may be deposited. Ions may then be implanted in this thin layer, and an optional annealing may be performed. Another layer of hard mask may then be deposited, followed by ion implantation, and so on. Additionally or alternatively, a final annealing may be performed after multiple layers of hard mask have been formed. This may result in full ion penetration depth for each layer of hard mask, thereby resulting in a hard mask layer with more complete ion penetration. For example, the ion penetration depth of a single ion process can be between approximately 200 Å and approximately 400 Å (e.g., approximately 350 Å). This process can be repeated to provide a hard mask with ion penetration throughout the entire depth of the hard mask. Alternatively, some ion types can provide greater penetration depths. For example, depending on the energy of the ion implantation process, aluminum can penetrate to depths between approximately 190 Å and approximately 1900 Å, and gallium can penetrate to depths between approximately 190 Å and approximately 425 Å. Even if the entire hard mask layer is not modified by the implanted ions, results indicate that in some integration scenarios, improving etch selectivity near the top of the hard mask while leaving underlying layers beneath the ions can still provide significant benefits. For example, after etching capacitor holes, the undoped layer near the bottom of the hard mask may be easier to remove. If greater ion penetration is desired, another technique is described below in FIG. 4.

[0055] Depending on the type of implant, the ion implantation process may utilize various energy levels. Typically, the energy of the ion implantation process may range from approximately 10 keV to approximately 100 keV. For example, the energy may range from approximately 10 keV to approximately 20 keV, from approximately 20 keV to approximately 30 keV, from approximately 30 keV to approximately 40 keV, from approximately 40 keV to approximately 50 keV, from approximately 50 keV to approximately 60 keV, from approximately 60 keV to approximately 70 keV, from approximately 60 keV to approximately 70 keV, from approximately 70 keV to approximately 80 keV, from approximately 80 keV to approximately 90 keV, or from approximately 90 keV to approximately 100 keV. The energy can also vary between any ranges within the ranges described above (e.g., between about 22.5 keV and about 60 keV, between about 12 keV and about 60 keV, etc.). The energy can also include any specific value within the ranges above (e.g., about 12 keV, about 27.5 keV, about 22.5 keV, about 32.5 keV, about 60 keV, about 80 keV, etc.).

[0056] The method may also include opening the hard mask (308) to expose the patterned layer of the underlying capacitor mold. For example, a capacitor hole may be opened in the hard mask so that a subsequent etching process can access the location for the capacitor hole in the underlying mold or DRAM structure through the opening in the hard mask. For example, opening the hard mask may include patterning the hard mask using tetraethyl orthosilicate (TEOS) hard mask deposition, carbon hard mask deposition, and lithographic stack deposition. The lithographic stack may then be patterned by a lithographic process, and the pattern may be etched into the carbon layer. The carbon layer may then be used as a hard mask to pattern the TEOS layer. Next, the TEOS layer may be used to pattern the hard mask layer and complete the hard mask opening step. Other processes and materials may be used depending on the embodiment.

[0057] The method may then include performing an etching process through the opening in the hard mask to etch the capacitor hole in the mold (310). One way to characterize the hard mask may include measuring the etch selectivity of the hard mask relative to other materials in the mold structure. More specifically, some embodiments may characterize the hard mask as an improvement in the etch selectivity of the hard mask compared to a hard mask without ion implantation. For example, some embodiments may characterize the hard mask with ion implantation as having an etch selectivity improvement relative to other mold materials of greater than or about 10% when compared to the same composition of the hard mask without ion implantation. In some embodiments, a 10% improvement in etch selectivity using ion implantation may result in a corresponding reduction in the thickness of the hard mask. For example, using an ion implanted hard mask may result in a 10% reduction in the thickness of the hard mask used to etch the capacitor hole.

[0058] Improvements in the hard mask's etch selectivity can be determined by the type of ions used for ion implantation. For example, doping the hard mask with boron (B) ions can improve the hard mask's etch selectivity by between approximately 4% and approximately 7%. Doping the hard mask with indium (In) ions can improve the hard mask's etch selectivity by between approximately 1% and approximately 18%. Doping the hard mask with helium (He) ions can improve the hard mask's etch selectivity by between approximately 11% and approximately 13%. Doping the hard mask with neon (Ne) ions can improve the hard mask's etch selectivity by up to approximately 13%. Doping the hard mask with lanthanum (La) ions can improve the hard mask's etch selectivity by between approximately 4% and approximately 6%. Etch selectivity can refer to the selectivity of the etch process for the hard mask relative to the underlying semiconductor structure (e.g., oxide / nitride layer, TEOS layer, etc.) when etching capacitor holes.

[0059] Improvements in the hard mask's etch selectivity can also be characterized by how much the hard mask's thickness can be reduced when ion implantation is used, compared to a hard mask of the same material without ion implantation. For example, a boron-based hard mask with ion implantation using the materials described above can be 10% thinner than the same boron-based hard mask without implantation to etch capacitor holes of the same size (e.g., same CDU, same depth, same width, etc.). In other embodiments, the hard mask's thickness can be reduced by between approximately 5% and approximately 7%, between approximately 7% and approximately 9%, between approximately 9% and approximately 11%, between approximately 11% and approximately 13%, between approximately 13% and approximately 15%, between approximately 15% and approximately 17%, and / or between approximately 17% and approximately 20%. The hard mask's thickness can also be reduced by any of the above ranges (e.g., between approximately 8% and approximately 12%). The thickness of the hard mask may also be reduced by any specific value within the above range (eg, approximately 10%).

[0060] It should be understood that the specific steps illustrated in FIG. 3 provide specific methods for forming a hard mask according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Furthermore, the individual steps illustrated in FIG. 3 may include multiple sub-steps, which may be performed in various sequences appropriate to the individual steps. Furthermore, additional steps may be added or removed depending on the specific application. Numerous variations, modifications, and alternatives are within the scope of this disclosure.

[0061] As described above, the ion implantation process may not be able to penetrate all the way down and / or through the entire thickness of the hard mask. This is particularly true when using a thicker hard mask. For example, when using indium as the ion implant, the etch selectivity of the hard mask relative to the underlying semiconductor structure can be increased by more than 10%. However, even when implanted at an energy of approximately 27.5 keV, the penetration depth of the indium ions can be less than approximately 400 Å. Furthermore, implanting ions in the hard mask can make the hard mask too hard for conventional hard mask opening steps, in which the hard mask layer is patterned to form capacitor holes in the hard mask. Therefore, another method, described below, can be used to provide a greater penetration depth, particularly around the capacitor holes in the semiconductor structure.

[0062] FIG4 illustrates a flow chart of a method 400 for forming a hard mask, according to some embodiments. The method may include forming a hard mask (402), as described above in operation 302 of method 300. For example, this operation may include forming a boron-based hard mask over a semiconductor structure. The boron-based hard mask may include any of the boron compositions described herein (e.g., greater than approximately 90% boron, doped with silicon, etc.). The semiconductor structure may include a DRAM structure or die, which may include a plurality of nitride / oxide layers (e.g., TEOS layers).

[0063] The method may also include opening the hard mask using a pattern of a plurality of holes to be formed in the semiconductor substrate (404). The plurality of holes may represent capacitor holes in a DRAM structure. The hard mask may be opened as described above in operation 308 of method 300. Note that instead of applying ion implantation to the hard mask before opening the hard mask, the method 400 may first open the hard mask and then perform the ion implantation process.

[0064] FIG. 5A illustrates a structure 500 having a hard mask 504 opened prior to performing an ion implantation process 507, according to some embodiments. The hard mask 504 may include an opening 507 that exposes an underlying semiconductor structure 502 (such as a top layer of a DRAM structure). An ion implantation process 508 may be performed on the hard mask 504 to implant ions therein. Note that the ion implantation process 508 may be directed perpendicular to the surface of the hard mask 504, such that the ions penetrate perpendicular to the surface of the hard mask 504.

[0065] FIG. 5B illustrates structure 500 after an ion implantation process, according to some embodiments. Hard mask 504 may now include doped regions 510 that have been doped using ion implantation. Note that the penetration depth is similar to that observed in method 300, where ion implantation process 508 may be performed before forming opening 507. However, opening 507 may be formed before hardening hard mask 504 via ion implantation process 508. This may allow for more precise opening of the hard mask using the techniques described above.

[0066] In some embodiments, the ion implantation process 508 may additionally or alternatively be performed at an angle that is not perpendicular to the surface of the hard mask 504. Thus, the method 400 may optionally include implanting the hard mask 504 with ions at an angle into the vertical sidewalls of the opening in the hard mask (406). For example, the ion implantation process 508 may be performed such that the ions penetrate the surface of the hard mask at an angle that is not perpendicular to the hard mask (e.g., less than 90°).

[0067] FIG. 6 illustrates a structure 600 in which an ion implantation process is performed at an angle, according to some embodiments. Changing the angle of the ion implantation process 608 can be performed by tilting a substrate support in an ion implantation semiconductor processing chamber. This can tilt the semiconductor structure 602 relative to the ion implantation process 608. Angle 611 can be less than 90°, as shown in FIG. The angle of the semiconductor structure 602 and / or hard mask 604 relative to the ion implantation process 608 can allow the ion implantation process 608 to penetrate the vertical sidewalls of the opening 607 in the hard mask 604, as diagrammatically shown in FIG.

[0068] Note that FIG. 6 only illustrates the angle 611 of the ion implantation process 608 relative to the semiconductor structure 602. Relative to the ion implantation chamber, the ion implantation process 608 can still be directed vertically downward toward the bottom of the chamber. In other words, the absolute direction of the ion implantation process does not need to change. As described above, angle 611 can be introduced by tilting the semiconductor substrate support within the ion implantation chamber. To induce ion penetration along the entire radius of the opening 607, the substrate support can be rotated about an axis (e.g., a central axis). This allows the ion penetration to rotate about the inner radius of the opening 607 and penetrate along the entire surface of the opening 607.

[0069] FIG7 shows a cross-sectional view 700 of a hard mask 704 when ion implantation is performed at an angle, according to some embodiments. Angle 713 (e.g., the tilt angle of the substrate support) can be calculated so that the ion implantation process 714 penetrates down to the bottom of the opening. Note that FIG6-7 only depicts a single opening. However, it should be understood that many other openings may exist in the hard mask 704 as part of the pattern of capacitor holes. Thus, distance 716 can represent the distance between adjacent capacitor holes in the DRAM structure. Angle 713 can be calculated using the thickness 710 of the hard mask 704 and the desired width 712 of the capacitor holes. Basic trigonometric functions can be used with these measurements to calculate the appropriate angle 713.

[0070] While FIG. 7 illustrates the ion implantation process 714 penetrating down to the bottom of the hard mask 704 (e.g., to the top of the semiconductor structure 702), the angle can be adjusted to leave portions of the hard mask 704 undoped by the ions. As described above, this can facilitate easy removal of the hard mask 704 after etching the capacitor holes. For example, the angle 713 can be calculated using the desired vertical penetration depth into the hard mask 704 rather than the thickness 710 of the hard mask 704. For example, some embodiments may penetrate to a depth less than approximately 60%, less than approximately 70%, less than approximately 80%, less than approximately 90%, or less than approximately 100% of the thickness 710 of the hard mask 704. Some embodiments may also be described as having a maximum penetration depth greater than approximately 60%, approximately 70%, approximately 80%, approximately 90%, and / or approximately 100% of the thickness 710 of the hard mask 704. The penetration depth may also be characterized by any value within the range described above (eg, about 80% penetration) or by any range encompassed by the range described above (eg, between about 75% and about 85%).

[0071] The horizontal depth of ion penetration into the sidewalls of the openings in hard mask 704 can be controlled by the implantation energy used during the ion implantation process. For example, applying higher energies during the implantation process can drive the ions deeper into the sidewalls of the openings. The implantation energy can be calculated by determining the distance 716 separating the openings in hard mask 704. This distance 716 can also correspond to the spacing of capacitor holes in the DRAM structure. For example, the spacing of the capacitor holes can be divided in half and used as the desired horizontal penetration depth (e.g., half of the distance 716 separating the openings, since penetration will come from both sides of adjacent openings).

[0072] In some embodiments, method 400 may be combined with method 300 for the ion implantation step. For example, a hard mask may be formed, and ions may be implanted vertically into the hard mask before opening. The hard mask may then be opened, and ions may then be implanted at an angle into the sidewalls of the opening. As described above, method 400 may also include annealing the hard mask (408) and performing an etch to form a plurality of holes (410) in the underlying semiconductor structure. For example, etching may form a plurality of capacitor holes in a DRAM structure through openings in a boron-based hard mask. The ions may increase the etch selectivity of the DRAM structure relative to the boron-based hard mask.

[0073] It should be understood that the specific steps illustrated in FIG. 4 provide specific methods for forming a hard mask according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. Furthermore, the individual steps illustrated in FIG. 4 may include multiple sub-steps, which may be performed in various sequences appropriate to the individual steps. Furthermore, additional steps may be added or removed depending on the specific application. Numerous variations, modifications, and alternatives are within the scope of this disclosure.

[0074] FIG8 shows a table 800 listing several different types of processing conditions for ion implantation recipes used in an ion implantation process, according to some embodiments. While many different types can be used, table 800 illustrates ions including boron, indium, helium, and neon. These exemplary ion implantation processes can use energies ranging from approximately 32.5 keV to approximately 60 keV, with a dose between approximately 1E+15 ions / cm² and approximately 1E+16 ions / cm².

[0075] Table 800 shows that the optional annealing process can improve etch selectivity compared to a hard mask without annealing after ion implantation. For example, when indium is used as the ion species, the etch selectivity does not show a significant change without the annealing process, but shows an etch selectivity improvement of approximately 17% with the annealing process.

[0076] The annealing process can be performed using an argon flow at the temperature described above (e.g., approximately 600°C) for between approximately 20 and 50 minutes (e.g., approximately 30 minutes). The annealing process can be performed after the ion implantation process has been completed. Alternatively, the annealing process can be performed simultaneously with the ion implantation process. For example, the substrate can be heated to a temperature above approximately 500°C. The ion implantation process can then be performed on the heated substrate, which can produce similar results as when a separate annealing process is performed after the ion implantation process is completed.

[0077] Table 800 also illustrates the effects of some non-metal implants, such as neon and helium. Thus, some embodiments may utilize metal ion implants, while others may utilize non-metal implants. Although neon and helium are inert and do not combine with other elements in the hard mask, some improvement in the hard mask etch selectivity can still be achieved when these non-metal ion implants are used. For example, metal ion implants can be said to exhibit chemically driven etch selectivity improvements. Non-metal implants (e.g., helium, neon, boron, etc.) can have a densifying effect and can remove elements, such as hydrogen, that may be embedded in the hard mask film.

[0078] As used herein, the terms "about" or "approximately" or "substantially" should be interpreted as being within the range expected by one of ordinary skill in the art in view of the present specification.

[0079] In the above description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be apparent that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and components are shown in block diagram form.

[0080] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the above description of the various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.

[0081] Specific details are provided in the above description to provide a thorough understanding of the present disclosure. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be illustrated as components in block diagram form in order to avoid obscuring the embodiments with unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be illustrated without unnecessary detail in order to avoid obscuring the embodiments.

[0082] Furthermore, it is noted that the individual embodiments may be described as processes, which may be depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. Although a flowchart may depict operations as a sequential process, many operations may be performed in parallel or concurrently. Furthermore, the order of the operations may be rearranged. A process may terminate when its operations are completed but may have additional steps not included in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to a return of the function to the calling function or the main function.

[0083] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subroutine, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or programming statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0084] Furthermore, embodiments may be implemented using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, code or code segments for performing necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0085] In the foregoing description, features are described with reference to specific embodiments thereof, but it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be utilized individually or in combination. Furthermore, the embodiments may be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the description. The description and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

[0086] Furthermore, for illustrative purposes, the methods are described in a particular order. It should be understood that, in alternative embodiments, the methods may be performed in a different order than that described. It should also be understood that the methods described above may be performed by hardware components or may be embodied in a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or logic circuit) programmed with the instructions to perform the methods. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy disk, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other type of machine-readable media suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

[0087] 100: Processing chamber 101: Controller 102: Chamber body 103:Substrate 104: substrate support 105: Surface 106: Cover assembly 107: Processor 112: Gas distributor 114: Entrance 118: aperture 120:Processing volume 122: first electrode 124: second electrode 126: Opening 136: Tuned Circuit 138:Electronic sensor 140: Electronic controller 142: First Power Source 144:Shaft 146: Pipeline 148:Filter 150: Second power source 152:Export 200:DRAM structure 202:Metal layer 204: Silicon nitride layer 206: oxide layer 208-2: Top nitride layer 210-2: Oxide layer 212: Hard Mask 214:Capacitor hole 300: Method 302: Operation 304: Operation 306: Operation 308: Operation 310: Operation 400:Method 402: Operation 404: Operation 406: Operation 408: Operation 410: Operation 500:Structure 502: underlying semiconductor structure 504: Hard Mask 507: Open 508: Ion Implantation Process 510: doped region 600:Structure 602:Semiconductor structure 604:Hard Mask 607: Opening 608: Ion Implantation Process 611: Angle 700: Cross-section 702:Semiconductor structure 704: Hard Mask 710:Thickness 712: Width 713: Angle 714: Ion Implantation Process 716: Distance 800: Table

[0088] Domestic storage information (please note the order of storage institution, date, and number) none

[0089] Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method of forming a hard mask, the method comprising: in a first semiconductor processing chamber: delivering a boron-containing precursor to a processing region of the semiconductor processing chamber; forming a plasma of all the precursor in the processing region of the first semiconductor processing chamber; and forming a boron-based hard mask on a substrate disposed in the processing region of the first semiconductor processing chamber; and in a second semiconductor processing chamber: implanting the boron-based hard mask using ion deposition.

2. The method as described in claim 1, further comprising, in the first semiconductor processing chamber: delivering a dopant-containing precursor together with the boron-containing precursor to the processing region of the first semiconductor processing chamber, wherein a dopant concentration within the boron-based hard mask is maintained at less than or about 10 atoms.

3. The method as described in claim 2, wherein the dopant-containing precursor comprises silicon.

4. The method as described in claim 1, wherein the plasma is implanted using a high ion beam current to implant the plasma in the boron-based hard mask.

5. The method as described in claim 1, wherein the plasma comprises indium ions.

6. The method as described in claim 1, wherein the plasma comprises helium ions.

7. The method as described in claim 1, wherein the plasma comprises neon ions.

8. A method using a hard mask, comprising: forming a dynamic random access memory (DRAM) structure comprising a plurality of alternating layers of oxide and nitride materials; forming a boron-based hard mask over the DRAM structure, wherein the boron-based hard mask comprises at least 90% boron; ion-planting the boron-based hard mask; opening the boron-based hard mask using a pattern of a plurality of capacitor vias to be formed in the DRAM structure; and performing an etching to form the plurality of capacitor vias in the DRAM structure through the openings in the boron-based hard mask, wherein ion-planting the boron-based hard mask increases the selectivity of the DRAM structure relative to the etching of the boron-based hard mask.

9. The method as described in claim 8, wherein the step of plasma-planting the boron-based hard mask increases the selectivity of the DRAM structure relative to the etching of the boron-based hard mask by at least 10%.

10. The method of claim 8, wherein the plasma is implanted in the boron-based hard mask to a depth greater than about 50% of a thickness of the boron-based hard mask, and the boron-based hard mask has a thickness of at least 3000 Å.

11. The method as described in claim 8, wherein the boron-based hard mask is implanted with plasma before opening the boron-based hard mask.

12. The method as described in claim 8, further comprising: annealing the boron-based hard mask before opening the boron-based hard mask.

13. The method as described in claim 8, wherein the plasma is implanted in the boron-based hard mask before opening the boron-based hard mask.

14. A method of forming a hard mask, comprising: forming a boron-based hard mask over a semiconductor structure; opening the boron-based hard mask using a pattern of a plurality of holes to be formed in the semiconductor structure; tilting a substrate support in a semiconductor processing chamber to tilt the semiconductor structure relative to an ion implantation process; and using the ion implantation process to implant the boron-based hard mask with ions, wherein the tilted substrate implants the plasma at an angle in the vertical sidewalls of the plurality of openings in the boron-based hard mask.

15. The method as described in claim 14, wherein the plasma is implanted in the boron-based hard mask to a depth greater than about 80% of the thickness of the boron-based hard mask.

16. The method as described in claim 14, further comprising: annealing the boron-based hard mask after opening the boron-based hard mask.

17. The method of claim 16, further comprising: performing an etching to form the holes in the semiconductor structure through the openings in the boron-based hard mask, wherein the step of plasma-implanting the boron-based hard mask increases the selectivity of the semiconductor structure relative to the etching of the boron-based hard mask by at least 10%.

18. The method as described in claim 17, wherein a critical dimension of the plurality of holes is at least 15:

1.

19. The method as described in claim 17, wherein a depth of the plurality of holes is at least 300 nm.

20. The method as described in claim 17, wherein the selectivity of the etching is increased by at least 15%.

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