Layout and structure of protection diode circuit for 3D IC

Abstract

This invention proposes a protection diode circuit for a three-dimensional wafer, comprising a silicon-coated insulator substrate, a back-end metal interconnect structure located on the silicon-coated insulator substrate, a bottom contact connecting the silicon substrate of the silicon-coated insulator substrate to a first portion of the back-end metal interconnect structure, a first protection diode having a first gate connected to the first portion, a first P-type doped region connected to the first portion, and a first N-type doped region connected to a second portion of the silicon-coated insulator substrate, and a second protection diode having a second gate connected to the second portion, a second P-type doped region connected to the second portion, and a second N-type doped region connected to a third portion of the back-end metal interconnect structure.

Description

Technical Field

[0001] The present invention is generally related to the layout and structure of a protective diode circuit, and more specifically, to the layout and structure of a protective diode circuit for a three-dimensional wafer. Prior Technology

[0002] 3D ICs are a next-generation technology that stacks and bonds multiple IC chips vertically and electrically connects them through advanced interconnect structures such as micro-bumps or through-silicon vias (TSVs). This structure increases the component density per unit area, shortens signal transmission paths to reduce latency and power consumption, and integrates various functional circuits and / or components (such as logic, memory, and RF) onto a single chip to improve system performance. Due to these advantages, 3D ICs can be applied in many fields, such as memory devices like DRAM and FLASH, processors like CPUs and GPUs, communication devices like RF and 5G components, and consumer electronics products with integrated multi-functional modules.

[0003] In the field of communication equipment, the rapid development of 5G communication technology in recent years has led to a year-on-year increase in the use of radio frequency (RF) front-end components, driving market demand for RF-SOI (Radio Frequency Silicon-on-Insulator) components. RF-SOI is a silicon-based material technology specifically designed for RF applications. This technology utilizes an SOI (silicon-on-insulator substrate) structure, placing a thin silicon wafer on an insulating layer. Compared to ordinary silicon substrates, it can effectively reduce leakage current and improve power efficiency, making it particularly suitable for RF equipment requiring long-term operation. Its excellent high-frequency characteristics allow the chip to operate stably in the frequency range of several GHz, making it suitable for applications such as wireless communication and radar. Combined with 3D IC technology, RF-SOI components can be highly integrated with digital circuits and other analog circuits, simplifying system design and reducing costs.

[0004] However, since 3D ICs are composed of multiple integrated chips, and these chips have different inherent potentials, the components are susceptible to changes in their electrical properties due to the influence of other chips, such as critical voltage deviation. Furthermore, the components are easily damaged by electrostatic discharge during high-frequency operation, affecting reliability and performance. Therefore, those skilled in the art need to design a circuit structure to protect 3D ICs and avoid these problems. Summary of the Invention

[0005] In view of the problems encountered in the aforementioned prior art, the present invention proposes a novel protection diode circuit layout and structure, which can be used to protect components in 3D ICs and is compatible with existing RF-SOI processes.

[0006] One aspect of this invention is to provide a protective diode circuit layout for a three-dimensional wafer, comprising: a silicon-coated insulator substrate, consisting of a silicon substrate, a buried oxide layer, and a silicon layer; a back-end metal interconnect structure located on the silicon-coated insulator substrate; a bottom contact penetrating the silicon layer and the buried oxide layer and electrically connecting the silicon substrate and a first portion of the back-end metal interconnect structure; a first protective diode comprising: a first gate located on the silicon layer and connected to the first portion of the back-end metal interconnect structure; and a first P-type doped region located on the silicon layer. The silicon layer on one side of the gate and connected to the first portion; and a first N-type doped region located in the silicon layer on the other side of the gate and connected to a second portion of the back-end metal interconnect structure; a second protection diode comprising: a second gate located on the silicon layer and connected to the second portion of the back-end metal interconnect structure; a second P-type doped region located in the silicon layer on one side of the second gate and connected to the second portion; and a second N-type doped region located in the silicon layer on the other side of the gate and connected to a third portion of the back-end metal interconnect structure.

[0007] Another aspect of the present invention is to provide a protective diode circuit structure for a three-dimensional wafer, comprising: a first die, comprising: a silicon-coated insulator substrate, consisting of a silicon substrate, a buried oxide layer, and a silicon layer; a back-end metal interconnect structure located on the silicon-coated insulator substrate; a bottom contact penetrating the silicon layer and the buried oxide layer and connecting a first portion of the silicon substrate and the back-end metal interconnect structure; a first protective diode, comprising: a first gate located on the silicon layer and connected to the first portion of the back-end metal interconnect structure; a first P-type doped region located in the silicon layer on one side of the gate and connected to the first portion; and a first N-type doped region. A second protective diode, comprising: a second gate located on the silicon layer and connected to the second portion of the back-end metal interconnect structure; a second P-type doped region located on one side of the second gate and connected to the second portion; and a second N-type doped region located on the other side of the gate and connected to a third portion of the back-end metal interconnect structure; and a second die having a semiconductor element, wherein the first die is directly bonded to the second die through the back-end metal interconnect structure to form a three-dimensional wafer, and the semiconductor element is connected to the back-end metal interconnect structure.

[0008] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Simple Explanation of the Diagram

[0009] Figure 1 is a cross-sectional schematic diagram of a 3D IC according to Embodiment 1 of the present invention; Figure 2 is a schematic diagram of the layout of a protection diode circuit for a 3D IC according to Embodiment 1 of the present invention; and Figure 3 is a cross-sectional schematic diagram of the protection diode circuit structure for 3D IC according to Embodiment 1 of the present invention. It should be noted that all illustrations in this specification are for illustrative purposes only. For clarity and ease of explanation, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments. Implementation

[0010] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of illustration only and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0011] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" not only means "directly on" something, but also includes being "on" something with an intervening feature or layering structure. Similarly, "above" or "above" not only means "above" or "above" something, but also includes being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0012] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0013] Readers can generally understand the terminology used in this invention, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0014] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they explicitly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0015] The text uses designations such as "N" and "P," generally referring to "N-type" and "P-type" to indicate donor and acceptor dopants that promote electron and hole transport, such as P-type boron (B) atoms or N-type phosphorus (P) and arsenic (As) atoms. A dopant type ending in "++" indicates that its doping concentration is higher than that of dopants ending in "+". Conversely, a dopant type ending in "-" indicates that its doping concentration is lower than that of dopants without a suffix.

[0016] First, please refer to Figure 1, which is a cross-sectional schematic diagram of a 3D IC according to an embodiment of the present invention. As shown in the figure, the 3D IC of the present invention can be formed by bonding a first chip IC1 and a second chip IC2. In this embodiment of the present invention, the first chip IC1 and the second chip IC2 can be radio frequency (RF) chips, which can be equipped with CMOS and various RF components, such as amplifiers, switches and / or filters in RF front-end modules, and are not limited thereto. Each chip in the figure will only show one component for illustrative purposes. The first chip IC1 uses a silicon-coated insulator substrate (SOI1) as the basis for the components thereon, wherein the silicon-coated insulator substrate (SOI1) can be composed of a silicon substrate 100, an embedded oxide layer 104 and a thin silicon layer 106. The silicon substrate 100, as the bulk silicon body of the silicon-coated insulator substrate (SOI1), has a relatively thick thickness, approximately 500 µm to 1000 µm. The buried oxide layer 104 is located above the silicon substrate 100, and its material can be silicon oxide with a thickness of approximately 100 nm to 400 nm. The buried oxide layer 104 electrically isolates the silicon substrate 100 from the thin silicon layer 106 above it to reduce leakage current, thereby improving device performance and reliability. In an embodiment, a trap-rich layer 102 may also be present between the buried oxide layer 104 and the silicon substrate 100, and its material can be silicon nitride with a thickness of approximately 10 nm to 100 nm. The trap-rich layer 102 can trap free carriers, reduce the carrier concentration in the silicon layer, and further improve the resistivity of the SOI substrate, making it particularly suitable for high-frequency or high-voltage applications. The thin silicon layer 106 is the device layer, in which various doped regions required for the device are formed, and its material can be p-type doped silicon with a thickness of approximately 50 nm to 200 nm.

[0017] Referring again to Figure 1. In this embodiment, a first element 10, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is formed on the silicon-coated insulator substrate SOI1. Its source / drain is formed in a thin silicon layer 106 of the silicon-coated insulator substrate SOI1, and its gate is disposed on the surface of the thin silicon layer 106. These terminals can be electrically connected to the upper back-end metal interconnects (BEOL) MI1 through contacts BC formed in the interlayer dielectric layer (ILD) 112. Furthermore, in this embodiment, the well-rich layer 102 in the silicon-coated insulator substrate SOI1 can also be electrically connected to the back-end metal interconnects MI1 through a bottom contact TBV1 to conduct the well-rich layer 102 to an external circuit, such as a high-frequency capacitor located on the other side. The back-end metal interconnect structure MI1 is composed of multiple metal layers and vertically connected vias, which are formed in the corresponding inter-metal dielectric (IMD) layers. It can electrically connect different components and parts, ensuring that signals and power can be transmitted throughout the circuit.

[0018] Referring again to Figure 1. In this embodiment, the structure of the second chip IC2 is largely the same as that of the first chip IC1, except that it lacks a well-rich layer. As shown, the second chip IC2 uses a silicon-coated insulator substrate (SOI2) as the basis for its components. The SOI2 can be composed of a silicon substrate 200, a buried oxide layer 204, and a thin silicon layer 206. A second element 20 is formed on the SOI2, and its endpoints can be electrically connected to the subsequent metal interconnect structure MI2 through a contact BC formed in the interlayer dielectric layer 212. Furthermore, the silicon substrate 200 in the SOI2 can also be electrically connected to the subsequent metal interconnect structure MI2 through a bottom contact TBV2, so as to be further connected to external radio frequency components, such as high-frequency capacitors, in subsequent processes. In this embodiment, the second chip IC2 is stacked on top of the first chip IC1, and the wafers are bonded together by interfacing their topmost bonding layers BL1 and BL2. BI in the figure represents the bonding interface. Furthermore, the hybrid vias HBV1 and HBV2 located in the bonding layers BL1 and BL2 are also interfacing with each other during this process to achieve circuit connections between the two chips. This constitutes a 3D IC architecture.

[0019] In practice, after the first chip IC1 and the second chip IC2 are bonded, the silicon substrate 200 on the back side of the second chip IC2 can be removed to expose the bottom contact TBV2 that penetrates the thin silicon layer 206 and is embedded in the oxide layer 204. 3D IC bonding and subsequent post-bonding processes can then be performed on this exposed substrate, such as fabricating MIM (metal-insulator-metal) high-frequency capacitors for radio frequency chips, metal layers and ultra-thick metal layers (UTM) for inductors, and external pads. Since these components are not the focus of this invention, they will not be described in detail here.

[0020] In this invention, because the first chip IC and the second chip IC2 have different inherent potentials V1 and V2, the potential difference between them after bonding can easily cause carriers in the well-rich layer 102 of the first chip IC to flow to the second element 20 in the second chip IC2 through the connected back-end metal interconnect structures MI1 and MI2, causing a critical voltage shift in the second element 20, and in severe cases, even damaging the element. Therefore, this invention proposes a protection diode circuit to solve this problem. The layout and structure of this protection diode circuit will be described with reference to Figures 2 and 3 in subsequent embodiments.

[0021] Please now refer to Figure 2, which is a schematic diagram of the layout of a protection diode circuit for 3D ICs according to an embodiment of the present invention. The protection diode circuit of the present invention mainly comprises two protection diodes connected in series. As shown in the figure, in the embodiment, each protection diode PD1, PD2 is composed of a gate G1, G2, a P-type doped region S1, S2 (i.e., the anode of the diode), and an N-type doped region D1, D2 (i.e., the cathode of the diode). The P-type doped region S1, S2 and the N-type doped region D1, D2 can be heavily doped regions formed in the aforementioned thin silicon layer 106 (Figure 1), and the two have different doping types (P+, N+) to form a diode. The gate G1, G2 serves as an isolation structure between the diode anode and cathode, and can be a polycrystalline silicon layer formed on the thin silicon layer 106, with its two sides adjacent to the P-type doped region S1, S2 and the N-type doped region D1, D2, respectively. In terms of shape, the gates G1 and G2, the P-type doped regions S1 and S2, and the N-type doped regions D1 and D2 can be elongated strips extending in a second direction d2, which is preferably orthogonal to the first direction d1. In practice, the thin silicon layer 106 is first defined by a shallow trench isolation structure (STI, see Figure 3) to define the diffusion region DF (also called the active region) of each device as the conductive region of the device. Then, N-type dopants such as phosphorus (P) and arsenic (As) are incorporated into the defined N-well region NW by ion implantation or diffusion process, thus forming an N-well in the silicon diffusion region DF. The P-type doped regions S1 and S2 and the N-type doped regions D1 and D2 can also be doped by using the gates G1 and G2 as a mask to dope the exposed diffusion region DF, thus forming a self-aligned N-well on the diffusion region DF. It should be noted that the various doped regions shown in the figure are photomask patterns. The size and range of the doped regions formed after the actual process will depend on the masking and substrate present during the process.

[0022] Refer to Figure 2 again. The protection diodes PD1, PD2 are preferably adjacent in the first direction d1, and the N-type doping region D1 of the protection diode PD1 will be adjacent to the P-type doping region S2 of the protection diode PD2 to facilitate the connection of the back-segment circuit. In embodiments, the protection diode PD1, the respective endpoints of PD2 are connected to the rear segment metal interconnect structure and / or an external circuit through their corresponding contacts. Specifically, in an embodiment of the present invention, the well-trap layer 102 in the preceding first wafer IC 1 is connected to the upper back-segment metal interconnect structure MI1 through the bottom contact TBV 1 passing through the isolayer structure of the embedded oxide layer 104 , the thin silicon layer 106 , and the interlayer dielectric layer 112 (Fig. 1 ). The bottom contacts TBV 1 may be arranged and aligned on the second direction d 2 , to which they may be the first portion P 1 of the first metal layer M 1 in the rear segment metal interconnect structure. The P-type doping region S1 of the protection diode PD1 is also connected upward to the first portion P1 through contacts BC2. In addition, the gate G1 protecting the diode PD1 is also connected upward to that first part P1 via contacts BC1. On the other hand, the N-type doping region D1 of the protection diode PD1 will be connected upward to a second part P2 of the first metal layer M1 through contact BC3, and the gate G2 and P-type doping region S2 of the protection diode PD2 will also be connected upward to the second part P2 via contacts BC1, BC2, respectively. The contacts BC1 may be arranged and aligned on the first direction d1. In this way, the protection diode PD1 and the protection diode PD2 are connected in series that is, through the second part P2 of the first metal layer M1. On the other hand, the N-type doping region D2 of the protection diode PD2 is connected upwards to a third portion P3 of the first metal layer M1 via contact BC3, and through the third portion P3 to the subsequent 3D IC circuit as desired protected component.

[0023] Please refer to Figure 3, which is a cross-sectional view of the aforementioned protective diode circuit along the line A-A' in Figure 2. The following embodiments will describe the structure of the protective diode circuit of the present invention from the perspective of this cross-section. As shown in the figure, the protective diodes PD1 and PD2 of the present invention are preferably formed on the silicon-coated insulator substrate SOI1 of the first chip IC1 (Figure 1). At the beginning of the circuit, the well-rich layer 102 and / or silicon substrate 100 in the silicon-coated insulator substrate SOI1 are first connected to the first portion P1 of the first metal layer M1 through the bottom contact TBV1, passing through layers such as the buried oxide layer 104, the shallow trench isolation structure STI, the buffer layer 108, the etch stop layer 110, and the interlayer dielectric layer 112. Protective diodes PD1 and PD2 can be disposed on the diffusion region (represented by the thin silicon layer 106 in this figure) near the bottom contact TBV1, which is surrounded and defined by a shallow trench isolation structure STI. The P-type doped regions S1 and S2 and the N-type doped regions D1 and D2 of the protective diodes PD1 and PD2 can be formed in the N-type well NW defined within the thin silicon layer 106. The isolation gates G1 and G2 of the protective diodes PD1 and PD2 are disposed on the thin silicon layer 106 between the P-type doped regions S1 and S2 and the N-type doped regions D1 and D2. A gate oxide layer 107 can be separated from the thin silicon layer 106 to further enhance the electrical isolation effect. Hard shielding layers 109 and spacers 111 are also formed on the top and sides of the gates G1 and G2 to facilitate patterning and the definition of the P-type doped regions S1 and S2 and the N-type doped regions D1 and D2.

[0024] Referring again to Figure 3, in this embodiment, the first portion P1 of the first metal layer M1 is connected downwards to the P-type doped region S1 of the protective diode PD1 via contact BC2, and the N-type doped region D1 at the other end of the protective diode PD1 is connected upwards to the second portion P2 of the first metal layer M1 via contact BC3. Similarly, the second portion P2 is connected downwards to the P-type doped region S2 of the protective diode PD2 via contact BC2, and the N-type doped region D2 at the other end of the protective diode PD2 is connected upwards to the third portion P3 of the first metal layer M1 via contact BC3, and then connected to the subsequent 3D IC circuit via the third portion P3.

[0025] According to the circuit design described in the above embodiment, in actual operation, the protection diodes PD1 and PD2 can protect the MOS components in the main circuit through a gate clamping mechanism. The high carrier concentration and tendency to generate electrostatic discharge (ESD) of the first chip IC1, with its well-rich layer 102 (i.e., input terminal In), is connected to the P-type doped region S1 (i.e., anode) and gate G1 of the protection diode PD1 through the bottom contact TBV1 and the first part P1 of the rear metal layer. The two protection diodes PD1 and PD2 are connected in series through the second part P2 of the rear metal layer. The polysilicon gates G1 and G2 provide better isolation in the protection diode PD1 and PD2 series, offering superior current carrying capacity and reduced turn-on resistance and turn-on time. The N-type doped region D2 (i.e., cathode) of the protection diode PD2 is connected to the source or drain of the circuit or MOS component to be protected (such as the second component 20 in the second chip IC2) through the third part P3 (i.e., output terminal Out) of the rear metal layer. Protection diodes PD1 and PD2 are adjusted to be off under normal operating conditions and turned on during electrostatic discharge (ESD) surges. Their turn-on voltage is greater than an absolute voltage value but less than the breakdown voltage of the component to be protected. This effectively clamps the voltage from the well-rich layer 102 to prevent it from exceeding its breakdown voltage, thus avoiding damage to the component or critical voltage deviation. This is the effectiveness of the present invention. The present invention further reduces the impact of the well-rich layer on other circuits by connecting the two protection diodes in series, where the thick gate oxide layer and polysilicon gate further reduce the impact of the well-rich layer on other circuits. This is another advantage of the present invention. The above-described protection diode circuit is compatible with existing RF-SOI processes and can be integrated with the first component 10 during the fabrication of the first chip IC1, saving costs and processes. This is another advantage of the present invention. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0026] 10: First Component 20: Second Component 100: Silicon substrate 102: Well-rich layer 104: Embedded oxide layer 106: Thin silicon layer 107: Gate oxide layer 108: Buffer layer 109: Hard mask layer 110: Etching Stop Layer 111: Spacer 112: Interlayer dielectric layer 200: Silicon substrate 204: Embedded oxide layer 206: Thin silicon layer 212: Interlayer dielectric layer BC: Contacts BC1: Contact element BC2: Contact element BC3: Contact element BI: Bonding Interface BL1: Bonding layer BL2: Bonding layer D1: N-type doped region D2: N-type doped region DF: Diffusion region d1: First direction d2: Second direction G1: Gate G2: Gate IC1: First chip IC2: Second chip In: Input end M1: First metal layer MI1: Back-end metal interconnect structure MI2: Back-end metal interconnect structure NW: N-type well (area) Out: Output terminal P1: Part 1 P2: Part Two P3: Part Three PD1: Protective diode PD2: Protective diode S1: P-type doped region S2: P-type doped region SOI1: Silicon-coated insulator substrate SOI2: Silicon-coated Insulator Substrate STI: Shallow Trench Isolation Structure TBV1: Bottom contact component TBV2: Bottom Contact V1: Potential V2: Potential

Claims

1. A protective diode circuit layout for a three-dimensional wafer, comprising: a silicon-coated insulator substrate, comprising a silicon substrate, a buried oxide layer, and a silicon layer; a back-end metal interconnect structure located on the silicon-coated insulator substrate; a plurality of bottom contacts penetrating the silicon layer and the buried oxide layer and electrically connecting the silicon substrate and a first portion of the back-end metal interconnect structure; a first protective diode, comprising: a first gate located on the silicon layer and connected to the first portion of the back-end metal interconnect structure; a first P-type doped region located in the silicon layer on one side of the first gate and connected to the first portion; and a first N-type doped region located in the silicon layer on the other side of the first gate and connected to a second portion of the back-end metal interconnect structure; and a second protective diode, comprising: a second gate located on the silicon layer and connected to the second portion of the back-end metal interconnect structure. A second P-type doped region is located in the silicon layer on one side of the second gate and connected to the second portion; and a second N-type doped region is located in the silicon layer on the other side of the second gate and connected to a third portion of the back-end metal interconnect structure.

2. The protective diode circuit layout for a three-dimensional wafer as described in claim 1, wherein the first P-type doped region of the first protective diode and the second P-type doped region of the second protective diode are adjacent in a first direction, and the first P-type doped region, the second P-type doped region, the first N-type doped region, the second N-type doped region, the first gate, and the second gate extend in a second direction.

3. The protective diode circuit layout for a three-dimensional wafer as described in claim 2, wherein the bottom contacts are aligned in the second direction.

4. The protective diode circuit layout for a three-dimensional wafer as described in claim 2, wherein the first gate and the second gate are respectively connected to the first portion and the second portion via first contacts, and the first contacts are aligned in the first direction.

5. The protective diode circuit layout for a three-dimensional wafer as described in claim 2, wherein the first P-type doped region and the second P-type doped region are respectively connected to the first portion and the second portion through second contacts, and the second contacts are aligned in the second direction.

6. The protective diode circuit layout for a three-dimensional wafer as described in claim 2, wherein the first N-type doped region and the second N-type doped region are respectively connected to the second portion and the third portion via third contacts, and the third contacts are aligned in the second direction.

7. The protective diode circuit layout for a three-dimensional wafer as described in claim 1, wherein the first portion, the second portion, and the third portion of the back-end metal interconnect structure are located in a first metal layer.

8. A protection diode circuit structure for a three-dimensional wafer, comprising: a first die, comprising: a silicon-coated insulator substrate, consisting of a silicon substrate, a buried oxide layer, and a silicon layer; a back-end metal interconnect structure located on the silicon-coated insulator substrate; a bottom contact penetrating the silicon layer and the buried oxide layer and electrically connecting the silicon substrate and a first portion of the back-end metal interconnect structure; a first protection diode, comprising: a first gate located on the silicon layer and connected to the first portion of the back-end metal interconnect structure; a first P-type doped region located in the silicon layer on one side of the first gate and connected to the first portion; and a first N-type doped region located in the silicon layer on the other side of the first gate and connected to a second portion of the back-end metal interconnect structure; and a second protection diode, comprising: a second gate located on the silicon layer and connected to the second portion of the back-end metal interconnect structure. A second P-type doped region is located in the silicon layer on one side of the second gate and connected to the second portion; and a second N-type doped region is located in the silicon layer on the other side of the second gate and connected to a third portion of the back-end metal interconnect structure; a second die having a semiconductor element, wherein the first die is directly bonded to the second die through the back-end metal interconnect structure to form a three-dimensional wafer, and the semiconductor element is connected to the back-end metal interconnect structure.

9. The protective diode circuit structure for a three-dimensional wafer as described in claim 8 further includes a well-rich layer located between the silicon substrate and the buried oxide layer, and the bottom contact connecting the well-rich layer to the first portion of the subsequent metal interconnect structure.

10. The protective diode circuit structure for a three-dimensional wafer as described in claim 8, wherein the second die includes another silicon-coated insulator substrate, and the second die is connected to the rear metal interconnect structure of the first die through another rear metal interconnect structure to form the three-dimensional wafer.

11. The protective diode circuit structure for a three-dimensional wafer as described in claim 10, wherein the bottom contact in the first die is connected to the semiconductor element in the second die through the rear metal interconnect structure and the other rear metal interconnect structure.

12. The protective diode circuit structure for a three-dimensional wafer as described in claim 8 further includes an N-type well located in the silicon layer, wherein the first P-type doped region, the second P-type doped region, the first N-type doped region, and the second N-type doped region are located in the N-type wells.

13. The protective diode circuit structure for a three-dimensional wafer as described in claim 8, wherein the first portion, the second portion, and the third portion of the back-end metal interconnect structure are located in a first metal layer.

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