Single-stage non-isolated buck converter with high conversion ratio

Abstract

This invention discloses a single-stage non-isolated buck converter with a high conversion ratio, comprising an input capacitor, an output capacitor, a main inductor, a first switching circuit, multiple second switching circuits, a third switching circuit, and a switch control circuit. The first switching circuit includes a first high-side switch, a first clamping capacitor, and a first low-side switch. At least one second switching circuit includes a second high-side switch, a second clamping capacitor, a first auxiliary inductor, and a second low-side switch. The third switching circuit includes a third high-side switch, a third low-side switch, and a second auxiliary inductor. The switch control circuit is configured to control the first high-side switch, the first low-side switch, the second high-side switches, and the second low-side switches to be turned on and off in multiple operating modes.

Description

Technical Field

[0001] This invention relates to a DC power converter, and more particularly to a single-stage non-isolated buck converter with a high conversion ratio. Prior Technology

[0002] The widespread adoption of cloud computing and advancements in other network services have led to a sharp increase in energy consumption in data centers, requiring continuous improvement in the efficiency of systems and converters [1]-[2]. In data centers, the CPUs / GPUs / DDRs used require well-regulated DC voltages provided by voltage regulator modules (VRMs). Currently, the trend for VRMs to power microprocessors is to use 48V or 12V as the DC bus. In order to reduce power distribution losses, improve efficiency, and achieve better deployment flexibility, the 48V bus voltage structure used in data centers is receiving increasing attention due to the large transmission losses of the existing 12V DC bus voltage.

[0003] As a widely used converter, the 48V DC bus VRM has a variety of different topologies. One of the most popular solutions for 48V to 1.xV conversion is cascading two converters, where the first stage steps down the unregulated 48V to 12V, and the second stage converts the 12V to 1.xV. Typically, the first-stage 40V to 12V is mainly used to maintain conversion efficiency, while the second-stage 12V to 1.xV includes a multiphase interleaved buck converter capable of supplying high current (tens of amperes) to the CPU and reducing the size of the output filter, while maintaining good efficiency over a wide load range.

[0004] However, the overall efficiency of a two-stage converter is typically limited by the combined efficiency of the two stages, especially under light and maximum load conditions. Furthermore, the first stage operates at a higher output voltage or relatively lower frequency, using large passive components, which leads to reduced power density.

[0005] Therefore, single-stage converters have recently become more attractive and widely used. Due to their extremely low duty cycle, traditional buck converters are unsuitable for such single-stage applications. For example, using a conventional half-bridge buck converter would require producing a 1 / 48 duty cycle. This very low duty cycle necessitates extremely precise duty cycle production, as any delay in the feedback path will severely distort the output regulation, potentially leading to load shutdown.

[0006] Furthermore, the high voltage difference between the input and output of the converter translates into high voltage stress on the power switches, leading to higher switching losses and limiting the selection of power switches with poor quality factors (RON×QR). Therefore, developing topologies with high voltage gain becomes crucial. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a single-stage non-isolated buck converter with a high buck conversion ratio, which addresses the shortcomings of the prior art.

[0008] To address the aforementioned technical problems, one technical solution adopted by this invention is to provide a single-stage non-isolated buck converter, comprising an input capacitor, an output capacitor, a main inductor, a first switching circuit, multiple second switching circuits, a third switching circuit, and a switching control circuit. The first and second terminals of the input capacitor are respectively connected to the first and second terminals of an input power supply. The first and second terminals of the output capacitor are respectively connected to the first and second terminals of a load. The main inductor is connected between a common node and the first terminal of the output capacitor. The first switching circuit includes a first high-side switch, a first clamping capacitor, and a first low-side switch. The first terminal of the first high-side switch is connected to the first terminal of the input capacitor. The first clamping capacitor is connected between the second terminal of the first high-side switch and the common node. The first low-side switch is connected between the common node and the second terminal of the output capacitor. At least one second switching circuit includes a second high-side switch, a second clamping capacitor, a first additional inductor, and a second low-side switch. The second high-side switch has a first terminal and a second terminal, and each second high-side switch is connected between the second terminal of the first high-side switch and the common node. The first terminal of the second clamping capacitor is connected to the second terminal of the second high-side switch. The first and second terminals of the first additional inductor are respectively connected to the second terminal of the second clamping capacitor and a common node. The second low-side switch is connected between the first terminal of the first additional inductor and the second terminal of the output capacitor. The third switching circuit includes a third high-side switch, a third low-side switch, and the second additional inductor. The first terminal of the third high-side switch is connected to the second terminal of one of the second high-side switches. The first and second terminals of the third low-side switch are respectively connected to the second terminal of the third high-side switch and the second terminal of the output capacitor. The first terminal of the second additional inductor is connected to the second terminal of the third high-side switch, the first terminal of the third low-side switch, and the common node. The switch control circuit is configured to control the first high-side switch, the first low-side switch, each of the second high-side switches, each of the second low-side switches, the third high-side switch, and the third low-side switch to be turned on and off in multiple operating modes.

[0009] One of the advantages of this invention is that the single-stage non-isolated buck converter provided by this invention, compared to the switching network of a conventional buck converter, adds clamping capacitors to reduce voltage stress on the switches and input voltage. In addition to the main inductor that transfers energy to the output side, multiple additional inductors also help reduce the burden on the clamping capacitors. Even at high voltage gain, switching control can be performed easily, and the voltage stress on the switches can be controlled by adjusting the order of the switching network. Furthermore, since high-voltage switches are not required, the on-resistance of low-voltage switches is lower, thereby reducing conduction losses. Moreover, high voltage gain requirements can also be met by increasing the order of the switching network.

[0010] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Simple Explanation of the Diagram

[0011] Figure 1 is a circuit diagram of a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0012] Figures 2A and 2B are the switching signal waveforms of all switching elements and the signal timing diagrams of voltage stress, inductor voltage, and inductor current in a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0013] Figure 3 shows a schematic diagram of the current flow path of a single-stage non-isolated buck converter in the first stage according to an embodiment of the present invention.

[0014] Figure 4 shows a schematic diagram of the current flow path of the single-stage non-isolated buck converter in the second, fourth, sixth and eighth stages of the present invention.

[0015] Figure 5 shows a schematic diagram of the current flow path of a single-stage non-isolated buck converter in the third stage according to an embodiment of the present invention.

[0016] Figure 6 shows a schematic diagram of the current flow path in the fifth stage of a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0017] Figure 7 shows a schematic diagram of the current flow path in the seventh stage of a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0018] Figure 8 is a circuit diagram of a single-stage non-isolated buck converter according to another embodiment of the present invention.

[0019] Figure 9 is a circuit diagram of a single-stage non-isolated buck converter according to another embodiment of the present invention. Implementation

[0020] The following specific embodiments illustrate the implementation of the "single-stage non-isolated buck converter" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0021] Figure 1 is a circuit diagram of a single-stage non-isolated buck converter according to an embodiment of the present invention. Referring to Figure 1, an embodiment of the present invention provides a single-stage non-isolated buck converter 1, which includes an input capacitor Cin, an output capacitor Cout, a main inductor L1, a first switching circuit 10, second switching circuits 12-1 and 12-2, a third switching circuit 14, and a switching control circuit 16.

[0022] The first and second terminals of the input capacitor Cin are connected to the first and second terminals of the input power supply Vin, respectively.

[0023] The first and second terminals of the output capacitor Cout are connected to the first and second terminals of the load R, respectively. The main inductor L1 is connected between the common node Nc and the first terminal of the output capacitor Cout.

[0024] The first switching circuit 10 includes a high-side switch S1H, a clamping capacitor C1, and a low-side switch S1L. The first terminal of the high-side switch S1H is connected to the first terminal of the input capacitor Cin. The clamping capacitor C1 is connected between the second terminal of the high-side switch S1H and the common node Nc. The low-side switch S1L is connected between the common node Nc and the second terminal of the output capacitor Cout.

[0025] The second switching circuit 12-1 includes a high-side switch S2H, a clamping capacitor C2, an additional inductor L2, and a low-side switch S2L. The high-side switch S2H has a first terminal and a second terminal, and is connected between the second terminal of the high-side switch S1H and a common node Nc. More specifically, the first terminal of the high-side switch S2H is connected to the second terminal of the high-side switch S1H and the clamping capacitor C1, and the second terminal of the high-side switch S2H is connected to the first terminal of the clamping capacitor C2. The first and second terminals of the additional inductor L2 are respectively connected to the second terminal of the clamping capacitor C2 and the common node Nc. The low-side switch S2L is connected between the second terminal of the additional inductor C2 and the second terminal of the output capacitor Cout.

[0026] The single-stage non-isolated buck converter 1 also includes another second switching circuit 12-2, which includes a high-side switch S3H, a clamping capacitor C3, an additional inductor L3, and a low-side switch S3L. The high-side switch S3H has a first terminal and a second terminal, and is connected between the second terminal of the high-side switch S2H and a common node Nc. More specifically, the first terminal of the high-side switch S3H is connected to the second terminal of the high-side switch S2H and the first terminal of the clamping capacitor C2, and the second terminal of the high-side switch S3H is connected to the first terminal of the clamping capacitor C3. The first and second terminals of the additional inductor L3 are respectively connected to the second terminal of the clamping capacitor C3 and the common node Nc. The low-side switch S3L is connected between the second terminal of the additional inductor C3 and the second terminal of the output capacitor Cout.

[0027] It should be noted that the number of the second switch circuits 12-1 and 12-2 in Figure 1 (2) is only an example. The number of the second switch circuits is m, where m is a positive integer greater than zero. When the number of the second switch circuits is complex, multiple high-side switches can be connected sequentially between the high-side switch S1H and the common node Nc.

[0028] On the other hand, the third switching circuit 14 includes a high-side switch S4H, a low-side switch S4L, and an additional inductor L4. The first terminal of the high-side switch S4H is connected to the second terminal of the high-side switch S3H in the last second switching circuit 12-2. The first and second terminals of the low-side switch S4L are respectively connected to the second terminal of the high-side switch S3H and the second terminal of the output capacitor Cout. The first terminal of the additional inductor L4 is connected to the second terminal of the high-side switch S4H, the first terminal of the low-side switch S4L, and the common node Nc.

[0029] To achieve a high voltage conversion ratio in isolated high-step DC-DC topologies, a high turns ratio and a high-frequency transformer are required. However, due to efficiency limitations from light to full load, relatively large and complex custom transformers, and expensive printed circuit boards (PCBs) and control complexity, non-isolated topologies are a good choice and have gained attention for their simple structure and high power density.

[0030] As can be seen from the circuit architecture in Figure 1, compared to the switching network of a traditional buck converter, the single-stage non-isolated buck converter 1 in this embodiment adds clamping capacitors C1, C2, and C3 to reduce voltage stress on the switches and input voltage. In addition to the main inductor L1 that transfers energy to the output side, the additional inductors L2, L3, and L4 also help to reduce the burden on clamping capacitors C1, C2, and C3.

[0031] The switch control circuit 16 can provide multiple sets of switch signals to control the high-side switches S1H, S2H, S3H, S4H and the low-side switches S1L, S2L, S3L, S4L to turn on and off in multiple operating modes. Even at high voltage gain, switch control can be performed easily, and the voltage stress on the switches can be controlled by adjusting the order of the switch network. Furthermore, since high-voltage switches are not required, the on-resistance of the low-voltage switches is lower, thereby reducing conduction losses. Moreover, for high voltage gain requirements, the requirements can be met by increasing the order of the switch network.

[0032] Figures 2A and 2B are the switching signal waveforms of all switching elements and the signal timing diagrams of voltage stress, inductor voltage, and inductor current in the single-stage non-isolated buck converter of this embodiment. Referring to Figures 2A and 2B, the working principle of the single-stage non-isolated buck converter 1 of this embodiment is explained in detail below. The duty cycle of the high-side switches S1H, S2H, S3H, and S4H is denoted as D, while the conduction time of the low-side switches S1L, S2L, S3L, and S4L is 1-DTS, where TS is the switching period and fS is the switching frequency. It should be noted that the duty cycle is less than 0.25 and the converter operates under CCM conditions. If the number of layers in the switching network is N, the duty cycle is limited to 1 / N. To simplify the analysis of the single-stage non-isolated buck converter 1, the following assumptions are made:

[0033] 1. Assume the switch is an ideal component.

[0034] 2. Four gate drivers S1H, S2H, S3H and S4H are phase-shifted by 90° to each other, and switches S1L, S2L, S3L and S4L are complementary switches of gate drivers S1H, S2H, S3H and S4H respectively.

[0035] 3. The clamping capacitors C1, C2, and C3 have the same capacitance value and are large enough to keep the voltage across them constant and without voltage ripple.

[0036] 4. This single-stage non-isolated buck converter 1 operates in continuous current mode (CCM) with a duty cycle D less than 0.25. Refer to Figures 2A and 2B for a detailed analysis of each mode; there are eight operating phases.

[0037] Figure 3 shows a schematic diagram of the current flow path of a single-stage non-isolated buck converter in the first stage according to an embodiment of the present invention.

[0038] First stage (time t0 to t1): During this time interval, the switch control circuit 16 enters the first working mode, the high-side switch S1H is turned on, and the low-side switch S1L is turned off. The high-side switches S2H, S3H and S4H are turned off, while the low-side switches S2L, S3L and S4L are turned on, as shown in Figure 3. The input voltage VIN of the input power supply Vin passes through the clamping capacitor C1, the main inductor L1 and the load R, thereby charging the clamping capacitor C1 and magnetizing the main inductor L1. The main inductor L1 is magnetized by the input voltage VIN – clamping capacitor voltage VC1 – output voltage VOUT, and the additional inductors L2, L3 and L4 are demagnetized by the voltage - input voltage VIN + clamping capacitor voltage VC1, as shown in the following equations (1) to (7): (1) (2) (3) (4) (5) (6) (7)

[0039] in, , , , These are the inductance voltages of the main inductor L1 and the auxiliary inductors L2, L3, and L4, respectively. , , , These are the inductance values ​​of the main inductor L1 and the auxiliary inductors L2, L3, and L4, respectively. , , , These represent the inductance currents of the main inductor L1 and the auxiliary inductors L2, L3, and L4, respectively. , , These are the capacitance values ​​of clamping capacitors C1, C2, and C3, respectively. , , This refers to the voltage change across clamping capacitors C1, C2, and C3. The clamping capacitor voltage of clamping capacitor C1, , , This represents the current across clamping capacitors C1, C2, and C3.

[0040] Figure 4 shows a schematic diagram of the current flow path of the single-stage non-isolated buck converter in the second, fourth, sixth and eighth stages of the present invention.

[0041] Phases two, four, six, and eight (times t1-t2, t3-t4, t5-t6, t7-TS): As shown in Figure 4, during this period, the switch control circuit 16 enters the second operating mode. High-side switches S1H, S2H, S3H, and S4H are turned off, while low-side switches S1L, S2L, S3L, and S4L are turned on. The main inductor L1 is demagnetized by the negative output voltage VOUT, and the voltage stress on the additional inductors L2, L3, and L4 is zero. Then, the inductor current... , , The cycle continues. At this time, clamping capacitors C1, C2, and C3 are not conducting, as shown in equations (8) to (11) below: (8) (9) (10) (11)

[0042] Figure 5 shows a schematic diagram of the current flow path of a single-stage non-isolated buck converter in the third stage according to an embodiment of the present invention.

[0043] It should be noted that when the number of second switching circuits is m, high-side switches S2H, S3H to SmH and low-side switches S2L, S3L to SmL will be provided, and these operating modes will include m third operating modes. In the nth third operating mode among the m third operating modes, the switch control circuit 16 controls the high-side switch S1H to turn off, the low-side switch S1L to turn on, the nth high-side switch (e.g., the high-side switch SnH among the high-side switches S2H, S3H to SmH) to turn on, and the remaining high-side switches to turn off. The nth low-side switch (e.g., the high-side switch SnH among the low-side switches S2L, S3L to SmL, where n is 1 to m) to turn off, and the remaining low-side switches to turn off. In addition, the high-side switches in the third switching circuit 14 are turned off, and the low-side switches are turned on. The following explanation assumes m is 2.

[0044] The third stage (time t2-t3): As shown in Figure 5, during this time interval, the switch control circuit 16 enters the first third operating mode, the high-side switch S2H is turned on, and the high-side switches S1H, S3H, and S4H are turned off. On the other hand, the low-side switch S2L is turned off, and the low-side switches S1L, S3L, and S4L are turned on. The main inductor L1 is continuously demagnetized by the voltage -V OUT, the voltage stress on the additional inductors L3 and L4 is zero, and then these currents circulate. The clamping capacitors C1 and C2 charge the inductor L2 as shown in equations (12) to (17) below: (12); (13); (14); (15); (16); (17);

[0045] in, This is the clamping capacitor voltage of clamping capacitor C2. After the third stage (time t2-t3) ends, the fourth stage, as shown in Figure 4, begins, and the switch control circuit 16 enters the second operating mode.

[0046] Figure 6 shows a schematic diagram of the current flow path in the fifth stage of a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0047] Fifth stage (time t4-t5): As shown in Figure 6, during this time interval, the switch control circuit 16 enters the second third working mode, the high-side switch S3H is turned on, and the high-side switches S1H, S2H, and S4H are turned off. At the same time, the low-side switch S3L is turned off and the low-side switches S1L, S2L, and S4L are turned on. The main inductor L1 is maintained at a negative output voltage VOUT, the voltage stress on the additional inductors L2 and L4 is zero, and then these currents circulate. Clamping capacitors C2 and C3 charge the additional inductor L3, and clamping capacitor C1 is turned off, as shown in equations (18) to (23) below: (18); (19); (20); (twenty one); (twenty two); (twenty three);

[0048] in, This is the clamping capacitor voltage of clamping capacitor C3. After the fifth stage (time t4-t5) ends, the sixth stage, as shown in Figure 4, begins, and the switch control circuit 16 enters the second operating mode.

[0049] Figure 7 shows a schematic diagram of the current flow path in the seventh stage of a single-stage non-isolated buck converter according to an embodiment of the present invention.

[0050] The seventh stage (time t6-t7): As shown in Figure 7, during this time interval, the switch control circuit 16 enters the fourth working mode, the high-side switch S4H is turned on, and the high-side switches S1H, S2H, and S3H are turned off. On the other hand, the low-side switch S4L is turned off, and the low-side switches S1L, S2L, and S3L are turned on. The main inductor L1 is continuously demagnetized by the negative output voltage VOUT, and the voltage stress on the additional inductors L2 and L3 is zero, so that the current on the additional inductors L2 and L3 circulates. The additional inductor L4 is charged by the clamping capacitor C3, while the capacitors C1 and C2 are turned off, as shown in equations (24) to (28) below: (twenty four); (25); (26); (27); (28);

[0051] After the seventh stage (time t6-t7) ends, the process enters the eighth stage as shown in Figure 4, where the switch control circuit 16 enters the second operating mode. Finally, the first to eighth stages are repeated continuously.

[0052] The following describes the steady-state analysis of the single-stage non-isolated buck converter 1 according to an embodiment of the present invention. Regarding the voltage conversion ratio and voltage stress, by performing voltage-second balance on the main inductor L1 and the additional inductors L2, L3, and L4 within one switching cycle, the relevant equation can be expressed as the following equation (29): (29);

[0053] Therefore, the relationship between the output voltage VOUT and the input voltage VIN can be described as follows: (30);

[0054] The voltage gain can be expressed as equation (31): (31);

[0055] In addition, the voltage of the clamping capacitor can be obtained by the following equation (32): (32);

[0056] Equation (32) shows the clamping capacitor voltage. , , These are 3 / 4, 1 / 2, and 1 / 4 of the input voltage, respectively, and the voltage ratio is reduced by a factor of four. This means that under the same duty cycle D, the voltage ratio can be controlled to be four times higher than that of a traditional buck converter. In addition, clamping capacitors C1, C2, and C3 store energy from the input terminal, thereby reducing the voltage stress on the switches. From equation (32) and Figures 3 to 7, it can be seen that the voltage stress of each switch during the switching cycle is... , , , , , , , It is given by the following formula: (33); (34); (35); (36); (37);

[0057] As shown in equations (33), (34), (35), (36), and (37), the voltage stress on the switches is lower than that of traditional buck converters due to the presence of clamping capacitors. Therefore, switch selection is more flexible because the voltage stress on these switches can be reduced. Furthermore, low-voltage switches have lower on-resistance compared to high-voltage switches, thus reducing conduction losses. Therefore, efficiency and cost can be improved for high-voltage ratio applications.

[0058] Please refer to Figure 2, which shows the inductor current waveforms of the main inductor L1 and the auxiliary inductors L2, L3, and L4 during the switching cycle Ts. As shown in the analysis in equations (1), (13), (20), and (27), the peak-to-peak inductor current... It can be represented as: (38)

[0059] Based on the previous analysis of each time interval, ampere-second balancing is applied to the clamping capacitor: (39)

[0060] From equation (39), the average inductor current can be expressed as: (40)

[0061] Since the average current of inductors L2, L3, and L4 is the same, the same inductance value can be chosen. Therefore, the minimum and maximum values ​​of these inductor currents can be obtained as follows: (41)

[0062] The operating conditions of the main inductor are: (42)

[0063] Substituting equation (40) into equation (42) yields the following equation: (43)

[0064] According to equations (41) and (43), the main inductor L1, the auxiliary inductors L2, L3 and L4 can be designed independently to operate in CCM or Discontinuous Current Mode (DCM).

[0065] From equation (43), the boundary conditions for each inductor can be obtained. : (44)

[0066] According to equation (44), if the inductance value is higher than the boundary inductance value, the single-stage non-isolated buck converter 1 will operate in CCM mode; otherwise, the single-stage non-isolated buck converter 1 will operate in Transient current mode (TCM).

[0067] Figure 7 shows the current stress waveform of these switches during one switching cycle. Based on Figure 5 and the preceding analysis, the current stress of the switches (subscripts indicate the corresponding high-side or low-side switches) can be expressed as: (45) (46) (47) (48)

[0068] Where SiH represents the high-side switching state, and SiL represents the low-side switching state. From the operation shown in Figures 3 to 7 and the current stress equation above, the current stress of each switch is the sum of the phase-shift inductor currents. However, since the current is shared through parallel internal inductors, this current stress is not very high compared to a conventional buck converter operating under the same conditions.

[0069] Figure 8 is a circuit diagram of a single-stage non-isolated buck converter according to another embodiment of the present invention, and Figure 9 is a circuit diagram of a single-stage non-isolated buck converter according to yet another embodiment of the present invention.

[0070] The single-stage non-isolated buck converters 2 and 3 derived from Figure 1 are shown in Figures 8 and 9, respectively. In the single-stage non-isolated buck converter 2 in Figure 8, a third-order switching network is used. The high-side switches S1H, S2H, and S3H are phase-shifted by 120°, while the low-side switches S1L, S2L, and S3L are complementary switches to the high-side switches S1H, S2H, and S3H, respectively.

[0071] Figure 9 shows a fifth-order switching network, which further includes a third second switching circuit, comprising a high-side switch S4H, an additional inductor L4, and a low-side switch S4L. The connection relationship of the third switching circuit is the same as in Figure 1, except that the labels are changed to high-side switch S5H, low-side switch S5L, and additional inductor L5. Since the switching network is fifth-order (m = 3, N = 5), the high-side switches S1H, S2H, S3H, S4H, and S5H are phase-shifted by 72 degrees, while switches S1L, S2L, S3L, S4L, and S5L are complementary switches to switches S1H, S2H, S3H, S4H, and S5H, respectively. For an N-order switching network (note that N is m+2), the following conditions must be ensured:

[0072] 1. Duty cycle:

[0073] 2. Switch The switching signals are phase-shifted to each other. .

[0074] Therefore, the switching voltage stress and average inductor current of the Nth order can be expressed as: (49); (50); (51); (52); (53);

[0075] Where N is the order of the switching network, i is the i-th order from 2 to N, and ii is the ii-th order from 1 to N. As the order of the switching network increases, the voltage ratio increases. From equations (49), (50), and (52), it can be seen that as the order of the switching network increases, the voltage drop across the clamping capacitor increases, and the voltage stress on the switch decreases, thereby reducing switching losses. As can be seen from the analysis above, the high-side switch S1H and the low-side switch S1L will carry more current from the inductor, but because the voltage stress is lower than other switches, efficiency can be balanced. The order of the switching network can be selected according to the application, voltage conversion ratio, and efficiency requirements.

[0076] [Beneficial Effects of the Examples]

[0077] One of the advantages of this invention is that the single-stage non-isolated buck converter provided by this invention, compared to the switching network of a conventional buck converter, adds clamping capacitors to reduce voltage stress on the switches and input voltage. In addition to the main inductor that transfers energy to the output side, multiple additional inductors also help reduce the burden on the clamping capacitors. Even at high voltage gain, switching control can be performed easily, and the voltage stress on the switches can be controlled by adjusting the order of the switching network. Furthermore, since high-voltage switches are not required, the on-resistance of low-voltage switches is lower, thereby reducing conduction losses. Moreover, high voltage gain requirements can also be met by increasing the order of the switching network.

[0078] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0079] 1,2,3: Single-stage non-isolated buck converters Cin: Input capacitance Cout: Output capacitor L1: Main Inductor L2, L3, L4: Additional inductors 10: First switching circuit 12-1, 12-2: Second switching circuit 14: Third Switching Circuit 16: Switch control circuit Nc: Shared Node R: Load C1, C2, C3: Clamping capacitors S1H, S2H, S3H, S4H, S5H: High-side switches S1L, S2L, S3L, S4L, S5L: Low-side switches Inductor current Inductor voltage Voltage stress Ts: Switching cycle VIN: Input voltage VC1, VC2: Clamping capacitor voltages V OUT: Output voltage t, t1, t2, t3, t4, t5, t6, t7: Time Vin: Input power

Claims

1. A single-stage non-isolated buck converter, comprising: An input capacitor, with its first and second ends respectively connected to the first and second ends of an input power supply; an output capacitor, with its first and second ends respectively connected to the first and second ends of a load; a main inductor connected between a common node and the first end of the output capacitor; a first switching circuit, including: a first high-side switch, with its first end connected to the first end of the input capacitor; a first clamping capacitor connected between the second end of the first high-side switch and the common node; and a first low-side switch connected between the common node and the second end of the output capacitor; at least one second switching circuit, each including: a second high-side switch having a first end and a second end, each second high-side switch being connected between the second end of the first high-side switch and the common node; a second clamping capacitor, with its first end connected to the second end of the second high-side switch; a first... An additional inductor, the first and second ends of which are respectively connected to the second end of the second clamping capacitor and the common node; a second low-side switch connected between the first end of the first additional inductor and the second end of the output capacitor; and a third switching circuit, comprising: a third high-side switch, the first end of which is connected to the second end of one of the second high-side switches; a third low-side switch, the first and second ends of which are respectively connected to the second end of the third high-side switch and the second end of the output capacitor; a second additional inductor, the first end of which is connected to the second end of the third high-side switch, the first end of the third low-side switch and the common node; and a switch control circuit configured to control the first high-side switch, the first low-side switch, each of the second high-side switches, each of the second low-side switches, the third high-side switch and the third low-side switch to be turned on and off in multiple operating modes.

2. The single-stage non-isolated buck converter as described in claim 1, wherein, The switching state of the first high-side switch is complementary to the switching state of the first low-side switch, the switching states of the second high-side switches are complementary to the switching states of the second low-side switches, and the switching states of the third high-side switch are complementary to the switching states of the third low-side switch.

3. The single-stage non-isolated buck converter as described in claim 2, wherein, These operating modes include a first operating mode in which the switch control circuit controls the first high-side switch to be turned on, the first low-side switch to be turned off, each of the second high-side switches to be turned off, and each of the second high-side switches to be turned on.

4. The single-stage non-isolated buck converter as described in claim 3, wherein, These operating modes include a second operating mode in which the switch control circuit controls the first high-side switch to be turned off and the first low-side switch to be turned on, each of the second high-side switches to be turned off and each of the second high-side switches to be turned on, the third high-side switch to be turned off and the third low-side switch to be turned on.

5. The single-stage non-isolated buck converter as described in claim 4, wherein, These operating modes include m third operating modes. In the nth third operating mode among the m third operating modes, the switch control circuit controls the first high-side switch to turn off and the first low-side switch to turn on. The second high-side switch of the nth second switch circuit is turned on, and the remaining second high-side switches are turned off. The second low-side switch of the nth second switch circuit is turned off, and the remaining second high-side switches are turned off. The third high-side switch is turned off, and the third low-side switch is turned on.

6. The single-stage non-isolated buck converter as described in claim 5, wherein, The number of at least one second switching circuit is m, where m is a positive integer greater than zero and n is from 1 to m.

7. The single-stage non-isolated buck converter as described in claim 6, wherein, These operating modes include a fourth operating mode in which the switch control circuit controls the first high-side switch to be turned off, the first low-side switch to be turned on, the second high-side switches to be turned off, the third high-side switch to be turned on, and the third low-side switch to be turned off.

8. The single-stage non-isolated buck converter as described in claim 7, wherein, The switch control circuit sequentially enters the first working mode, the second working mode, m third working modes, the second working mode, the fourth working mode, and the second working mode.

9. The single-stage non-isolated buck converter as described in claim 8, wherein, The switch control circuit also enters a second operating mode between two adjacent third operating modes.

10. The single-stage non-isolated buck converter as described in claim 9, wherein, The first high-side switch, the m second high-side switches, and the third high-side switch are phase-shifted by 360° / (m+2) to each other.

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