Step voltage during current force read of programmable resistance memory cell with threshold switching selector

Abstract

A technique for reading memory cells in a cross-connect memory array. Each memory cell has a threshold switching selector connected in series with a programmable resistive memory element. During a current-forced read of one of the programmable resistive memory cells in the cross-connect memory array, a step voltage pulse is applied to the memory system. In one state, the step voltage pulse is used to turn on the threshold switching selector. In another state, the step voltage pulse is applied after the threshold switching selector is turned on when a backflow current may be present. In yet another state, the step voltage pulse is applied after the backflow current has dissipated.

Description

[Technical Field]

[0001] This invention relates to a step voltage during a forced current read of a programmable resistive memory cell with a threshold switching selector. [Previous Technology]

[0002] Memory systems are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery pack). Non-volatile memory can be made non-volatile, at least for a limited time, by adding a battery pack back to the power supply outside the memory chip.

[0003] Memory cells can reside in a cross-point memory array. In a memory array with a cross-point architecture, one set of conductive lines travels across the surface of the substrate, and another set of conductive lines is formed above this set of conductive lines, traveling in an orthogonal direction relative to the initial layer. The memory cells are located at the intersection of the two sets of conductive lines. Cross-point memory arrays are sometimes called cross-bar memory arrays.

[0004] Programmable resistive memory cells are formed from materials with programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed into one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states can be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. Compared to some other memory technologies that use electron charge (DRAM) or voltage (SRAM) to store data, MRAM cells use magnetization to indicate that data has been stored. One bit of data is written to the MRAM cell by changing the magnetization direction of a magnetic element ("free layer") within the MRAM cell, and one bit is read by measuring the resistance of the MRAM cell, which changes with the magnetization direction. However, crosspoint memory arrays can have other types of memory cells. For example, cross-point memory arrays may have memory cells of other technologies, such as ReRam, PCM (phase change memory), or FeRam.

[0005] In a crosspoint memory array, each memory cell may contain a threshold switching selector connected in series with a material having a programmable resistor. The threshold switching selector has a high resistance (off or non-conductive) until it is biased to a voltage higher than its threshold voltage (Vt) or a current (It) higher than its threshold current, and until its voltage bias drops below Vhold ("Voffset") or its current drops below the holding current Ihold. After crossing Vt and simultaneously crossing Vhold, the threshold switching selector has a relatively low resistance (on or conductive). The threshold switching selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by turning it on before determining the resistance state of the memory. An example of a threshold switching selector is an ovonic threshold switch (OTS). Other examples of limit switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metals (MIMs), or other materials that provide a highly nonlinear dependence of current on the selected voltage.

[0006] Forced current technology can be used to read or write programmable resistive memory cells in a crosspoint array, thereby driving current to memory cells whose addresses are selected for reading or writing ("selected memory cells"). The crosspoint array consists of orthogonal conductor groups located in two or more planes. For example, a voltage is applied to the selected conductor in the Y direction while current is driven to the selected conductor in the X direction. This current will charge the voltage across the selected memory cell until a threshold switching selector is turned on. Then, while driving current through the programmable resistive memory element of the selected memory cell, the voltage on the selected cell is sensed.

[0007] The switching of the threshold switching selector can cause a backflow current. Specifically, after the threshold switching selector is turned on, the voltage on the memory cell drops rapidly, resulting in a backflow current. This backflow current can flow through the programmable resistive memory element, which may change the state of the programmable resistive memory element before sensing the bit state of the memory element; for example, causing read disturbances that result in missed reads. Therefore, programmable resistive memory elements (such as, but not limited to, MRAM elements) may unintentionally and undesirably change their states due to the backflow current flowing through the memory element during a read operation.

[0008] Figure 1 illustrates the timing of the voltage used for forced reading of a memory cell with a programmable resistive memory element connected in series with a threshold selector. Initially, the voltages on the bit line and word line are each set to Vinital. At t1, the bit line is connected to ground, where the voltage on the bit line decreases from Vinital to ground before t2. In this example, the selection voltage for the bit line is grounded. And, at t1, the voltage on the word line (WL) begins to increase due to the read current through the selected word line. When the voltage on the threshold selector reaches the threshold voltage (Vth) of the threshold selector, the threshold selector is turned on. At t3, the threshold selector is turned on. However, the threshold voltage of different memory cells can vary considerably. Furthermore, the threshold voltage of the threshold selector tends to drift over time. This variation in the voltage at which the threshold selector is turned on can cause problems with read accuracy and timing.

[0009] The resistance of the threshold selector decreases rapidly when it is turned on; this is referred to herein as a "snapback." The snapback voltage is the difference between the voltage (Vth) on the threshold selector when it is turned on and the threshold selector offset voltage (i.e., the voltage on the threshold selector when it is turned on, or Von at graph 16). Since it is grounded via the select bit line, the snapback voltage is the difference between the voltage on the select word line when the threshold selector is turned on and the voltage on the select word line after the word line voltage has stabilized. At t3, the voltage on the word line begins to drop (see graph 12). The snapback can cause unwanted currents in the memory element, which can potentially flip the state of the memory element, leading to read errors. [Summary of the Invention]

[0010] A technique for reading memory cells in a cross-connect memory array. Each memory cell has a threshold switching selector connected in series with a programmable resistive memory element. During a current-forced read of one of the programmable resistive memory cells in a cross-connect memory array, a step voltage pulse is applied to the memory system. In one state, the step voltage pulse is used to turn on the threshold switching selector. In another state, the step voltage pulse is applied after the threshold switching selector is turned on when a backflow current may be present. In yet another state, the step voltage pulse is applied after the backflow current has dissipated.

Implementation Method

[0012] Techniques for a memory system and a method for reading programmable resistive memory cells in a cross-switch memory array are disclosed. Each memory cell has a threshold switching selector connected in series with the programmable resistive memory element. Embodiments and memory systems apply a step voltage pulse during a forced current read of a programmable resistive memory cell in a cross-switch memory array. In one embodiment, the step voltage pulse is used to turn on the threshold switching selector. Therefore, even if the threshold voltages of the threshold switching selectors of different memory cells vary, each memory cell will still experience the same peak voltage on that cell. In one embodiment, the step voltage pulse is applied after the threshold switching selector is turned on when a backflow current may be present. Therefore, excess charge can be removed to prevent backflow current from flowing through the programmable resistive memory element and unintentionally flipping the state of the memory cell. In a further embodiment, the step voltage pulse is applied after the backflow current has dissipated. In this case, each memory cell will experience a step voltage across the cell, which can compensate for the difference in threshold voltage between the threshold switching selectors of different memory cells.

[0013] A technique for reading programmable resistive memory cells is called global reference readout. Global reference readout is sometimes called midpoint readout or midpoint reference readout. Global reference readout can use a reference voltage between a lower resistance state (LRS) and a higher resistance state (HRS). Here, LRS and HRS refer to the voltages presented across the cell in response to the read current. For example, the midpoint reference may be a reference voltage located midway between two voltages corresponding to a cell with an LRS or HRS. In the forced current method, the state of the memory cell is determined based on whether the sensed voltage Vsense is higher or lower than the midpoint reference voltage VREF.

[0014] Another technique for reading programmable resistive memory cells is commonly referred to as self-referenced read (SRR). In SRR, instead of using a midpoint reference independent of the cell's state, a reference is generated based on sensing the cell itself. In destructive SRR, the state of the memory cell can be altered (e.g., destroyed) by an SRR write operation. One SRR technique includes a first read (Read1), followed by a destructive write to a known state (e.g., a high-resistance state HRS), and a second read (Read2). The results of the two reads are compared to determine the original state of the cell. One technique for the first read is to apply a read current through the memory cell, causing the voltage across the cell to have a value representing the resistance of the memory cell. The voltage is stored and adjustable (e.g., adjusted up or down by 150mV) for comparison with a voltage sample from the second read. For each state, the voltage adjustment may be approximately half the signal difference across the MRAM. For example, if the MRAM low resistance state (LRS) is 25 Kohm, the high resistance state is 50 Kohm, and the read current is 15 µA, then the difference from the state change is 375 mV, which can be adjusted by approximately 182.5 mV from the Read1 storage voltage of the SRR. The determination of the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage. For example, if the first sample voltage from Read1 of the SRR is adjusted upwards and written to the HRS, then if the cell was originally in HRS, the second sample voltage from Read2 should be approximately the same as Read1, and therefore lower than the first read voltage after adjustment. Then, if the cell was originally in LRS, then because of the higher Read2 voltage obtained from writing bits from the low resistance LRS to the HRS, the second sample voltage from Read2 should be higher than the upward adjustment voltage from Read1.

[0015] In one embodiment, the memory system is used to read programmable resistive memory cells residing in a crosspoint memory array. In a memory array with a crosspoint architecture, one set of conductive lines travels across the surface of the substrate, and another set of conductive lines is formed above the first set of conductive lines and travels on the substrate in a direction perpendicular to the first set of conductive lines. The memory cell is located at the crosspoint junction of the two sets of conductive lines. Crosspoint memory arrays are sometimes referred to as cross-bar memory arrays. In one embodiment, each memory cell has a magnetoresistive memory element connected in series with an OTS, which may be referred to as an MRAM memory cell. However, crosspoint memory arrays may have other types of memory cells. For example, crosspoint memory arrays may have memory cells of other technologies, such as ReRAM, PCM (phase-change memory), and FeRAM. Furthermore, the threshold switching selector does not need to be an OTS and may be a pair of diodes with one of an anode and a cathode.

[0016] In some embodiments, the programmable resistive memory cell has a magnetoresistive random access memory (MRAM) element. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction set by another element of the MRAM ("reference layer"). In some embodiments, low resistance is referred to as parallel or P state or LRS, and high resistance is referred to as antiparallel or AP state or HRS. The MRAM can use spin-transfer torque effect to change the magnetization direction from P state to AP state and vice versa, which generally requires bipolar (bidirectional write) operation for writing. However, the SRR of the programmable resistive memory cell as disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0017] Figure 2 is a block diagram of one embodiment of a non-volatile memory system (or more simply, a "memory system") 100 connected to a host system 120. The memory system 100 may implement the techniques presented herein for system reading of programmable resistive memory cells having threshold switching selectors. In one embodiment, the memory cell has a programmable resistive memory element (e.g., an MRAM element) connected in series with a threshold switching selector (such as an OTS). Many types of memory systems can be used with the techniques presented herein. Example memory systems include dual in-line memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems may also be used.

[0018] The memory system 100 of FIG2 includes a memory controller 102, a memory 104 for storing data, and local memory 140 (e.g., MRAM, ReRAM, DRAM). Local memory 140 may be non-volatile and retain data after power is turned off. Local memory 140 may be volatile and not expected to retain data after power is turned off. In one embodiment, local memory 140 is MRAM. In one embodiment, local memory MRAM does not need to retain data after power is turned off. However, local memory MRAM may retain data after power is turned off. In one embodiment, memory controller 102 and / or local memory controller 164 provide access to programmable resistive memory cells in local memory 140. For example, memory controller 102 may provide access to an array of cross-point MRAM cells in local memory 140. In another embodiment, memory controller 102 or interface 126, or both, are removed, and the memory package is directly connected to host 120 via a bus such as DDRn, or connected to the host memory management unit (MMU). In another case, memory controller 102 or part thereof is moved to memory 104 to directly connect memory 104 to the host, such as by providing parity bits, ECC, and wear leveling on memory 104, and a DDRn interface to / from the host or MMU. As used throughout this document, the term "memory system" is not limited to memory system 100. For example, local memory 140, or a combination of local memory 140 and local memory controller 164, can be considered a memory system. Similarly, host memory 124, or a combination of host processor 122 and host memory 124, can be considered a memory system.

[0019] The components of the memory system 100 depicted in Figure 2 are circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, regeneration logic 172, and a loss balancing 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to the network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use time-independent asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements beyond conventional bus and crossbar interconnects. Compared to other designs, NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signaling wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, regeneration logic 172, and wear leveling 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 may be DRAM, SRAM, or another type of volatile memory.

[0020] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs encoding and decoding of data provided on memory or in memory-unavailable co-bits as part of a code word for error correction of data retrieved from memory 140 or 104. In one embodiment, the ECC engine 158 is implemented by software-programmable circuitry. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is implemented by custom-designed hardware circuitry without any software. In one embodiment, the functionality of the ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 has an ECC engine with or without a wear-leveling engine. In one embodiment, memory 104 has an ECC engine with or without a wear-leveling engine.

[0021] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management procedures including wear leveling. A separate wear leveling 174 is depicted, but wear leveling 174 can be implemented by processor 156. Additionally, renewal logic 172 is depicted, but renewal logic can also be implemented by processor 156. In one embodiment, processor 156 is programmed via firmware. In other embodiments, processor 156 is a custom-designed hardware circuit without any software. Processor 156 also implements a translation module as either software / firmware or as dedicated hardware circuitry. In many systems, the non-volatile memory system uses physical addresses associated with one or more memory chips to internally address the storage system. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses, and the storage system can freely store data between locations of one or more memory chips as desired. To implement this system, memory controller 102 (e.g., translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory die. One implementation is a maintenance table (i.e., the L2P table mentioned above) that identifies the current translation between logical and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Although the logical address-to-physical address table (or L2P table) includes the word "table," it does not need to be a table literally. Rather, the logical address-to-physical address table (or L2P table) can be any type of data structure. In some instances, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached (the L2P cache) in local high-speed memory 140.

[0022] Memory interface 160 communicates with memory 104. In one embodiment, memory 104 includes programmable resistive memory cells in a cross-point array. In one embodiment, memory 104 includes NAND memory cells. In one embodiment, the memory interface provides a toggle-mode interface. Other interfaces may also be used. In some example implementations, memory interface 160 (or another part of controller 102) implements a scheduler and buffer for transferring data to one or more memory chips and receiving data from the one or more memory chips.

[0023] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0024] In one embodiment, memory 104 includes a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, memory controller 102 is connected to one or more memory chips. In one embodiment, the memory package may include other types of memory, such as storage class memory (SCM) based on programmable resistor random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, memory controller 102 provides access to memory cells in a cross-point array in memory 104.

[0025] The memory controller 102 communicates with the host system 120 via an interface 152 implementing a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be removed, and the memory package can be placed directly on the host bus, such as DDRn or CXL. To work with the memory system 100, the host system 120 includes a host processor 122, host memory 124, and interface 126 connected along bus 128. The host memory 124 is the host's physical memory and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of storage. In one embodiment, the host memory 124 includes a crosspoint array of programmable resistive memory cells, wherein each memory cell includes a programmable resistive memory element and a threshold switching selector connected in series with the programmable resistive memory element.

[0026] The host system 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded in the host system 120. The host memory 124 may be referred to herein as the memory system. Hereinafter, the combination of the host processor 122 and the host memory 124 may be referred to as the memory system. In one embodiment, this host memory may be a cross-point memory using MRAM.

[0027] FIG3A is a block diagram depicting an example of a memory die 292 that may implement the techniques described herein. In one embodiment, the memory die 292 is included in local memory 140, and in another embodiment, the memory die 292 is included in memory 104. In one embodiment, the memory die 292 is included in host memory 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various layers(s) of word lines organized into columns and various layers(s) of bit lines organized into rows. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes a column control circuitry 220, the outputs 208 of which are connected to the individual word lines of the memory structure 202. The column control circuitry 220 receives a set of M column address signals and one or more various control signals from the system control logic circuitry 260, and generally includes circuitry such as a column decoder 222, a column driver 224, and a block selection circuitry 226 for both read and write operations. The column control circuitry 220 may also include a read / write circuitry system. In one embodiment, the column decoding and control circuitry 220 has sense amplifiers 228, each containing circuitry for sensing the condition (e.g., voltage) of the word lines of the memory structure 202. In one embodiment, determining the condition or bit state of memory cells in the cross-point array by sensing word line voltage is done directly by comparing the voltage of the accessed memory cell with a reference voltage using a sense amplifier. Alternatively, a less direct approach involves first accessing the memory cell and storing the read voltage generated by forcing a read current through the cell and adjusting it up or down by 150mV (or half the voltage difference resulting from a change in bit state), then writing the cell to the AP state, accessing the memory cell again with the read current, and comparing the resulting voltage with the stored voltage adjusted, for example, by 150mV (or half the voltage difference resulting from two different bit states). The memory die 292 also includes a row decoding and control circuitry system 210, whose inputs / outputs 206 are connected to the individual bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays or "tiles" that can be individually accessed. The line control circuitry 210 receives a group of N line address signals and one or more various control signals from the system control logic 260, and may generally include circuitry such as a line decoder 212, a line decoder and driver 214, a block selection circuitry 216, a read / write circuitry, and an I / O multiplexer.

[0028] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, PCIe, and others. In another embodiment, such data and commands are sent and received directly from memory package 104 to the host without a separate controller, and any required controller is within the individual die or within the die added to the multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 that provides die-level control for memory operation. In one embodiment, state machine 262 may be software-programmable. In other embodiments, state machine 262 is implemented entirely in hardware (e.g., circuitry) without using software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the columns and rows of memory structure 202 during memory operation, and may include charge pump and regulator circuitry for generating regulated voltages, and on / off control for word line bit line selection of memory cells. In some embodiments, power control 264 includes one or more current sources. The current sources(s) can be used to provide read and / or write currents. System control logic 260 includes a memory 266 that can be used to store parameters for operating memory structure 202. System control logic 260 also includes refresh logic 272 and loss balancing logic 274. Such system control logic can be commanded by host 120 or memory controller 102 to refresh logic 272, which can load on-chip stored column and row addresses (indicators) that can be incremented after refresh. Only such address(s) bits(s) can be selected (to refresh OTS). Alternatively, such addresses can be read, corrected via ECC engine 269, and then stored in a "spare" location. This is also incremented (therefore, under the control of wear leveling logic 274, all codewords are periodically read, corrected, and relocated throughout the chip) to achieve wear leveling, resulting in more even use of each bit on the chip. This operation can be more directly controlled by an external controller, such as a PCIe, CXL, or DDRn controller located separately from or on the memory chip.

[0029] Commands and data are transferred between the memory controller 102 and the memory die 292 via the memory controller interface 268 (also referred to as the "communication interface"). This interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a dual-state thixotropic interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a dual-state thixotropic interface connected to the memory interfaces 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn (such as DDR5 or LPDDR5) or a subset thereof with smaller page sizes and / or more lenient timings.

[0030] The system control logic 260 in the controller located on the memory die within the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cell. That is, the on-die ECC engine 269 can be used to encode data and corresponding bits to be stored in the memory structure 202, and to decode and correct errors in the decoded data. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 can be used to execute decoding algorithms and perform error correction. Therefore, the ECC engine 269 can decode ECC codewords. In one embodiment, the ECC engine 269 can decode data more quickly by direct decoding, without iteration. Having the ECC engine 269 on the same die as the memory cell allows for faster decoding. The ECC Engine 269 can use a variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC).

[0031] In some embodiments, all elements of memory die 292 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies; for example, an external controller chip.

[0032] In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile or volatile memory cells, wherein multiple memory layers are formed over a single substrate (such as a wafer). The memory structure may contain any type of non-volatile or volatile memory formed monolithically in one or more solid layers of memory cells, such memory having an active region disposed over a silicon (or other type) substrate on silicon or an insulator. In another embodiment, the memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells.

[0033] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. For the purposes of the new claimed embodiments presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0034] One example of a ReRAM or MRAM crosspoint memory includes a programmable resistance switching element configured in series with an OTS selector in a crosspoint array accessed via X and Y lines (e.g., word lines and bit lines). In another embodiment of the crosspoint, it is a PCM connected in series with the OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes (one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper)) having a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programmability threshold of the conductive bridge memory cell. Therefore, conductive bridge memory elements have a wide range of programmed limits in terms of temperature.

[0035] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. The element is formed of two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. For field-controlled MRAM, one of the two layers is set as a permanent magnet of a specific polarity; the magnetization of the other layer can be changed by applying an external field to store memory. Other types of MRAM cells are possible. The memory device can be constructed from a grid of MRAM cells or as a SOT magnetoresistive memory. MRAM-based memory embodiments will be discussed in more detail below.

[0036] Phase change memory (PCM) utilizes the unique behavior of sulfide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply altering the coordination state of germanium atoms using laser pulses (or light pulses from another source). The memory cell is programmed or switches between amorphous and crystalline states by altering the common coordination of the PCM material via current pulses. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. Furthermore, the current forced for writing can, for example, be rapidly driven to a peak and then linearly sloping down at, for example, an edge rate of 500 ns. Such peak current force can be limited by a zoned voltage compliance that varies along the position of the memory cell along the word line or bit line. In one embodiment, the phase change memory cell has a phase change memory element connected in series with a threshold switching selector (such as an OTS).

[0037] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory construction, or material composition, but are encompassed within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0038] The components in Figure 3A can be divided into two parts: the memory structure 202 and the peripheral circuitry, including all other components. An important characteristic of the memory circuitry is its capacity, which can be increased by increasing the area allocated to the memory die 292 of the memory structure 202; however, this reduces the area available for the peripheral circuitry on the memory die, or increases the cost associated with the chip area. This can place significant limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die 292 is the trade-off between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry. Such trade-offs can result in a larger IR drop due to the use of a larger xy memory array between the word lines and bit lines, which in turn can benefit more from the use of voltage limiting and partitioning of the constant current output voltage according to the memory cell location along the word lines and bit lines.

[0039] Another reason why the memory structure 202 and its peripheral circuitry are often inconsistent is due to the processing involved in forming these regions, as these regions often involve different processing techniques and trade-offs between different techniques on a single die. For example, components in the system control logic 260 (such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuitry) typically employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS technology alone.

[0040] To mitigate these limitations, the embodiments described below can separate the elements of FIG. 3A onto separately formed dies that are subsequently bonded together. FIG. 3B depicts an integrated memory assembly 270 having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuitry elements (including one or more control circuits) are formed on the control die 290. For example, the memory structure die 280 may be formed solely of memory elements, such as an array of memory cells of MRAM, PCM, ReRAM, or other memory types. Some or all of the peripheral circuitry (including even elements such as decoders, current sources, and sense amplifiers) may then be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows for more space to be used for peripheral elements, which can now be combined with additional capabilities that were previously limited by the margin of identical dies in the memory cell array. The two dies can then be bonded together in a bonded multi-die integrated memory assembly, wherein an array on one die is connected to peripheral elements on the other die. While the following will focus on an integrated memory assembly with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0041] Similar to the memory die 292 in FIG. 3A, the memory structure die 280 in FIG. 3B includes a memory structure 202, which may include multiple independently accessible arrays or "blocks". System control logic 260, column control circuitry 220, and row control circuitry 210 are located in the control die 290. In some embodiments, all or part of the row control circuitry 210 and all or part of the column control circuitry 220 are located on the memory structure die 280. In some embodiments, some circuitry in the system control logic 260 is located on the memory structure die 280.

[0042] Figure 3B shows the row control circuitry 210 on the control die 290 coupled to the memory structure 202 on the memory structure die 280 via electrical path 293. For example, electrical path 293 can provide electrical connections between the row decoder 212, the row driver circuitry 214, and the block select 216 and the bit lines of the memory structure 202. The electrical path can extend from the row control circuitry 210 in the control die 290 through pads on the control die 290 that bond to corresponding pads on the memory structure die 280, which are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 can have a corresponding electrical path connected to the row control circuitry 210 in the electrical path 293 (including a pair of bonding pads). Similarly, the column control circuitry system 220, including the column decoder 222, column driver 224, block selector 226, and sense amplifier 228, is coupled to the memory structure 202 via electrical paths 294. Each of the electrical paths 294 may correspond to, for example, a word line. Additional electrical paths may also be provided between the control die 290 and the memory structure die 280.

[0043] For the purposes of this document, the phrase "a control circuit" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, row control circuit system 210, column control circuit system 220, host processor 122, microcontroller, state machine, and / or other control circuit system, or other similar circuitry for controlling non-volatile memory. A control circuit may include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or other type of circuitry. Such a control circuit system may include a driver that drives to a fixed voltage (such as a power supply), such as via a connection through a node of a fully conducting transistor (gate to power supply). Such a control circuit system may include a current source driver.

[0044] For the purposes of this document, the term "apparatus" may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, memory 104, memory chip 292, integrated memory assembly 270, and / or control chip 290.

[0045] In the following discussion, the memory structure 202 of Figures 2 and 3 will be discussed in the context of a crosspoint architecture. In a crosspoint architecture, a first set of conductive lines or wires (such as word lines) travels in a first direction relative to the underlying substrate; and a second set of conductive lines or wires (such as bit lines) travels in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. Memory cells at these crosspoints can be formed according to any of a variety of techniques (including those described above). The following discussion will primarily focus on embodiments based on a crosspoint architecture using MRAM memory cells, each MRAM memory cell being connected in series with a threshold switching selector (such as a bidirectional threshold switch (OTS)) to form an optional memory bit. However, the embodiments are not limited to providing current to a crosspoint architecture having MRAM cells (each of which has a magnetic memory element in the series OTS selector). For example, cross-point memory arrays may have memory cells of other technologies, such as ReRam, PCM (phase change memory), or FeRam.

[0046] FIG4A depicts an embodiment of a portion of a memory array 402 forming an intersection architecture in a perspective view. The memory array 402 of FIG4A is an example of an embodiment of the memory structure 202 in FIG3A or FIG3B, wherein the memory die 292 or memory structure die 280 may include a plurality of such memory arrays 402. The memory array 402 may be included in local memory 140 or host memory 124. Bit lines BL1 to BL5 are arranged in a first direction relative to the substrate below the die (not shown) (but indicated as rows entering the drawing), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction, or diagonally to provide an intersection of memory cells interconnected between WL and BL. Figure 4A shows an example of a horizontal crossover structure, where word lines WL 1 to WL 5 and BL 1 to BL 5 both extend horizontally relative to the substrate, while memory cells (two of which are indicated by 401) are oriented such that current flows vertically through the memory cells (e.g., shown as I cells). In memory arrays with additional memory cell layers, such as those discussed below in relation to Figure 4D, there will be additional corresponding layers of bit lines and word lines. A pattern, for example, would come from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0047] As depicted in Figure 4A, the memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as ReRAM, MRAM, PCM, or other materials with programmable resistors. Memory cells 401 may be referred to herein as programmable resistive memory cells. One type of programmable resistive memory cell is called an MRAM cell, which is a memory cell comprising MRAM memory elements. Memory cells 401 may also include a threshold switching selector as an additional series element within the memory cell 401, such as a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on varying selection voltages. The following discussion will focus on memory cells composed of MRAM memory elements combined in series with bidirectional threshold switching elements, but much of the discussion is applicable more generally. The current in the memory cells of the first memory stage is shown to flow upwards, as indicated by the arrow I cell, but the current can flow in either direction to read or write the memory cell bit state, as discussed in more detail below.

[0048] Figures 4B and 4C present a side view and a top view of the intersection structure in Figure 4A, respectively. The side view of Figure 4B shows a bottom conductor (or word line) WL1 and top conductors (or bit lines) BL1 to BLn. The intersections between the top and bottom conductors are MRAM memory cells 401; however, PCM, ReRAM, FeRAM, or other technologies can also be used as memory elements. Figure 4C is a top view illustrating the intersection structure of M bottom conductors WL1 to WLM and N top conductors BL1 to BLN. In a binary embodiment, the MRAM cell at each intersection can be programmed into one of two resistance states: high and low. Further details of the MRAM memory cell design and its read-through techniques are given below. In some embodiments, these conductor sets are arranged consecutively in "blocks," and such blocks can be adjacent in the word line (WL) direction and orthogonally paired in the bit line direction to form modules. Such modules can consist of 2 x 2 blocks to form a four-block combination, where the WL driver between these blocks is "center driven" between the blocks, and the WL travels continuously above the transistor driver at approximately the center of the line. Similarly, the BL driver can be located between paired block pairs in the BL direction for center driving, whereby the transistor driver and its area are shared between a pair of blocks. Copper or other types of low-resistance vias can decode the transistor driver / selector and connect it to the WL or BL. In addition to memory elements, series select elements, such as OTS, can also be included between the WL and BL in the memory cell.

[0049] Figure 4A illustrates an embodiment with a single layer of word lines and bit lines, wherein the MRAM or other memory technology for the memory cells is located at the intersection of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. Figure 4D illustrates a two-layer example.

[0050] FIG4D depicts an embodiment of a portion of a second-order memory array forming a cross-point architecture in oblique view. Similar to FIG4A, FIG4D shows a first layer 418 of memory cells 401 of memory array 403, which is connected at the intersection of the first layer word lines WL 1,1 to WL 1,4 and the bit lines BL 1 to BL 5 above. Memory array 403 may be included in memory structure 202 of FIG3A or FIG3B. Second layer memory cells 420 are formed above bit lines BL 1 to BL 5 and between these bit lines and the second set of word lines WL 2,1 to WL 2,4. In fact, BL is shared. In an alternative, the second layer may include another stack of BL located above the shown BL and below the second stack of WL. Although Figure 4D shows two layers 418 and 420 of memory cells, the structure can extend upwards with additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array of Figure 4D can be biased for read or programmed operations, such that current flows from the word line layer to the bit line layer, or vice versa, in each layer. The two layers can be structured to have current flow in the same direction in each layer for a given operation, or to have current flow in opposite directions by driver selection in positive or negative directions. Memory cells can be placed in the same orientation within the first and second layers, thereby enabling the use of current in opposite directions for read or write operations layer by layer. Alternatively, memory cells can be placed in the opposite or flipped orientation when placed between BL and WL in the second layer (thereby enabling the use of current in the same direction as that used for read or write operations in the memory cells within the first layer). It is obvious to those skilled in the art that the system can be extended from two layers to three or more layers.

[0051] The use of a crosspoint architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each crosspoint can be resistive memory cells, where data values ​​are encoded as different resistance levels, such as two levels in MRAM, or two or more levels for other memory element technologies (such as PCM). Depending on the embodiment, the memory cell can be a binary value having a low-resistance state or a high-resistance state, or it can be a multi-level cell (MLC) with additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein can be used in memory die 292 of FIG. 3A, in local memory 140 of FIG. 2, and / or in host memory 124 of FIG. 2, or in any other configuration where additional memory is applicable. Resistive memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented primarily in the context of memory arrays using crosspoint architecture with binary-valued MRAM memory cells, but most of the discussion can be applied more generally to other memory elements in memory cells within crosspoint arrays or other configurations that are obvious to those of ordinary knowledge in the art.

[0052] FIG5 illustrates the structure of an embodiment of an MRAM cell. The MRAM cell can be used as, for example, the programmable resistive memory cell 401 shown in FIG4A to FIG4D. The MRAM memory cell includes a bottom electrode 501, spacers 512, a threshold switching selector 502, spacers 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated in this example by a separating or tunneling layer of magnesium oxide (MgO) 505, and a top electrode 511 separated from the free layer 507 by spacers 509. Spacers 509 may be composed of an MgO capping layer in contact with the free layer 507. Spacers 509 may also contain additional metal layers. In another embodiment, the positions of the reference layer 503 and the free layer 507 are interchanged, wherein the reference layer 503 is on top of the MgO 505, and the free layer 507 is below the MgO 505. In another embodiment, the critical limit switching selector 502 is located between the free layer 507 and the top electrode 511.

[0053] In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 503 and the free layer 507: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 503 is fixed, and in the example of FIG5, the orientation is upward. The reference layer 503 is also referred to as a fixed layer or pinned layer. The reference layer 503 may consist of multiple ferromagnetically coupled layers in a structure commonly referred to as a synthetic antiferromagnet or SAF for short.

[0054] Data is written to MRAM memory cells by programming the free layer 507 to have the same or opposite orientation relative to the reference layer 503. An array of MRAM memory cells can be placed in an initial (or erased) state by setting all MRAM memory cells to a low-resistance state, wherein all their free layers have the same magnetic field orientation as their reference layers. Then, each memory cell is selectively programmed (also called "written") by placing its free layer 507 in a high-resistance state (by reversing the magnetic field to the opposite of the reference layer 503). The reference layer 503 is formed such that it retains its orientation when programming the free layer 507. The reference layer 503 can have a more complex design, including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the diagrams and discussion, which focus only on the fixed magnetic layer of the tunneling magnetoresistance in the main responsible cell.

[0055] The threshold switching selector 502 has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage or a current higher than its threshold current, and until its voltage bias drops below Vhold (also referred to as "Voffset") or its current drops below Ihold. After crossing Vt and while exceeding Vhold, the switching selector has a low resistance (in a conducting or conductive state). The threshold switching selector remains conducting until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. Therefore, to program memory cells at the crossover point, a voltage or current sufficient to turn on the associated threshold switching selector is applied to set or reset the memory cell; and similarly, to read the memory cell, the threshold switching selector is activated by turning on the threshold switching selector before determining the resistance state of the memory cell. A set of examples of threshold switching selectors are bidirectional threshold switching materials for bidirectional threshold switching devices (OTS). Examples of threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, wherein the atomic percentage of each element ranges from a fractional percentage to more than 90%. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also contain an additional conductive layer at the interface with the reference layer 503. For example, a spacer 514 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 514 at the interface with the reference layer 503 may consist of a single conductive layer or multiple conductive layers. The threshold switching selector 502 may also contain an additional conductive layer at its interface with the bottom electrode 501. For example, a spacer 512 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 512 at the interface with the bottom electrode 501 may consist of a single conductive layer or multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicate, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. The threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes substantially from insulating or quasi-insulating to conductive.

[0056] In one embodiment, a current-forced method is used to access the MRAM cell. The current-forced method can be used to read or write to the MRAM cell. In the current-forced method, the access current (e.g., Iread or Iwrite) is driven through the bottom electrode 501 by a current driver. The current is provided by a transistor- or resistor-based current source. In one embodiment, the current driver may be part of an address-selectable column driver circuitry (e.g., array driver 224) for electrode 501. However, alternatively, the current driver may be part of an address-selectable row driver circuitry (e.g., driver circuitry 214) for electrode 501. A voltage (e.g., Vselect) is provided to the top electrode 511. In this document, the terms "read current" (Iread) and "write current" (Iwrite) will be used in conjunction with the access current driven through the MRAM cell (or other programmable resistor cell). The write current can change the state of the MRAM cell. As an example, an MRAM cell with a critical dimension (CD) of approximately 20 nanometers and a RA of 10 Ωµm² can be switched from a P state to an AP state using a write current of approximately 30 µA for approximately 50 ns. If the application time is limited (e.g., < 20 ns), the read current can be approximately half the write current. A write current flowing through the MRAM cell in one direction changes an AP-state MRAM cell to a P state. A write current flowing through the MRAM cell in the other direction (e.g., in the read direction) changes a P-state MRAM cell from a P state to an AP state. Generally, the read current is preferably set low enough and the read duration short enough before determining the cell state or capturing and storing the voltage level associated with the memory cell state, so that the MRAM cell state is not changed from P to AP or vice versa during the read operation. Generally, the write current required to switch the MRAM state from P to AP is greater in absolute terms than the write current required to switch the MRAM state from AP to P. Therefore, this provides a better read direction with a margin of safety against state changes before correctly sensing the bit state. The current value can be adjusted accordingly by the write direction, or by the current used for P to AP when using a single value.

[0057] In some embodiments, a read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some embodiments, the MRAM cell is read by performing an SRR (Self-Reference Read). In one embodiment, the SRR has a first read (Read1 in the P2AP direction), a first write (Write 1 to the AP state), and a second read (Read2 in the P2AP direction). The cell's original state can then be restored by the second write (Write_Back for bits initially in the P state to the P state). Alternatively, in another embodiment, for example, when the second layer is addressed with a memory cell having the same orientation as in the first layer, the SRR read current and the destructive write current are reversed.

[0058] In one embodiment, the voltage level of the memory cell caused by Read1 in the P2AP direction is sensed and stored, for example, on a capacitor; or converted into digital bits by an analog-to-digital converter, and stored in memory (e.g., SRAM) until used in Read2. The state stored on the capacitor can be adjusted, for example, by applying a voltage to one terminal of the capacitor connected to the storage capacitor. Alternatively, the digitally stored level can be adjusted by digitally adding or subtracting 150mV to the stored bit. The 150mV can be adjusted according to the typical bit resistance. For example, if the low resistance state of the bit is 25K ohms and the high resistance is 50K ohms, then the difference is 25K ohms. If the current reading is 15 µA, then the voltage difference between states is 25 Kohms x 15 µA = 375 mV, making a choice of 150 mV acceptable, but perhaps indicating that 187.5 mV would be better, for example.

[0059] Although the foregoing describes a read in the P2AP direction and a destructive write to the AP state (whereby the write back to the P state is performed after the SRR), in an alternative embodiment, the first SRR has a first read (Read1 in the AP2P direction), a destructive write to the P state (Write 1), and a second read in the AP2P direction (Read2).

[0060] In one embodiment, an MRAM cell is read by applying, for example, approximately 0V to the top electrode 511 while driving a current, for example, 15 microamperes (µA), through the bottom electrode 501, by turning on a transistor connected between 511 and a power supply. This read current can flow from the bottom electrode 501 to the top electrode 511. Note that the read can be Read1 or Read2 in the P2AP direction. P2AP means that the current flows in the direction of writing bits from P to AP, or from AP to AP. In some embodiments, bipolar write operations are used to write data to the MRAM cell. In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, 3V to the top electrode 511 while driving a write current, for example, -30 µA, through the bottom electrode 501. This write current will flow from the top electrode 511 to the bottom electrode 501. In one embodiment, an MRAM cell is written from a P state to an AP state by simultaneously applying, for example, 0V to the top electrode 511 while driving a current, for example, 30 µA, through the bottom electrode 501. This write current flows from electrode 501 to electrode 511.

[0061] As an alternative to the method in FIG5, a selection voltage may be applied to the bottom electrode 501 as the applied access current passes through the top electrode 511. In one embodiment, an MRAM cell is read by applying, for example, 3V to the bottom electrode 501 while driving, for example, a read current of -15 µA through the top electrode 511. This read current may flow from the bottom electrode 501 to the top electrode 511.

[0062] In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, -3V to the bottom electrode 501 while driving a write current, for example, 30 µA, through the top electrode 511. The electron flow will flow from the bottom electrode 501 to the top electrode 511. In one embodiment, an MRAM cell is written from the P state to the AP state by applying, for example, 0V to the bottom electrode 501 while driving a current, for example, -30 µA, through the top electrode 511. The electron flow will flow from the top electrode 511 to the bottom electrode 501. The direction of the current polarity that switches the magnetization direction of the bit to the P or AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0063] Some biasing techniques may cause voltage to be generated in the unselected memory cells in the array, which may induce "leakage" current in the unselected memory cells. Although this power consumption waste can be mitigated to some extent by designing the memory cells to have relatively high resistance levels in both the high-resistance state and the low-resistance state when WL or BL is not addressed, this burden leakage will still lead to increased current and power consumption and impose additional design constraints on the memory cell and array design due to the lack of read and write margin. One way to solve this unwanted current leakage is to place selector elements in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, the select transistor can be placed in series with each resistive memory cell element in Figures 4A to 4D, so that memory cell 401 is now a composite of select transistor and programmable resistor. This architecture can be called 1T1R. However, the use of select transistors requires the introduction of additional control lines and cell areas to enable the corresponding transistor of the selected memory cell. Furthermore, transistors often cannot scale in the same way as the write current of resistive memory elements, making the use of transistor-based selectors a limiting factor, for example, in reducing cost, when memory arrays are miniaturized. An alternative to the selection transistor is to use a threshold switching selector (e.g., threshold switching selector 502) connected in series with a programmable resistive element. A two-terminal threshold switching selector can turn on the corresponding selection transistor for selecting a memory cell without requiring the aforementioned additional control lines and additional cell area. In some embodiments, the memory system performs a read as described herein, reading a memory cell having a two-terminal threshold switching selector connected in series with a programmable resistive memory element.

[0064] Figures 6A and 6B illustrate an embodiment incorporating an adjacency switching selector into an MRAM memory array with a crosspoint architecture. The examples in Figures 6A and 6B show two MRAM cells (layer 1 cell and layer 2 cell) in a two-layer crosspoint array, as shown in Figure 4D, but presented in a side view. As depicted in Figure 6A, keeping the orientation of the MRAM layers the same as that of layer 1 and layer 2 cells allows for identical manufacturing processes for each layer. Figure 6B features an inverting memory cell that allows the drive circuitry system to operate in the same manner; for example, BL is reduced to Read P2AP for each layer. Figures 6A and 6B show the first lower conductive line of word line 1 600, the first upper conductive line of word line 2 620, and the second intermediate conductive line of bit line 610. In these figures, for ease of presentation, all such lines are shown traveling from left to right across the plane. However, in the intersection array, it is more accurately represented in the oblique view of Figure 4D, where word lines (or first conductive lines or wires) travel in a direction parallel to the surface of the underlying substrate, and bit lines (or second conductive lines or wires) travel in a second direction parallel to the surface of the substrate, primarily orthogonal to the first direction. MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and intermediate tunneling barrier. However, in actual implementations, additional structures related to Figure 5 described above are generally included.

[0065] An MRAM element 602, comprising a free layer 601, a tunneling barrier 603, and a reference layer 605, is formed above a threshold switching selector 609, wherein this series combination of the MRAM element 602 and the threshold switching selector 609 forms a layer 1 cell between bit line 610 and word line 1 600. The series combination of the MRAM element 602 and the threshold switching selector 609 operates largely as described above when the threshold switching selector 609 is turned on. However, the threshold switching selector 609 initially requires a voltage higher than its threshold voltage Vth to be turned on, and the bias current or voltage then needs to be maintained high enough to exceed a holding current or holding voltage higher than the threshold switching selector 609 to keep it on during subsequent read or write operations.

[0066] On the second layer, an MRAM element 612, including a free layer 611, a tunneling barrier 613, and a reference layer 615, is formed above a threshold switching selector 619. The series combination of the MRAM element 612 and the threshold switching selector 619 forms a layer 2 cell between bit line 610 and word line 2 620. The layer 2 cell operates as a layer 1 cell, except that the lower conductor now corresponds to bit line 610, and the upper conductor is now a word line (word line 2 620). Other paired layers may similarly share another bit line among them, having the following patterns: WL1, BL1, WL2; WL3, BL2, WL4; or having separate bit lines in the pattern, such as WL1, BL1, WL2, BL2. Or having separate bit lines in the pattern of WL1, BL1, BL2, WL2.

[0067] In the embodiment of FIG. 6A, the threshold switching selector 609 / 619 is formed below the MRAM elements 602 / 612, but in an alternative embodiment, the threshold switching selector may be formed above one or two layers of MRAM elements. MRAM memory cells are directional. In FIG. 6A, MRAM elements 602 and 612 have the same orientation, with the free layer 601 / 611 above the reference layer 605 / 615 (relative to a substrate not shown). Since each of these two layers, and subsequent layers in embodiments with more layers, can be formed according to the same manufacturing sequence, forming such layers with the same structure between conductive lines can have several advantages, particularly regarding process advantages.

[0068] FIG. 6B illustrates an alternative embodiment configured in a similar manner to the embodiment of FIG. 6A, except that in the layer 2 cell, the positions of the reference layer and the free layer are reversed. More specifically, as in FIG. 6A, between word line 1 650 and bit line 660, the layer 1 cell includes an MRAM element having a free layer 651 formed above a tunneling barrier 653, which in turn is formed above a reference layer 655, wherein an MRAM element 652 is formed above a threshold switching selector 659. The second layer of the embodiment of FIG. 6B again has an MRAM element 662 formed above a threshold switching selector 669 between bit line 660 and word line 2 670, but with the MRAM element 662 reversed relative to FIG. 6A, the reference layer 661 is now formed above the tunneling barrier 663 and the free layer 665 is now below the tunneling barrier 663. Alternatively, the configuration of MRAM element 662 can be used in layer 1 cells, and the configuration of MRAM cell 652 can be used in layer 2 cells.

[0069] Although the embodiment of FIG. 6B requires different program sequences to form layers, it may have advantages in some embodiments. Specifically, the directionality of the MRAM structure can make the embodiment of FIG. 6B attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit lines are biased to the lower and upper layers in the same way, and the word lines are also biased in the same way. For example, if memory cells of layer 1 and layer 2 are sensed in the P2AP direction (relative to the reference layer and the free layer), bit line layer 660 will be biased to a lower voltage level (e.g., 0V) for both the upper and lower cells, while word lines 1 650 and 2 670 are both biased to a higher voltage level. Regarding writing, the situation is similar when writing to a high-resistance AP state. With both word line 1 650 and word line 2 670 biased to a higher voltage level, bit line 660 is biased to a lower voltage level (e.g., 0V) for both the upper and lower cells.

[0070] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switching selector is placed in series with an MRAM element, the threshold switching selector can be turned on by applying sufficient voltage and passing sufficient current across the series combination of the threshold switching selector and the MRAM element before current can pass through the MRAM element.

[0071] FIG. 7 depicts an embodiment of a memory array 700 with a cross-point architecture. The memory array 700 may be included in the memory structure 202 of FIG. 3A or FIG. 3B. The array 700 has a set of first conductive lines 706a to 706h and a set of second conductive lines 708a to 708d. In one embodiment, the set of first conductive lines 706a to 706h are word lines, and the set of second conductive lines 708a to 708b are bit lines. For ease of discussion, the set of first conductive lines 706a to 706h may be referred to as word lines, and the set of second conductive lines 708a to 708b may be referred to as bit lines. However, the set of first conductive lines 706a to 706h may be bit lines, and the set of second conductive lines 708a to 708b may be word lines.

[0072] The memory array 700 has a plurality of programmable resistive memory cells 401. Each memory cell 401 is connected between one of the first conductive lines 706 and one of the second conductive lines 708 (e.g., at the intersection between one of the first conductive lines 706 and one of the second conductive lines 708). In one embodiment, each memory cell 401 has a magnetoresistive random access memory (MRAM) element connected in series with a threshold switching selector. The threshold switching selector 502 is configured to conduct with a lower resistance in response to a voltage level applied exceeding a threshold voltage of the threshold switching selector 502, and to remain on with a lower resistance until the current through the switching selector 502 decreases below the selector holding current (Ihold). The threshold switching selector 502 may be a two-terminal device. In one embodiment, the threshold switching selector 502 includes an OTS.

[0073] For the purposes of discussion, memory cell 401a is selected for access. This can be read or write access. The selected memory cell 401a is located at the intersection of the selected word line 706g and the selected bit line 708b. A selected memory cell means a memory cell selected for memory operations (such as read or write). The selected memory cell is connected between the selected word line and the selected bit line. To select memory cell 401a, a select voltage (V select_BL) such as near ground is provided to the selected bit line (e.g., bit line 708b), and an access current (I access) is driven (or forced) through the selected word line (e.g., word line 706g). A selected word line means that the word line is connected to at least one selected memory cell. The selected word line will generally be connected to one or more unselected memory cells. A selected bit line means that the bit line is connected to at least one selected memory cell. Selected bit lines are typically connected to one or more unselected memory cells.

[0074] In one embodiment, assuming an I access is applied to the selected word line with a constant current output voltage sufficient relative to the BL voltage, then V select_BL has a sufficient value such that the threshold switching selector 502 in the selected memory cell will be turned on. For example, V select_BL may be approximately 0V. On the other hand, V unsel_BL has a value such that the threshold switching selector 502 in the unselected memory cell will not be turned on; for example, if the positive supply is 3.3V, then V unsel_BL may be approximately 1.65V. After the OTS is turned on, an access current (I access) is driven through at least a portion of the selected word line 706g. This access current may also flow through a portion of the selected memory cell 401a and the selected bit line 708b after the OTS is turned on. This selected I access can be driven up to, for example, 15 µa for reading or up to, for example, 30 µa for writing by a current source having a constant current output voltage of, for example, 3.3V. To write the opposite polarity, the selected word line is forced with, for example, -30 µA, and the selected bit line is forced to approximately 3.3V.

[0075] Other memory cells are not selected for access (i.e., unselected memory cells). Unselected memory cells mean that the memory cells are currently not selected for access (e.g., read or write). Unselected word lines are connected only to unselected memory cells. Unselected bit lines are connected only to unselected memory cells. Unselected word lines and bit lines are referred to as unselected word lines or unselected bit lines, respectively. In one embodiment, a word line or bit line can be deselected by forcing it to an unselected voltage (such as Vmid, e.g., 1.65V), which is approximately half of the driving constant current output voltage; for example, 3.3V. The unselected voltage (Vunsel_BL) is provided to the unselected bit lines (e.g., bit lines 708a, 708c, 708d). An unselected voltage (Vunsel_WL) such as Vmid is provided to the unselected word lines (e.g., word lines 710a, 710b, 710c, 710d, 710e, 710f, and 710h). Iaccess can flow from either direction through the selected word lines (and through the selected bit lines). In one embodiment, no current is forced through the unselected word lines (e.g., 706a, 706b, 706c, 706d, 706e, 706f, and 706h) except for leakage current.

[0076] In the example of FIG. 7, there are more word lines than bit lines in the crosspoint array. In another embodiment, there are more bit lines than word lines in the crosspoint array. In another embodiment, the number of bit lines in the crosspoint array is equal to the number of word lines. In the example of FIG. 7, there are up to twice as many word lines as bit lines in the crosspoint array; however, different ratios can be used. Thus, different block sizes can be implemented. For example, a block may have 1024 BL x 2048 WL, which can be configured into a module of 2048 x 4096 units by means of WL and BL between four blocks driven by a center. In one embodiment, a set of memory is read by, for example, selecting a memory unit from several blocks. In some embodiments, more than one memory unit from a block may be selected for reading.

[0077] In some embodiments, a current-forced method is used to access memory cells in a crosspoint memory array. A threshold switching selector may be used in series with a programmable resistive memory element. The threshold switching selector may be connected in series with the programmable resistive memory element between the word line and the bit line. Therefore, any voltage on the threshold switching selector will reduce the voltage on the programmable resistive memory element. Generally, there will be some variation in the offset or holding voltage between threshold switching selectors. The current-forced method can help mitigate the offset voltage variation between threshold switching selectors or the critical size (CD) variation of the memory element voltage, thereby helping to minimize the variation in selected cell current between cells.

[0078] Figure 8 is a diagram of one embodiment of a system for reading memory cells having a threshold switching selector connected in series with a programmable resistive memory element. The system has a current source 802, a control circuit 804, and a voltage source Vstep 806. In one embodiment, Vstep 806 is the supply voltage. One memory cell 401 of a plurality of memory cells in a crosspoint array is depicted. Other circuit elements, such as drivers and decoders, are not depicted in Figure 8. For example, a transistor may be present between the current source 802 and S1. And, one or more decoding transistors may be present between S1 and the word line (WL). Each memory cell 401 has a programmable resistive memory element 702 connected in series with a threshold switching selector 502. In one embodiment, memory cell 401 is an MRAM cell, wherein the programmable resistive memory element 702 is a magnetoresistive memory element, and the threshold switching selector 502 is an OTS. However, the memory cell can be a PCM cell, a ReRaM cell, a FeRam cell, etc. The threshold switching selector 502 does not need to be an OTS. The threshold switching selector 502 can be replaced by a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current on the selection voltage. The voltage Vselect on the bit line (BL) is a voltage with a suitable magnitude for selecting the memory cell. In one embodiment, Vselect to the bit line is close to 3.3V. In another embodiment, Vselect to the bit line is close to 0V.

[0079] Control circuit 804 controls switch S1 to provide a read current (Iread) or a step voltage to the selected word line. A write current can be provided to the selected word line at different times. The read current Iread can have a positive or negative value, as indicated by the direction of the current arrow below Iread in Figure 8. Therefore, the term "current source" will be used herein regardless of the direction of current flow at the output of the current source. Those skilled in the art sometimes use the terms "sourcing a current" and "sinking a current" to distinguish between the directions of current flow. Current source 802 can "source" or "sink" current relative to the direction of current flow. In addition, phrases such as "the current source 802 providing a current" or "the current source 802 driving a current" include output current Iread which is positive (e.g., "outflow current") and negative (e.g., "collection current").

[0080] In one embodiment, current source 802 provides a first write current to "set" the memory cell and a second write current to "reset" the memory cell, wherein the two write currents have opposite polarities (i.e., positive and negative). During a read operation, the current increases the voltage across the selected memory cell until the threshold switching selector 502 is turned on. In one embodiment, the read current has a positive polarity and charges the selected word line (where the bit line is at a lower voltage) until the threshold switching selector 502 is turned on. In another embodiment, the read current has a negative polarity similar to the reset or set current and decreases the voltage across the selected word line (where the selected bit line is at a higher voltage) until the threshold switching selector 502 is turned on. After the threshold switching selector 502 is turned on, Iread is driven through memory cell 401.

[0081] When the threshold switching selector 502 is turned on, a backflush current may be generated. This backflush is a function of the voltage change caused by the voltage drop across the threshold switching selector 502 and the capacitance. The combination of read current and backflush current may cause the current through the programmable resistive memory element 702 to be too large, thereby unintentionally flipping the state of the memory element 702. In one embodiment, when a backflush current is present, the control circuit 804 controls the switch S1 to connect Vstep 806 to the selected word line. Therefore, unintentional bit flipping caused by the backflush current flowing through the programmable resistive memory element 702 can be prevented.

[0082] The threshold voltage of the threshold switching selector 502 in different units (and the drift of the threshold voltage in any unit over time) can vary considerably. In one embodiment, the control circuit 804 controls the switch S1 to connect Vstep 806 to the select word line to turn on the threshold switching selector 502. Therefore, each unit will have the same maximum voltage during reading, which compensates for the variation in the threshold voltage of the threshold switching selector 502. In one embodiment, the control circuit 804 controls the switch S1 to connect Vstep 806 to the select word line after the return current has dissipated, which also compensates for the variation in the threshold voltage of the threshold switching selector 502.

[0083] Figure 9 is a flowchart of one embodiment of a procedure 900 for reading programmable resistive memory cells in a crosspoint array. Procedure 900 can be used to read memory cells having a threshold switching selector 502 connected in series with a programmable resistive memory element 702. Procedure 900 can improve read accuracy (bit error rate) by preventing the memory cell from unintentionally flipping its state before sensing the memory cell. Procedure 900 can improve read accuracy (bit error rate) by compensating for different threshold voltages of the threshold switching selector 502. In one embodiment, procedure 900 is used for midpoint reads (also known as "direct cell read relative to reference voltage" or full-domain reference reads). In one embodiment, procedure 900 is used in an SRR. Procedure 900 can be executed by the system in Figure 8, but is not limited thereto.

[0084] Step 902 includes driving a read current to a selected word line connected to the selected memory cell. A selection voltage may be applied to the selected bit line when driving the read current to the selected word line. In one embodiment, the selected bit line is maintained at approximately 0V when a read current of approximately 15 µA is driven to the selected word line. In one embodiment, the selected bit line is maintained at approximately 3.3V when a read current of approximately -15 µA is driven to the selected word line.

[0085] Step 904 includes applying a step voltage Vstep to the selected word line while the threshold switching selector is on. The phrase "applying the step voltage Vstep to the selected word line while the threshold switching selector is on" means that the threshold switching selector is on for at least a portion of the time during which the step voltage Vstep is applied to the selected word line. The step voltage is not necessarily applied directly to the selected word line. In one embodiment, there is one or more decoding transistors between S1 and the selected word line, wherein the one or more decoding transistors provide the step voltage to the selected word line. In one embodiment, control circuitry 804 operates S1 to disconnect Iread and connect Vstep. Step 904 may be performed at different points in the read operation. In one embodiment, the step voltage Vstep is used to turn on the threshold switching selector 502. In one embodiment, the step voltage Vstep is applied after the threshold switching selector is on when a backflow current may be present. The phrase "the step voltage Vstep is applied while a snapback current is present" means that a snapback current exists for at least a portion of the time the step voltage is applied. In one embodiment, the step voltage Vstep is applied after the snapback current has dissipated. Figures 10A through 15C provide further details of various embodiments of the timing of the applied step voltage pulse.

[0086] In one embodiment, a step voltage Vstep is applied after the threshold switching selector 502 is turned on, when a backflow current may be present. The threshold switching selector 502 may have a high resistance before being turned on; however, when the threshold switching selector 502 is turned on, this resistance may drop rapidly. This rapid drop in resistance can lead to what may be called "excess charge." During sensing, excess charge may flow in memory element 702 as excess current greater than the steady-state memory cell current. This may alter the state of memory element 702, thereby causing read errors. In one embodiment, excess charge is transferred to voltage source 806, which reduces the flow of unwanted excess current (above the desired Iread current) in memory element 702, thereby reducing the probability of premature changes in the state of memory element 702.

[0087] Step 906 includes sensing the selected memory cell when driving the read current through the memory element 702. In one embodiment, the sensing is for a Read1 with SRR. In one embodiment, the sensing is for a Read2 with SRR after being written to a specific state. In one embodiment, the sensing is for a global reference read.

[0088] Figures 10A, 10B, and 10C depict the timing of voltage and current during one embodiment of current forced read using a step voltage. The threshold voltage of the threshold switching selector can vary considerably. Cell-to-cell variation can exist. And over time, the threshold voltage of a given threshold switching selector tends to drift. In one embodiment, a step voltage is used to turn on the threshold switching selector 502, thus removing the variation in word line voltage when the threshold switching selector 502 is turned on. Figure 10A shows the timing of one embodiment of the voltage applied to the selected word line. Before time t1, the memory system applies Vmid to the selected word line (line 1002). Between t1 and t2, the memory system applies a step voltage Vstep to the selected word line (line 1004). Referring now to Figure 10C, the voltages on the selected word line and the selected bit line will be discussed. Before t1, the memory system drives both the selected word line and the selected bit line to Vmid. Between t1 and t2, the word line voltage increases to Vstep. The bit line voltage may also drop to ground. The step voltage is large enough to create a voltage on the memory cell sufficient to turn on the threshold selector 502. Note that there may be a considerable difference between the threshold voltages of the threshold selector 502 in different memory cells. The y-axis shows the general range where Vstep is greater than the threshold voltage (Vt) of the threshold selector 502. Now referring to Figure 10B, between t2 and t4, the read current is driven to the selected word line (line 1012). Returning to Figure 10A, at t2, the step voltage is removed from the selected word line. Referring again to Figure 10C, at t2, the voltage on the selected word line begins to drop. Depending on the state of the memory element 702, the word line voltage stabilizes at a voltage corresponding to the high resistance state (HRS) or low resistance state (LRS). The memory cell can be read at approximately t3. At t4, the word line and bit line voltages drop to Vmid. Note that regardless of the Vt of the threshold switching selector 502, each memory cell will have the same voltage at t2, thereby removing some of the variability of the variation of Vt of the threshold switching selector 502.

[0089] Figures 11A, 11B, and 11C depict the timing of voltage and current during one embodiment of current-forced read using a step voltage. A considerable backflow current may exist after the threshold switching selector 502 is turned on. In one embodiment, a step voltage is applied when a backflow current is present, which removes charge and thereby prevents too much current from flowing through the programmable resistive memory element 702. Figure 11A shows the timing of one embodiment of the voltage applied to the select word line. Before time t1, the memory system applies Vmid to the select word line (line 1102). Figure 11B shows the read current driven to the select word line (line 1112) between t1 and t3. Referring now to Figure 11C, the voltages on the select word line and the select bit line will be discussed. Before t1, the memory system drives both the select word line and the select bit line to Vmid. After t1, the bit line voltage can drop to ground. The word line voltage increases between t1 and t2 due to the read current. At t2, the threshold switching selector is turned on. When the threshold switching selector 502 is turned on, the resistance of the threshold switching selector can decrease rapidly. A large backflow current can be generated due to the voltage change and circuit capacitance. This backflow current may toggle the state of the memory cell before reading. However, in one embodiment, a step voltage is applied when a backflow current is present. Referring back to FIG11A, a step voltage is applied between t3 and t4 (line 1104). Referring again to FIG11B, the read current is not driven to the selected word line between t3 and t4. The step voltage will have a magnitude sufficient to keep the threshold switching selector 502 in the on state. Referring back to FIG11A, the step voltage is removed after t4. Referring again to FIG11B, the read current is driven to the selected word line again between t4 and t6 (line 1114). Referring now to Figure 11C, depending on the state of memory element 702, the word line voltage stabilizes at a voltage corresponding to either the high resistance state (HRS) or the low resistance state (LRS). The memory cell can be read at approximately t5. At t6, the word line and bit line voltages drop to Vmid.

[0090] Figures 12A, 12B, and 12C depict the timing of voltage and current during one embodiment of current-forced read using a step voltage. The threshold voltage of the threshold switching selector 502 can vary considerably. In one embodiment, a step voltage is applied after the return current has dissipated, which helps to reduce the impact of this Vt variation. Figure 12A shows the timing of one embodiment of the voltage applied to the selected word line. Before time t1, the memory system applies Vmid to the selected word line (line 1202). Figure 12B shows the read current driven to the selected word line (line 1212) between t1 and t3. Referring now to Figure 12C, the voltages on the selected word line and the selected bit line will be discussed. Before t1, the memory system drives both the selected word line and the selected bit line to Vmid. After t1, the bit line voltage can drop to ground. The word line voltage increases between t1 and t2 due to the read current. Figure 12C illustrates two examples of the threshold voltage for the threshold selector 502. In one case, the threshold selector 502 is turned on at t2. In the other case, the threshold selector 502 is turned on at t3. For both cases, the word line voltage stabilizes before t4. Referring back to Figure 12A, a step voltage (line 1204) is applied between t4 and t5. Referring again to Figure 12B, no read current is driven to the selected word line between t4 and t5. The step voltage will have a magnitude sufficient to keep the threshold selector 502 in the on state. Referring back to Figure 12A, the step voltage is removed after t5. Referring again to Figure 12B, the read current is driven to the selected word line again between t5 and t7 (line 1214). Now referring to Figure 12C, the word line voltage stabilizes at the voltage corresponding to the high resistance state (HRS) or low resistance state (LRS). In this example, separate graphs are not plotted for HRS and LRS. Memory cells can be read at approximately t6. At t7, the word line and bit line voltages drop to Vmid. Note that Figure 12C shows that even if the threshold switch Vt varies (see t2, t3), each cell should be at Vstep at t5, thereby providing greater uniformity in the behavior of the threshold switching selector 502.

[0091] In some embodiments, a step voltage is applied to the word line, which is at a higher voltage than the bit line. In other embodiments, a step voltage is applied to the word line, which is at a lower voltage than the bit line. Figures 13A, 13B, and 13C depict the timing of voltage and current during one embodiment of current forced read using a step voltage, wherein the word line is at a lower voltage than the bit line. Figures 13A, 13B, and 13C have similar concepts discussed in conjunction with Figures 10A, 10B, and 10C. In one embodiment, the step voltage is used to turn on a threshold switching selector, which removes the variation in word line voltage when the threshold switching selector is turned on. Figure 13A shows the timing of one embodiment of the voltage applied to the selected word line. Before time t1, the memory system applies Vmid to the selected word line (line 1302). Between t1 and t2, the memory system applies a step voltage Vstep to the select word line (Figure 1304). Now referring to Figure 13C, the voltages on the select word line and the select bit line will be discussed. Before t1, the memory system drives both the select word line and the select bit line to Vmid. Between t1 and t2, the word line voltage decreases to Vstep. This brings the bit line voltage to the select voltage, which can be approximately twice Vmid. The magnitude of the step voltage is sufficient (combined with the bit line voltage) to create a voltage on the memory cell sufficient to activate the threshold switching selector. Note that there can be a considerable difference between the threshold voltages of different memory cells. The y-axis shows the typical range where Vstep is less than the threshold voltage (Vt) of the threshold switching selector. Now referring to Figure 13B, between t2 and t4, the read current is driven to the select word line (Figure 1312). Returning to Figure 13A, at t2, the step voltage is removed from the select word line. Referring again to Figure 13C, at t2, the voltage on the selected word line begins to increase. Therefore, the voltage on the selected memory cell begins to decrease, as is also the case in the example in Figure 10C. Depending on the state of memory element 702, the word line voltage stabilizes at a voltage corresponding to either the high resistance state (HRS) or the low resistance state (LRS). The memory cell can be read at approximately t3. At t4, the word line and bit line voltages drop to Vmid.

[0092] Figures 14A, 14B, and 14C depict the timing of voltage and current during one embodiment of current-forced read using a step voltage. Figures 14A, 14B, and 14C are similar to Figures 11A, 11B, and 11C, but are used for embodiments where the word line voltage is lower than the bit line select voltage. In one embodiment, a step voltage is applied when a backflow current is present, which removes charge and thereby prevents too much current from flowing through the programmable resistive memory element 702. Figure 14A shows the timing of one embodiment of the voltage applied to the selected word line. Before time t1, the memory system applies Vmid to the selected word line (line 1402). Figure 14B shows the read current driven to the selected word line (line 1412) between t1 and t3. Referring now to Figure 14C, the voltages on the selected word line and the selected bit line will be discussed. Before t1, the memory system drives both the selected word line and the selected bit line to Vmid. After t1, the bit line voltage can be increased to the bit line select voltage. The bit line select voltage can be approximately twice Vmid. The word line voltage decreases between t1 and t2 due to the read current. At t2, the threshold switching selector is turned on. When the threshold switching selector 502 is turned on, the resistance of the threshold switching selector can decrease rapidly. A large backflow current can be generated due to the voltage change and circuit capacitance. This backflow current may toggle the state of the memory cell before reading. However, in one embodiment, a step voltage is applied when the backflow current is present. Referring back to FIG14A, a step voltage (line 1404) is applied between t3 and t4. Referring again to FIG14B, the read current is not driven to the selected word line between t3 and t4. The step voltage will have a magnitude sufficient to keep the threshold switching selector 502 in the on state. Referring back to FIG14A, the step voltage is removed after t4. Referring again to Figure 14B, the read current is driven again to the selected word line (line 1414) between t4 and t6. Now referring to Figure 14C, depending on the state of memory element 702, the word line voltage stabilizes at the voltage corresponding to the high resistance state (HRS) or low resistance state (LRS). The memory cell can be read at approximately t5. At t6, the word line and bit line voltages drop to Vmid.

[0093] Figures 15A, 15B, and 15C depict the timing of voltage and current during one embodiment of current-forced read using a step voltage. Figures 15A, 15B, and 15C are similar to Figures 12A, 12B, and 12C, but are used for embodiments where the word line voltage is lower than the bit line select voltage. The threshold voltage of the threshold switching selector can vary considerably. In one embodiment, a step voltage is applied after the rush current has dissipated, which helps to reduce the impact of this variation. Figure 15A shows the timing of one embodiment of the voltage applied to the selected word line. Before time t1, the memory system applies Vmid to the selected word line (line 1502). Figure 15B shows the read current driven to the selected word line between t1 and t3 (line 1512). Referring now to Figure 15C, the voltages on the selected word line and the selected bit line will be discussed. Before t1, the memory system is driven to Vmid via both the select word line and the select bit line. After t1, the bit line voltage can drop to ground. The word line voltage decreases between t1 and t2 due to the read current. Figure 15C shows two examples of the threshold voltage of the threshold selector 502. In one case, the threshold selector 502 is turned on at t2. In another case, the threshold selector 502 is turned on at t3. For both cases, the word line voltage stabilizes before t4. Referring back to Figure 15A, a step voltage (line 1504) is applied between t4 and t5. Referring again to Figure 15B, no read current is driven to the select word line between t4 and t5. The step voltage will have a magnitude sufficient to keep the threshold selector 502 on (giving the bit line voltage). Referring back to Figure 15A, the step voltage is removed after t5. Referring again to Figure 15B, the read current is driven back to the selected word line (line 1514) between t5 and t7. Now referring to Figure 15C, the word line voltage stabilizes at the voltage corresponding to the high resistance state (HRS) or low resistance state (LRS). In this example, separate lines are not drawn for HRS and LRS. The memory cell can be read at approximately t6. At t7, the word line and bit line voltages drop to Vmid.

[0094] As can be seen from the above, according to one embodiment, a device includes one or more control circuits configured to communicate with a crosspoint memory structure having a first conductive line, a second conductive line, and memory cells. Each memory cell is located at the intersection of the first conductive line and the second conductive line. Each memory cell has a programmable resistive memory element connected in series with a threshold switching selector. The one or more control circuits are configured to apply a fixed-value read current to a selected first conductive line when the selected second conductive line is at a selection voltage. The selected first conductive line is connected to the selected memory cell. The one or more control circuits are configured to apply a step voltage to the selected first conductive line when the threshold switching selector is turned on. The one or more control circuits are configured to sense the selected memory cell after the step voltage is removed from the selected first conductive line and when driving the fixed-value read current through the selected memory cell.

[0095] In a further embodiment, the one or more control circuits are configured to begin applying the step voltage to the selected first conductor before the threshold switching selector is turned on and to continue applying the step voltage to the selected first conductor after the threshold switching selector has been turned on.

[0096] In a further embodiment, the one or more control circuits are configured to begin applying the step voltage to the selected first conductor after the threshold switching selector of the selected memory cell is turned on by applying the fixed value read current to the selected first conductor.

[0097] In a further embodiment, the one or more control circuits are configured to apply the step voltage to the selected first conductor in the presence of a backflow current. The backflow current is generated due to the voltage drop across the threshold switching selector after the threshold switching selector is turned on.

[0098] In a further embodiment, the one or more control circuits are configured to begin applying the step voltage to the selected first conductor after the return current has dissipated. The return current is generated due to the voltage drop across the threshold switching selector after the threshold switching selector is turned on.

[0099] In a further embodiment, the programmable resistive memory element includes an MRAM element.

[0100] In a further embodiment, the threshold switching selector includes an omonic threshold switch (OTS).

[0101] In a further embodiment, the step voltage includes a step-up voltage pulse.

[0102] In a further embodiment, the step voltage includes the supply voltage and the step voltage includes a step down voltage pulse.

[0103] One embodiment includes a method for reading programmable resistive memory cells in a crosspoint memory array. The method includes applying a fixed-value read current to a selected first conductor in the crosspoint memory array when a selected second conductor is at a selection voltage. The fixed-value read current establishes a voltage on the selected memory cell between the selected first conductor and the selected second conductor that turns on a threshold switching selector of the selected memory cell. The method includes applying a step voltage pulse to the selected first conductor after the threshold switching selector is turned on and a backflow current is present. The method includes sensing the selected memory cell when the threshold switching selector is turned on and the fixed-value read current is driven through the selected memory cell.

[0104] One embodiment includes a memory system comprising a cross-point memory structure having a first conductive line, a second conductive line, and memory cells. Each memory cell is located at the intersection of the first and second conductive lines. Each memory cell has a programmable resistive memory element connected in series with a threshold switching selector. The memory system includes one or more control circuits communicating with the cross-point memory structure. The one or more control circuits are configured to apply a fixed-value read current to the selected first conductive line when the selected second conductive line is at a selection voltage. The fixed-value read current establishes a voltage on the selected memory cell that turns on the threshold switching selector of the selected memory cell. The one or more control circuits are configured to apply a step voltage pulse to the selected first conductive line after the threshold switching selector is turned on. The one or more control circuits are configured to sense the selected memory cell after the step voltage pulse is removed from the selected first conductive line and when driving the fixed-value read current through the selected memory cell.

[0105] For the purposes of this document, references to "an embodiment", "one embodiment", "some embodiments" or "another embodiment" in this specification may be used to describe different or the same embodiments.

[0106] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as a connection or coupling to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is referred to as a direct connection to another element, there is no intermediary element between the element and the other element. If two devices are directly or indirectly connected such that they can transmit electronic signals between them, the devices are "in communication".

[0107] For the purposes of this document, the term "based on" can be interpreted as "based at least in part on".

[0108] For the purposes of this document, without additional context, the use of numerical terms (such as “first” object, “second” object, and “third” object) may not imply the order of objects, but may be used instead for identification purposes to identify different objects.

[0109] The terms “top” and “bottom”, “upper” and “lower”, and “vertical” and “horizontal” and their forms used herein are for illustrative purposes only, and are not intended to limit the description of the technique, as the items referred to can be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially” and / or “about” mean that the specified dimensions or parameters may vary within acceptable tolerances for a given application.

[0110] The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or limited to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments have been selected to best explain the principles and practical application of the proposed technology, thereby enabling those skilled in the art to best utilize it in various embodiments and to contemplate various modifications suitable for that particular purpose. It is intended that this scope be defined by the appended claims. [Simplified Explanation of the Diagram]

[0011] Components with similar numbers refer to common components in different diagrams. [Figure 1] Depicts the timing of voltages used for forced reading of a memory cell having a programmable resistive memory element connected in series with a threshold switching selector. [Figure 2] A block diagram of an embodiment of a non-volatile memory system connected to a host computer. [Figure 3A] A block diagram of an embodiment of a memory die. [Figure 3B] A block diagram of an embodiment of an integrated memory assembly containing a control die and a memory structure die. [Figure 4A] An embodiment of a memory array forming a crosspoint architecture is depicted in perspective view. [Figure 4B] and [Figure 4C] respectively present a side view and a top view of the crosspoint structure in Figure 4A. [Figure 4D] An embodiment of a second-order memory array forming a crosspoint architecture is depicted in perspective view. [Figure 5] An embodiment of the structure of an MRAM memory cell is illustrated, for example, here the selected cell is driven by a current source for reading or writing. [Figure 6A] and [Figure 6B] illustrate embodiments of incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture. [Figure 7] depicts an embodiment of a memory array with a crosspoint architecture accessed using a forced current method. [Figure 8] is a diagram of an embodiment of a system for reading memory cells with a threshold switching selector. [Figure 9] is a flowchart of an embodiment of a procedure for reading programmable resistive memory cells in a crosspoint array. [Figures 10A], 10B, and 10C] depict the voltage and current timing during a current forced read using a step voltage applied when the threshold switching selector is turned on. [Figures 11A], 11B, and 11C] depict the voltage and current timing during a current forced read using a step voltage applied when a backflow current is present. [Figures 12A], 12B, and 12C] depict the voltage and current timing during one embodiment of forced current reading using a step voltage applied after a quick-return current dissipation. [Figures 13A], 13B, and 13C] depict the voltage and current timing during one embodiment of forced current reading using a step voltage applied to an on-limit switching selector, where the word line is at a lower voltage than the bit line. [Figures 14A], 14B, and 14C] depict the voltage and current timing during one embodiment of forced current reading using a step voltage applied after a quick-return current dissipation, where the word line is at a lower voltage than the bit line. [Figures 15A], 15B, and 15C] depict the voltage and current timing during one embodiment of forced current reading using a step voltage applied after a quick-return current dissipation, where the word line is at a lower voltage than the bit line.

Claims

1. A memory device comprising: one or more control circuits configured to communicate with a cross-point memory structure having a first conductive line, a second conductive line, and memory cells, each memory cell being located at a cross-point of the first conductive line and the second conductive line, each memory cell having a programmable resistive memory element connected in series with a threshold switching selector; the one or more control circuits being configured to: apply a fixed-value read current to a selected first conductive line when a selected second conductive line is at a selection voltage, the selected first conductive line being connected to a selected memory cell; apply a step voltage to the selected first conductive line when the threshold switching selector is turned on; and sense the selected memory cell after the step voltage is removed from the selected first conductive line and while driving the fixed-value read current through the selected memory cell.

2. The memory device of claim 1, wherein the one or more control circuits are configured to: begin applying the step voltage to the selected first conductor before the threshold switching selector is turned on; and continue applying the step voltage to the selected first conductor after the threshold switching selector has been turned on.

3. The memory device of claim 1, wherein the one or more control circuits are configured to: after the threshold switching selector of the selected memory cell is turned on by applying the fixed value read current to the selected first conductor, begin to apply the step voltage to the selected first conductor.

4. The memory device of claim 3, wherein the one or more control circuits are further configured to: apply a step voltage to the selected first conductor in the presence of a shunt current, the shunt current being generated by a voltage drop across the threshold switching selector after the threshold switching selector is turned on.

5. The memory device of claim 3, wherein the one or more control circuits are configured to: begin applying the step voltage to the selected first conductor after a return current has dissipated, the return current being generated by a voltage drop across the threshold switching selector after the threshold switching selector is turned on.

6. The memory device of claim 1, wherein the one or more control circuits are configured to: apply a step voltage to the selected first conductor in the presence of a shunt current, the shunt current being generated by a voltage drop across the threshold switching selector after the threshold switching selector is turned on.

7. The memory device of claim 1, wherein the one or more control circuits are further configured to: begin applying the step voltage to the selected first conductor after a return current has dissipated, the return current being generated by a voltage drop across the threshold switching selector after the threshold switching selector is turned on.

8. The memory device of claim 1, wherein the programmable resistive memory element includes an MRAM element.

9. The memory device of claim 1, wherein the threshold switching selector includes an omonic threshold switch (OTS).

10. The memory device of claim 1, wherein the step voltage includes a step-up voltage pulse.

11. The memory device of claim 1, wherein the step voltage includes a step down voltage pulse.

12. The memory device of claim 1, wherein the step voltage includes a supply voltage.

13. A method for reading a programmable resistive memory cell in a crosspoint memory array, the method comprising: applying a fixed-value read current to a selected first conductor in the crosspoint memory array when a selected second conductor is at a selection voltage, the fixed-value read current establishing a voltage of a threshold switching selector for conducting the selected memory cell between the selected first conductor and the selected second conductor; applying a step voltage pulse to the selected first conductor after the threshold switching selector is turned on and a ripple current is present; and sensing the selected memory cell when the threshold switching selector is turned on and the fixed-value read current is driven through the selected memory cell.

14. The method of claim 13, wherein applying the step voltage pulse to the selected first conductor includes applying a boost voltage pulse to the selected first conductor in response to a voltage drop on the selected memory cell.

15. The method of claim 13, wherein applying the step voltage pulse to the selected first conductor includes applying a buck voltage pulse to the selected first conductor in response to a voltage drop on the selected memory cell.

16. A memory system comprising: a crosspoint memory structure having a first conductive line, a second conductive line, and memory cells, each memory cell being located at a crosspoint of the first conductive line and the second conductive line, each memory cell having a programmable resistive memory element connected in series with a threshold switching selector; and one or more control circuits communicating with the crosspoint memory structure, the one or more control circuits being configured to: apply a fixed-value read current to a selected first conductive line when a selected second conductive line is at a selection voltage, the fixed-value read current establishing a voltage across the selected memory cell for the threshold switching selector to conduct the selected memory cell; apply a step voltage pulse to the selected first conductive line after the threshold switching selector is turned on; and sense the selected memory cell after the step voltage pulse is removed from the selected first conductive line and while driving the fixed-value read current through the selected memory cell.

17. The memory system of claim 16, wherein the one or more control circuits are configured to: apply a step voltage pulse to the selected first conductor in the presence of a ripple current, the ripple current being generated by a voltage drop across the threshold selector after the threshold selector is turned on.

18. The memory system of claim 16, wherein the one or more control circuits are configured to: apply a step voltage pulse to the selected first conductor after a return current has dissipated, the return current being generated by a voltage drop across the threshold selector after the threshold selector is turned on.

19. The memory system as described in request item 16, wherein: The selected voltage applied to the selected second conductor is grounded; and the one or more control circuits are configured to apply the step voltage pulse as a boost voltage pulse to the selected first conductor.

20. The memory system as described in request item 16, wherein: The selected voltage applied to the selected second conductor is a high voltage; and the one or more control circuits are configured to apply the step voltage pulse as a step voltage pulse to the selected first conductor.

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