Substrates, apparatus and methods for epitaxial growth of silicon wafers, and epitaxial silicon wafers.

Abstract

This invention provides a substrate, apparatus, and method for epitaxial growth of silicon wafers, and an epitaxial silicon wafer, belonging to the field of semiconductor manufacturing technology. The substrate for epitaxial growth of silicon wafers includes: a disk-shaped support portion for supporting the silicon wafer; and an annular periphery extending radially outward from the disk-shaped support portion, the annular periphery forming a plurality of spaced-apart trench regions uniformly distributed circumferentially along the annular periphery, the trench regions being fan-shaped, and each trench region having a plurality of arrayed pits.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a base, a device and a method for epitaxial growth of silicon slices, and an epitaxial silicon wafer. Prior Art

[0002] Growing a single crystal thin film on a single crystal polished wafer is called an epitaxial silicon wafer. Compared with polished wafers, epitaxial silicon wafers have fewer surface defects, excellent crystallinity and controllable resistivity, and are widely used in the manufacturing process of highly integrated integrated circuit (IC) components and metal-oxide-semiconductor field-effect transistors (MOS). Generally, epitaxial growth of wafers is carried out by chemical vapor deposition. First, the wafer is transferred to the base of the reaction chamber that supports the wafer, and then the reaction chamber is heated. After reaching the preset temperature, a clean gas (such as hydrogen) is introduced to remove the natural oxide on the surface of the wafer, and then a silicon source gas is introduced to continuously and evenly grow an epitaxial layer on the front of the wafer.

[0003] The preparation of wafer epitaxial layer is mainly divided into two stages. In the first stage, the reaction chamber is self-cleaned, and hydrogen (H 2) and etching gas (HCl) are introduced; in the second stage, the epitaxial layer is grown, and hydrogen (H 2), silicon source gas (SiHCl 3 / H 2) and doping gas (B 2H 6 / H 2) are introduced. In the first stage, hydrogen is used as the main gas flow to carry the etching gas (HCl) to react with the by-products deposited in the reaction chamber to clean the reaction chamber; in the second stage, hydrogen reacts with the natural oxide layer on the surface of the wafer to obtain a clean epitaxial substrate. In the deposition stage, hydrogen is used as the main gas flow to carry the film-forming gas and doping gas to grow an epitaxial layer with controllable resistivity on the surface of the wafer.

[0004] With the continuous development of semiconductor process technology, the flatness requirements for epitaxial silicon wafers are becoming more and more stringent. Epitaxial silicon wafers with poor flatness may cause defocus, and may even affect the chemical mechanical polishing (CMP) process, affecting product yield. When the local flatness of the epitaxial silicon wafer is poor, over-polishing or under-polishing may occur; over-polishing may cause early breakdown of the component, and under-polishing may cause errors in component contact. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a base, a device and a method for epitaxial growth of silicon slices, and an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer.

[0006] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present invention is: A base for epitaxial growth of silicon wafers, comprising: A disc-shaped supporting portion for supporting the silicon wafer; An annular rim radially extending from the disc-shaped bearing portion toward the epitaxial crystal is formed with a plurality of groove areas arranged at intervals. The groove areas are evenly distributed along the circumference of the annular rim, and the groove areas are fan-shaped. Each of the groove areas is provided with a plurality of array-arranged pits.

[0007] In some embodiments, the central angle of the sector in which the groove area is located is 40-60°.

[0008] In some embodiments, four groove areas are evenly distributed along the circumference of the annular rim.

[0009] In some embodiments, the depth of the pit is 0.1 mm-1 mm; and / or The area of the pit is 0.1 square millimeter to 0.4 square millimeter.

[0010] The embodiment of the present invention also provides a device for epitaxial growth of silicon wafers, comprising: A base as described above; A reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; a gas inlet for delivering a silicon source gas into the upper reaction chamber to grow an epitaxial layer on the silicon wafer; An exhaust port for discharging the reaction tail gas generated by epitaxial growth out of the reaction chamber.

[0011] The embodiment of the present invention further provides a method for epitaxial growth of a silicon wafer. The method for epitaxial growth of a silicon wafer is applied to the apparatus for epitaxial growth of a silicon wafer as described above. The method for epitaxial growth of a silicon wafer comprises: The silicon wafer is placed on the base so that the silicon wafer <100> The crystal direction is aligned with the central axis of the groove region of the annular periphery; Delivering a silicon source gas into the upper reaction chamber through the gas inlet to grow an epitaxial layer on the silicon wafer; The flow rate of the silicon source gas flowing through the groove area is greater than the flow rate of the silicon source gas flowing through other areas of the annular periphery, so that the thickness of the epitaxial layer grown on the silicon wafer is uniform; The reaction tail gas generated by the epitaxial growth is discharged from the reaction chamber through the exhaust port.

[0012] In some embodiments, the silicon chip is placed on the base so that the silicon chip <100> The crystal orientation is aligned with the central axis of the groove region of the annular periphery including: Obtaining the crystal direction corresponding to the V-groove of the silicon wafer; If the V-groove is <110> The silicon wafer is placed on the base in the crystal direction so that the angle between the central axis of the V-shaped groove and the central axis of the groove area is 45°.

[0013] In some embodiments, the silicon chip is placed on the base so that the silicon chip <100> The crystal orientation is aligned with the central axis of the groove region of the annular periphery including: Obtaining the crystal direction corresponding to the V-groove of the silicon wafer; If the V-groove is <100> The silicon wafer is placed on the base in the crystal direction so that the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°.

[0014] The embodiment of the present invention further provides an epitaxial silicon wafer, which is manufactured by using the above-mentioned method for epitaxial growth of silicon wafers. When the thickness of the epitaxial layer of the epitaxial silicon wafer is not greater than 6 micrometers, the maximum value of the front reference least square range ESFQR value of the edge portion of the epitaxial silicon wafer is not greater than 57.1 nanometers.

[0015] In some embodiments, when the thickness of the epitaxial layer of the epitaxial silicon wafer is 3-4 microns, the ESFQR value of the epitaxial silicon wafer ranges from 23 to 33.9 nanometers; when the thickness of the epitaxial layer of the epitaxial silicon wafer is 4-6 microns, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 to 57.1 nanometers.

[0016] The beneficial effects of the present invention are: In this embodiment, a groove area is formed on the annular periphery, and a plurality of pits are arranged in the groove area. When epitaxial growth is performed and silicon source gas is introduced into the reaction chamber, due to the arrangement of the pits, the flow rate of the silicon source gas flowing through the groove area can be greater than the flow rate of the silicon source gas flowing through other areas of the annular periphery; the growth rates of different crystal directions of the silicon wafer are different. When epitaxial growth is performed, the silicon wafer can be rotated at different angles according to the crystal direction corresponding to the V-groove of the silicon wafer, so that the crystal direction of the silicon wafer matches the position of the groove area, and the crystal direction with a slower growth rate of the epitaxial layer is aligned with the groove area, so as to increase the growth rate of the epitaxial layer in this crystal direction. In this way, the growth rates of the epitaxial layer in different crystal directions of the silicon wafer can be compensated, and the flatness of the epitaxial silicon wafer can be improved. Simple diagram description

[0017] Figure 1 shows a schematic diagram of the epitaxial reaction chamber gas flow; Figure 2 shows a schematic diagram of the direction of the silicon wafer crystal; Figure 3 shows a schematic diagram of the direction of the silicon wafer crystal; Figure 4 shows a schematic diagram of the edge flatness of an epitaxial silicon wafer prepared by the related art; Figure 5 shows a schematic diagram of the process of preparing epitaxial silicon wafers according to the related art; Figure 6 shows a schematic diagram of a base for epitaxial growth of a silicon wafer in the related art; Figure 7 shows a schematic diagram of a pedestal for epitaxial growth of a silicon wafer according to an embodiment of the present invention; Figure 8 shows a schematic diagram of a pedestal for epitaxial growth of a silicon wafer according to an embodiment of the present invention; Figure 9 shows a schematic diagram of the process of preparing epitaxial silicon wafers according to an embodiment of the present invention; FIG. 10 shows an embodiment of the present invention where a V-shaped groove is formed in <100> Schematic diagram of the crystal orientation of the silicon wafer placed on the base; FIG. 11 shows an embodiment of the present invention where a V-shaped groove is formed in <110> Schematic diagram of the crystal orientation of the silicon wafer placed on the base; FIG. 12 shows an embodiment of the present invention where a V-shaped groove is formed in <110> Schematic diagram of the crystal orientation of the silicon wafer placed on the base; FIG. 13 is a schematic diagram showing the edge flatness of an epitaxial silicon wafer prepared according to an embodiment of the present invention. Implementation

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by those with ordinary knowledge in the technical field belong to the scope of protection of the present invention.

[0019] The flatness of epitaxial silicon wafers usually includes flatness indicators such as edge site frontsurface referenced least sQuares / Range (ESFQR), site frontsurface referenced least sQuares / Range (SFQR), and global backsurface-referenced ideal plane / Range (GBIR). Among them, ESFQR is used to measure the edge flatness of epitaxial silicon wafers.

[0020] FIG1 is a schematic diagram of the gas flow in the epitaxial reaction chamber, wherein the arrow indicates the gas flow direction. After the silicon wafer is transferred to the susceptor 2 that carries the silicon wafer in the epitaxial reaction chamber, the susceptor 2 carries the silicon wafer and rotates at a certain speed. After the reaction chamber is heated to a preset temperature, a clean gas (H2) is introduced to pass through the preheating ring 1 and the edge of the susceptor 2 to reach the surface of the silicon wafer to remove the natural oxide on the surface of the silicon wafer. Then, the main gas flow carries the film-forming gas and the doping gas through the preheating ring 1 and the edge of the susceptor 2 to reach the surface of the silicon wafer to grow an epitaxial layer with controllable resistivity.

[0021] Figures 2 and 3 are schematic diagrams showing the crystal orientation of a silicon wafer. As shown in Figure 2, if the three o'clock direction of the silicon wafer is the radial direction of 0° / 360° and <110> If the crystal direction is 0° / 360°, the radial directions of 90°, 180° and 270° clockwise relative to the radial direction of 0° / 360° are also the radial directions of the silicon wafer. <110> The radial directions of 45°, 135°, 225° and 315°, which are rotated clockwise relative to the radial direction of 0° / 360°, are the radial directions of the silicon wafer. <100> That is to say, for this silicon wafer, the four <110> The crystal directions correspond to the four radial directions distributed at 90° intervals along the circumference of the silicon wafer. <100> The crystal directions also correspond to the four radial directions distributed at 90° intervals along the circumference of the silicon wafer, and the adjacent <110> Crystal orientation and <100> The crystal direction is spaced 45° along the circumference of the silicon wafer. As shown in FIG3 , in order to position the silicon wafer, a V-shaped groove 4 is provided on the silicon wafer 3. The V-shaped groove 4 can correspond to the <100> The crystal direction can also correspond to the silicon wafer <110> Crystal orientation.

[0022] FIG4 is a schematic diagram showing the edge flatness of an epitaxial silicon wafer prepared by the related art. FIG4 shows the ESFQR result of a silicon wafer with a diameter of 300 mm at a position 1 mm away from the radial edge when a conventional base for epitaxial growth of silicon wafers is used. In FIG4, the horizontal axis represents the angle of the silicon wafer in the radial direction, and the vertical axis represents the ESFQR value of the silicon wafer at the corresponding angle position (in nanometers). As shown in FIG4, the radial directions of 0° / 360°, 90°, 180° and 270° correspond to the ESFQR value of the silicon wafer. <100> Crystal direction area, 45°, 135°, 225° and 315° radial directions correspond to the silicon wafer <110> In the crystal direction area, it can be seen that the edge flatness at the radial directions of 0° / 360°, 90°, 180° and 270° is good, while the edge flatness at the radial directions of 45°, 135°, 225° and 315° is poor. <100> Crystal orientation and <110> The edge flatness quality in the crystal direction fluctuates greatly. This is because the physical properties of single-crystal silicon wafers in different crystal directions are different, and the growth rate of the epitaxial layer in different crystal directions of the silicon wafer is different. <110> The growth rate of the epitaxial layer in the crystal direction is greater than that of the silicon wafer <100> Epitaxial layer growth rate in the crystal direction.

[0023] In order to solve the above problems, the present invention provides a base, a device and a method for epitaxial growth of silicon slices, and an epitaxial silicon wafer, which can improve the flatness of the epitaxial silicon wafer.

[0024] An embodiment of the present invention provides a base for epitaxial growth of silicon wafers, comprising: a disc-shaped bearing portion for carrying said silicon wafer; From the annular periphery of the disc-shaped bearing part extending radially toward the epitaxy, the annular periphery forms a grooved region with multiple intervals arranged along the circumferential direction of the annular periphery.

[0025] In this embodiment, at the annular periphery forming a groove region, the groove area is provided with multiple pits, when performing epitaxial growth, the silicon source gas is passed into the reaction chamber, due to the setting of the pits, the flow rate of silicon source gas flowing through the groove region is greater than the flow rate of silicon source gas flowing through other areas of the annular periphery; By rotating the silicon wafer at different angles according to the corresponding crystal direction of the V-slot of the silicon wafer, so that the crystal direction of the silicon wafer matches the position of the groove region, the crystal direction with a slower growth rate of the epitaxial layer is aligned with the groove area.

[0026] Figure 5 shows the flow schematic diagram of the preparation of epitaxial silicon wafers by the related technology, and Figure 6 shows the schematic diagram of the base used for the epitaxial growth of the silicon wafer in the related technology, as shown in Figure 6. The base 2 in the related technology includes for bearing The disc-shaped bearing portion 21 of the silicon wafer and the annular perimeter 22 extending radially from the disc-shaped bearing portion 21 toward the epitaxy is shown in Fig. 5. In the preparation of the epitaxial silicon wafer, the single-crystal silicon rod is first prepared and cut segment, according to product demand, V-shaped slots are processed in the specific crystal direction of the segment, then the segment is sliced, ground, polished, cleaned and measured to obtain substrate silicon wafers. The substrate silicon wafers are judged qualified (OK).

[0027] FIG7 and FIG8 are schematic diagrams of a base for epitaxial growth of silicon wafers according to an embodiment of the present invention, wherein the base 5 comprises a disc-shaped bearing portion 51 and an annular periphery 52 extending radially from the disc-shaped bearing portion 51 toward the epitaxial growth. As shown in FIG7 , compared with the base shown in FIG6 , the embodiment of the present invention adds a groove area 6 on the annular periphery 52 of the base 5, and the annular periphery 52 is formed with a plurality of groove areas 6 arranged at intervals, and the groove areas 6 are evenly distributed along the circumference of the annular periphery 52, and the groove areas 6 are fan-shaped, that is, the groove areas 6 are axially symmetrical, and the central axis of the groove areas 6 is in the radial direction of the base 5; each of the groove areas 6 is provided with a plurality of array-arranged pits 61, and the pits 61 are recessed downward compared to other areas of the annular periphery 52, and when epitaxial growth is performed, the amount of gas flowing through the groove area 6 to the surface of the silicon wafer can be increased by the provision of the pits 61, thereby increasing the epitaxial layer growth rate of the silicon wafer area corresponding to the groove area 6.

[0028] In this embodiment, when epitaxial growth is performed, the silicon wafer may be <100> The crystal direction is aligned with the groove area 6 of the base, that is, the silicon wafer <100> The crystal direction is in the direction of the central axis of the groove region 6, so that during epitaxial growth, the silicon wafer can be <100> The growth rate of the epitaxial layer in the crystal direction area is increased, reducing the silicon wafer <110> The growth rate of the epitaxial layer in the crystal direction is related to <100> The difference between the growth rates of the epitaxial layer in the crystal direction can improve the epitaxial silicon wafer <110> Edge flatness in the crystal direction.

[0029] The technical solution of this embodiment is not limited to silicon wafers. <100> The crystal direction must be in the direction of the central axis of the groove area 6. <100> The angle between the crystal direction and the central axis of the groove region 6 is no greater than 20°, that is, the angle between the crystal direction and the central axis of the groove region 6 is no greater than 20°. <100> The angle between the crystal direction and the direction of the central axis of the groove region 6 can be 0°, 5°, 10°, 15° or 20°. <110> The growth rate of the epitaxial layer in the crystal direction is relatively large. In order to reduce the silicon wafer <110> The growth rate of the epitaxial layer in the crystal direction is related to <100> The difference between the growth rate of the epitaxial layer in the crystal direction, preferably, the annular edge 52 and the silicon wafer <110> The groove region 6 is not arranged in the radial direction corresponding to the crystal direction.

[0030] In some embodiments, as shown in FIG. 7 , D1, D2, D3 or D4 is at a 45° direction of the base, and the gas injection port direction, exhaust port direction, silicon wafer inlet and outlet direction or auxiliary gas main inlet direction of the epitaxial reaction chamber is at a 0° direction of the base. Four groove areas 6 can be evenly arranged in the circumference of the annular periphery 52, corresponding to the gas injection port direction, exhaust port direction, silicon wafer inlet and outlet direction and auxiliary gas main inlet direction of the epitaxial reaction chamber. As shown in FIG. 2 and FIG. 3 , the silicon wafer includes four <100> Crystal direction, so that when the silicon wafer is placed on the base 5 of this embodiment for epitaxial growth, each silicon wafer can be <100> Each crystal direction corresponds to a groove area 6, improving each <100> The growth rate of the epitaxial layer in the crystal direction can effectively improve the epitaxial silicon wafer <110> Edge flatness in the crystal direction.

[0031] In some embodiments, as shown in FIG. 8 , the central angle a corresponding to the sector of the groove region 6 may be 40-60°, for example, 40°, 45°, 50°, 55° or 60°. <100> After the crystal direction is aligned with the central axis of the groove area 6 of the base, the silicon wafer can be effectively improved. <100> The edge flatness of the crystal direction and nearby areas.

[0032] In this embodiment, the pits 61 can be arranged along the radial direction of the base 5, and the depth of the pits 61 can be 0.1 mm-1 mm, for example, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm or 1 mm. When the depth of the pits 61 adopts the above dimensions, the amount of silicon source gas flowing through the groove area 6 to reach the surface of the silicon wafer during epitaxial growth can be effectively increased.

[0033] The area of the pit 61 can be 0.1 square millimeter-0.4 square millimeter, for example, it can be 0.1 square millimeter, 0.2 square millimeter, 0.3 square millimeter or 0.4 square millimeter. When the area of the pit 61 adopts the above size, the amount of silicon source gas flowing through the groove area 6 to reach the surface of the silicon wafer during epitaxial growth can be effectively increased.

[0034] In this embodiment, the shape of the orthographic projection of the pit 61 on the horizontal plane can be a regular shape such as a rectangle, a circle, a parallelogram, etc., or an irregular shape.

[0035] In some embodiments, the distribution density of the pits gradually decreases along the direction from the middle of the groove area to the edge of the groove area, so that when epitaxial growth is performed, the silicon wafer is placed <100> After the crystal direction is aligned with the central axis of the groove area 6 of the base, the silicon wafer can be moved from <100> Crystal direction to <110> The degree of decrease in the growth rate in the crystal direction gradually decreases, so that the growth rate in the entire circumferential direction of the silicon wafer is more balanced, and the thickness of the epitaxial layer grown on the silicon wafer is more uniform, thereby obtaining an epitaxial silicon wafer with better flatness.

[0036] The embodiment of the present invention also provides a device for epitaxial growth of silicon wafers, comprising: A base as described above; A reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; a gas inlet for delivering a silicon source gas into the upper reaction chamber to grow an epitaxial layer on the silicon wafer; An exhaust port for discharging the reaction tail gas generated by epitaxial growth out of the reaction chamber.

[0037] In addition, like the device for epitaxial growth of silicon wafers in the related art, the device can also include: a base support frame, an upper quartz bell jar and a lower quartz bell jar that together enclose a reaction chamber, a plurality of heating bulbs, mounting components, etc., and there is also a small gap between the radial edge of the base and adjacent components so that the base can be driven by the base support frame to rotate around its own central axis at a certain speed, which will not be repeated here.

[0038] The embodiment of the present invention further provides a method for epitaxial growth of a silicon wafer, the method for epitaxial growth of a silicon wafer is applied to the above-mentioned device for epitaxial growth of a silicon wafer, and the method for epitaxial growth of a silicon wafer comprises: The silicon wafer is placed on the base so that the silicon wafer <100> The crystal direction is aligned with the central axis of the groove region of the annular periphery; Delivering a silicon source gas into the upper reaction chamber through the gas inlet to grow an epitaxial layer on the silicon wafer; The flow rate of the silicon source gas flowing through the groove area is greater than the flow rate of the silicon source gas flowing through other areas of the annular periphery, so that the thickness of the epitaxial layer grown on the silicon wafer is uniform; The reaction tail gas generated by the epitaxial growth is discharged from the reaction chamber through the exhaust port.

[0039] In this embodiment, when performing epitaxial growth, the silicon wafer can be rotated at different angles according to the corresponding crystal direction of the V-slot of the silicon wafer, so that the crystal direction of the silicon wafer matches the position of the groove region, aligning the crystal direction with a slower epitaxial layer growth rate to the groove region, improving the growth rate of the epitaxial layer in the direction of that crystal.

[0040] Figure 9 shows a schematic flow of the preparation of epitaxial silicon wafers in an embodiment of the present invention. The substrate silicon wafers are graded and sorted.

[0041] 9, the method of preparing epitaxial silicon wafer in an embodiment of the present invention further includes: Step 101, Set the substrate silicon wafer sorting rules according to the V-slot orientation; The V-shaped slot of the silicon wafer is used to determine the crystallization direction of the silicon wafer. According to different product requirements, the V-shaped slot of some silicon wafers is in <110> In the crystal direction, some silicon wafers have V-slots <100> The crystal orientation, in this embodiment, it is necessary to obtain the crystal orientation corresponding to the V-slot of the silicon wafer.

[0042] Step 102: Qualified substrate silicon wafers with different V-slot orientations rotate at different angles when sorting to the corresponding carriers; In related techniques, when placing the silicon wafer on the base, the V-slot of the silicon wafer is generally aligned with the 0° direction of the base, that is, the gas injection port direction, exhaust port direction, silicon wafer inlet and outlet direction or auxiliary gas main inlet direction of the epitaxial reaction chamber.

[0043] Step 103: Slot the V in the <110> crystal-oriented substrate silicon wafers rotated 45°; If the V-groove is <110> In the crystal direction, before entering the epitaxial reaction chamber, the V-shaped groove is <110> The substrate silicon wafer is rotated 45° in the crystal direction so that after the silicon wafer is placed on the base, the angle between the central axis of the V-shaped groove and the central axis of the groove area is 45°. <100> The crystal direction is aligned with the groove area 6 of the base, that is, the silicon wafer <100> The crystal direction is in the direction of the central axis of the groove region 6, and during epitaxial growth, the silicon wafer can be <100> The epitaxial layer growth rate in the crystal direction area is increased, reducing the silicon wafer <110> The growth rate of the epitaxial layer in the crystal direction is related to <100> The difference between the growth rates of the epitaxial layer in the crystal direction improves the epitaxial silicon wafer <110> Edge flatness at the crystal direction position.

[0044] Step 104: Place the V-groove on <100> The substrate wafer is rotated 0° in the crystal direction.

[0045] If the V-groove is <100> In the crystal direction, before entering the epitaxial reaction chamber, the V-shaped groove is <100> The substrate silicon wafer in the crystal direction is rotated 0°, that is, it does not rotate, so that the silicon wafer is placed on the base, and the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°. <100> The crystal direction is aligned with the groove area 6 of the base, that is, the silicon wafer <100> The crystal direction is in the direction of the central axis of the groove region 6, and during epitaxial growth, the silicon wafer can be <100> The epitaxial layer growth rate in the crystal direction area is increased, reducing the silicon wafer <110> The growth rate of the epitaxial layer in the crystal direction is related to <100> The difference between the growth rates of the epitaxial layer in the crystal direction improves the epitaxial silicon wafer <110> Edge flatness at the crystal direction position.

[0046] FIG. 10 shows an embodiment of the present invention where a V-shaped groove is formed in <100> Schematic diagram of a silicon wafer 3 placed on a base in the crystal direction; as shown in FIG2, the V-shaped groove 4 of the silicon wafer is <100> The crystal direction, then the area where the silicon wafer is 45° and 135° away from the V-groove 4 is the silicon wafer <110> The crystal direction, the area where the silicon wafer is 90° and 180° apart from the V-groove 4 is the silicon wafer <100> Crystal orientation.

[0047] As shown in FIG7 , there is a groove region 6 at the edge of the pedestal at 0°. Compared with the pedestal at 45°, the gas flow rate of the groove region 6 at 0° increases during epitaxial growth. The increase in gas flow rate accelerates the growth rate of the epitaxial layer. Therefore, in order to ensure that the growth rates of different regions of the silicon wafer are the same during epitaxial growth, it is necessary to make the silicon wafer <100> The crystal direction matches the 0° direction of the base (the direction of the groove area of the base), making the silicon wafer <110> The crystal direction matches the 45° direction of the base, so that when epitaxial growth is carried out, the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction increases, making the epitaxial layer on the silicon wafer <100> Crystal orientation and <110> The thickness is the same in all crystal directions.

[0048] As shown in FIG10 , since the direction of the base is fixed when the epitaxial reaction chamber is installed, the 0° direction of the groove area 6 on the edge of the base is the gas injection port direction, exhaust port direction, silicon wafer inlet and outlet direction or auxiliary gas main inlet direction of the epitaxial reaction chamber, and the V-shaped groove is fixed at the bottom of the base. <100> The crystal direction of the silicon wafer is rotated 0°, that is, it does not rotate, so that the silicon wafer <100> The crystal direction matches the 0° direction of the base (the direction corresponding to the groove area of the base, the gas flow on the silicon wafer surface increases), making the silicon wafer <110> The crystal direction matches the 45° direction of the base, compensating for the difference in growth rate of the epitaxial layer caused by different crystal directions of the silicon wafer and improving the edge flatness of the silicon epitaxial wafer.

[0049] 11 and 12 show an embodiment of the present invention where a V-shaped groove is formed in <110> Schematic diagram of a silicon wafer placed on a base in the crystal direction. As shown in FIG11 , the V-shaped groove 4 of the silicon wafer 3 is formed on the silicon wafer. <110> The crystal direction, then the area where the silicon wafer is 45° and 135° away from the V-groove 4 is the silicon wafer <100> The crystal direction, the area where the silicon wafer is 90° and 180° apart from the V-groove 4 is the silicon wafer <110> Crystal orientation.

[0050] As shown in FIG7 , there is a groove region 6 at the edge of the pedestal at 0°. Compared with the pedestal at 45°, the gas flow rate of the groove region 6 at 0° increases during epitaxial growth. The increase in gas flow rate accelerates the growth rate of the epitaxial layer. Therefore, in order to ensure that the growth rates of different regions of the silicon wafer are the same during epitaxial growth, it is necessary to make the silicon wafer <100> The crystal direction matches the 0° direction of the base (the direction of the groove area of the base), making the silicon wafer <110> The crystal direction matches the 45° direction of the base, so that when epitaxial growth is carried out, the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction increases, making the epitaxial layer on the silicon wafer <100> Crystal orientation and <110> The thickness is the same in all crystal directions.

[0051] As shown in FIG12, since the direction of the base is fixed when the epitaxial reaction chamber is installed, the 0° direction of the groove area 6 on the edge of the base is the gas injection port direction, exhaust port direction, silicon wafer inlet and outlet direction or auxiliary gas main inlet direction of the epitaxial reaction chamber. <110> The crystal direction of the silicon wafer is rotated 45°, so that the silicon wafer <100> The crystal direction matches the 0° direction of the base (the direction corresponding to the groove area of the base, the gas flow on the silicon wafer surface increases), making the silicon wafer <110> The crystal direction matches the 45° direction of the base, compensating for the difference in growth rate of the epitaxial layer caused by different crystal directions of the silicon wafer and improving the edge flatness of the silicon epitaxial wafer.

[0052] The embodiment of the present invention further provides an epitaxial silicon wafer, which is manufactured by using the above-mentioned method for epitaxial growth of silicon wafers. When the thickness of the epitaxial layer of the epitaxial silicon wafer is not greater than 6 micrometers, the maximum value of the front reference least square range ESFQR value of the edge portion of the epitaxial silicon wafer is not greater than 57.1 nanometers.

[0053] FIG13 is a schematic diagram showing the edge flatness of an epitaxial silicon wafer prepared according to an embodiment of the present invention. In FIG13 , the horizontal axis represents the angle of the silicon wafer in the radial direction, and the vertical axis represents the ESFQR value (in nanometers) of the silicon wafer at the corresponding angle position. It can be seen that the phenomenon of periodic fluctuation of the flatness of the edge of the epitaxial silicon wafer at an interval of 45° is improved, the quality of the flatness of the edge of the epitaxial silicon wafer is improved, and the ESFQR value of the epitaxial silicon wafer can be reduced by 14 nanometers, which effectively improves the quality and yield of the epitaxial silicon wafer.

[0054] In some embodiments, the ESFQR value of the epitaxial silicon wafer is inversely proportional to the depth of the pit and inversely proportional to the area of the pit. When other parameters of the base remain unchanged, the depth of the pit increases, the amount of gas participating in the film-forming reaction in the groove area during the epitaxial growth process increases, the compensation effect of the difference in the growth rate of the epitaxial layer in different crystal directions of the silicon wafer is better, the ESFQR value is smaller, and the improvement effect of the edge flatness quality of the prepared epitaxial silicon wafer is more significant. When other parameters of the base remain unchanged, the area of the pit increases, the amount of gas participating in the film-forming reaction in the groove area during the epitaxial growth process increases, the compensation effect of the difference in the growth rate of the epitaxial layer in different crystal directions of the silicon wafer is better, the ESFQR value is smaller, and the improvement effect of the edge flatness quality of the prepared epitaxial silicon wafer is more significant.

[0055] In some embodiments, when the thickness of the epitaxial layer of the epitaxial silicon wafer is 3-4 microns, the ESFQR value of the epitaxial silicon wafer ranges from 23 to 33.9 nanometers; when the thickness of the epitaxial layer of the epitaxial silicon wafer is 4-6 microns, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 to 57.1 nanometers.

[0056] In specific embodiment 1, a V-shaped groove is selected. <100> For a silicon wafer in the crystal direction, the central angle of the sector where the groove area of the base is located is 40°-50°, for example, it can be 45°; the depth of the pit is 0.1 mm-1 mm, for example, it can be 0.48-0.52 mm, and further, it can be 0.5 mm; the area of the pit is 0.1 square millimeter-0.4 square millimeter, for example, it can be 0.18-0.22 square millimeter, and further, it can be 0.2 square millimeter; the silicon wafer is placed on the base, and the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°, so that the silicon wafer <100> The crystal direction is aligned with the groove area of the base for epitaxial growth. During the epitaxial growth process, the flow rate of the carrier gas hydrogen H2 is 80000sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6000sccm, the film-forming reaction temperature is 1100℃, and the epitaxial layer with a thickness of 3.3-3.5 microns is grown. For example, when the thickness of the epitaxial layer is 3.5 microns, the ESFQR value of the obtained epitaxial silicon wafer is 29.3±4.6 nanometers. Compared with conventional technology, the ESFQR value of the epitaxial silicon wafer can be reduced by 8.6 nanometers, thereby improving the quality of the epitaxial silicon wafer. This is because the pits set in the groove area increase the process gas flow in the groove area, making the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction is accelerated, compensating for the epitaxial layer growth process. <110> Crystal orientation and <100> Differences in growth rates along crystal directions.

[0057] In specific embodiment 2, V-shaped grooves are selected. <100> For a silicon wafer in the crystal direction, the central angle of the sector where the groove area of the base is located is 40°-50°, for example, 45°; the depth of the pit is 0.78-0.82 mm, for example, 0.8 mm; the area of the pit is 0.38-0.42 square millimeters, for example, 0.4 square millimeters; the silicon wafer is placed on the base, and the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°, so that the silicon wafer <100> The crystal direction is aligned with the groove area of the base for epitaxial growth. During the epitaxial growth process, the flow rate of the carrier gas hydrogen H2 is 80000sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6000sccm, the film-forming reaction temperature is 1100℃, and the epitaxial layer with a thickness of 3.3-3.5 microns is grown. For example, when the thickness of the epitaxial layer is 3.5 microns, the ESFQR value of the obtained epitaxial silicon wafer is 26.8±3.8 nanometers. Compared with conventional technology, the ESFQR value of the epitaxial silicon wafer can be reduced by 11.1 nanometers, thereby improving the quality of the epitaxial silicon wafer. This is because the pits set in the groove area increase the process gas flow in the groove area, making the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction is accelerated, compensating for the epitaxial layer growth process. <110> Crystal orientation and <100> In addition, compared with the specific embodiment 1, the depth and area of the pits in the groove area are increased, and the amount of gas participating in the film forming reaction in the groove area during the epitaxial growth process is increased, the compensation effect of the difference in the growth rate of the epitaxial layer in different crystal directions of the silicon wafer is better, the ESFQR value is smaller, and the edge flatness quality improvement effect of the prepared epitaxial silicon wafer is more significant.

[0058] In specific embodiment 3, V-shaped grooves are selected. <100> For a silicon wafer in the crystal direction, the central angle of the sector where the groove area of the base is located is 40°-50°, for example, it can be 45°; the depth of the pit is 0.1 mm-1 mm, for example, it can be 0.48-0.52 mm, and further, it can be 0.5 mm; the area of the pit is 0.1 square millimeter-0.4 square millimeter, for example, it can be 0.18-0.22 square millimeter, and further, it can be 0.2 square millimeter; the silicon wafer is placed on the base, and the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°, so that the silicon wafer <100> The crystal direction is aligned with the groove area of the base for epitaxial growth. During the epitaxial growth process, the flow rate of the carrier gas hydrogen H2 is 80000sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6000sccm, the film-forming reaction temperature is 1100℃, and the epitaxial layer with a thickness of 4.8-5 microns is grown. For example, the epitaxial layer with a thickness of 5 microns is grown, and the ESFQR value of the obtained epitaxial silicon wafer is 48.4±8.7 nanometers. Compared with conventional technology, the ESFQR value of the epitaxial silicon wafer can be reduced, thereby improving the quality of the epitaxial silicon wafer. This is because the pits set in the groove area increase the process gas flow in the groove area, making the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction is accelerated, compensating for the epitaxial layer growth process. <110> Crystal orientation and <100> Differences in growth rates along crystal directions.

[0059] In specific embodiment 4, V-shaped grooves are selected. <100> For a silicon wafer in the crystal direction, the central angle of the sector where the groove area of the base is located is 40°-50°, for example, 45°; the depth of the pit is 0.78-0.82 mm, for example, 0.8 mm; the area of the pit is 0.38-0.42 square millimeters, for example, 0.4 square millimeters; the silicon wafer is placed on the base, and the angle between the central axis of the V-shaped groove and the central axis of the groove area is 0°, so that the silicon wafer <100> The crystal direction is aligned with the groove area of the base for epitaxial growth. During the epitaxial growth process, the flow rate of the carrier gas hydrogen H2 is 80000sccm, the flow rate of the film-forming gas SiHCl3 / H2 is 6000sccm, the film-forming reaction temperature is 1100℃, and the epitaxial layer with a thickness of 4.8-5 microns is grown. For example, the thickness of the epitaxial layer is 5 microns, and the ESFQR value of the obtained epitaxial silicon wafer is 43.8±6.4 nanometers. Compared with conventional technology, the ESFQR value of the epitaxial silicon wafer can be reduced, thereby improving the quality of the epitaxial silicon wafer. This is because the pits set in the groove area increase the process gas flow in the groove area, making the silicon wafer <100> The growth rate of the epitaxial layer in the crystal direction is accelerated, compensating for the epitaxial layer growth process. <110> Crystal orientation and <100> In addition, compared with the specific embodiment 3, the depth and area of the pits in the groove area are increased, and the amount of gas participating in the film forming reaction in the groove area during the epitaxial growth process is increased, the compensation effect of the difference in the growth rate of the epitaxial layer in different crystal directions of the silicon wafer is better, the ESFQR value is smaller, and the edge flatness quality improvement effect of the prepared epitaxial silicon wafer is more significant.

[0060] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.

[0061] Unless otherwise defined, the technical or scientific terms used in the present invention shall be the common terms used by those with ordinary knowledge in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. The words "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, the element can be “directly on” or “under” the other element or intervening elements may be present.

[0063] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0064] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technical field with ordinary knowledge can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the patent application.

[0065] 1: Preheating ring 2: Base 21: Disc-shaped bearing part 22: Annular rim 3: Silicon wafer 4: V-groove 5: Base 51: Disc-shaped bearing part 52: Annular rim 6: Groove area 61: pit 101~104: Steps

Claims

1. A substrate for epitaxial growth of silicon wafers, comprising: A disc-shaped support portion for supporting the silicon wafer; an annular periphery extending radially outward from the disc-shaped support portion, the annular periphery forming a plurality of spaced-apart groove regions, the groove regions being uniformly distributed circumferentially along the annular periphery, the groove regions being fan-shaped, each groove region having a plurality of arrayed pits; wherein, the silicon wafer is placed on the base such that the <100> crystal direction of the silicon wafer is aligned with the central axis of the groove region of the annular periphery; no groove region is provided in the radial direction of the annular periphery corresponding to the <110> crystal direction of the silicon wafer; the distribution density of the pits gradually decreases along the direction from the middle of the groove region to the edge of the groove region.

2. The substrate for epitaxial growth of silicon wafers as described in claim 1, wherein, The central angle of the sector containing the trench area is 40-60°.

3. The substrate for epitaxial growth of silicon wafers as described in claim 1, wherein, Four grooved areas are evenly distributed along the circumference of the ring.

4. The substrate for epitaxial growth of silicon wafers as described in claim 1, wherein, The depth of the pit is 0.1 mm to 1 mm; and / or the area of ​​the pit is 0.1 square millimeter to 0.4 square millimeter.

5. An apparatus for epitaxial growth of silicon wafers, comprising: The base as claimed in any one of claims 1 to 4, wherein the silicon wafer is placed on the base such that the <100> crystal direction of the silicon wafer is aligned with the central axis of the groove region of the annular periphery; a reaction chamber for accommodating the base, wherein the base divides the reaction chamber into an upper reaction chamber and a lower reaction chamber, and the silicon wafer is placed in the upper reaction chamber; an inlet for supplying silicon source gas to the upper reaction chamber for growing an epitaxial layer on the silicon wafer; and an exhaust port for discharging the reaction tail gas generated during epitaxial growth from the reaction chamber.

6. A method for epitaxial growth of a silicon wafer, the method being applied to the apparatus for epitaxial growth of a silicon wafer as described in claim 5, the method comprising: The silicon wafer is placed on the base such that the <100> crystal orientation of the silicon wafer is aligned with the central axis of the trench region on the annular periphery; silicon source gas is supplied to the upper reaction chamber through the gas inlet to grow an epitaxial layer on the silicon wafer; the flow rate of the silicon source gas flowing through the trench region is greater than the flow rate of the silicon source gas flowing through other regions on the annular periphery, so that the thickness of the epitaxial layer grown on the silicon wafer is uniform; the reaction exhaust gas generated during epitaxial growth is discharged from the reaction chamber through the exhaust port.

7. The method for epitaxial growth of silicon wafers as described in claim 6, wherein, Placing the silicon wafer on the base such that the <100> crystal direction of the silicon wafer is aligned with the central axis of the trench region of the annular periphery includes: obtaining the crystal direction corresponding to the V-groove of the silicon wafer; if the V-groove is in the <110> crystal direction of the silicon wafer, placing the silicon wafer on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 45°.

8. The method for epitaxial growth of silicon wafers as described in claim 6, wherein, Placing the silicon wafer on the base such that the <100> crystal direction of the silicon wafer is aligned with the central axis of the trench region of the annular periphery includes: obtaining the crystal direction corresponding to the V-groove of the silicon wafer; if the V-groove is in the <100> crystal direction of the silicon wafer, placing the silicon wafer on the base such that the angle between the central axis of the V-groove and the central axis of the trench region is 0°.

9. An epitaxial silicon wafer, fabricated using the epitaxial growth method for silicon wafers as described in any one of claims 6 to 8, wherein the epitaxial layer thickness of the epitaxial silicon wafer is not greater than 6 micrometers, and the maximum value of the frontal reference least squares range ESFQR value of the edge portion of the epitaxial silicon wafer is not greater than 57.1 nanometers.

10. The epitaxial silicon wafer as described in claim 9, wherein, When the epitaxial layer thickness of the epitaxial silicon wafer is 3-4 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 23 to 33.9 nanometers; when the epitaxial layer thickness of the epitaxial silicon wafer is 4-6 micrometers, the ESFQR value of the epitaxial silicon wafer ranges from 37.4 to 57.1 nanometers.

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