Method for reticle enhancement technology

Abstract

A method for mask enhancement (RET) includes: representing a target wafer pattern or a predicted wafer pattern as a smoothed function captured by a function sample array, the function sample array being an array of function values. A continuous tone mask (CTM) is provided, wherein the CTM is used to generate the predicted wafer pattern. The method for RET also includes inputting a target wafer pattern, wherein the target wafer pattern spans an entire design region. The entire design region is divided into a plurality of blocks, each block having a halo region around it. A proposed mask for one of the entire design regions is iterated until the proposed mask satisfies a criterion for generating the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of blocks; and updating the proposed mask for that block; wherein all blocks in the subset are calculated before the next iteration.

Description

Technical Field

[0001] This application claims the benefit of U.S. Non - provisional patent application Ser. No. 15 / 853,311, filed Dec. 22, 2017, and titled "MODELING OF A DESIGN IN RETICLE ENHANCEMENT TECHNOLOGY"; the patent application is incorporated by reference for all purposes.

[0002] The present invention relates to the modeling of a design in reticle enhancement technology. Background Art

[0003] Sub - micron manufacturing uses lithography techniques to build material layers on a substrate to form transistors, diodes, light - emitting diodes (LEDs), capacitors, resistors, inductors, sensors, wires, optical fibers, micro - electro - mechanical systems (MEMS), and other components that together produce a device for a certain function. Substrate lithography is a printing process in which a mask (sometimes called a reticle) is used to transfer a pattern to a substrate to form a device. In the production or manufacture of devices such as integrated circuits or flat panel displays, substrate lithography can be used to manufacture the devices. When the device to be formed is an integrated circuit, the substrate is typically a silicon wafer. In forming an integrated circuit, lithography is semiconductor lithography, which is usually substrate lithography for high - volume production. Other substrates can include flat panel displays, liquid crystal panel displays, masks for flat panel displays, nanoimprint elements, or other substrates, and even other masks.

[0004] In semiconductor lithography, one or more masks can contain circuit patterns corresponding to individual layers of an integrated circuit or a portion of a layer in multiple patterning processes. This pattern can be imaged onto an area on a substrate that has been coated with a radiation - sensitive material (called photoresist or resist) layer. Once the patterned layer is transferred, the layer can undergo various other processes such as etching, ion implantation (doping), metallization, oxidation, and polishing. These processes are used to complete the individual layers in the substrate. If several layers are needed, the entire process or its variations will be repeated for each new layer. Eventually, a combination of multiple devices (which can be integrated circuits) will exist on the substrate. These devices can then be separated from each other by dicing or sawing and then mounted into individual packages.

[0005] Optical lithography can be light at 193 nm with or without immersion, or extreme ultraviolet light (EUV), or X - ray lithography, or any other frequency of light or any combination thereof.

[0006] Lithography using 193 nm light waves cooperates with refractive optical elements and a transmissive photomask or reticle. The mask selectively blocks, partially blocks, or allows light waves to penetrate onto a substrate that is typically coated with a resist during the lithography process to partially expose or expose different portions of the substrate or a certain material on the substrate. The mask is typically magnified by a factor of 4 relative to the size of the target substrate.

[0007] Extreme ultraviolet lithography (EUV) uses light with a wavelength of approximately 13.5 nm and refractive optical elements. Some implementations use a deformed mask with a magnification factor of 8 in one dimension and a magnification factor of 4 in another dimension.

[0008] Generally, light with a smaller wavelength can resolve finer geometries of features on a substrate, finer spacing between geometries, and higher frequencies (densities). It is also generally more difficult to reliably generate and control light with a smaller wavelength. Economically, it is optimal to use light with the largest wavelength that can resolve the feature sizes, spacings, and frequencies required for the device. Therefore, enhancing the resolution achievable by light of any given wavelength is of interest.

[0009] For any lithography with a specific resolution, additional techniques such as off-axis illumination, phase-shifting masks, and multiple patterning extend the resolution capabilities. When using multiple patterning, a single substrate layer is exposed multiple times, each time using a different mask, referred to as a mask layer.

[0010] A mask is formed by an electron beam (eBeam) machine that shoots electrons at a photoresist-coated surface, which is then processed to create the desired openings in the mask. The amount of energy of the spot delivered to the mask is called the dose, which may have no energy at a dose set to 0.0 and is conventionally标称 dose set to 1.0. When the dose exceeds a certain threshold value (which is conventionally around 0.5), a pattern will be recorded. The critical dimension (CD) variation is especially negatively correlated with the slope of the dose curve at the resist threshold, which is called the edge slope or dose margin.

[0011] There are multiple techniques for use with eBeam machines. Three common types of charged particle beam lithography are variable-shaped beam (VSB), character projection (CP), and multi-beam projection (MBP). The most commonly used system for front-end mask generation is VSB. VSB and CP are subcategories of shaped-beam charged particle beam lithography, where the electron beam is shaped and steered by a series of apertures to expose a resist-coated surface. MBP uses a plurality of charged particle beams, while VSB and CP machines typically have a single beam.

[0012] It is difficult to print features that are similar in size to or smaller than the wavelength of light used for lithography. The industry has applied various techniques to address the difficulty of reliably printing the desired shape on a substrate. The field of computational lithography has emerged to use computation to enhance substrate lithography, which is also known as wafer lithography in semiconductor lithography. Mask enhancement techniques (RET) include computational methods and systems for designing a target mask shape to project the desired pattern more precisely and reliably onto a substrate through target mask shapes in manufacturing variations. RET often uses computation to enhance the image on the mask to print the desired substrate pattern more accurately and reliably with flexibility for manufacturing variations. Two common techniques in RET are optical proximity correction (OPC) and inverse lithography technology (ILT). OPC and ILT are often iterative optimization algorithms that adjust the parameters defining the mask until the predicted pattern on the wafer is within an acceptable tolerance for a set or series of conditions. OPC manipulates the mask geometry and simulates the wafer pattern near the target edges. ILT treats mask transparency as pixel manipulation, and ILT typically simulates the entire wafer pattern, a process called dense simulation. Iterative optimization algorithms generally consist of: (1) evaluating a proposed solution to assign a cost to be minimized; (2) stopping if the cost is lower than a cost criterion; (3) calculating the gradient of each element of the proposed solution that would result in a lower cost; (4) adjusting the proposed solution based on the calculated gradient; (5) returning to (1). The cost is typically defined by a positive value, where zero is the best possible score, as assumed herein. However, alternative cost definitions can be used.

[0013] RET generally means improving the printability of all desired features under nominal (expected) manufacturing conditions and within the expected manufacturing variations around the nominal manufacturing conditions. Since the manufacturing process is not perfect, the design needs to be flexible for a certain expected manufacturing variation. A larger process window means being more flexible for manufacturing variations, especially pattern differences caused by defocus and dose variations within an acceptable tolerance. Providing an adequate process window for as many features as possible is the goal of RET. The percentage of wafers that function as specified after manufacturing is often referred to as the yield. Many factors affect the yield. Improving the process window is generally regarded as related to improving the yield among those skilled in the art. Summary of the Invention

[0014] In some embodiments, a method for a mask enhancement technique includes representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as an array of function samples (FSA). The FSA is an array of function values such as a set of real numbers, complex numbers, or numbers. A continuous tone mask (CTM) is provided, where the CTM is used to generate the predicted wafer pattern that spans an entire design region.

[0015] In some embodiments, a method for a mask enhancement technique includes inputting a target wafer pattern that spans an entire design region. The entire design region is divided into a plurality of blocks, each block having a halo region around the block. An attempted mask for the entire design region is iterated until the attempted mask meets criteria for generating the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of blocks, the subset having two to all of the plurality of blocks, where the calculation is performed for each block in the subset and its halo region. Each iteration also includes updating the attempted mask for the block, where all blocks in the subset are calculated before the next iteration.

[0016] This embodiment also includes a system for RET, where the system includes a computer processor configured to: receive a target wafer pattern for a mask enhancement technique; calculate an array of function samples (FSA) for the target wafer pattern, the target wafer pattern being a smooth function; calculate a continuous tone mask (CTM), where the CTM is represented as a smooth function captured as an array of function samples (FSA); and compare the target wafer pattern with the predicted wafer pattern generated by the CTM. Brief Description of the Drawings

[0017] FIG. 1 is a block diagram of a wafer design processed as a wafer as known in the art.

[0018] FIGS. 2A to 2D illustrate examples of representing patterns by smooth functions according to embodiments of the present disclosure.

[0019] FIG. 3 shows sampling of a band-limited function and reconstructing a function from samples as known in the art.

[0020] FIG. 4 is an example of boundary mismatch ripples as Gibbs phenomenon as known in the art.

[0021] FIG. 5 shows the application of a Gaussian envelope factor to reduce the periodic boundary condition mismatch effect according to an embodiment of the present disclosure.

[0022] FIG. 6 shows the reconstruction of a sampled band-limited function using a filter with a Gaussian envelope factor. Embodiments of the present disclosure capture a smooth function at sample points. FIG. 6 demonstrates the capture of the smooth function and then demonstrates the reconstruction. The reconstruction allows embodiments to calculate the values of the smooth function at a finer granularity than the sampling rate.

[0023] FIG. 7 is an embodiment of a method according to the present disclosure.

[0024] FIGS. 8A-8B show the application of a filter to a target pattern according to an embodiment of the present disclosure.

[0025] FIG. 9A is another embodiment of a method according to the present disclosure.

[0026] FIG. 9B provides an example illustration of the steps corresponding to the flowchart of FIG. 9A.

[0027] FIG. 10A is an example of a distributed calculation for a FET as known in the art, where the design is decomposed into blocks and then the individual blocks undergo an optimization loop, and then the entire design is combined back together from the blocks.

[0028] FIG. 10B is an embodiment of a distributed calculation for a mask enhancement technique according to the present disclosure, where the entire design is iterated within an optimization loop at a certain time.

[0029] FIGS. 11A-11B show an embodiment of a block having a boundary region.

[0030] FIG. 12 shows a 1-D example of Gaussian local interpolation for overlapping blocks.

[0031] FIG. 13 is a block diagram of an embodiment of a computing hardware system that can be used in an embodiment of the present disclosure.

[0032] FIG. 14 is a block diagram of another embodiment of a computing hardware system, a computing design platform (CDP), that can be used in an embodiment of the present disclosure. Embodiments

[0033] Related Applications In this disclosure, the use of the term wafer lithography generally refers to substrate lithography. That is, the embodiments are described in terms of semiconductor lithography as an example to simplify understanding, but the embodiments are also applicable to other types of substrate lithography and overall mask enhancement techniques. The term "substrate" in this disclosure may refer to a mask for lithography, a silicon wafer, a flat panel display, a liquid crystal panel display, a mask for a flat panel display, a nanoimprint element, or other substrates, or other masks. Prior Art

[0034] A conventional semiconductor manufacturing process 100 is shown in FIG. 1. In step 110, chip design is completed by forming a composition of wafer layers. In step 120, some of the wafer layers are divided into mask layers. This step also includes a step sometimes referred to as the coloring step, in which each feature on the wafer layer is colored to reflect the assignment of the feature to a specific mask layer. Once the mask layers are individually identified, each mask layer undergoes a RET step 130. A mask data preparation (MDP) step 140 then prepares the data for the mask writer. This step may include "splitting" the data into trapezoids, rectangles, or triangles. Mask process correction (MPC) geometrically modifies the shape and / or assigns a dose to the shape to make the resulting shape on the mask closer to the desired shape. MPC is sometimes performed in step 130, sometimes in step 140, sometimes in step 150, and sometimes performed in any combination. Pixel-level dose correction (PLDC) may also be applied in step 150. In step 150, the mask is fabricated and verified, and step 150 includes steps such as mask writing, mask inspection, metrology, mask defect deposition, mask repair, and wafer surface inspection of the mask. In step 160, the wafer is written using a series of consecutive masks fabricated in step 150.

[0035] In each of the steps in FIG. 1, there may or may not be a verification step that thoroughly verifies or sanity checks the output of that step. In the present technology, some of the steps in FIG. 1 are performed in a different order or in parallel. An example of pipeline processing in a semiconductor manufacturing process is when the design is divided into multiple blocks (e.g., an array of equally sized blocks), and then the first step is performed on the blocks, and then the second step is performed on the blocks without waiting for the other blocks to complete the first step. For example, the RET step 130 and the MDP step 140 may be pipelined to reduce the turnaround time. In another example, the MPC of step 140 and the mask fabrication of step 150 may be pipelined.

[0036] In wafer lithography, it has been found that the desired features (referred to as main features) on a substrate are printed with greater fidelity and an improved process window when additional features are added to be too small to print their own masks, but still advantageously affect the way nearby main features are printed. These additional features are called sub-resolution assist features (SRAFs). They are isolated shapes not attached to the main features, and these shapes are small enough not to print on the substrate.

[0037] Calculating SRAR and main feature modification is highly computationally intensive and has brittle results. False additional patterns may be printed, the target pattern may not fit well, and the process window may be unnecessarily restricted. Typical RET methods have OPC verification to identify and correct hotspots. A hotspot is an area that requires ideal conditions to print properly and is thus inflexible to manufacturing variations, or in some cases will not print properly even under ideal conditions. Hotspots result in poor yield.

[0038] ILT often generates surprising mask patterns that provide excellent results. The ILT algorithm naturally forms curved shapes that include many SRAFs. These patterns have proven to be impractical for variable-shaped beam (VSB) mask writing machines with conventional splitting because there are too many geometries to handle. Mask writing time is a critical business factor, and VSB writing scales with the number of VSB shots required to print. Thus, the ILT algorithm spends a large amount of run time converting the curved shapes to approximations more suitable for VSB writing, which is often referred to as Manhattanization. Model-based mask data preparation using overlapping shots can significantly reduce the impact of writing time. However, curved shapes take longer to write. Recently introduced multi-beam electron beam mask writing systems write curved shapes directly on the mask without spending any additional time. This enables ILT to output curved shapes without Manhattanization. The remaining problem with ILT is the huge computational requirements for full design, especially for full mask layers of full mask sizes, which are typically about 3.0 cm x 2.5 cm for wafer sizes of such designs in semiconductor manufacturing.

[0039] Multi-beam writing eliminates the need to Manhattanize curved shapes for VSB writing. But mask printability and resilience to manufacturing variations are still important considerations for mask shapes output by ILT. For example, shapes that are too small or too close to each other, or have too sharp turns in the contour of the shape, make it difficult to reliably fabricate the mask, especially in manufacturing variations.

[0040] The energy delivered by an electron beam machine is often approximated by a point spread function (PSF). Although there are many effects that affect the way energy spreads, a monotonically continuous PSF is a reasonable representation of the energy distribution in electron beam-based mask fabrication for variable-shaped beam or multi-beam writing. In this disclosure, for ease of understanding, a simple single Gaussian distribution will be used as the PSF, but the embodiments are applicable to any suitable PSF.

[0041] When delivering energy at a unit dose over a large enough area in a Gaussian distribution, there is enough dose inside the area to reach the unit dose. However, if the area is small, the highest dose inside the area does not reach the unit dose. Similarly, if the spacing between areas is large enough, the lowest dose reaches zero. However, if the spacing is small, the lowest dose does not reach zero. When the area or the spacing between areas is small, the dose curve is narrow. The mask manufacturing process is designed to provide enough dose margin for reasonable areas and spacings, such as 100 nm lines separated by 100 nm intervals, where the unit dose is for a typical front-end mask for 193i lithography. Smaller areas and spacings have lower dose margins at the contour edges of the areas. If the dose applied is the unit dose, the smaller the area, the worse the dose margin.

[0042] The dose margin also becomes worse in a typical mask writing process because of proximity effect correction (PEC). Mask writing by an electron beam, whether VSB, CP or MBP, has a backscattering effect well known in the art. The electrons strike the resist surface, and the secondary electrons released by the electrons bounce back to expose the resist in a 10 micron-scale area around the exposure position. This has a scattering effect, a long-distance effect, and thereby partially exposes the resist in the surrounding 10 micron-scale area. The aggregate of these partial exposures from all the exposures around a given area is significant enough to require correction. The software-based correction for backscattering and other long-distance effects is called PEC and is typically applied in line with the mask writer during mask writing. PEC essentially reduces the unit dose of a shot (or pixel in the case of MBP) to compensate for the pre-dose from the aggregate of surrounding shots (or pixels). Almost all masks produced are written with PEC turned on in the machine. When the dose density in the 10 micron-scale area is high, the amount of PEC applied is also high. This has the effect of reducing the height of the Gaussian (or PSF) of the exposure, and thus reducing the dose margin at the contour edges in that dense area. Therefore, small shapes written in areas of high dose density have a worse dose margin compared to the same-sized shapes written in areas of low dose density.

[0043] Dose margin is important because a shallow slope means that a given percentage change in dose results in a larger difference in CD. Since those skilled in the art know that dose margin is a good proxy for many (if not most) sources of manufacturing variation, measuring CD variation versus dose variation is an important measure of the resilience to manufacturing variation.

[0044] Mask process corrections, which can be performed offline, on-line, or inline with a mask writer, can manipulate the shape or dose applied to the mask in order to correct for linearity and enhance critical dimension uniformity (CDU) and line edge roughness (LER) in addition to other measures of resilience to manufacturing variation. Improving CDU and LER includes enhancing dose margin and improving the uniformity of dose margin across features in the mask. Enhancement of dose margin (edge slope) is disclosed in U.S. Patent 8,473,875, "Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography," which is owned by the assignee of the present application. Reduction of CD crack, which occurs when more than one shot is used to define opposite edges of a critical dimension feature, also improves CDU for writing masks with a VSB or CP writer. An example of CD crack is disclosed in U.S. Patent 8,745,549, "Method and System for Forming High Precision Patterns Using Charged Particle Beam Lithography," which is owned by the assignee of the present application.

[0045] In a typical semiconductor manufacturing process, the RET of step 130 in FIG. 1 generates a target mask shape. When the mask does not automatically satisfy all the desired mask constraints and characteristics (such as allowable penetration value, minimum feature size, minimum pitch, or sufficient dose margin and others), the assessment of the suitability of the mask requires introducing terms that increase the cost associated with violating these constraints. In the field of inverse problems, introducing such terms is called regularization and is a way to select a solution from a potentially infinite set of solutions that equally or similarly well conform to the desired result but also have other a priori desired characteristics. An example of inverse modeling of a mask is Fourier ILT as disclosed in U.S. Patent No. 7,856,612, "Lithography Mask Design Through Mask Functional Optimization and Spatial Frequency Analysis," which is owned by the assignee of the present disclosure and is incorporated herein by reference. Some aspects of the present disclosure extend to Fourier ILT and other RET systems and methods.

[0046] Semiconductor manufacturing and sub-micron manufacturing generally follow Moore's Law, which predicts that the manufacturing infrastructure advances together to allow the resolution to improve at a relatively predictable and stable rate over time. An important aspect of Moore's Law is that the computing power of the infrastructure scales with Moore's Law because the impacts on power consumption and costs - such as computing bandwidth, computing speed, memory capacity, memory access speed, communication bandwidth, communication speed, long-term storage (whether solid state or hard disk) capacity and speed - also scale according to Moore's Law. Introducing new manufacturing technologies (such as EUV lithography or MBP-based mask writing) creates discontinuities in the computing requirements. Introducing new computing technologies, such as graphics processing unit (GPU) acceleration, also creates discontinuities in computing power and scalability.

[0047] Computational algorithms are generally worse than linear in terms of design complexity. This means that computing a block with 1000 components will typically take more than twice as long as computing a block with 500 components. Depending on how long it takes to compute a block with 1000 components, it may be faster to split it into two blocks of 500 components and then stitch them back together to form a block of 1000 components. Depending on the computational task and the interaction between the blocks, the splitting and stitching can have complexity. There is a complex trade-off in determining the appropriate block size for the most efficient computation. This effect worsens when the amount of memory required to store sufficient information for the design far exceeds the amount of memory available on an economically viable computing system. In data processing for chip design or chip manufacturing, or generally in any device design or device manufacturing of sub-micron devices, whole chip designs, or more generally full-size devices, most computational steps need to be divided into much smaller blocks. This is because the amount of data to be computed and the computational capacity scale with Moore's law. The results are then stitched back together for processing by the next step and also for error and data reporting. This is called block-based computation. The blocks are usually rectangular, but can be hexagonal or a mixture of different shapes and / or sizes. Predicting the wafer pattern in a block needs to include the data around the block. The surrounding data is called the halo. The halo must be large enough to capture the significant influence on the predicted pattern of the block.

[0048] All known computer-aided design (CAD) algorithms for the design or manufacture of devices use block-based computation. Additionally, when iterative optimization algorithms are utilized, which typically arise in NP-complete problems, block-based computation iteratively optimizes each of the blocks independently in an optimization loop. Block-based systems suffer from the halo region data becoming stale due to changes made by the optimization procedures in neighboring blocks. The larger the number of optimization iterations in a block, the more obsolete its neighboring block halos become. The stitching problem occurs when it becomes difficult to maintain the solution for the data at the boundaries of the blocks. The blocks are typically computed in situations where the output only changes inside the block but the computation occurs as the visibility of the influence of neighboring blocks on the block, as seen in the halo, changes. Details of this embodiment

[0049] Some embodiments of the present disclosure generate a continuous tone mask (“CTM”) for a large section of a mask that includes the entire mask layer at once. For masks used in 193i projection for semiconductor wafers, the systems and methods known in the art on current computing platforms do not allow for generating a CTM for an area larger than 400 - 1000 square microns of wafer size at once. To generate a CTM for a tile, each tile and its halo are independently subjected to an optimization cycle and then stitched together to form the entire mask layer, thus requiring additional processing to handle stitching artifacts. In contrast, some embodiments of the present disclosure enable the entire mask layer of a wafer size of 7.5 square centimeters area to be generated together in one large optimization cycle. The CTM captures values of an amplitude transmission coefficient map that varies continuously, from which the transmission intensity can be calculated. The present disclosure describes methods and systems for constructing a correction to avoid stitching problems by iteratively optimizing the entire large section instead of iteratively optimizing tiles of large regions independently as known in the art. The large section can be, for example, 5 microns by 5 microns. In embodiments where the large section is the entire mask, the entire mask avoids stitching problems.

[0050] In some embodiments, techniques are applied to identify tiles that do not need to be refined in subsequent iterations until otherwise determined. In such cases, many of the tiles remain unchanged when the entire proposed mask is iterated. Such techniques can significantly improve computational performance.

[0051] In some embodiments, by refreshing the halo at each iteration of the optimization, a smaller halo region than known in the art is utilized. The prior art requires multiplying the halo width by as many iterations as there may be stitching errors that occur or are encountered due to inconsistent optimizations in neighboring tiles. Additionally, in some embodiments, tile sizes that are one to two orders of magnitude larger than conventional methods and systems are achieved. Increasing the tile size reduces the percentage of the processed area in the halo region. The combination of a smaller halo width and a larger tile size reduces the amount of memory and processing burden that the halo region adds to the tiles when processing and storing the tiles.

[0052] Some embodiments additionally utilize a novel and more efficient data representation of the CTM and the target wafer pattern. In these embodiments, the grid points are 4 or 5 times sparser than existing measurements, and the data stored at each data point is minimal, yet represents accurately within the accuracy of the modeled optical system. Together, in some embodiments, the CTM and the target wafer pattern of the entire mask layer for the optical (193i) projection of wafer lithography can be stored in the combined memory of all the compute nodes of currently commercially viable computing platforms. When EUV lithography requires ILT, a similarly commercially viable computing platform at that time can store the entire mask layer for EUV projection. The ILT of EUV requires higher precision and thus more memory to represent the data. In this disclosure, for ease of understanding, the discussion uses the 193i mask case, where the entire mask layer is stored in the collective memory of the computing platform and optimized iteratively together. This disclosure is applicable to processing large segments of the entire mask layer, even in cases where the collective memory is not sufficient to store the entire mask layer. In these embodiments, at all times during the processing of the entire mask layer, the CTM and the target wafer pattern of all the tiles of the entire mask layer can reside in memory. This avoids time-consuming non-resident memory accesses, whether to a solid state drive or a hard disk drive, thus enabling rapid updates of the halos in the compute nodes. The memory required to hold a large segment is easily calculated as [(X dimension / grid pitch) * (Y dimension / grid pitch) * (data size per grid point)]. In some embodiments, the intermediate results are held in memory only for the duration of the calculations within a tile.

[0053] Keeping the CTM and the target wafer function sample arrays of all the tiles of the entire mask layer always in memory also enables this embodiment to calculate the optimization iterations of the entire mask layer in one go, rather than optimizing each tile independently of one another as is done in the present technology. Thus, this embodiment eliminates the stitching problem in a constructive correction manner and efficiently calculates the CTM of large segments including the entire mask layer using commercially viable computing platforms.

[0054] In some embodiments, a certain mask process correction is performed during RET, or the resilience to mask manufacturing variations is enhanced, where the mask will be used in the lithography process to form a pattern on the wafer.

[0055] In some embodiments, the sampled values of a smooth function (which is a continuously differentiable function) on the grid are captured in an array. In some embodiments, how well the predicted wafer pattern matches the target wafer pattern is represented as a smooth function. This technique eliminates the need to look for contour edges on the predicted wafer pattern and then compare them with the contour edges on the target wafer pattern, which is done in most existing ILT implementations.

[0056] In some embodiments, the process may cause the ILT process to descend to a point where the number of regions remaining to be further optimized is small enough, and the blocks containing such regions are large enough such that statistically it is likely that optimizing those regions will not affect the halo of the neighbors within the block. By understanding where such regions are in the design, re-blocking the design at this stage can select block sizes and regions that may include non-rectangular regions or even curved boundaries and corresponding halos along the perimeter.

[0057] In some embodiments, there may be iterations among different optimization strategies, such as where in one strategy the entire design is optimized all together, and in another strategy the blocks are optimized independently of each other. The strategies may be pre-set, such as optimizing the entire design for a preset number of optimization iterations, then optimizing the blocks until each block meets a "cost criterion" (which may reach the maximum allowable number of iterations, or meet a certain quality criterion, or not sufficiently improve the quality criterion), then iterating the entire design again for another preset number of iterations. In another example, the strategy may be adaptive to a certain set of criteria that observe the state of the mask design and include the global and local optimization progress of the rate of change of the optimization criterion and the rate of change of the rate of change, where different strategies are deployed with different parameters and possibly different blockings as the ILT process proceeds. Function sample array

[0058] The goal of RET is to form a mask such that the energy in the substrate is below a threshold everywhere the substrate should be clear (or dark in a negative resist), above the threshold everywhere the substrate should be dark (or clear in a negative resist), and transitions through the threshold at the desired locations. In some embodiments, a smoothing function is used to represent the clear regions, dark regions, and transition locations. The smoothing function is continuous and differentiable. The smoothing function is captured on a fine enough grid to define the function within a tolerance. The array representing the values of the smoothing function shall be referred to in this disclosure as the function sample array (FSA), which is an array of real or possibly complex values of the underlying function at the sampling locations. In some embodiments, the smoothing function is implemented as a band-limited function, which is inherently infinitely differentiable. A band-limited function is a function that contains frequency components only within fixed limits, as opposed to an infinite number of components in theory. The nature of the band-limited function determines the sampling rate (grid spacing). This embodiment uniquely recognizes that the light emitted from the mask and the energy absorbed by the substrate are naturally represented by a smoothing function. The target wafer pattern, predicted wafer pattern, and CTM are modeled as FSAs.

[0059] Knowledge of optical lithography allows the selection of a smoothing function such that the exact function can be defined more coarsely on the grid compared to that used in existing RET methods. The lithographic imaging resolution is based on the wavelength and numerical aperture of the lithographic imaging system. In this embodiment, the FSA grid has a plurality of grid points, and the grid points are spaced apart by a grid pitch. The grid pitch can be set by selecting a transition distance less than the lithographic imaging resolution of the lithographic imaging system and dividing the transition distance by a value such as from 3 to 6, or can be set based on a predefined edge placement error specification. The determining factor for the divisor is the accuracy required at the point where the determining function crosses the threshold value. The key to these embodiments is that the smoothing function is accurately captured by its values at the grid points. This means that the predicted mask pattern grid points can be directly compared with the target mask pattern grid points without having to calculate the exact position of the mask pattern contour. The ability to accurately represent the pattern by a finite number of samples enables the calculation of large blocks with less memory and higher speed compared to conventional methods. This enables a fast, exact, and distributed calculation of a differentiable cost function that measures the degree of shape matching - which can be based on, for example, a GPU.

[0060] Figure 2A shows a smoothing function (x, y) represented on a grid. This function has an edge of the pattern appear where it passes through a threshold value as shown in plane 230. This plane 230 can be visualized as a contour curve of a surface , which surface is defined by . Figure 2A shows a typical smoothing function 200 and the intersection of the function with plane 230. The grid point location 220 is where the grid lines 210 intersect each other. In this example, where 0.5 is the shape contour level of plane 230, the smoothing function 200 has a value of 0.5 within the target shape and a value of <0.5 outside the target shape. This three-dimensional plot shows the smoothing function as the height in the z direction, where the height represents the sampled value at the grid point 220. A set of values at the grid points of the smoothing function 200 can be captured by a function sample array (FSA). The 2-D plot 235 in Figure 2B shows a y-plane slice along the grid line that cuts through the L-shaped pattern. The grid pitch 237 is selected such that there are multiple grid points on the transition 239 of the function from z = 0 to z = 1. The multiple grid points ensure that the position where the function transition passes through the threshold value is within tolerance.

[0061] The smoothing function demonstrated in Figures 2A and 2B can be used to represent the target pattern and the predicted pattern. In some embodiments, the cost and cost derivative can be calculated analytically because of the smoothing characteristics of the target pattern function and the predicted pattern function.

[0062] This embodiment forms a grid based on the physical properties of a lithographic imaging system for all stages from the CTM to the target pattern FSA and has the ability to reliably resample to a finer grid. Because of this, this embodiment can operate on a large area in a single computing node. Additionally, this embodiment decomposes the calculation of extremely large areas of an entire mask layer, such as a 193i mask, into blocks without stitching artifacts. These possibilities are obvious for the optical mask enhancement technology industry because there are multiple stumbling blocks to be solved, such as accurate grid-based pattern representation without an ultra-fine grid and reliable interpolation to a finer grid during operation. For example, instead of using a 1-4 nm sampling grid for 193i lithography RET as typical in the prior art, in this embodiment, a sampling grid on the order of 10 nm can be used. This magnification of the grid sampling saves 5 to 100 times or more in the required memory.

[0063] Generate the FSA of the target wafer pattern from the input target geometry. Figure 2C shows a sample target geometry 240 in three dimensions as it would look if anything inside the shape had a value of 1 and anything outside the shape had a value of 0. Since this representation is not achievable, this embodiment applies a low-pass filter such as Gaussian blur to the geometry to generate the smoothed function 250 of Figure 2D. The pattern 260 obtained from the smoothed function 250 of Figure 2D is accurately captured as it appears by comparing it with the target geometry 240 of Figure 2C.

[0064] Generate the FSA of the predicted wafer pattern from the CTM using a lithography system model. The predicted wafer pattern FSA is tampered with to have characteristics similar to the target pattern FSA, such as values close to 1 inside the shape, values close to 0 outside the shape, and having a smooth transition between these regions. This tampering prevents a mismatch between a value of 0.15 in the predicted pattern and a value of 0.0 in the target pattern in a clear (or dark in a negative resist) region. The only critical values are at the threshold where the function transition passes. Thus, when the value at the grid point of the predicted wafer pattern FSA matches the value of the target wafer pattern FSA, the mask will accurately form the desired pattern on the substrate. The smoothed function representation in the FSA supports optimizing values without any explicit information about edge positions in the target mask pattern. Use of the fast Fourier transform

[0065] This embodiment is independent of U.S. Patent No. 7,856,612, which is based on the insight that the physical properties of a lithographic imaging system can be highly adapted to a 2D Fourier (plane wave) basis for representing all quantities, thus enabling the use of fast Fourier transform (FFT) methods for efficient calculations. There is great value in machines that harness linear vector spaces, and this method exploits this advantage by representing the CTM as a linear combination of a complete set of orthogonal basis functions. The physical properties of lithographic imaging are particularly suitable for a 2-D Fourier basis because only the components cut by the spatial frequency f will contribute to the projected image, where f-cut is the system resolution cutoff. The cutoff depends on the details of the illumination and projection optics, but for partially coherent imaging with quasi-monochromatic light of wavelength and an imaging system with numerical aperture NA, typically f-cut 2NA / .

[0066] Two main benefits of using a Fourier basis set are that the convolution required to compute the image is now a simple multiplication in Fourier space, and efficient FFT implementations are generally available. The most computationally intensive optimization work can be performed only by the low-frequency mask components within the lithographic imaging cutoff. Inspired further by the lithographic imaging cutoff, some embodiments of the Fourier-based method seek the optimal mask function captured in the CTM band-limited to f-cut. Once this is found, the CTM can be used to generate a manufacturable physical mask in a separate process.

[0067] In some embodiments, efficiency is obtained because over-aliasing is avoided for the grid used to represent the band-limited mask function, and then the grid is interpolated to a finer grid as required for calculating the pattern and cost density. A brief introduction to the discrete sampling of the band-limited function and its reconstruction from these samples should first be presented.

[0068] Consider the band-limited function and its Fourier transform , as shown in Figure 3(a). The double-headed arrow in the figure indicates that the left and right figures are a Fourier transform pair. By multiplying the function by the sampling function to the function Sampling, sampling function is a series of Dirac delta functions spaced by " ", as shown in Fig. 3(b). Fig. 3(c) shows the sampled function and its transform. There is no aliasing in this example because the convolved images do not overlap, which is the condition for establishing the Nyquist criterion. Now shown is the reconstruction from its samples. Referring to Fig. 3(d), the spectrum is multiplied by an ideal low-pass filter to eliminate all but the fundamental frequency spectrum by filtering out the higher-order convolved images. This corresponds to convolving the sampled function with . The result shown in Fig. 3(e) matches the initial function in Fig. 3(a).

[0069] The FFT acts directly on the sample values but treats the data as periodic outside the interval of the data being analyzed. There is a class of functions for which the FFT and the continuous Fourier transform are the same (within possible scale constants) and thus the reconstruction of intermediate values for such functions will be exact. In this class of functions, the function must be periodic, must be band-limited, the sampling rate must be at least twice the maximum frequency component of , and the data interval must be an integer number of periods of . The last requirement is equivalent to the absence of a mismatch due to the imposition of periodic boundary conditions (PBC).

[0070] The value mismatch from the imposed PBC is the value jumping from one side of the boundary to the other. There is ringing near these boundaries in the reconstructed function, which is equivalent to the Gibbs phenomenon for step discontinuities. Any mismatch from the PBC will behave exactly like a step discontinuity at the midpoint between the sample points. Fig. 4 provides an illustration showing the samples of a square pulse and the result of Fourier interpolation near the sudden jump of the sample values. The smooth curve is a band-limited periodic (over the entire interval) function consistent with the samples, and it shows the ringing characteristics of the Gibbs phenomenon.

[0071] To reduce ringing, some embodiments localize the Fourier interpolation kernel by an envelope factor. A Gaussian envelope factor is described herein, but others may be used. Additionally, other interpolation methods (such as splines, polynomials, rational functions, etc.) may be used in place of Fourier interpolation. The Fourier interpolation kernel may be localized by applying a Gaussian envelope factor to the ordinary kernel, which smoothly and strongly restricts its extent. Basically, this is a modification of the Fourier transform pair shown in Fig. 3(d) to Fig. 5, where the width parameter has been set to in this embodiment. This width provides a trade-off between interpolation accuracy and the increased halo thickness required to give a fully converged result (i.e., an increase to the boundary layer of the block, as will be described in a later section). In the frequency space, the width tunes the width of the error function roll-off of the low-pass filter. To accurately reconstruct the highest frequency components, the function may be band-limited to the flat top of the filter. Using this method, the approximation is uniform because the same range of samples is used to interpolate everywhere, and the values at the original sample points are preserved.

[0072] Figure 6 graphically shows what operations are performed in this method to reconstruct a function using Gaussian local interpolation. Figure 6 is similar to Figure 3, except for step (d). Thus, the descriptions of Figure 3(a), Figure 3(b), Figure 3(c), and Figure 3(e) apply to Figure 6(a), Figure 6(b), Figure 6(c), and Figure 6(e). In step (d), the low-pass filter is in the real space and in the frequency space. That is, this method involves a Gaussian local interpolation Fourier transform pair.

[0073] FIG. 7 is an example flowchart 700 of a method for a mask enhancement technique, where a smoothing function is captured by FSA and used for a target pattern and a mask for generating the target pattern (e.g., a target wafer pattern). For example, flowchart 700 describes a method of representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured by FSA, where FSA is an array of function values, and the function values can be real numbers, complex numbers, or a collection of numbers. In step 710, a target pattern for the mask enhancement technique is input, such as pattern 711. The target pattern 711 may include many patterns of a design (e.g., individual rectangular and square patterns in target pattern 711), as shown in FIG. 7, such as an entire mask layer of a semiconductor wafer, or may be a single pattern to be written onto a surface, such as the individual L-shaped pattern shown in FIG. 2C. Next, in FIG. 7, in step 720, a target pattern FSA of the target pattern is calculated. Generating the target pattern FSA in step 720 may include applying a low-pass filter to the target pattern in some embodiments. The target pattern function is periodically represented as function 721 in FIG. 7, where function 721 is slightly blurred compared to target pattern 711. The target pattern function 721 is band-limited to the bandwidth of the low-pass filter and is sampled on a pattern grid with a first sampling rate that can be at least twice the bandwidth of the low-pass filter. The low-pass filter bandwidth can be set to maintain edge positions and allow rounding of corners consistent with lithography system characteristics or specifications provided by the target pattern.

[0074] In step 730, CTM 731 is calculated. CTM 731 can be initialized by an initial value (such as a constant value), a low-pass filter applied to the target pattern, a previously determined CTM (e.g., a preliminary result calculated previously), or a low-pass filtered mask obtained in other ways (e.g., when solving hotspots in an existing mask design or checking solutions provided by another system).

[0075] In step 740, a predicted pattern FSA (representing a predicted wafer pattern) is calculated from the CTM and the system model.

[0076] In step 750, the target pattern FSA is compared with the predicted pattern FSA calculated for the CTM. The comparison of the target pattern FSA and the predicted pattern FSA uses the grid points of the pattern grid. The comparison may include using the target pattern function and the predicted pattern function to calculate a cost density function. The predicted pattern function (FSA) can be generated using the CTM, the lithography imaging system model, and the resist process model.

[0077] Figures 8A to 8B provide details of the smoothing function for generating an FSA (such as a target mask pattern) of the present embodiment. For simplicity, the graphs are shown in 1-D, where the x-axis represents the spatial position and the y-axis represents the value of the smoothing function. The smoothing function is generated by convolving a low-pass filter, which can also be described as applying blurring. Figure 8A has three curves showing the smoothed representation of the target pattern. Curve 810 is the ideal target pattern, which has edges at spatial positions x = +0.5 and -0.5 in this example. Curve 820 is the result after applying a Gaussian blur with a (1 / e) width to curve 810, and curve 830 is the result after applying a wider Gaussian blur with a (1 / e) width to curve 810. Note that all curves 810, 820, and 830 intersect at the ideal edge position at a y-value of 0.5, and the y-value of 0.5 is the result of an arbitrary choice. For this example embodiment, a y-value of 1 indicates inside the shape, and a y-value of 0 is outside the shape. Aside from any other considerations, the geometric target shape can thus be represented as the contour of the smoothed curve at a y-value of 0.5. Gaussian blur means that the curve is effectively limited in spatial frequency; in fact, blurring multiplies the spectrum by a Gaussian with a 1 / e width ( ). The criterion of 20 dB attenuation for defining the bandwidth of the Gaussian filter corresponds to using 3 to 4 sample points in the smooth edge transition from approximately 0 to approximately 1 to almost perfectly capture the smoothed curves 820 and 830.

[0078] The graph of Figure 8B shows how the pattern can be kept as the smoothest representation (blur width 1 / 3) but then sharpened to something very similar to a module width of 1 / 10 (curve 820) by passing the y-values of the blurred curve through a soft thresholding function. The result is curve 832, which looks almost exactly like the result of a narrower blur of curve 820 in Figure 8A, and which is flat at all values away from the edge. This is good for making comparisons without the explicit contour chasing used by conventional methods. Using this blurring technique, the present method can take the difference between two curves that are stylistically similar to the blurred 1 / 10 curve (curve 820) or the sharpened blurred 1 / 3 curve (curve 832) to examine the degree of mismatch between two patterns. Optimizing CTM

[0079] This embodiment utilizes an optimization technique that iterates on a proposed solution until a desired result is achieved. The proposed solution is captured as a CTM. A measurement of desirability is determined by comparing the predicted pattern with the FSA of the target design pattern. The FSA comparison involves comparing values at equivalent grid points representing two functions, possibly within a certain tolerance. The goal of the described procedure is to reduce the cost to as close to 0 as possible. Other techniques may converge using different cost metrics.

[0080] Figure 9A is an example flowchart 900 of a method for a mask enhancement technique, where FSA is used in all steps related to generating a mask for a target pattern on a wafer. In step 910, an input such as a substrate lithography system model for wafer lithography is provided. The substrate lithography system model includes one or more of an optical, EUV, or other lithography system model, a resist process model, and any other model required to predict the printed pattern on the substrate from the mask. The models included in the substrate lithography system model can be complex physical accurate models, simpler empirical models, or models of any other level, including a zero model that removes most or all of its influence on the final result. The substrate imaging system model can include parameters such as wavelength, illumination pattern, numerical aperture, refractive index, etc.

[0081] Step 920 includes inputting a target pattern to be formed on the substrate using the substrate lithography process, where the target pattern is within the design area. In some embodiments, the target pattern includes a plurality of patterns on the wafer, and the design area includes a large section of the mask layer of the semiconductor wafer, such as the entire mask layer. In step 920, in some embodiments of the present disclosure, certain geometric manipulations of the target pattern can be performed. For example, an edge bias considering the etching effect during the processing of the substrate can be pre-calculated in step 930 and before subsequent optimization steps.

[0082] In step 930, a target pattern FSA is calculated for the target pattern (such as the target wafer pattern). In some embodiments, the calculation of the target pattern function includes applying a low-pass filter (which may also be referred to as blurring) to the target pattern, as described with respect to Figure 8A. The low-pass filter can be, for example, a Gaussian filter or any other filter that is better localized in space and frequency.

[0083] In step 940, a CTM (i.e., the proposed mask) is calculated, as explained in step 730 of Figure 7.

[0084] In step 950, a substrate lithography system model is used to calculate a predicted pattern FSA that will be generated by the CTM on the substrate. In some embodiments, the calculation of the predicted pattern FSA (e.g., the predicted resist pattern function) may include calculating a projection image function from the CTM using a substrate imaging system model. The projection mask image FSA and the resist process model are then used to calculate the predicted pattern FSA generated by the projection image function. The calculation of the projection image function may be transferred to a finer grid using local Fourier interpolation according to the calculation method or the subsequent use of the projection image.

[0085] In step 960, a cost is calculated using the target mask pattern FSA and the predicted mask pattern FSA, and a function derivative of the cost with respect to the CTM is also calculated. The cost may be, for example, the total cost. The cost may be represented by a smooth function. In some embodiments, the cost may be overall cost data, which may include, for example, local partial costs, cost density, and cost gradient. In some embodiments, the calculation of the function derivative takes into account adjacent pattern information in the boundary region around the design region. In some implementations, the calculation of the cost includes using the target pattern function and the predicted resist pattern function to calculate a cost density function, and integrating the cost density function over the design region. The calculation of the cost density function may include the variance between the target pattern function and the predicted resist pattern function, the absolute value of this difference, or any formula that produces positive values that tend to zero in the case of pattern matching and tend to larger numbers in the case of pattern mismatch. These cost density values may also be weighted according to other information provided by or derived from the target pattern. For example, weights may be used to emphasize edge compliance and reduce the importance of matching corners.

[0086] In step 970, the cost and the function derivative are compared with a cost criterion. In other words, this comparison determines the mismatch between the predicted pattern and the desired pattern. The cost criterion may include a value that causes the cost to converge to a value close to the minimum, or minimizes the magnitude of the function derivative or its components. That is, when the change from a further iteration to the previous solution does not exceed a certain amount, the cost criterion may be considered satisfied. In some embodiments, the cost criterion may include evaluating the distribution of the values of the cost density function within the design region. The cost criterion may also be defined as a mismatch amount, such as a specified acceptable amount, such as a geometric value or a percentage.

[0087] It should be noted that in flowchart 900, variations are possible. For example, the order of steps 910 and 920 may be interchanged. In some embodiments of the present disclosure, step 930 may be an empty step. Steps 940 and 950 may be combined into one step. In steps 960 and 970, the calculation of the derivative is optional. Other calculations may be performed in steps 960 and 970 to assist in iterating the CTM.

[0088] In some methods, the soft thresholding function can be applied to the target pattern function in step 935 to sharpen the edges of the target pattern function to generate a target pattern function with clearer edges before the calculation of the cost in step 960. This thresholding is shown in FIG. 8B. Soft thresholding converts the encoded pattern into a higher resolution function, which has fewer features at the transition away from the edge, thus giving more weight to the contour without directly determining the contour. This allows the target pattern function to be stored at a lower grid resolution than when used for comparison. The cost, such as the total cost, is calculated using the target pattern FSA in step 960 after the sharpening and prediction of the resist pattern function for any application.

[0089] In an example of thresholding the target pattern FSA, the target pattern FSA in step 930 is generated by applying a low-pass filter to the target pattern such that the target pattern function is band-limited to the bandwidth of the low-pass filter. The target pattern function is sampled on a first pattern grid with a first sampling rate, which can be at or above the Nyquist rate for this bandwidth, and the thresholded target pattern function generated in step 935 is sampled on a second pattern grid with a second sampling rate higher than the first sampling rate. The soft thresholding function can be, for example, an S-shaped function that sharpens the transition between the minimum and maximum values in the target pattern. For example, the slope of the thresholded target pattern function can be increased at the transition between the minimum and maximum values in the target pattern, thus sharpening the edges of the target pattern function.

[0090] Soft thresholding enables the function to more closely match the results of the predicted resist pattern function. Soft thresholding can be implemented as mapping 0 to "0" (soft range), mapping 1 to "1", and mapping the threshold value to the threshold value (e.g., ½ to "½"); and can be implemented as a smooth monotonic increasing switching function based on the Gaussian error function, hyperbolic tangent, or any other S-shaped function that can be想到 by one of ordinary skill in the art. In some embodiments, this first soft thresholding function can also be applied to the predicted resist pattern function to generate a second predicted resist pattern function for comparison with the target pattern.

[0091] Return to step 970 of FIG. 9A. If the cost criterion is not met, the method is iterated by modifying the CTM in step 990 to reduce the cost by using the function derivative of the cost to provide guidance on how to modify the mask, as indicated in step 980. This will use derivative calculations and use any suitable algorithm, such as conjugate gradient, to pick the "guidance" for moving from the current mask parameters to reduce the cost. The cost or a partial contribution to the cost can be explicitly used in this procedure, or the gradient components, or both. In some embodiments, step 960 includes calculating the printability of the mask shape and the resilience to manufacturing variations, which will be used as part of optimizing the cost. The size, pitch, and slope of the CTM at a certain threshold value or multiple threshold values of the CTM are examples of such components in the cost. Steps 950, 960, 970, 980, and 990 will then repeat as indicated by loop "A" until the cost criterion is met. Each iteration's modification of the CTM can consider further factors in addition to the function derivative, such as historical data about previously calculated solutions. The final CTM is then output in step 995. The CTM data can then be "legalized" into a mask pattern that can be manufactured more reliably. In some embodiments, step 995 includes a separate step of generating a mask that can be manufactured more reliably. An example of this step is to force all shapes and pitches to "join" to comply with the specified minimums. By incorporating these factors as part of the cost during the optimization loop in step 960, the amount of joining will be negligible, where the impact on the resulting quality of the predicted pattern FSA is negligible. These mask patterns can also be further processed to incorporate a certain MPC of the mask manufacturing effects (such as mask etch bias). Step 995 can include all MPCs. The output of the legalization step can be in the form of data that drives an electron beam machine, such as directly generating exposure instructions from the CTM.

[0092] FIG. 9B provides an example illustration of the steps described in flowchart 900. The target pattern geometry 921 is an example of the target pattern input in step 920, where in this embodiment the target pattern geometry 921 includes a number of rectangular shapes. The target wafer pattern FSA 931 corresponds to the target function generated in step 930. An initial CTM 941 is generated in step 940, and a predicted pattern FSA 951A is generated by the initial CTM 941 in step 950. FIG. 951 shows the predicted pattern FSA 951A as an open curve shape and the target wafer pattern FSA 951B as a hatched shape. The difference between the predicted pattern FSA 951A and the target wafer pattern FSA 951B as shown in 951 is used to calculate the cost and the function derivative of the cost in step 960. If the cost criteria are not met in steps 970 and 980, a modified (improved) CTM 991 is calculated in step 990. Then iteration of loop A is performed, where a modified predicted pattern FSA is calculated using the improved CTM 991 in step 950. Similar to FIG. 951, FIG. 952 shows the difference between the modified predicted pattern FSA 952A and the target wafer pattern FSA 952B. The open shape is not visible, indicating that the modified (and improved) predicted pattern FSA 952A is close enough to the target wafer pattern FSA 952B such that the difference in FIG. 951 is not visible. The difference between the improved predicted pattern FSA 952A and the target wafer pattern FSA 952B is used to determine whether the cost criteria are met. It should be noted that in FIG. 9B, the function is shown as a conventional contour of a geometric shape, where in this example the contour is shown at the resist exposure threshold level. These contours show how the pattern shape is improved using the present method. However, as explained throughout this disclosure, some embodiments of the present method perform calculations using FSA rather than working with geometric contours. Distributed processing

[0093] Aspect of this embodiment is a combination of data representations of FSA captured on a regular grid that efficiently delivers data and receives data from each procedure of a distributed program.

[0094] As previously mentioned, in some embodiments, the entire CTM of the entire mask layer and the target mask pattern are kept in memory. To predict the mask pattern of the CTM and compare the predicted wafer pattern with the target wafer pattern, this embodiment decomposes the design into blocks. Although this embodiment that optimizes the entire design via distributed processing should be described in terms of CTM, the embodiment can also be applied to types of proposed masks other than the CTM described herein.

[0095] When performing calculations on a specific block of the entire pattern, the sections of the FSA can be sampled at a higher rate. For example, the pattern can be divided into a plurality of blocks, and the calculations on the plurality of blocks are performed in a distributed program. The distributed programs operate independently, and many programs can run simultaneously. Multiple blocks are processed in parallel on the nodes of the computing cluster. In any of the plurality of blocks, the CTM and the target mask pattern FSA are delivered at the designed wide grid spacing, but when more detailed calculations are needed, the values of the FSA can be calculated at any spacing. The results of the distributed program are returned at the designed wide grid spacing. That is, when performing calculations on a specific block, the sampling rate can be increased for higher resolution calculations, but the additional values of the FSA (higher sampling rate) do not need to be stored in memory during the calculation of the entire pattern. This saves memory and enables the calculation of the entire mask layer in a distributed program. Upsampling can be performed by the following operations: adopting a discrete Fourier transform via the FFT algorithm, expanding the transform to a higher frequency corresponding to a higher sampling rate via periodic extension, multiplying the result in the frequency space by a low-pass filter, which corresponds to an ideal filter that multiplies by a local Gaussian in the real space, and applying an inverse discrete Fourier transform via the FFT algorithm. The stitching error between the blocks can be reduced to the point of elimination by adding more to the boundaries of the blocks such that the mismatch occurs at a specified number of Gaussian widths away from the block edges. The above describes the use of the Gaussian localization factor, but other forms of limiting the spatial range may be suitable, as known to those skilled in the art. The sampling rate is also set higher than the Nyquist minimum rate such that the function bandwidth stays within the flat part of the filter in the frequency space and with a specified accuracy.

[0096] This method achieves Graphics Processing Unit (GPU) acceleration because of the regular grid-structured calculations. The FSA helps with GPU calculations because many grids can be processed simultaneously. The calculations involve Single Instruction Multiple Data (SIMD) operations without contour chasing. Exact function resampling is achieved via a highly optimized FFT. The GPU calculation time is greatly reduced because of the reduced data transfer time, since the amount of grid sample data that needs to be kept in memory is based on only the coarsest grid necessary to exactly represent the function. Minimizing the data transfer to / from the GPU is important because the GPU is particularly fast at calculations but is usually limited by its data transfer rate. This method increases the area of the block suitable for a given memory size by 30 to 100 times compared to the conventional method, where the burden is correspondingly reduced by 5 to 10 times and the gap between the blocks is correspondingly reduced by 5 to 10 times.

[0097] Using localized Fourier interpolation via FFT and a localization function that limits the influence of the mismatch boundary to a specified distance allows the calculation to operate on whichever resolution grid is most appropriate and only store the continuously optimized quantities on its smallest grid. Without this, it becomes impossible to meet the memory requirements for the entire mask layer. Another benefit of this method is that the calculation of the cost function and its derivative uses large chunks with sufficient overlap to be distributed, allowing for the lithographic imaging neighborhood and the localized Fourier interpolation range, while still within the entire mask layer, rather than stitching to optimize all mask parameters block by block.

[0098] Using a decomposition into chunks with halo, an independent evaluation of the contribution of each chunk to the cost function and the derivative can be performed, and the benefit of the band-limited smoothing function allows a single node to hold the values of large design regions for memory efficiency. Chunking also enables computational acceleration, such as using a GPU, which is further enabled as needed by conventional grid-based calculations and the utilization of FFT. The independent evaluation of the chunks also means that multiple nodes can be used to first handle even larger design regions (this is weak scaling, which calculates larger problem sizes in a similar amount of time) and then achieve a more parallel execution of the chunk evaluations (this is strong scaling, which occurs when the computational time decreases correspondingly for a fixed problem size with more functional units). Optimizing the entire design

[0099] Figure 10A is an example flowchart 1000 for conventional distributed calculations for RET, and Figure 10B is an example flowchart 1001 for distributed calculations for global-level mask enhancement techniques made possible by this method. The method iteratively optimizes large sections of the mask layer (such as the entire mask layer) as should be described with respect to Figure 10B, instead of iteratively optimizing each block individually as shown in the prior art example of Figure 10A. In step 1010 of the conventional method of Figure 10A, the design and the mask are represented. In step 1020, the mask is segmented into multiple blocks. In steps 1030a / b...n, each block with a large halo region is iterated individually, where the cost and the derivative are calculated in steps 1030a / b…n, and if the cost does not meet the cost criterion in steps 1050a / b…n, then the proposed mask for each block is modified in steps 1060a / b…n. After each block has been optimized, the mask is assembled from the blocks in step 1070. Thus, in the conventional method, the design is decomposed into blocks and then each individual block undergoes an optimization cycle; then the entire design of the large region is assembled back together from the blocks. A well-known problem with all prior art systems is stitching.

[0100] In FIG. 10B of the method for mask enhancement technology, the entire design is iterated within an optimization cycle. In each cycle iteration, the data of the halo of each block is refreshed from adjacent blocks. Therefore, there will be no difference in the data processed by adjacent blocks. In step 1011 of flowchart 1001, the entire target wafer pattern is input and the mask to be proposed is prepared, such as a continuous tone mask (CTM). In some embodiments, the target wafer pattern and the proposed mask can be represented as an array of function samples. The design of the entire target wafer pattern can be, for example, the entire mask layer of a chip design. The target wafer pattern spans the entire design area. Step 1011 corresponds to steps 920, 930, and 940 of FIG. 9A. In step 1021, the entire design area is divided into a plurality of "N" blocks. The proposed mask for the entire design area (such as CTM) is iterated, as indicated by loop "B" in FIG. 10B, where in the iteration, each block is calculated independently from any other block. The calculation of each block and its halo region in steps 1031a, 1031b to 1031n includes calculating the cost and derivative data of each block. Steps 1031a / b...n correspond to steps 950 and 960 of FIG. 9A. The cost and derivative data are based on comparing the target design with the predicted design to be generated by the proposed mask (e.g., CTM). All blocks are calculated in a distributed program.

[0101] Each iteration also includes step 1041: collecting the cost and derivative data of all blocks in the plurality of blocks to calculate the cost. In some embodiments, the collected cost includes the cost of the reliable manufacturability of the mask as discussed in step 960. If the cost does not meet the cost criteria in step 1051, the cost and derivative data are used to modify the proposed mask in step 1061. Step 1051 corresponds to steps 970 and 980 of FIG. 9A, and step 1061 corresponds to step 990 of FIG. 9A. Then the program is iterated as indicated by loop B. In step 1091, after it has been determined that the cost meets the cost criteria, the proposed mask is converted into the output shape. Further processing of the mask shape for reliable manufacturing, MPC, or format output of the mask as described in step 995 applies to step 1091. Variations to the procedure shown in FIG. 10B include: (1) in some iterations, blocks that have met the optimization criteria and are known not to have changed their halo regions are not optimized; (2) re-blocking the design and / or the proposed mask after certain criteria have been met (such as a number of blocks meeting the optimization criteria) or after a certain number of iterations have been performed; (3) using different optimization techniques for some of the iterations; (4) only optimizing blocks with high costs for a new iteration before continuing to optimize the entire design.

[0102] In an example embodiment, a target wafer pattern or a predicted wafer pattern is represented as a smooth function captured as a function sample array (FSA), where the FSA is an array of function values that can be real numbers, complex numbers, or aggregates of numbers. A computational lithography model (CTM) is provided, where the CTM is used to generate a predicted wafer pattern that spans the entire design region. In some embodiments, the entire design is segmented into a plurality of blocks, and the CTM for the entire design region is iterated until the CTM meets the criteria for generating the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for at least a subset of the blocks - such as one block, or two or more blocks that need to be optimized - and calculating all the blocks in the subset before the next iteration. In some embodiments, the iteration can include calculating for each block, where all the blocks are calculated before the next iteration. In some embodiments, the calculations are performed on a computing platform that has a total memory of the set of all computing nodes of the computing platform, where the total memory of the set holds the target wafer pattern and the CTM for the entire design region during all iterations. In some embodiments, the calculation of the predicted wafer pattern further includes calculating cost and derivative data based on comparing the predicted wafer pattern with the target wafer pattern; and updating the CTM of the block using the cost and derivative data. The cost can also be represented as a smooth function, where the smooth function of the cost can be different from the smooth function of the target wafer pattern, the predicted wafer pattern, or the CTM. In this disclosure, the cost can also be referred to as a cost function. In some embodiments, the CTM is represented as a smooth function captured as a function sample array (FSA), where the FSA is an array of function values that can be real numbers, complex numbers, or aggregates of numbers. The FSA of the CTM can be different from the FSA of the target wafer pattern or the predicted wafer pattern. For example, the target wafer pattern can be represented by a first FSA, and the CTM can be represented as a second FSA.

[0103] In some embodiments, each block has a halo around the block; the calculations are calculated for each block and its halo; and each iteration further includes updating the CTM of the individual blocks in the subset of blocks after calculating the predicted wafer pattern, and using the updated CTM of the individual blocks to update the halo of the blocks adjacent to the individual blocks. In certain embodiments, the halo of a block among the plurality of blocks has a thickness around the block that is from 1.5 to 4 times the lithographic imaging proximity cutoff value of the substrate lithography system of RET.

[0104] In some embodiments, the calculations for each block are performed on a computing node accelerated by a graphics processing unit. In some embodiments, representing the target wafer pattern as an FSA includes applying a low-pass filter to the target wafer pattern. In some embodiments, the FSA of the target wafer pattern is band-limited to the spatial frequency cut-off value of the substrate lithography system and may optionally be sampled on a grid that satisfies the Nyquist criterion. In some embodiments, the target wafer pattern is for a mask layer of a semiconductor wafer.

[0105] In other example embodiments, a method for RET includes inputting a target wafer pattern that spans an entire design area. The entire design is segmented into a plurality of blocks, each block having a halo around the block. An attempted mask (which may be a CTM) for the entire design area is iterated until the attempted mask (e.g., CTM) meets the criteria for producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of blocks, the subset having two to all of the plurality of blocks, where the calculation is performed for each block in the subset and its halo. Each iteration also includes updating the attempted mask for the block, where all calculations for the subset are calculated before the next iteration. The subset may include two or more of the plurality of blocks, such as up to all of the blocks. For example, blocks that require further optimization or have not exceeded a certain iteration count may be included in the subset for the calculations of that iteration. Other blocks that have met the optimization criteria or have been iterated a certain number of times need not be included in each iteration.

[0106] In some embodiments, the attempted mask is a continuous tone mask (CTM), and the CTM is represented as a smooth function captured as an array of function samples (FSA), where the FSA is an array of function values (such as real numbers, complex numbers, or aggregates of numbers). The function values characterize the mask values at grid points.

[0107] In some embodiments of the method of FIG. 10B, the attempted mask may be represented in some way other than a CTM. For example, the attempted mask may be a modifiable mask having geometric shapes intended to produce the pattern, where the edges of each shape may be disrupted and manipulated near the target pattern edges.

[0108] In some embodiments, the predicted wafer pattern is represented as a smooth function captured as an array of function samples (FSA), where the FSA is an array of real values, complex numbers, or aggregates of numbers.

[0109] In some embodiments, the target wafer pattern is represented as a smooth function captured as an array of function samples (FSA), where the FSA is an array of real values, complex numbers, or a collection of numbers. The function values characterize the target wafer pattern values at grid points. Representing the target wafer pattern as an FSA may include applying a low-pass filter to the target wafer pattern. The FSA of the target wafer pattern may be band-limited to the spatial frequency cut-off value of the substrate lithography system and sampled on a grid that satisfies the Nyquist criterion.

[0110] In some embodiments, the calculation for each block further includes calculating cost and derivative data, which are based on comparing the predicted wafer pattern with the target wafer pattern, where the cost is also represented as a smooth function. In some embodiments, each iteration further includes updating the halo of the blocks adjacent to an individual block using the updated proposed mask of the individual block among a plurality of blocks. In some embodiments, the calculation is performed on a computing platform having a total memory of the set of all computing nodes of the computing platform, where the total memory of the set holds the target wafer pattern and the proposed mask for the entire design region during all iterations. Decomposition and boundary conditions

[0111] FFT means applying periodic boundary conditions (PBCs), which must be solved to use them successfully. The spatial localization of the substrate projection model means that the PBCs can be made to appear to be essentially harmless by adding the halo of adjacent mask regions to the region being worked on so that the convolution result is correct in the original region. The filter kernel that describes the substrate projection model is considered to be strictly band-limited in frequency, but its influence is also well-localized in space, at least when considering its weights. This is consistent with the idea of "lithographic imaging proximity effect". The lithographic imaging proximity range cut-off value r cuts 5 - 10 Mask values outside of 5 - 10 / NA do not affect what is printed in the region; thus, most issues regarding PBCs can be avoided by adding the halo and values of adjacent mask regions when calculating within the region.

[0112] To correctly calculate the projected image in the region, mask values are required in the surrounding halo (boundary layer) cut at depth r. The value r cut is the spatial localization distance. This is illustrated in FIG. 11A for a block with a halo region 1100, where a first boundary layer (halo) 1110 of thickness r cut is added to the block 1120 to enable calculation of the image intensity. The change in the mask value in the central image calculation region (block 1120) adds the image in that region to the image within the first halo region. This is because the light energy spreads within the region. The light projected through a particular portion of the mask will cause the energy to penetrate to the nearby substrate. The distance of the significant projected energy determines the halo distance. Therefore, in order to obtain the change in cost for the change in the mask value for the central region (block 1120), the image needs to be corrected and include the first halo 1110. In the present method, this condition is achieved by adding a second extended halo region 1130 of the mask value, as shown in FIG. 11B. In FIG. 11B, adding the second halo region 1130 obtains the correct image value for the extended central region (block 1120 with the first halo 1110), which in turn allows for the correct calculation of the functional derivative of the mask value within the central region (block 1120).

[0113] If the region being calculated has a boundary that is one of the outer boundaries of the entire layer, then a halo of a new mask region to be optimized should be added, and another to obtain the desired mask boundary value, such as complete penetration or blockage. The new mask region to be optimized will allow the present pattern representation modeling method to add sub-resolution assist features (SRAFs) to the layout near the edge, and its goal in this region will be to print nothing.

[0114] If everything is represented on the finest grid required, then all is well except for the possibly onerous memory requirements. Standard Fourier interpolation used to avoid blanket oversampling causes new ripple problems because of PBC. Fourier interpolation of resampling from a mask or image grid to, for example, a finer cost function grid can still be a problem because it is inherently non-local. Any mismatch caused by PBC will result in ripples that only decay as 1 / R, where R is the distance from the boundary. A solution must be found to mitigate the ripples, or the mask must be oversampled to the cost function grid, which increases the amount of memory required to store it by one or two orders of magnitude or more. Embodiments of the present disclosure solve this resampling problem by applying a localization filter, such as the ideal low-pass filter with a Gaussian envelope factor as previously discussed. Decomposition without stitching solution

[0115] There are two main data distribution options for distributed computing strategies to harness sufficient computing power and memory to handle constructing a band-limited continuous tone mask (CTM): 1-D strip decomposition or 2-D block decomposition. 1-D decomposition enables the 2-D FFT operation itself to be parallelized. This method implements 2-D decomposition but does not result in the stitching problems that occur in conventional methods.

[0116] 1-D decomposition requires a large amount of memory and there can be arithmetic precision problems in calculating the FFT for very large arrays. 1-D decomposition across multiple graphics processing units (GPUs), central processing units (CPUs), and computing nodes for the entire mask layer is intended to allow parallelization of the 2-D FFT within the mask layer. The "computing unit" for this decomposition is essentially the entire mask layer because everything will be treated as if it were done all at once. Specifically, any temporary quantities needed to compute the improved CTM will be calculated and held for the entire mask layer until their storage is released. Computing the entire mask layer all at once, there may be no stitching problems.

[0117] The 2-D FFT operation involves performing all the 1-D FFTs along one axis and then all the 1-D FFTs along the other axis. Thus, with strip decomposition, all the local 1-D FFTs are first performed (along the length of each strip), a communication step is performed to change the decomposition axis, and then all the 1-D FFTs are performed along the (now local) second axis.

[0118] In cases where there are many 2-D FFTs to be performed along with other computations, there is an opportunity to pipeline, which hides most of the communication burden in overlapping computations. The main challenges are storing to hold intermediate quantities for the entire mask layer on a fine grid and possible precision problems when calculating the FFT for very large arrays. One major advantage of computing across the entire mask layer is not stitching the strips back together, thus completely avoiding the stitching problems that plague the simplest 2-D decomposition methods.

[0119] In this disclosure, 2-D block decomposition does not directly process the entire mask layer all at once, but achieves the same effect without any stitching. 2-D decomposition localizes all computations to blocks (plus their halos), so these are the computational units. In some embodiments, the contributions to the total cost and the derivative of the cost with respect to the mask values for each block can be computed completely independently. The number of fine grid points similar to the cost density is temporary and only requires enough memory to hold the temporary values for several blocks working simultaneously. When all blocks have computed the energy and derivatives, the net result will be the same as if the entire mask layer were treated as a unit, and even the intermediate values for the whole need not be stored except for checkpoints for error recovery or debugging.

[0120] Optimization steps can be carried out across the entire mask layer at this point, followed by a communication phase to update the halo data for each adjacent block for the next iteration. The update can involve exchanging block data with adjacent blocks by memory sharing, local copying, by message passing in a distributed system, or by other means, and if the memory of adjacent blocks is an adjacent subarray of an array containing two blocks, it may not be necessary to exchange block data.

[0121] In some embodiments, each block is selected to allow its local computations to reside on a single node GPU, while allowing pipelined GPU computations and data transfers to and from main memory and device memory. The computations can be performed in double floating point precision, single floating point precision, half floating point precision, or other floating point precisions, or in various integer formats, according to the needs of speed, memory, and accuracy.

[0122] This method enables seamless optimization over very large domains and effectively eliminates the effects of PBC mismatches during interpolation, thus implementing a viable method of 2-D parallel decomposition where each block is a computational unit, where the temporary memory requirements are limited to those blocks being processed simultaneously, where the entire mask layer is optimized together, and where the memory requirements during optimization involve some quantity on the grid for the band-limited mask.

[0123] A 1-D example is presented in FIG. 12, which shows the interpolation of long-term data, such as Gaussian local interpolation, treating the data as four linearly contiguous blocks with overlapping halo regions. The lower curve is a thirteen-period sine curve evaluated at 1024 sample points, and the Gaussian width parameter used is s = 4 samples. The data is decomposed into four equal-sized blocks with overlapping halos of sixteen samples. For clarity, in FIG. 12(a), the four contiguous blocks are shown with a vertical offset, each block having its halo, with conventional Fourier interpolation to a 10-fold finer grid. Note the ringing at the end of each curve in the halo region of the blocks. FIG. 12(b) shows the curves recombined from the central block region for conventional Fourier interpolation and high-speed local Fourier interpolation. The difference between the curves is too small to be seen at this scale. For further study, in FIG. 12(c), the difference between the recombined Fourier interpolation curve and the ideal sine curve is plotted. The difference reaches a level of 1% at the block boundaries and shows a long distance to the center of each block. In contrast, the difference for the high-speed local Fourier interpolation shown in FIG. 12(d) reaches only a fraction of 10^-9 at the block boundaries and then decays extremely rapidly therefrom. Computing system

[0124] The computing and processing steps described in this disclosure can be implemented using a general-purpose computer with suitable computer software as a computing device. Multiple computers or processor cores can also be used in parallel. In some embodiments, dedicated hardware devices used singly or in multiplicity can be used to perform the calculations of one or more steps at a speed greater than that of using a general-purpose computer or processor core. In certain embodiments, the dedicated hardware device can be a graphics processing unit (GPU). In other embodiments, other dedicated hardware devices can be used as co-processors, such as a digital signal processor (DSP), a tensor processing unit (TPU), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC).

[0125] FIG. 13 is a block diagram of an example of a computing hardware device 1300 that can be used to perform the calculations described in this disclosure. The computing hardware device 1300 includes a central processing unit (CPU) 1302 with an attached main memory 1304. The CPU 1302 can include, for example, eight processing cores, thus enhancing the performance of any part of the multi-threaded computer software. The size of the main memory 1304 can be, for example, 64 gigabytes. The CPU 1302 is connected to a high-speed peripheral component interconnect (PCIe) bus 1320. A graphics processing unit (GPU) 1314 can also be connected to the PCIe bus 1320. In the computing hardware device 1300, the GPU 1314 may or may not be connected to a graphics output device, such as a video monitor. If not connected to the graphics output device, the GPU 1314 can be used only as a high-speed parallel computing engine. Compared with using the CPU 1302 for all calculations, the computing software can achieve significantly higher performance by using the GPU 1314 for a part of the calculations. The CPU 1302 communicates with the GPU 1314 via the PCIe bus 1320. In other embodiments (not shown), the GPU 1314 can be integrated with the CPU 1302 instead of being connected to the PCIe bus 1320. A disk controller 1308 can also be attached to the PCIe bus 1320, where, for example, two disks 1310 are connected to the disk controller 1308. Finally, a local area network (LAN) controller 1312 can also be attached to the PCIe bus and provide gigabit Ethernet (GbE) connectivity to other computers. In some embodiments, the computer software and / or design data are stored on the disks 1310. In other embodiments, the computer program or design data or both the computer program and design data can be accessed from other computers or file server hardware via the GbE Ethernet or other connectivity solutions such as InfiniBand.

[0126] FIG. 14 is another embodiment of a system for performing the calculations of this embodiment. The system 1400 can also be referred to as a computing design platform (CDP) and includes a main node 1410, an optional viewing node 1420, an optional network file system 1430, and a node 1440 with GPU capabilities. The viewing node 1420 may not exist or alternatively may have only one node, or may have other numbers of nodes. The node 1440 with GPU capabilities can include one or more nodes with GPU capabilities. Each node 1440 with GPU capabilities can be, for example, a GPU, a CPU, a paired GPU and CPU, multiple GPUs for a CPU, or other combinations of GPUs and CPUs. The GPU and / or CPU can be on a single chip, such as a GPU chip with a CPU, where the CPU is accelerated by the GPU on the chip, or a CPU chip with a GPU that accelerates the CPU. The GPU can be replaced by other co-processors.

[0127] The master node 1410 and the viewing node 1420 can be connected to the network file system 1430 and the node 1440 with GPU capabilities via switches and high-speed networks such as networks 1450, 1452, and 1454. In an example embodiment, network 1450 can be a 56 Gbps network, 1452 can be a 1 Gbps network, and 1454 can be a management network. In various embodiments, there can be fewer or more numbers of such networks, and there can be various combinations of network types such as high-speed and low-speed. The master node 1410 controls the CDP 1400. An external system can be connected to the master node 1410 from the external network 1460. In some embodiments, work is published from the external system. Before publishing the work, the data of the work is loaded onto the network file system 1430, and the program is used to dispatch and monitor tasks on the node 1440 with GPU capabilities. The progress of the work can be seen via a graphical interface such as the viewing node 1420 or by the user on the master node 1410. Tasks are executed on the CPU using a script that runs a suitable executable on the CPU. The executable connects to the GPU, runs various computing tasks, and then disconnects from the GPU. The master node 1410 can also be used to deactivate any faulty node 1440 with GPU capabilities and then operate as if the node does not exist.

[0128] In some embodiments, a system for mask enhancement technology includes a computer processor configured to: receive a target wafer pattern to be used for mask enhancement technology; and compute a function sample array (FSA) for the target wafer pattern, where the FSA of the target wafer pattern is a smooth function. The computer processor is also configured to: compute a continuous tone mask (CTM), where the CTM is represented as the smooth function captured as the function sample array (FSA); and compare the target wafer pattern with the predicted wafer pattern generated by the CTM. In a further embodiment, the target wafer pattern is divided into a plurality of blocks, and the computer processor is further configured to compute the cost and derivative data for each of the plurality of blocks, and the computation of the plurality of blocks is performed in a distributed procedure. The cost and derivative data are based on comparing the target wafer pattern with the predicted wafer pattern generated by the CTM.

[0129] In a general embodiment, the system is a computer processor which, in some embodiments, may include a graphics processing unit or other co-processors for performing distributed computing, such as parallel processing. In some embodiments, the graphics processing unit or other co-processors may be configured to interconnect with each other for fast communication. The computer processor is configured to receive a target pattern to be used for mask enhancement technology and generate a target pattern function for the target pattern, where the target pattern function is an FSA. The computer processor is also configured to generate a CTM and compare the target pattern function with a predicted pattern function generated by the CTM. The CTM is a smoothing function. Legalization

[0130] In this disclosure, the CTM can be transformed into a mask that can be reliably manufactured. The CTM (i.e., the proposed mask) can be modified to ensure that it is physically realizable.

[0131] In some embodiments, iterative optimization of the CTM uses a cost related to the reliable manufacturability of the mask shape. In some embodiments, a set of constraints related to the reliable manufacturability of the mask shape prohibits considering certain shapes. In some embodiments, after satisfying the cost criterion, the mask shape can be further modified to conform to the exact specifications of mask manufacturability. The costs and criteria of mask manufacturability include but are not limited to minimum size and pitch, maximum allowable curvature, minimum dose margin, and mask edge error factor (MEEF). Optimization of MEEF and other factors is disclosed in U.S. Patent No. 8,719,739, "Method and System for Forming Patterns Using Charged Particle Beam Lithography", which is owned by the assignee of the present application.

[0132] In addition to incorporating the mask manufacturability costs and constraints during ILT, MPC and other mask reliability enhancement and mask data preparation steps are performed during ILT. The combined effect can be referred to as mask wafer co-optimization. In some embodiments, the technique for achieving mask wafer co-optimization is the dual simulation disclosed in U.S. Patent No. 9,038,003, "Method and System for Critical Dimension Uniformity Using Charged Particle Beam Lithography", which is owned by the assignee of the present application.

[0133] The CTM has a continuous range of values that must be converted into contiguous regions with an allowable transparency value. The contiguous regions with a fixed transparency value correspond to shapes on the manufacturable mask. The allowable transparency value depends on the type of mask; for example, it is conventionally 0 or 1 for a chromium-on-glass mask, or and 1 for a 6% attenuated phase-shift mask.

[0134] In an embodiment, this conversion is achieved via regularization, where regularization adds terms that favor the manufacturable mask to the cost.

[0135] The main regularization required favors masks that are very close to the allowable transparency value everywhere, with the possible exception of the transition from one allowable value to another that may contain intermediate values. In an embodiment, a term is introduced, which shall be referred to as the "value shaping term", which favors the allowable values and a short transition between regions with one value and boundary regions with another value.

[0136] The CTM selected using the value shaping term in optimization may contain shapes that are difficult to manufacture reliably. In an embodiment, a second term is introduced, which favors shapes with good dose margins during mask manufacturing. This term can use the PSF to measure how much the shape has changed and calculate the cost based on the change.

[0137] From the above discussion, it will be understood that the present invention can be embodied in many example forms, including but not limited to the following: Example 1, a method for optical mask enhancement technology (RET), the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smooth function captured as an array of function samples (FSA), where the FSA is an array of function values that can be real numbers, complex numbers, or a set of numbers; and providing a continuous tone mask (CTM), where the CTM is used to generate the predicted wafer pattern that spans an entire design area. Example 2, the method as in Example 1, the method further comprising: dividing the entire design area into a plurality of blocks; and iterating the CTM of the entire design area until the CTM meets the criteria for generating the target wafer pattern, where each iteration includes: calculating the predicted wafer pattern for a subset of the plurality of blocks; where all blocks in the subset are calculated before the next iteration. Example 3, a method as in Example 2, wherein the calculation is performed on a computing platform having a total memory of a set of all computing nodes of the computing platform, and wherein the total memory of the set holds the target wafer pattern and the CTM of the entire design region during all iterations. Example 4, a method as in Example 2, wherein the calculation further comprises: calculating cost and derivative data, the cost and the derivative data being based on comparing the predicted wafer pattern with the target wafer pattern, wherein the cost is also expressed as a smooth function; and updating the CTM of the block using the cost and the derivative data. Example 5, a method as in Example 4, the method further comprising representing the CTM as a smooth function captured as an array of function samples (FSA), wherein the FSA is an array of function values that can be real numbers, complex numbers, or a collection of numbers. Example 6, a method as in Example 2, wherein: each block has a halo region around the block; the calculation is performed for each block and its halo region; and each iteration further comprises: after calculating the predicted wafer pattern, updating the CTM of an individual block in a subset of blocks; and using the updated CTM of the individual block to update the halo regions of the blocks adjacent to the individual block. Example 7, a method as in Example 6, wherein the halo region has a thickness around the block, the thickness being 1.5 to 4 times a lithographic imaging proximity cutoff value of a substrate lithography system for the RET. Example 8, a method as in Example 2, wherein the calculation for each block is performed on a computing node accelerated by a graphics processing unit. Example 9, a method as in Example 1, wherein representing the target wafer pattern as an FSA includes applying a low-pass filter to the target wafer pattern. Example 10, a method as in Example 1, wherein the FSA of the target wafer pattern is band-limited to a spatial frequency cutoff value of a substrate lithography system and is sampled on a grid satisfying a Nyquist criterion. Example 11, a method as in Example 1, wherein the target wafer pattern is for a mask layer of a semiconductor wafer. Example 12, a method for optical mask enhancement technology (RET), the method comprising: a) inputting a target wafer pattern that spans an entire design region; b) Divide the entire design area into a plurality of blocks, each block having a halo around the block; c) Iterate on a proposed mask for the entire design area until the proposed mask meets the criteria for generating the target wafer pattern, where each iteration includes: Calculate a predicted wafer pattern for a subset of the plurality of blocks, the subset having two to all of the plurality of blocks, where the calculation is performed for each block in the subset and its halo; and Update the proposed mask for the block; where all blocks in the subset are calculated before the next iteration. Example 13, the method as in Example 12, the method further comprising representing the predicted wafer pattern as a smooth function captured as a function sample array (FSA), where the FSA is an array of function values, and the function values can be real numbers, complex numbers, or a collection of numbers. Example 14, the method as in Example 12, the method further comprising representing the target wafer pattern as a smooth function captured as a function sample array (FSA), where the FSA is an array of function values, and the function values can be real numbers, complex numbers, or a collection of numbers. Example 15, the method as in Example 14, where representing the target wafer pattern as an FSA includes applying a low-pass filter to the target wafer pattern. Example 16, the method as in Example 14, where the FSA is band-limited to a spatial frequency cut-off value of a substrate lithography system and sampled on a grid satisfying a Nyquist criterion. Example 17, the method as in Example 12, where the proposed mask is a continuous tone mask (CTM), and represent the CTM as a smooth function captured as a function sample array (FSA), where the FSA is an array of function values, and the function values can be real numbers, complex numbers, or a collection of numbers. Example 18, the method as in Example 12, where the calculation for each block further includes calculating cost and derivative data, the cost and the derivative data being based on comparing the predicted wafer pattern with the target wafer pattern, where the cost is also represented as a smooth function. Example 19, the method as in Example 12, where each iteration further includes using the updated proposed mask of an individual block in the plurality of blocks to update the halo of the blocks adjacent to the individual block. Example 20, a method as in Example 12, wherein the calculation is performed on a computing platform having a total memory of a set of all computing nodes of the computing platform, and the total memory of the set holds the target wafer pattern and the proposed mask for the entire design region during all iterations. Example 21, a system for optical mask enhancement technology (RET), the system comprising: a computer processor configured to: receive a target wafer pattern for use in optical mask enhancement technology; compute a function sample array (FSA) for the target wafer pattern, the FSA of the target wafer pattern being a smooth function; compute a continuous tone mask (CTM), wherein the CTM is represented as a smooth function captured as a function sample array (FSA); and compare the target wafer pattern with a predicted wafer pattern generated by the CTM. Example 22, a system as in Example 21, wherein: the target wafer pattern is segmented into a plurality of blocks; the computer processor is further configured to compute a cost and derivative data for each of the plurality of blocks, the computing of the plurality of blocks being performed in a distributed program; and the cost and the derivative data are based on comparing the target wafer pattern with the predicted wafer pattern generated by the CTM.

[0138] Reference has been made in detail to embodiments of the disclosed invention, and one or more examples of the invention are shown in the accompanying drawings. Each example has been provided by way of explanation of the technology, and not as a limitation thereof. In fact, although the specification has been described in detail with respect to specific embodiments of the invention, it should be understood that those skilled in the art can readily conceive of changes, variations, and equivalents of these embodiments upon obtaining an understanding of the above. For example, features shown or described as part of one embodiment can be used with another embodiment to yield yet another embodiment. Accordingly, the subject matter is intended to cover all such modifications and variations within the scope of the appended claims and their equivalents. Such and other modifications and variations of the invention can be practiced by those of ordinary skill in the art without departing from the scope of the invention, which is more particularly set forth in the appended claims. In addition, those of ordinary skill in the art will understand that the above description is by way of example only and is not intended to limit the invention.

[0139] 100: Semiconductor manufacturing process 110, 120, 150, 160, 710, 720, 730, 740, 750, 910, 920, 930, 935, 940, 950, 960, 970, 980, 990, 995, 1010, 1011, 1020, 1021, 1030a / b...n, 1041, 1050a / b…n, 1051, 1060a / b…n, 1061, 1070, 1091: Step 130: RET Step 140: Mask Data Preparation (MDP) Step 200, 250: Smoothing Function 210: Grid Lines 220: Grid Point Positions 230: Plane 235: Graph 237: Grid Spacing 239: Transition 240: Target Geometry 260: Pattern 700, 900: Flow Chart 711: Target Pattern 721: Function 731: Calculate CTM 820, 830: Smooth Curve 820, 832: Curve 921: Marked Pattern Geometry FSA 931, FSA 951B, FSA 952B: Target Wafer Pattern 941: Initial CTM FSA 951A, FSA 952A: Predicted Pattern 1100: Halo Region 1110: First Boundary Layer (Halo) 1120: Central Region (Block) 1130: Second Halo Region 1300: Computing Hardware Device 1302, 1314: GPU 1304: Main Memory 1308: Disk Controller 1310: Disk 1312: Local Area Network (LAN) Controller 1320: PCIe Bus 1400: System 1410: Main Node 1420: Viewing Node 1430: Network File System 1440: Node with GPU Capability 1450, 1452, 1454: Network

Claims

1. A method for mask enhancement (RET) comprising: inputting a target wafer pattern spanning an entire design region; iterating over a proposed mask for one of the entire design regions until the proposed mask satisfies a criterion for generating the target wafer pattern, wherein each iteration comprises: calculating a predicted wafer pattern from the proposed mask; wherein the calculation comprises calculating cost and derivative data based on a comparison of the predicted wafer pattern with the target wafer pattern; and wherein the cost further comprises mask manufacturability specifications.

2. The method of claim 1, wherein the specifications of mask manufacturability include at least one of minimum size, minimum spacing, maximum curvature, or minimum dose margin.

3. The method of claim 1, wherein the proposed mask is a continuous tone mask (CTM), and wherein the CTM is represented by a continuous range of values.

4. The method of claim 3, wherein the range of continuous values ​​is converted into adjacent areas of permissible penetration values, wherein such adjacent areas correspond to a shape on a manufacturable mask.

5. The method of claim 1, further comprising dividing the entire design area into a plurality of blocks, each block having a halo around it, wherein the calculation is performed for each block and its halo.

6. The method of claim 5, wherein each iteration further comprises updating the proposed mask of one of the plurality of blocks, and using the updated proposed mask of the one of the plurality of blocks to update the halo region of the block adjacent to the one of the blocks, wherein all the blocks of the plurality of blocks are computed before the next iteration.

7. The method of claim 1, wherein the computation is performed on a computing platform having a total memory of a set of all computing nodes of the computing platform, wherein the total memory of the set holds the target wafer pattern and the proposed mask of the entire design region during all iterations.

8. The method of request item 1, wherein the calculation further includes masking procedure correction (MPC).

9. The method of claim 8, wherein the MPC includes one or more of corrected linearity, enhanced critical dimension uniformity (CDU), and enhanced line edge roughness (LER) as a measure of resilience to manufacturing variations.

10. A method for manufacturing a semiconductor device, comprising: iterating over a continuous tone mask (CTM) to optimize the CTM for reliable manufacturability in achieving a mask shape, wherein the CTM is represented by a continuous range of values, and wherein each iteration comprises: calculating a predicted wafer pattern from the CTM; and calculating cost and derivative data based on a comparison of the predicted wafer pattern with a target wafer pattern.

11. The method of claim 10, wherein the manufacturability of the mask shape includes at least one of minimum size, minimum spacing, maximum curvature, or minimum dose margin.

12. A method for photomask enhancement (RET) in a lithography system, the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured by a function sample array (FSA), wherein the FSA is an array of sampled values ​​of the smoothing function, the smoothing function being a continuously differentiable function; providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning an entire design area; and calculating the predicted wafer pattern from the CTM, wherein the calculation comprises: calculating a cost based on comparing the predicted wafer pattern with the target wafer pattern, wherein the cost is represented as a third smoothing function; and updating the CTM using the cost.

13. The method of claim 12, further comprising: determining the CTM, wherein the CTM captures the value of a continuously varying amplitude penetration coefficient graph.

14. The method of claim 12, wherein the FSA band is limited to a spatial frequency cutoff value of a substrate lithography system and is sampled on a grid that satisfies a Nyquist criterion.

15. The method of claim 12, further comprising inputting a target geometry, wherein the FSA of the target wafer pattern is generated from the input target geometry.

16. The method of claim 12, wherein the calculation further comprises: calculating a derivative data based on comparing the predicted wafer pattern with the target wafer pattern.

17. The method of claim 12, further comprising iterating the CTM over the entire design area until the CTM meets the criteria for generating the target wafer pattern.

18. The method of claim 17, wherein the computation is performed on a computing platform comprising a plurality of computing nodes having a total memory of one set of all computing nodes of the computing platform, wherein the total memory of the set holds the target wafer pattern and the CTM of the entire design region during all iterations.

19. The method of claim 17, further comprising: dividing the entire design region into a plurality of blocks, wherein the iteration comprises computing the predicted wafer pattern for a subset of the plurality of blocks; wherein all blocks in the subset are computed before the next iteration.

20. The method of claim 19, wherein each block in the subset of the plurality of blocks has a halo region around the block, wherein the calculation for each block includes its halo region, and wherein each iteration further comprises: updating the CTM of the individual block after calculating the predicted wafer pattern of the individual block in the subset of the blocks; and using the updated CTM of the individual block to update the halo regions of the blocks adjacent to the individual block.

21. The method of claim 20, wherein the halo region has a thickness around the block, the thickness being 1.5 to 4 times the lithography proximity cutoff value of a substrate lithography system of the RET.

22. The method of claim 19, wherein the computation of one block in the subset of the plurality of blocks is performed on a computing node accelerated by a graphics processing unit.

23. A method for a photomask enhancement technique (RET) in a lithography system, the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured by a function sample array (FSA), wherein the FSA is an array of sampled values ​​of the smoothing function, the smoothing function being a continuously differentiable function; providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning an entire design area; and representing the CTM as a second smoothing function captured by a second function sample array (FSA), wherein the second FSA is an array of sampled values ​​of the second smoothing function, the second smoothing function being a continuously differentiable function.

24. The method of claim 23, further comprising determining the CTM, wherein the CTM captures the value of a continuously varying amplitude penetration coefficient graph.

25. The method of claim 23, wherein the FSA band is limited to a spatial frequency cutoff value of a substrate lithography system and is sampled on a grid that satisfies a Nyquist criterion.

26. The method of claim 23 further includes inputting a target geometry, wherein the FSA of the target wafer pattern is generated from the input target geometry.

27. A method for photomask enhancement (RET) in a lithography system, the method comprising: representing a target wafer pattern or a predicted wafer pattern as a smoothing function captured by a function sample array (FSA), wherein the FSA is an array of sampled values ​​of the smoothing function, the smoothing function being a continuously differentiable function; and providing a continuous tone mask (CTM), wherein the CTM is used to generate the predicted wafer pattern, the predicted wafer pattern spanning an entire design area; wherein the FSA of the target wafer pattern or the predicted wafer pattern has a plurality of grid points, and the grid points are spaced apart by a grid spacing, wherein the grid spacing is set by a transition distance less than the lithography resolution of the lithography system.

28. The method of claim 27, further comprising determining the CTM, wherein the CTM captures the value of a continuously varying amplitude penetration coefficient graph.

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