Timing controller and operation method thereof

Abstract

This invention provides a timing controller and its operating method. The timing controller includes a timing signal generation section and a screen signal generation section. The timing signal generation section generates a clock signal for multiple source drivers used to drive a display panel. The screen signal generation section generates a screen signal synchronized with the clock signal. The screen signal includes multiple data segments corresponding to different source drivers. The timing controller adjusts the phase of at least one of the clock signal and the screen signal, so that the clock signal has different time deviations for different data segments, to adapt to the different transmission path delays between the timing controller and these source drivers.

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a timing controller and its operating method. [Previous Technology]

[0002] Point-to-multipoint (multi-drop) architecture is widely used in various electronic devices. For example, in a display device, the data transmission interface between different integrated circuits may be a Low-Voltage Differential Signaling (LVDS) interface or a mini-LVDS interface. Mini-LVDS is a multi-drop architecture. A multi-drop architecture means that multiple source drivers receive signals from a timing controller (TCON) through the same transmission path (e.g., a clock signal transmission path and a screen signal transmission path). The timing controller provides clock signals to the multiple source drivers through the same clock signal transmission path. Similarly, the timing controller provides data signals to the multiple source drivers through the same screen signal transmission path. Each source driver de-latches the screen signal data based on the phase of the clock signal. Therefore, the phase relationship (timing skew) between the clock signal and the screen signal is related to the accuracy of the latch data.

[0003] In practical applications of multi-drop architecture, the clock signal transmission path and the screen signal transmission path often have different transmission path delays. Due to these differences, the clock and screen signals received by different source drivers have different time deviations. For example, suppose the time deviation between the clock and screen signals received by the first source driver is a first deviation, while the time deviation between the clock and screen signals received by the second source driver is a second deviation. The first source driver may correctly latch the screen signal data based on the first deviation, but the second source driver may incorrectly latch the screen signal data based on the second deviation. [Summary of the Invention]

[0004] The present invention provides a timing controller and its operation method to output clock signals and screen signals to multiple source drivers for driving a display panel.

[0005] In one embodiment of the present invention, the timing controller includes a timing signal generation section and a screen signal generation section. The timing signal generation section generates a clock signal for driving a plurality of source drivers of a display panel. The screen signal generation section generates a screen signal synchronized with the clock signal. The screen signal includes a plurality of data segments corresponding to different source drivers. The timing controller adjusts the phase of at least one of the clock signal and the screen signal, so that the clock signal has different timing skews for different data segments, to adapt to the different transmission path delays between the timing controller and these source drivers.

[0006] In one embodiment of the present invention, the above-described operation method includes: generating a clock signal by a timing controller to a plurality of source drivers for driving a display panel; generating a screen signal synchronized with the clock signal by the timing controller, wherein the screen signal includes a plurality of data segments corresponding to different source drivers; and adjusting the phase of at least one of the clock signal and the screen signal so that the clock signal has different time deviations for different data segments, in order to adapt to the different transmission path delays between the timing controller and these source drivers.

[0007] Based on the above, the timing controller described in the embodiments of the present invention adjusts the phase of at least one of the clock signal and the screen signal, so that the clock signal has different time deviations for different data segments. By adjusting the time deviations of different data segments, the timing controller can compensate for the different transmission path delays between the timing controller and these source drivers, thereby avoiding the source drivers from incorrectly latching the screen signal data.

[0008] In order to make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are given in conjunction with the accompanying drawings.

Implementation Method

[0010] The term "coupled (or connected)" as used throughout the entire specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout the entire specification (including the claims) are used to name elements or distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of elements, nor to limit the order of elements. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0011] FIG1 is a schematic circuit block diagram of a display device 100 according to an embodiment of the present invention. The display device 100 shown in FIG1 includes a timing controller (TCON) 110, multiple source drivers (e.g., source drivers 120_1, 120_2, and 120_3 shown in FIG1), and a display panel 130. The actual number of source drivers in the display device 100 can be determined according to the actual application. Source drivers 120_1 to 120_3 are used to drive multiple data lines (or source lines, not shown) of the display panel 130. In the embodiment shown in FIG1, a point-to-multipoint (multi-drop) architecture is applied between the timing controller 110 and the source drivers 120_1 to 120_3. The so-called multi-drop architecture means that the timing controller 110 provides the clock signal CLK1 to the multiple source drivers 120_1 to 120_3 through the same clock signal transmission path. Similarly, timing controller 110 provides screen signal DATA1 (data signal) to multiple source drivers 120_1 to 120_3 through the same screen signal transmission path. For example, timing controller 110 transmits clock signal CLK1 and screen signal DATA1 to source drivers 120_1 to 120_3 through a mini-LVDS interface or other multi-drop architecture interface. Each source driver 120_1 to 120_3 latches the data of screen signal DATA1 based on the phase of clock signal CLK1. Therefore, the phase relationship (i.e., timing skew) between clock signal CLK1 and screen signal DATA1 is related to the correctness of latching the data.

[0012] Figure 2 is a schematic diagram illustrating the time deviation between the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3, according to an embodiment, when "the time deviation between the clock signal CLK1 output by the timing controller 110 and the screen signal DATA1 is fixed". The horizontal axis of Figure 2 represents time. The upper part of Figure 2 shows a timing diagram of the clock signal CLK1 and the screen signal DATA1 output by the timing controller 110. The screen signal DATA1 includes multiple data segments corresponding to different source drivers 120_1 to 120_3, such as data segments D21, D22 and D23 shown in Figure 2. Data segment D21 is used to provide data to source driver 120_1, data segment D22 is used to provide data to source driver 120_2, and data segment D23 is used to provide data to source driver 120_3. The screen signal DATA1 contains one or more sets of differential signals (taking three sets of differential signals LV21, LV22, and LV23 as an example) which are provided to the screen signal transmission path. In the example shown in Figure 2, the time deviation of the clock signal CLK1 output by the timing controller 110 in different data segments D21 to D23 is the same deviation amount S20.

[0013] The lower part of Figure 2 shows the timing diagram of the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3. In the actual application scenario of multi-drop architecture, the clock signal transmission path and the screen signal transmission path often have different transmission path delays. Due to the difference in transmission paths, the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3 have different time deviations. For example, the time deviation between the clock signal CLK1 and the screen signal DATA1 received by source driver 120_1 is deviation S21, the time deviation between the clock signal CLK1 and the screen signal DATA1 received by source driver 120_2 is deviation S22, and the time deviation between the clock signal CLK1 and the screen signal DATA1 received by source driver 120_3 is deviation S23. Source driver 120_2 may correctly latch the data of screen signal DATA1 based on the deviation amount S22, but source drivers 120_1 and 120_3 may incorrectly latch the data of screen signal DATA1 based on the deviation amounts S21 and S23.

[0014] Even if the timing controller 110 fine-tunes the time deviation of the clock signal CLK1 in the same direction (e.g., to the right), the adjusted time deviation of the clock signal CLK1 still cannot simultaneously satisfy each source driver 120_1 to 120_3. For example, adjusting the time deviation of the clock signal CLK1 to the right (i.e., shortening the deviation S20 shown in the upper part of FIG2) may be beneficial for the source driver 120_1 to correctly latch the data of the screen signal DATA1, but may not be applicable to the source drivers 120_2 to 120_3. Conversely, increasing the deviation S20 shown in the upper part of FIG2 may be beneficial for the source driver 120_3 to correctly latch the data of the screen signal DATA1, but may not be applicable to the source drivers 120_1 to 120_2.

[0015] The timing controller 110 includes a screen signal generation section 111 and a timing signal generation section 112. Depending on the design, in some embodiments, the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 may be implemented as hardware circuitry. In other embodiments, the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 may be implemented as hardware, firmware, software (i.e., a program), or a combination of the foregoing.

[0016] In terms of hardware, the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 described above can be implemented as logic circuits on an integrated circuit. For example, the related functions of the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The related functions of the timing controller 110, the screen signal generation section 111 and / or the timing signal generation section 112 can be implemented as hardware circuits, such as various logic blocks, modules and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0017] In software and / or firmware form, the functions of the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 can be implemented using programming codes. For example, the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. Electronic devices (such as computers, CPUs, hardware controllers, microcontrollers, hardware processors, or microprocessors) can read and execute the programming code from the non-transitory machine-readable storage medium to realize the related functions of the timing controller 110, the screen signal generation section 111, and / or the timing signal generation section 112.

[0018] FIG3 is a schematic flowchart of an operation method of a display device according to an embodiment of the present invention. Referring to FIG1 and FIG3, in step S310, the timing signal generation section 112 generates a clock signal CLK1 to a plurality of source drivers 120_1 to 120_3 for driving the display panel 130. The screen signal generation section 111 generates a screen signal DATA1 synchronized with the clock signal CLK1. The screen signal DATA1 includes a plurality of data segments corresponding to different source drivers 120_1 to 120_3.

[0019] Figure 4 is a schematic diagram illustrating the time skew between the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3 when the time skew between the clock signal CLK1 output by the timing controller 110 and the screen signal DATA1 is adapted to the different transmission path delays between the timing controller 110 and different source drivers 120_1 to 120_3, according to an embodiment of the present invention. The horizontal axis of Figure 4 represents time. The upper part of Figure 4 shows a timing diagram of the clock signal CLK1 and the screen signal DATA1 output by the timing controller 110.

[0020] The screen signal DATA1 contains one or more sets of differential signals (taking three sets of differential signals LV21, LV22, and LV23 as an example) that are provided together to the screen signal transmission path. The screen signal DATA1 includes multiple data segments corresponding to different source drivers 120_1 to 120_3, such as data segments D41, D42, and D43 shown in Figure 4. Data segment D41 is provided to source driver 120_1, data segment D42 is provided to source driver 120_2, and data segment D43 is provided to source driver 120_3.

[0021] In step S320, the timing controller 110 adjusts the phase of at least one of the clock signal CLK1 and the screen signal DATA1, so that the clock signal CLK1 has different time deviations for different data segments D41 to D43, in order to adapt to the different transmission path delays between the timing controller 110 and different source drivers 120_1 to 120_3. In the example shown in FIG4, the time deviation of the clock signal CLK1 output by the timing controller 110 in data segment D41 is adaptively adjusted to a deviation amount S41, the time deviation of the clock signal CLK1 in data segment D42 is adaptively adjusted to a deviation amount S43, and the time deviation of the clock signal CLK1 in data segment D43 is adaptively adjusted to a deviation amount S45.

[0022] For example, as shown in Figure 4, the clock signal CLK1 includes a first clock segment corresponding to data segment D41, a second clock segment corresponding to data segment D42, and a third clock segment corresponding to data segment D43. The timing controller 110 adjusts the phase of the first clock segment of the clock signal CLK1 to a first phase, adjusts the phase of the second clock segment of the clock signal CLK1 to a second phase different from the first phase, and adjusts the phase of the third clock segment of the clock signal CLK1 to a third phase different from the first and second phases, so that the clock signal CLK1 has different time deviations S41, S43, and S45 for different data segments D41 to D43.

[0023] For another example, the timing controller 110 adjusts the phase of data segment D41 of the screen signal DATA1 to a first phase, adjusts the phase of data segment D42 of the screen signal DATA1 to a second phase different from the first phase, and adjusts the phase of data segment D43 of the screen signal DATA1 to a third phase different from the first and second phases. Therefore, the timing controller 110 can make the clock signal CLK1 have different time deviations S41, S43, and S45 for different data segments D41 to D43.

[0024] The lower part of Figure 4 shows a timing diagram of the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3. In the actual application scenario of multi-drop architecture, the clock signal transmission path and the screen signal transmission path often have different transmission path delays. Because the timing controller 110 has adaptively adjusted the time deviation of the clock signal CLK1 to different deviations S41, S43 and S45 in different data segments D41 to D43, the time deviation between the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3 can be optimized.

[0025] For example, the time deviation between the clock signal CLK1 received by the source driver 120_1 and the screen signal DATA1 is deviation S42, the time deviation between the clock signal CLK1 received by the source driver 120_2 and the screen signal DATA1 is deviation S44, and the time deviation between the clock signal CLK1 received by the source driver 120_3 and the screen signal DATA1 is deviation S46. Because the timing controller 110 has adaptively adjusted the time deviation of the clock signal CLK1 to different deviations S41, S43 and S45 in different data segments D41 to D43, the time deviations S42, S44 and S46 between the clock signal CLK1 and the screen signal DATA1 received by different source drivers 120_1 to 120_3 can all approach the optimal deviation. Source driver 120_1 correctly latches the data of screen signal DATA1 based on the optimized deviation amount S42, source driver 120_2 correctly latches the data of screen signal DATA1 based on the optimized deviation amount S44, and source driver 120_3 correctly latches the data of screen signal DATA1 based on the optimized deviation amount S46.

[0026] In summary, the timing controller 110 adjusts the phase of at least one of the clock signal CLK1 and the screen signal DATA1, so that the clock signal CLK1 has different time deviations S41, S43 and S45 for different data segments D41 to D43. By adjusting the time deviations S41, S43 and S45 of different data segments D41 to D43, the timing controller 110 can compensate for the different transmission path delays between the timing controller 110 and these source drivers 120_1 to 120_3, thereby avoiding the source drivers 120_1 to 120_3 from incorrectly latching the data of the screen signal DATA1.

[0027] In the embodiment shown in FIG4, there is a stop period SP41 between the output period of data segment D41 and the output period of data segment D42, and a stop period SP42 between the output period of data segment D42 and the output period of data segment D43. The timing controller 110 stops toggle the clock signal CLK1 during the stop periods SP41 and SP42. The timing controller 110 can also set the signal characteristics of at least one of the clock signal CLK1 and the screen signal DATA1 based on at least one signal characteristic parameter during the stop periods SP41 and SP42. Based on practical design, the signal characteristics include at least one of phase, slew rate, swing, and pre-emphasis.

[0028] Figure 5 is a waveform diagram of the signal output by the timing controller 110 according to an embodiment of the present invention. The horizontal axis of Figure 5 represents time. The slew rate and pre-emphasis are marked in the pulse shown on the left side of Figure 5, and the amplitude is marked in the pulse shown on the right side of Figure 5.

[0029] During a stop period, the timing controller 110 can set the signal characteristics (e.g., phase, slope, amplitude, and pre-enhancement at least one of) of the clock signal CLK1 and the screen signal DATA1 based on at least one signal characteristic parameter of SP41 and SP42. Through adaptive adjustment of the signal characteristics, the timing controller 110 can disperse the signal intensity in the frequency domain or time domain, thereby reducing the energy of electromagnetic interference (EMI). At the same time, because the amplitude of the shorter transmission path is reduced, the power consumption of the timing controller 110 can also be reduced, thus providing the advantage of power reduction.

[0030] Furthermore, the timing controller 110 described in the embodiment of Figure 3 can overcome the high-speed transmission problem by being paired with conventional source drivers available on the market. The timing controller 110 adjusts the clock skew (CLK skew) for each source driver. When paired with a corresponding source driver, the timing controller 110 can define a golden key and hand-shake mechanism for the transmitted data content. Based on this, the timing controller 110 can automatically adjust the optimal clock skew for each source driver, thereby increasing ease of use.

[0031] FIG6 is a circuit block diagram of a timing controller 110 according to an embodiment of the present invention. The timing controller 110 shown in FIG6 can be one of many embodiments of the timing controller 110 shown in FIG1. ​​The timing controller 110 shown in FIG6 can be referred to the relevant descriptions in FIG1 and FIG3-5. In the embodiment shown in FIG6, the timing controller 110 includes a screen signal generation section 111, a timing signal generation section 112, a phase circuit 113, a selection circuit 114_1, a selection circuit 114_2, a selection circuit 114_3, a selection circuit 114_4, and a control circuit 115. The control circuit 115 outputs control signals CS61, CS62, CS63, and CS64 to the selection circuits 114_1-114_4 to control the routing of the selection circuits 114_1-114_4.

[0032] Phase circuit 113 generates multiple candidate pulse trains with different phases and sends them to selection circuits 114_1 to 114_4. Selection circuits 114_1 to 114_4 are coupled to phase circuit 113 to receive the multiple candidate pulse trains. Based on the control of control circuit 115, selection circuit 114_1 selects one of these candidate pulse trains as the first trigger pulse train and sends it to timing signal generation section 112 to adjust the phase of clock signal CLK1.

[0033] In the embodiment shown in FIG6, the timing signal generation section 112 includes a parallel-to-serial converter P2S61 and an output buffer OB61. The parallel-to-serial converter P2S61 converts the clock pattern (CLK pattern) data CPD61 into a clock signal CLK1 based on the trigger pulse train output by the selection circuit 114_1. The input terminal of the output buffer is coupled to an output terminal of the parallel-to-serial converter, wherein the output buffer OB61 outputs the clock signal OB61 to the source drivers 120_1 to 120_3.

[0034] In the embodiment shown in FIG6, the image signal DATA1 includes multiple sets of differential signals (taking three sets of differential signals LV21, LV22, and LV23 as an example). The selection circuit 114_2 selects one of the multiple candidate pulse trains generated by the phase circuit 113 as the second trigger pulse train to the image signal generation section 111 to adjust the phase of the differential signal LV21 of the image signal DATA1. Similarly, the selection circuit 114_3 selects one of these candidate pulse trains as the third trigger pulse train to the image signal generation section 111, and the selection circuit 114_2 selects one of these candidate pulse trains as the fourth trigger pulse train to the image signal generation section 111 to adjust the phase of the differential signals LV22 and LV23 of the image signal DATA1.

[0035] In the embodiment shown in FIG. 6, the image signal generation section 111 includes multiple parallel-to-serial converters (e.g., parallel-to-serial converters P2S62, P2S63, and P2S64 shown in FIG. 6) and multiple output buffers (e.g., output buffers OB62, OB63, and OB64 shown in FIG. 6). Parallel-to-serial converter P2S62 converts parallel data PD61 into a differential signal LV21 of image signal DATA1 based on the trigger pulse train output by selection circuit 114_2. The input terminal of output buffer OB62 is coupled to the output terminal of parallel-to-serial converter P2S62. Output buffer OB62 outputs the differential signal LV21 to source drivers 120_1 to 120_3. Parallel-to-serial converter P2S63 converts parallel data PD62 into a differential signal LV22 of image signal DATA1 based on the trigger pulse train output by selection circuit 114_3. The input terminal of output buffer OB63 is coupled to the output terminal of parallel-to-serial converter P2S63. Output buffer OB63 outputs the differential signal LV22 to source drivers 120_1 to 120_3. Parallel-to-serial converter P2S64 converts the parallel data PD63 into the differential signal LV23 of the screen signal DATA1 based on the trigger pulse train output by selection circuit 114_4. The input of output buffer OB64 is coupled to the output of parallel-to-serial converter P2S64. Output buffer OB64 outputs the differential signal LV23 to source drivers 120_1 to 120_3.

[0036] FIG7 is a circuit block diagram of control circuit 115 according to an embodiment of the present invention. The control circuit 115 shown in FIG7 can be one of many embodiments of the control circuit 115 shown in FIG6. The control circuit 115, parallel-to-serial converter P2S61, parallel-to-serial converter P2S62, parallel-to-serial converter P2S63, parallel-to-serial converter P2S64, output buffer OB61, output buffer OB62, output buffer OB63 and output buffer OB64 shown in FIG7 can be referred to the relevant description in FIG6. In the embodiment shown in FIG7, control circuit 115 includes write control circuit 710, line buffer 720, read control circuit 730, logic circuit 740, parameter register 750 and output controller 760.

[0037] The write control circuit 710 is coupled to the line buffer 720. The write control circuit 710 receives different data segments from the data source 70. Depending on the application scenario, the data source 70 may include a scaler, a graphics processing unit (GPU), or other data sources. The data source 70 transmits different data segments (data signals) to the write control circuit 710 through a transmission interface (e.g., LVDS). The write control circuit 710 writes these data segments sequentially to the line buffer 720. The read control circuit 730 is coupled to the line buffer 720. The read control circuit 730 reads the corresponding data segments (parallel data PD61 to PD63) from the line buffer 720 at different times and sends them to the parallel-to-serial converters P2S62 to P2S64 of the screen signal generation section 111.

[0038] For example, FIG8 is a timing diagram illustrating the read control circuit 730 reading data from the line buffer 720 at different times according to an embodiment of the present invention. The horizontal axis of FIG8 represents time. Referring to FIG4, FIG7 and FIG8, during the first period, the read control circuit 730 reads data segment D41 from the line buffer 720 and sends it to the serial converters P2S62 to P2S64. During the stop period SP41 after the first period, the read control circuit 730 stops reading any data segment from the line buffer 720. During the second period after the stop period SP41, the read control circuit 730 reads data segment D42 from the line buffer 720 and sends it to the serial converters P2S62 to P2S64. During the stop period SP42 after the second period, the read control circuit 730 stops reading any data segment from the line buffer 720. During the third period after the stop period SP42, the read control circuit 730 reads the data segment D43 from the line buffer 720 and sends it to the parallel serial converters P2S62 to P2S64.

[0039] Logic circuit 740 is controlled by read control circuit 730. In response to read control circuit 730 reading data segment D41 from line buffer 720 and feeding it to parallel-to-serial converters P2S62-P2S64 during the first period, logic circuit 740 outputs clock pattern data CPD61 to parallel-to-serial converter P2S61 of timing signal generation section 112 to generate clock signal CLK1. The actual pattern of clock pattern data CPD61 can be determined according to the actual design and application scenario. For example, clock pattern data CPD61 can be multiple consecutive "0xAA" (hexadecimal number AA, i.e., binary number 10101010) or other patterns.

[0040] In response to the read control circuit 730 stopping the reading of any data segment from the line buffer 720 during the stop period, the logic circuit 740 stops outputting clock pattern data CPD61 to the parallel-to-serial converter P2S61 to stop generating the clock signal CLK1. The timing controller 110 confirms the partitioning of data required by different source drivers 120_1 to 120_3. By controlling the readout of the line buffer 720, the logic circuit 740 inserts a corresponding amount of dummy data (e.g., "0") into the SP41 during the stop period between different periods. The corresponding amount of dummy data allows the timing controller 110 sufficient operating time to switch signal characteristic parameters. In response to the read control circuit 730 reading data segment D42 from the line buffer 720 to the parallel-to-serial converters P2S62 to P2S64 during the second period, the logic circuit 740 outputs clock pattern data CPD61 to the parallel-to-serial converter P2S61 to resume generating the clock signal CLK1.

[0041] Parameter register 750 is coupled to read control circuit 730. Read control circuit 730 writes at least one signal characteristic parameter into parameter register 750. Based on practical design, the signal characteristic parameter includes control parameters related to at least one of phase, slope, amplitude, and pre-enhancement. Output controller 760 is coupled to parameter register 750. Output controller 760 outputs control signals CS71, CS72, CS73, and CS74 to output buffers OB61-OB64. Output controller 760 generates control signals CS71-CS74 based on the signal characteristic parameters of parameter register 750 to control the signal characteristics of at least one of output buffers OB61-OB64 (i.e., setting the signal characteristics of at least one of clock signal CLK1 and differential signals LV21-LV23). For example, during the stop periods SP41 and SP42 (during which the control circuit 115 stops switching the clock signal CLK1), the output controller 760 can set the signal characteristics of at least one of the output buffers OB61 to OB64 based on the signal characteristic parameters of the parameter register 750. Depending on the actual design, the signal characteristics may include at least one of phase, slope, amplitude, and pre-enhancement.

[0042] Figure 9 is a circuit block diagram of the timing controller 110 according to an embodiment of the present invention. The control circuit 115, selection circuit 114_1, parallel-to-sequence converter P2S61 and output buffer OB61 shown in Figure 9 can be referred to the relevant description in Figure 6. Referring to Figures 6 and 9, based on the control of the control circuit 115, the selection circuit 114_1 selects one of the multiple candidate pulse trains (e.g., candidate pulse trains PHASE9_1 and PHASE9_2 shown in Figure 9) generated by the phase circuit 113 as the trigger pulse train P2S_CLK to the parallel-to-sequence converter P2S61 to adjust the phase of the clock signal CLK1. Based on the trigger pulse train P2S_CLK output by the selection circuit 114_1, the parallel-to-sequence converter P2S61 converts the clock pattern data CPD61 into the clock signal CLK1. In the embodiment shown in Figure 9, the control circuit 115 can output a reset signal RST9 to reset the parallel-to-sequence converter P2S61.

[0043] Figure 10 is a waveform diagram illustrating a glitch in the trigger pulse train P2S_CLK according to an embodiment of the present invention. The horizontal axis of Figure 10 represents time. Referring to Figures 9 and 10, during the switching of different clock skews (CLK skew), the trigger pulse train P2S_CLK output by the selection circuit 114_1 may generate glitch. The control circuit 115 can be used as a glitch-free circuit to prevent the parallel-to-sequence converter P2S61 from erroneously reading the clock pattern data CPD61 due to the glitch in the trigger pulse train P2S_CLK. In time zone T10 where the trigger pulse train P2S_CLK may generate glitch, the control circuit 115 resets the parallel-to-sequence converter P2S61 by using the reset signal RST9 (e.g., pulling the reset signal RST9 up to a high level). After the phase switching of the selection circuit 114_1 is completed, the control circuit 115 releases the reset signal RST9 (e.g., pulling it down to a low level).

[0044] The embodiments shown in Figures 9 and 10 use the parallel-to-sequence converter P2S61 as an example of glitch-free processing. The descriptions of glitch-free processing for the parallel-to-sequence converter P2S61 can be extrapolated to other parallel-to-sequence converters, such as P2S62 to P2S64. The descriptions in Figures 4 to 10 above illustrate the presence of stop periods (e.g., SP41 and SP42) between the output periods of different data segments. In other embodiments, there may be no stop period between the output periods of different data segments.

[0045] For example, Figures 11 and 12 are illustrations according to other embodiments of the present invention, showing the time skew between the clock signal CLK1 output by the timing controller 110 and the screen signal DATA1, adapted to the different transmission path delays between the timing controller 110 and different source drivers 120_1 to 120_3, and the time skew between the clock signal CLK1 and the screen signal DATA1 received by the different source drivers 120_1 to 120_3. The horizontal axis of Figures 11 and 12 represents time. The upper part of Figures 11 and 12 shows a timing diagram of the clock signal CLK1 output by the timing controller 110 and the screen signal DATA1. The lower part of Figures 11 and 12 shows a timing diagram of the clock signal CLK1 and the screen signal DATA1 received by the different source drivers 120_1 to 120_3. The related description in Figure 4 can be extrapolated to the embodiments shown in Figures 11 and 12. Unlike the embodiment shown in Figure 4, in the embodiment shown in Figure 11, there may be no stop period between the output periods of different data segments D111, D112 and D113, and in the embodiment shown in Figure 12, there may be no stop period between the output periods of different data segments D121, D122 and D123.

[0046] In the embodiment shown in FIG11, the timing controller 110 adjusts the phase of the clock signal CLK1 so that the clock signal CLK1 has different time deviations for different data segments D41 to D43. Referring to FIG6 and FIG11, the control circuit 115 controls the routing of the selection circuit 114_1 through the control signal CS61. Based on the control of the control circuit 115, the selection circuit 114_1 selects different trigger pulses corresponding to different source drivers 120_1 to 120_3 from these candidate pulses and sends them to the parallel sequence converter P2S61 to adjust the phase of the clock signal CLK1. Therefore, the clock signal CLK1 output by the timing controller 110 has different time deviations for different data segments D41 to D43 to adapt to the different transmission path delays between the timing controller 110 and the source drivers 120_1 to 120_3.

[0047] In the embodiment shown in FIG12, the timing controller 110 adjusts the phase of the screen signal DATA1 (differential signals LV21 to LV23) so that the clock signal CLK1 has different time deviations for different data segments D41 to D43. Referring to FIG6 and FIG12, the control circuit 115 controls the routing of the selection circuits 114_2 to 114_4 through the control signals CS62 to CS64. Based on the control of the control circuit 115, the selection circuits 114_2 to 114_4 select different trigger pulse trains corresponding to different source drivers 120_1 to 120_3 from these candidate pulse trains and send them to the parallel sequence converters P2S62 to P2S64 to adjust the phase of the differential signals LV21 to LV23. Therefore, the clock signal CLK1 output by the timing controller 110 has different time deviations for different data segments D41 to D43, in order to adapt to the different transmission path delays between the timing controller 110 and the source drivers 120_1 to 120_3.

[0048] FIG13 is a circuit block diagram of phase circuit 113 according to an embodiment of the present invention. The phase circuit 113 shown in FIG13 can be one of many embodiments of the timing phase circuit 113 shown in FIG6. The phase circuit 113, selection circuits 114_1, 114_2, 114_3, 114_4, parallel-to-sequence converters P2S61, P2S62, P2S63, P2S64, output buffers OB61, OB62, OB63, and OB64 shown in FIG13 can be referred to the relevant description in FIG6. In the embodiment shown in FIG13, phase circuit 113 includes a phase locked loop (PLL) 1310 and multiple phase dividers (e.g., phase dividers 1320_1 to 1320_n shown in FIG13). The PLL 1310 generates a basic pulse train. The number n of phase separators 1320_1 to 1320_n can be determined according to the actual design. Phase separators 1320_1 to 1320_n are coupled to phase-locked loop 1310 to receive the basic pulse train. These phase separators 1320_1 to 1320_n perform phase division on the basic pulse train of phase-locked loop 1310 to generate multiple candidate pulse trains with different phases for selection circuits 114_1 to 114_4.

[0049] FIG14 is a circuit block diagram of phase circuit 113 according to another embodiment of the present invention. The phase circuit 113 shown in FIG14 can be one of many embodiments of the timing phase circuit 113 shown in FIG6. The phase circuit 113, selection circuit 114_1, selection circuit 114_2, selection circuit 114_3, selection circuit 114_4, parallel-to-sequence converter P2S61, parallel-to-sequence converter P2S62, parallel-to-sequence converter P2S63, parallel-to-sequence converter P2S64, output buffer OB61, output buffer OB62, output buffer OB63 and output buffer OB64 shown in FIG14 can be referred to the relevant description in FIG6. In the embodiment shown in FIG14, the phase circuit 113 includes a phase-locked loop 1410, a first phase separator (e.g., phase separators 1420_1 to 1420_n shown in FIG14), a second phase separator (e.g., phase separators 1430_1 to 1430_n shown in FIG14), a third phase separator (e.g., phase separators 1440_1 to 1440_n shown in FIG14), and a fourth phase separator (e.g., phase separators 1450_1 to 1450_n shown in FIG14). The phase-locked loop 1410 generates a basic pulse train.

[0050] The number n of phase separators can be determined according to the actual design. Phase separators 1420_1~1420_n, 1430_1~1430_n, 1440_1~1440_n, and 1450_1~1450_n are coupled to the phase-locked loop 1410 to receive the basic pulse train. Phase separators 1420_1~1420_n perform phase division on the basic pulse train of the phase-locked loop 1410 to generate multiple first candidate pulse trains with different phases for selection circuit 114_1. Phase separators 1430_1~1430_n perform phase division on the basic pulse train of the phase-locked loop 1410 to generate multiple second candidate pulse trains with different phases for selection circuit 114_2. Phase separators 1440_1 to 1440_n perform phase division on the basic pulse train of the phase-locked loop 1410 to generate multiple third candidate pulse trains with different phases for selection circuit 114_3. Phase separators 1450_1 to 1450_n perform phase division on the basic pulse train of the phase-locked loop 1410 to generate multiple fourth candidate pulse trains with different phases for selection circuit 114_4.

[0051] In summary, the transmitters (e.g., timing controllers 110) in the above embodiments, under a point-to-multipoint (multi-drop) architecture (e.g., mini-LVDS interface), adjust the timing skew relationship between the clock signal CLK1 and the screen signal DATA1 in a stop-clock manner for different receivers (e.g., source drivers 120_1 to 120_3). This ensures that the positive and negative edges of the clock and the corresponding order of the data (screen signal DATA1) remain unchanged when each receiver receives data. Such adjustments allow each receiver to obtain the optimal setup / hold time eye diagram, thereby overcoming reception problems that may occur during high-speed transmission.

[0052] In addition to switching different time offsets according to different receiving ends, the above embodiments also have the function of adjusting the analog characteristics of signals at different transmitting ends (e.g., signal slope, signal amplitude, signal pre-enhancement, etc.). The above embodiments can disperse the distribution of signal strength, thereby reducing the energy of electromagnetic interference (EMI). Furthermore, the above embodiments can also reduce power consumption by adjusting the amplitude of the shorter path, providing the advantage of power reduction.

[0053] In addition, the above embodiments can overcome the high-speed transmission problem by using existing general source drivers. If a corresponding source driver is used, a golden key and a hand shake mechanism can be defined in the transmission content, and the optimal clock deviation of each source driver can be adjusted automatically, increasing the ease of application.

[0054] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a circuit block diagram of a display device according to an embodiment of the present invention. Figure 2 is a schematic diagram of the time skew between the clock signal and the screen signal received by different source drivers when the timing skew between the clock signal output by the timing controller and the screen signal is fixed, according to an embodiment of the present invention. Figure 3 is a flowchart of an operation method of a display device according to an embodiment of the present invention. Figure 4 is a schematic diagram of the time skew between the clock signal and the screen signal received by different source drivers when the timing skew between the clock signal output by the timing controller and the screen signal is adapted to the different transmission path delays between the timing controller and different source drivers, according to an embodiment of the present invention. Figure 5 is a waveform diagram of the signal output by the timing controller according to an embodiment of the present invention. Figure 6 is a circuit block diagram of the timing controller according to an embodiment of the present invention. Figure 7 is a circuit block diagram of the control circuit according to an embodiment of the present invention. Figure 8 is a timing diagram illustrating the read control circuit reading data from the line buffer at different times according to an embodiment of the present invention. Figure 9 is a circuit block diagram of a timing controller according to an embodiment of the present invention. Figure 10 is a waveform diagram illustrating a glitch in the trigger pulse train according to an embodiment of the present invention. Figures 11 and 12 are diagrams illustrating the time deviation between the clock signal and the screen signal received by different source drivers when the time deviation between the clock signal output by the timing controller and the screen signal is adapted to the different transmission path delays between the timing controller and different source drivers, according to other embodiments of the present invention. Figure 13 is a circuit block diagram of a phase circuit according to an embodiment of the present invention. Figure 14 is a circuit block diagram of a phase circuit according to another embodiment of the present invention.

Claims

1. A timing controller, comprising: A timing signal generation section generates a clock signal to multiple source drivers used to drive a display panel; And a screen signal generation section generates a screen signal synchronized with the clock signal, wherein the screen signal includes multiple data segments corresponding to different source drivers, and the timing controller adjusts the phase of at least one of the clock signal and the screen signal so that the clock signal has different time deviations for different data segments, in order to adapt to the different transmission path delays between the timing controller and the source drivers.

2. The timing controller as claimed in claim 1, wherein the timing controller transmits the clock signal and the screen signal to the source drivers via a mini low-voltage differential interface.

3. The timing controller as claimed in claim 1, wherein the data segments include a first data segment and a second data segment, the timing controller has a stop period between the period of outputting the first data segment and the period of outputting the second data segment, the timing controller stops switching the clock signal during the stop period, and the timing controller sets the signal characteristics of at least one of the clock signal and the screen signal based on at least one signal characteristic parameter during the stop period.

4. The timing controller as claimed in claim 3, wherein the at least one signal characteristic parameter includes at least one of phase, slope, amplitude, and pre-enhancement.

5. The timing controller as described in claim 3, further comprising: A line buffer; A write control circuit, coupled to the line buffer, wherein the write control circuit receives the first data segment and the second data segment from a data source, and writes the first data segment and the second data segment to the line buffer; and a read control circuit, coupled to the line buffer, wherein the read control circuit reads the first data segment from the line buffer and provides it to the screen signal generation section during a first period, the read control circuit stops reading any data segment from the line buffer during a stop period after the first period, and the read control circuit reads the second data segment from the line buffer and provides it to the screen signal generation section during a second period after the stop period.

6. The timing controller as described in claim 5, further comprising: A logic circuit, controlled by the read control circuit, wherein, in response to the read control circuit reading the first data segment from the line buffer and supplying it to the screen signal generation section during a first period, the logic circuit outputs clock pattern data to the timing signal generation section to generate the clock signal; in response to the read control circuit stopping reading any data segment from the line buffer during a stop period, the logic circuit stops outputting the clock pattern data to the timing signal generation section to stop generating the clock signal; and in response to the read control circuit reading the second data segment from the line buffer and supplying it to the screen signal generation section during a second period, the logic circuit outputs the clock pattern data to the timing signal generation section to resume generating the clock signal.

7. The timing controller as described in claim 5, further comprising: A parameter register is coupled to the read control circuit, wherein the read control circuit writes the at least one signal characteristic parameter into the parameter register. And an output controller coupled to the parameter register, wherein the output controller controls at least one of the timing signal generation part and the screen signal generation part based on the at least one signal characteristic parameter of the parameter register, so as to set the signal characteristics of at least one of the clock signal and the screen signal.

8. The timing controller as claimed in claim 1, wherein the data segments include a first data segment and a second data segment, the clock signal includes a first clock segment corresponding to the first data segment and a second clock segment corresponding to the second data segment, the timing controller adjusting the phase of the first clock segment to a first phase, and the timing controller adjusting the phase of the second clock segment to a second phase different from the first phase, so that the clock signal has different time deviations for different data segments.

9. The timing controller as claimed in claim 1, wherein the data segments include a first data segment and a second data segment, the timing controller adjusts the phase of the first data segment to a first phase, and the timing controller adjusts the phase of the second data segment to a second phase different from the first phase, so that the clock signal has different time deviations for different data segments.

10. The timing controller as claimed in claim 1, wherein the timing signal generation section includes: A parallel-to-serial converter that converts clock pattern data into a clock signal based on a trigger pulse train; And an output buffer having an input coupled to an output of the parallel-to-serial converter, wherein the output buffer outputs the clock signal to the source drivers.

11. The timing controller as claimed in claim 1, wherein the screen signal generation portion includes: A parallel-to-serial converter converts parallel data corresponding to a screen signal into the screen signal based on a trigger pulse train; And an output buffer having an input coupled to an output of the parallel-to-serial converter, wherein the output buffer outputs the screen signal to the source drivers.

12. The timing controller as described in claim 1, further comprising: A single-phase circuit generates multiple candidate pulse trains with different phases; A first selection circuit, coupled to the phase circuit, receives the candidate pulse trains, wherein the first selection circuit selects one of the candidate pulse trains as a first trigger pulse train for the timing signal generation section to adjust the phase of the clock signal; and a second selection circuit, coupled to the phase circuit, receives the candidate pulse trains, wherein the second selection circuit selects one of the candidate pulse trains as a second trigger pulse train for the screen signal generation section to adjust the phase of the screen signal.

13. The timing controller as claimed in claim 12, wherein the phase circuit includes: A phase-locked loop generates a basic pulse train; And multiple phase dividers coupled to the phase-locked loop to receive the base pulse train, wherein the phase dividers perform phase division on the base pulse train to generate candidate pulse trains with different phases for the first selection circuit and the second selection circuit.

14. The timing controller as described in claim 1, further comprising: A phase-locked loop generates a basic pulse train; A first phase divider, coupled to the phase-locked loop (PLL) to receive the base pulse train, wherein the first phase divider performs phase division on the base pulse train to generate a plurality of first candidate pulse trains with different phases; a first selection circuit, coupled to the first phase divider to receive the first candidate pulse trains, wherein the first selection circuit selects one of the first candidate pulse trains as a first trigger pulse train for the timing signal generation section to adjust the phase of the clock signal; and a second phase divider, coupled to the PLL to receive the base pulse train, wherein the second phase divider performs phase division on the base pulse train to generate a plurality of second candidate pulse trains with different phases. And a second selection circuit coupled to the second phase divider to receive the second candidate pulse trains, wherein the second selection circuit selects one of the second candidate pulse trains as a second trigger pulse train to the screen signal generation section to adjust the phase of the screen signal.

15. A method for operating a timing controller, comprising: The timing controller generates a clock signal to multiple source drivers used to drive a display panel; The timing controller generates a screen signal synchronized with the clock signal, wherein the screen signal includes multiple data segments corresponding to different source drivers; and adjusts the phase of at least one of the clock signal and the screen signal so that the clock signal has different time deviations for different data segments to adapt to different transmission path delays between the timing controller and the source drivers.

16. The operating method as described in claim 15 further includes: The timing controller transmits the clock signal and the screen signal to the source drivers via a mini low-voltage differential signal interface.

17. The operating method as claimed in claim 15, wherein the data segments include a first data segment and a second data segment, the timing controller has a stop period between the period of outputting the first data segment and the period of outputting the second data segment, and the operating method further includes: During this stop, the clock signal switching is stopped; And during the stop period, the signal characteristics of at least one of the clock signal and the screen signal are set based on at least one signal characteristic parameter.

18. The method of operation as described in claim 17, wherein the at least one signal characteristic parameter includes at least one of phase, slope, amplitude, and pre-enhancement.

19. The operating method as described in claim 17 further includes: The timing controller receives the first data segment and the second data segment from a data source via a write control circuit. The first data segment and the second data segment are written to a line buffer of the timing controller; and a read control circuit of the timing controller reads the first data segment from the line buffer during a first period and sends it to a screen signal generation section of the timing controller; the read control circuit stops reading any data segment from the line buffer during a stop period after the first period; and the read control circuit reads the second data segment from the line buffer during a second period after the stop period and sends it to a screen signal generation section of the timing controller.

20. The operating method as described in claim 19 further includes: In response to the read control circuit reading the first data segment from the line buffer and supplying it to the screen signal generation section during the first period, a logic circuit of the timing controller outputs clock pattern data to a timing signal generation section of the timing controller to generate the clock signal; in response to the read control circuit stopping reading any data segment from the line buffer during the stop period, the logic circuit stops outputting the clock pattern data to the timing signal generation section to stop generating the clock signal; and in response to the read control circuit reading the second data segment from the line buffer and supplying it to the screen signal generation section during the second period, the logic circuit outputs the clock pattern data to the timing signal generation section to resume generating the clock signal.

21. The operating method as described in claim 19 further includes: The read control circuit writes at least one signal characteristic parameter into a parameter register of the timing controller; And an output controller of the timing controller controls at least one of a timing signal generation part and a screen signal generation part of the timing controller based on at least one signal characteristic parameter of the parameter register, so as to set the signal characteristics of at least one of the clock signal and the screen signal.

22. The operating method as described in claim 15, wherein the data segments include a first data segment and a second data segment, the clock signal includes a first clock segment corresponding to the first data segment and a second clock segment corresponding to the second data segment, and the operating method further includes: Adjust the phase of this first clock segment to a first phase; And adjust the phase of the second clock segment to a second phase that is different from the first phase, so that the clock signal has different time deviations for different data segments.

23. The operating method as described in claim 15, wherein the data segments include a first data segment and a second data segment, and the operating method further includes: Adjust the phase of the first data segment to a first phase; And adjust the phase of the second data segment to a second phase that is different from the first phase, so that the clock signal has different time deviations for different data segments.

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