Memory device and reading method thereof

Abstract

A memory device has been disclosed comprising a four-transistor (4T-SRAM) cell and a sensing circuit. The 4T-SRAM cell includes two P-type MOSFETs for data bit storage and two N-type MOSFETs for access switching. The advantage of the 4T-SRAM cell is its smaller number of MOSFETs, enabling a smaller cell size and lower leakage current. The sensing circuit includes a switching device, a sensing latch, and a discharging device. The switching device, coupled between the sensing latch and a ground voltage rail, is designed to reduce read interference from the sensing circuit to the 4T SRAM cell by interrupting the leakage current path from the NMOSFET transistors in the sensing latch to the ground voltage rail. The differential voltage signal used to read the digital data stored in the 4T SRAM cell is enhanced by increasing the sensing time. The read margin of the 4T SRAM is then greatly improved, resulting in excellent and reliable reads.

Description

Technical Field

[0001] This invention relates to a sensing circuit and timing scheme for reading a single bit of information stored in a four-transistor static random access memory (4T SRAM) cell. Specifically, the sensing circuit and timing scheme of this invention can reduce read disturbance caused by minute differential bit line voltage signals (generated by storage nodes within the 4T SRAM cells of the memory array). The sensing circuit and timing scheme of this invention can also significantly improve the read margin of the 4T SRAM, resulting in excellent read reliability. Prior Technology

[0002] Semiconductor memory is widely used in electronic systems. Electronic systems require semiconductor memory to store instructions and data, which are derived from the basic control functions of complex computational processes. Semiconductor memory can be divided into volatile memory and non-volatile memory. Volatile memory includes Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), whose stored data disappears when the memory is powered off. Non-volatile memory, such as Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Flash memory, retains its stored data even when the memory is powered off.

[0003] Because computer processors operate at very high clock speeds (tens of MHz to tens of GHz), the access time for reading and modifying data in memory must match the processing speed of the computer processor. Due to the fast random access time of read / write operations, volatile SRAM and DRAM have become the memory choices for computer processors. A DRAM cell includes a MOSFET device and a capacitor, where the MOSFET device acts as an access switch and the capacitor stores one bit of data. DRAM cells can be manufactured at extremely high densities using DRAM manufacturing technology at very low manufacturing costs. However, DRAM requires constant refreshing, resulting in high power consumption, while SRAM does not require data refreshing, thus consuming far less power than DRAM. Furthermore, SRAM is manufactured using complementary metal-oxide-semiconductor (CMOS) technology, the same technology used to manufacture digital processor integrated circuits (ICs). Therefore, SRAM is typically embedded within ICs as memory for digital processors. However, because a traditional SRAM cell used for storage contains six MOSFET devices, it occupies a relatively large area compared to a DRAM cell (one MOSFET device and one capacitor), resulting in a much higher per-bit storage cost for SRAM than for DRAM. Therefore, the industry urgently needs to reduce the cell size of SRAM by using fewer MOSFET devices, thereby improving memory density and reducing the per-bit storage cost in digital processor IC chips. Referring to Figure 1, a conventional SRAM cell 100 contains six MOSFET devices: two N-type MOSFET devices 13 and 14, which serve as data access switches, and a pair of cross-coupled inverter latches: a P-type MOSFET device 11 and an N-type MOSFET device 15, and a PMOSFET device 12 and an NMOSFET device 16, which serve as one bit of data storage. The pair of cross-coupled inverter latches form two storage nodes n1 and n2, respectively. Please refer to Figure 2. The 4T SRAM cell 200 contains four MOSFET devices: two N-type MOSFET devices 23 and 24, which are used as data access switches, and two mutually coupled P-type MOSFET devices 22 and 21, which are used as one bit of data storage. The drain electrodes of the pair of mutually coupled P-type MOSFET devices 21 and 22 form two storage nodes n3 and n4, respectively.Regarding the reduction in the cost per SRAM cell, the size of a 4T SRAM cell 200 is typically about 25% to 35% smaller than the 6T SRAM cell 100 in Figure 1 (manufactured using the same CMOS process technology generation). Although the 4T SRAM cell 200 uses fewer MOSFET devices to save on the cost per cell, how to reliably read the stored data from the 4T SRAM cell remains an important issue for the widespread application of 4T SRAM in IC chips.

[0004] One-bit data is stored by setting asymmetric voltage potentials to the two storage nodes n3 and n4 of the 4T SRAM unit 200, such as setting V DD (digital supply / high voltage) and V SS (ground voltage) to the two storage nodes n3 and n4 respectively to store data 1, and setting the two storage nodes n3 and n4 to V SS and V DD to store data 0, respectively. Thereafter, the storage data in the 4T SRAM unit 200 is read back by sensing the asymmetric voltage potential on the two storage nodes n3 and n4. Regarding the data storage of the 6T SRAM, the pair of mutually coupled reverse latches (inverter devices 11 and 15 and inverter devices 12 and 16) in the 6T SRAM unit 100 of FIG The SS, therefore, is able to read data from the conventional 6T SRAM unit 100 directly utilizing conventional SRAM sensing circuits and methods or newer read-assist sensing circuits. When data is written to the 4T SRAM unit 200 of FIG. However, during the data retention period after the data is written to the 4T SRAM unit 200 (access transistors 23 and 24 are turned off (off)), unlike the 6T SRAM unit 100 , one of the storage nodes of the 4T SRAM unit 200 of FIG. As disclosed in the literature in Taiwan Patent Application No. 113117394, depending on the leakage current balance between the channel diffusion current of the PMOSFET and the leakage current of the access NMOSFET diode in the 4T SRAM unit 200, the potential of this float node will rise from the ground voltage to a stable voltage potential at a V-digit supply / high voltage potential below.

[0005] In order to minimize read errors of floating storage nodes in 4T SRAM cell 200, the sensing circuit 350 in Figure 3 of Taiwan Patent Application No. 113103434 reads data from the rising floating voltage potential on one storage node n3 / n4 and VDD on the other storage node n4 / n3 in the following manner: (1) Before accessing a 4T SRAM cell 200, the bit line BL 321 and the complementary bit line are connected by two NMOSFET devices 311. (2) Discharge residual charge on 322 to avoid unwanted read interference; (3) Sensing connection bit line BL 321 and complementary bit line 322 (transmitted from two storage nodes n3 and n4) differential voltage potential; and (3) during cell data read / process, simultaneously refreshing the original data voltage potentials VDD and VSS on the two storage nodes. When the word line 334 (gate of cell access MOSFETs 24 and 23) of the selected 4T SRAM cell 200 is activated to perform the cell data read process, due to the initial inter-capacitance charge sharing effect between the small gate capacitance of the cell PMOSFET device and the large capacitance of the bit line, the differential voltage initially transmitted from cell storage nodes n3 and n4 to (connected to read sensing circuit 350) bit line 321 and complementary bit line 322 will be further reduced to a smaller differential voltage signal, as shown in the second row of FIG4. For example, in one embodiment, regarding the bit line capacitance connecting 256 memory cells in a 4T SRAM memory array, when the word line voltage potential (first column in Figure 4) is turned on, initially, the voltage potential of the high-voltage storage node n3, representing the stored data "1" (second column in Figure 4), drops from 1.2V to 175.6 millivolts (mV). Simultaneously, during the bit line voltage drop, the voltage on storage node n4 (connected to the gate of PMOSFET device 22) also drops to compensate for the complementary capacitance sharing effect, and the voltage potential of storage node n4 changes from an initial 17.4 mV to 131.6 mV. When the gate voltages of the two PMOSFET devices 21 and 22, which are initially in the "on" state, are lower than (VDD - cell PMOSFET threshold voltage (approximately 0.42 V)), they begin to charge the capacitors 341 of bit line 321 and 342 of complementary bit line 322, respectively, to increase the storage node voltage potential and the voltage potentials of the bit line and complementary bit line, as shown in the second and third columns of Figure 4, respectively. Meanwhile, regarding the case of reading a 4T SRAM cell containing stored data "1", since the gate voltage potential of PMOSFET 21 connected to storage node n3 (initial value 175.6 mV) is higher than the gate voltage potential of PMOSFET 22 connected to storage node n4 (initial value 131.6 mV), PMOSFET device 22 charges bit line 321 to the first voltage potential faster, while PMOSFET device 21 charges complementary bit line 322 to the second voltage potential slower, and the first voltage potential should be higher than the second voltage potential.However, as shown in Figure 4, due to erroneous reads of the 4T SRAM cell storing data "1", the differential voltage potential ΔV between the bit line and the complementary bit line can evolve into a cross-over voltage, i.e., the voltage potentials of the bit line and the complementary bit line are equal (i.e., ΔV = 0 V), or even develop into a state opposite to the original differential voltage sign. This causes the sensing circuit 350 to read the wrong bit and change the cell bit, as shown in the second and third columns of Figure 4. Due to variations in the manufacturing process and different operating temperature environments of the MOSFET devices, the margin design of the sensing circuit 350 and the inaccurate sensing timing produced by the timing circuit may increase the aforementioned erroneous read events. It has been found that the channel leakage current of the NMOSFET devices 313 and 314 in the sensing circuit 350 is the cause of the erroneous read events. In this invention, we redesigned the new sensing circuit 550 to cut off the channel leakage current path of the NMOSFETs 313 and 314 to prevent the sensing circuit from causing read interference to the 4T SRAM cell. By employing novel sensing circuitry and timing sensing methods, the read margin of 4T SRAM can be enhanced to address variations in MOSFET device performance caused by different operating temperatures of the process and integrated circuit chips. Summary of the Invention

[0006] Unlike traditional 6T-SRAM cells that always bias one of their storage nodes to ground, the 4T-SRAM cell 200 does not have a low-voltage node VSS connected to ground. Therefore, during cell data reading, one of the floating storage nodes n4 / n3 of the 4T-SRAM cell 200 needs to be restored to ground to retain the original stored data. The sensing circuit 550 of this invention is designed to restore the floating storage node of the selected 4T-SRAM cell to ground during cell data reading.

[0007] For the 4T-SRAM cell 200, since the voltage potential of the floating storage node is lower than the high voltage potential VDD of the other storage node during the data retention period, the sensing circuit 550 is designed to detect the asymmetric voltage difference (VDD - Vfloating) between the two storage nodes of the selected 4T-SRAM cell 200 in order to obtain a complete digital voltage signal, i.e., the high voltage VDD and the ground voltage VSS, as an output signal, where Vfloating represents the voltage potential of the floating storage node of the 4T-SRAM cell 200 during the data retention period, as shown in Figure 6. The floating storage node voltage potential Vfloating is lower than the supply voltage VDD and higher than the ground voltage. The floating is due to the diffusion current of the PMOSFET device 21 / 22 channels ( To a stable And reverse P-drain / N-well junction leakage current ( To a stable ) and access NMOSFET devices 23 / 24 (stable) By balancing the reverse N-drain / P-substrate junction leakage current, the steady-state floating storage node voltage potential of the 4T SRAM cell 200 can be obtained. (As shown by curve 605 in Figure 6). Generally speaking, the larger the reverse N-drain / P-substrate junction leakage current of the NMOSFET device 23 / 24, the lower the stable floating storage node voltage potential towards ground.

[0008] Figure 5 shows a schematic diagram of a sensing circuit 550 for reading a 4T SRAM cell 200 according to the present invention. The sensing circuit 550 of the present invention includes two bit-line reset NMOSFET devices 311, a transmit enable PMOSFET device 312, two interconnected inverters 5a and 5b, a tri-state buffer 315, and an NMOSFET device 516. The two bit-line reset NMOSFET devices 311 are used to connect bit line BL 321 (with load capacitance C BL341) and complementary bit line... The residual charge on 322 (with load capacitor C BL342) is discharged, and the NMOSFET device 516 is used to cut off the leakage current path from the sensing circuit to ground potential. The gate electrode of the NMOSFET device 516 is connected to the sensing voltage signal "S n", and the NMOSFET device 516 is coupled between the source electrode (node ​​57) of NMOSFET devices 313 and 314 and the ground potential, as shown in Figure 5. The NMOSFET device 516 is used to cut off the channel leakage current path of NMOSFETs 313 and 314 to prevent the sensing circuit from reading from interfering with the 4T SRAM cell.

[0009] The read timing for 4T SRAM cell 200 initially involves applying a voltage pulse signal BLrst VDD to node 331 for a duration τ to connect bit line BL 321 and complementary bit line 200. 322 is reset to ground potential, as shown in the first column of Figure 6. After the time τ of discharging bit line 321 and complementary bit line 322, a voltage signal VDD is applied at node 534 in the 4T SRAM memory array to turn on the selected word line (the third column of Figure 6). When the selected word line is turned on, due to the charge sharing between the bit line capacitance and the complementary bit line capacitance and the cell PMOSFET gate capacitance at storage nodes n3 and n4, the voltage potential at storage nodes n3 and n4 of the selected 4T SRAM cell 200 initially drops to a voltage potential close to ground voltage. For the stored cell data "1", this can be roughly expressed mathematically as follows: Vb (V DD× (C pg / (C pg+C bL))) and V cb (V floating × (C pg / (C pg + C bL))), as shown in the fourth column of Figure 6, for the stored cell data "0", and vice versa, where V b and V cb represent the stable bit line voltage potential and complementary bit line voltage potential after achieving balanced capacitor charge sharing, respectively; C pg represents the gate capacitance of the selected 4T SRAM PMOSFET (21 / 22), and C bL represents the bit line / complementary bit line capacitance. Since the voltage potential at the storage nodes (n3 and n4) after capacitor charge sharing will be lower than the voltage (V DD - the critical voltage of cell PMOSFET 21 / 22), both cell PMOSFET devices 21 and 22 are initially turned on to charge the bit line and complementary bit line to a higher voltage potential. In the absence of leakage current interference from NMOSFET devices 314 and 313 (which are cut off by NMOSFET device 516), for a 4T SRAM cell storing data "1", the cell PMOSFET 22 with a slightly lower voltage potential at its gate or node n4 will conduct more than the cell PMOSFET 21 with a slightly higher voltage potential at its gate or node n3 (i.e., Vn3 > Vn4). This results in bit line 321 charging faster than its complementary bit line 321, and vice versa for a 4T SRAM cell storing data "0". Therefore, for 4T SRAM cells storing data "1" and data "0", the differential voltage potential between the bit lines and complementary bit lines at sensing nodes 56 and 55 will increase over time, as shown in the fifth and sixth rows of Figure 6, respectively. After time "Dt", when the differential voltage potential between the bit line and the complementary bit line increases to a significant differential voltage margin ΔV, a voltage signal Sn with a voltage potential VDD is applied at node 332 to turn on the sensing circuit 550 to initialize a sensing process to increase the differential voltage between the bit line and the complementary bit line from ΔV to the maximum differential voltage VDD. As shown in the fifth and sixth columns of Figure 6, the voltage curves of the bit line and the complementary bit line of the 4T SRAM cell storing data "1" and data "0" are respectively displayed.

[0010] The "Sn" signal with voltage potential VDD applied to node 332 also turns on the tri-state buffer 315 to output the data voltage signal VDD (data "1") stored in the cell from the sensing voltage signal VSS at the complementary sensing node 55 to the data output bus. Simultaneously, the Sn signal with voltage VDD also turns on the PMOSFET device 312 to accelerate the sensing process, charging bit line BL 321 to the highest voltage potential VDD. It should be noted that during the sensing process, the cell node n4 is refreshed from the previously floating storage node during the data retention period to the ground potential using the ground voltage at the gate and the digital supply voltage VDD at the base (body) from the previously floating storage node situation during the data retention period, so that the total charge on the gate of the PMOSFET device 22 can be fully restored using the ground voltage at the gate and the digital supply voltage VDD at the base (body) to fully charge the capacitance of the gate and base (body) (N-well). Therefore, the data originally stored in the selected 4T SRAM cell is refreshed completely and correctly. Simple Explanation of the Diagram

[0011] To better understand the present invention and illustrate how to implement it, reference will now be made to the following figures, which illustrate preferred embodiments of the invention, wherein:

[0012] Figure 1 shows a schematic diagram of a conventional 6T-SRAM cell.

[0013] Figure 2 shows a schematic diagram of a conventional 4T-SRAM cell.

[0014] Figure 3 shows a schematic diagram of the sensing circuit 350 of the 4T SRAM cell disclosed in Taiwan Patent Application No. 113103434.

[0015] Figure 4 shows a case of erroneous reading when using the sensing circuit 350 in Figure 3 to read a 4T SRAM cell.

[0016] The figure shows a schematic diagram of a sensing circuit 550 for a 4T SRAM cell according to the present invention.

[0017] Figure 6 shows the voltage potential waveform of the reading timing of the sensing circuit in Figure 5 according to the present invention.

[0018] Figure 7 shows a memory array layout topology using 40nm CMOS process technology provided by a wafer foundry according to an embodiment of the present invention, illustrating the circuit simulation waveform for reading a 4T SRAM cell, wherein the 4T SRAM cell has extracted parasitic resistance and capacitance parameters of bit lines and complementary bit lines. Implementation

[0019] The following detailed description is illustrative only and not limiting. It should be understood that other embodiments and various MOSFET devices, such as FinFET devices and Gate All Around (GAA) devices, can be used and all fall within the scope of the claims. Furthermore, it should be understood that the syntax and terminology used in this specification are for illustrative purposes only and should not be considered limiting. Those skilled in the art will understand that the embodiments of methods and schematic diagrams in this specification are merely illustrative and not limiting. Those skilled in the art who understand the spirit of the invention through the disclosure of this specification may use other embodiments, all of which should fall within the scope of the claims.

[0020] In one embodiment, the sensing circuit 550 of the 4T SRAM memory array is implemented in a 1Mb 4T SRAM chip manufactured using 40nm CMOS logic process technology from a wafer foundry. Parasitic resistance and capacitance parameters are extracted from the topology of the 4T SRAM memory array. Simultaneously, 4T SRAM write / read operation simulations are performed using the MOSFET SPICE model in the wafer foundry's Process Design Kit (PDK). Complete chip simulations have been performed for different process deviation corners and different temperature environments. Figure 7 shows a typical simulated read waveform to illustrate the working principle of the sensing circuit 550 and sensing method of the 4T SRAM memory array of the present invention. As shown in the second column of Figure 7, when the word line is turned on using the voltage potential VDD, due to the charge sharing between the cell PMOSFET gate capacitance and the bit line capacitance, the voltage potential of the selected 4T SRAM cell storage nodes n3 and n4 initially drops to a low voltage potential to turn on the two cell PMOSFET devices 21 and 22. Then, the two conducting PMOSFET devices 22 and 21 charge the bit lines and complementary bit lines to a higher voltage potential. When reading the data "1" stored in the 4T SRAM cell, after the word lines are turned on, the differential voltage potential between storage nodes n3 and n4 increases from 30 mV at 0.58 nanoseconds (ns), 41 mV at 0.89 ns, to 72 mV at 1.29 ns. Simultaneously, after the word lines are turned on, the differential voltage potential between the bit line at sensing node 56 and the complementary bit line at sensing node 55 also increases accordingly, from 9.92 mV at 0.58 ns, 14.3 mV at 0.89 ns, to 18.3 mV at 1.29 ns. As shown in Figure 7, as the sensing time Dt increases, the sensing circuit 550 with the timing sensing method is used to amplify the large differential voltage between sensing nodes 55 and 56 to the maximum differential voltage VDD. In the post-simulation of the complete wafer, the wafer passed tests for all process deviation edge values ​​and different temperature environments.

[0021] The preferred embodiments provided above are merely illustrative of the invention and are not intended to limit the invention to a specific type or exemplary embodiment. Therefore, this specification should be considered illustrative rather than restrictive. The preferred embodiments provided above are intended to effectively illustrate the spirit of the invention and its best mode of implementation, thereby enabling those skilled in the art to understand the various embodiments and modifications of the invention to suit specific uses or purposes. The scope of the invention is defined by the appended claims and their equivalents, wherein all terms are intended to have the broadest reasonable meaning unless otherwise specified. Therefore, terms such as "the invention" do not limit the scope of the claims to a particular embodiment, and any references to specific preferred embodiments of the invention are not intended to limit the invention, nor is any such limitation presumed. The invention is defined only by the scope and spirit of the appended claims. The abstract of the invention is provided in accordance with regulatory requirements to enable a searcher to quickly identify the subject matter of this disclosure from any patents approved under this specification, and is not intended to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the invention. It should be understood that various modifications or alterations can be made by those skilled in the art, all of which should fall within the scope of the invention as defined in the appended claims. Furthermore, none of the elements and components in this specification are intended to be made public, whether or not they are listed in the appended claims.

[0022] 100:6T SRAM cells 200:4T SRAM cells 13, 14, 15, 16, 23, 24, 311, 313, 314, 516: NMOSFET devices 11, 12, 21, 22, 312: PMOSFET device 350, 550: Sensing circuit BL 321: Bitline 322: Complementary bit line n1, n2, n3, n4: Storage nodes C BL341, C BL342: Load capacitor 315: Tri-state buffer BLrst: Voltage pulse signal Nodes 35, 36, 37, 55, 56, 57, 331~333, 534 WL 334: Character Line Sn: Voltage signal Dt: Time Steady-state floating storage node voltage potential Vfloating curve of 605:4T-SRAM cell 5a, 5b: Inverters

Claims

1. A memory device comprising: a static random access memory (SRAM) cell having only four transistors, including: a pair of mutually coupled PMOSFET transistors coupled to a digital voltage rail and two storage nodes; and two access transistors responsive to a word line and coupled to the storage nodes and the pair of bit lines; and a sensing circuit comprising: a sensing latch coupled between a first connection node and a second connection node and having two output nodes respectively coupled to the pair of bit lines; a discharge device responsive to a first control signal to discharge the pair of bit lines to a ground voltage, the discharge device being coupled to the output nodes, the pair of bit lines and the ground voltage rail; and a switching device responsive to a second control signal to selectively connect the second connection node to the ground voltage rail.

2. The memory device as claimed in claim 1, wherein the first control signal is activated before the character line is activated, and wherein the character line is activated before the second control signal is activated.

3. The memory device as claimed in claim 2, wherein the discharge device comprises: a first reset transistor and a second reset transistor for responding to the first control signal, wherein the first reset transistor is coupled to one of the output nodes, one of the alignment lines and the ground voltage rail, and wherein the second reset transistor is coupled to another output node of the output nodes, another alignment line and the ground voltage rail.

4. The memory device as claimed in claim 2, wherein when the word line is activated, due to charge sharing between the gate capacitance of the pair of mutually coupled PMOSFET transistors and the capacitance of the pair of word lines at the storage nodes, the voltage at the storage nodes drops below (VDD - Vthp), causing the pair of mutually coupled PMOSFET transistors to be turned on to charge the pair of word lines, such that the differential voltage between the pair of word lines increases over time, wherein Vthp represents the critical voltage of the pair of mutually coupled PMOSFET transistors, and the digital voltage rail carries a supply voltage (VDD).

5. The memory device as claimed in claim 2, wherein, prior to the activation of the second control signal, the switching device is turned off to cut off the channel leakage current path from the source electrodes of the plurality of NMOSFET transistors in the sensing latch to the ground voltage rail.

6. The memory device as claimed in claim 2, wherein the sensing circuit further includes: an accelerator transistor, responding to the second control signal, for selectively coupling the digital voltage rail to the first connection node.

7. The memory device as claimed in claim 6, wherein when the second control signal is activated, the switching device, the accelerating transistor, and the sensing latch are turned on, such that the differential voltage between the bit lines is amplified to a supply voltage carried by the digital voltage rail.

8. The memory device as claimed in claim 1, wherein the sensing circuit further comprises: a tri-state buffer having a data input node coupled to one of the output nodes for responding to the second control signal and selectively outputting a data bit based on the voltage at one of the output nodes.

9. The memory device as claimed in claim 1, wherein the switching device is an NMOSFET transistor, and the gate electrode of the NMOSFET transistor receives the second control signal.

10. A reading method for reading a data bit from a static random access memory (SRAM) cell of a memory device, wherein the memory device includes a sensing circuit, and the SRAM cell has only four transistors, including a pair of mutually coupled PMOSFET transistors and two access transistors, wherein the pair of mutually coupled PMOSFET transistors are coupled to a digital voltage rail and two storage nodes, wherein the two access transistors are responsive to form a word line and are coupled to the two storage nodes and the pair of bit lines, wherein the sensing circuit includes a switching device, a sensing latch, and a discharging device, wherein the sensing latch is coupled between a first connection node and a second connection node and has two output nodes respectively coupled to the pair of bit lines, wherein the discharging device is coupled to the two output nodes, the pair of bit lines, and the ground voltage rail, and the switching device is coupled between the second connection node and the ground voltage rail, the method comprising the steps of: (1) (1) Discharge the pair line to a ground voltage by activating the discharge device; (2) Turn off the switching device; (3) After steps (1) and (2), activate the word line, causing the voltage at the two storage nodes to drop to near the ground voltage, and then causing the pair line to be charged; and (4) After step (3), during a sensing period, activate the switching device and the sensing latch to increase the differential voltage between the pair lines to a supply voltage (VDD) carried by the digital voltage rail.

11. The method of claim 10, wherein step (3) comprises: activating the word line, causing the voltage at the two storage nodes to drop to near the ground voltage due to charge sharing between the gate capacitance of the pair of mutually coupled PMOSFET transistors and the capacitance of the pair of word lines at the two storage nodes; and when the voltage at the two storage nodes drops below (VDD - Vthp), causing the pair of mutually coupled PMOSFET transistors to be turned on to charge the pair of word lines, such that the differential voltage between the pair of word lines increases over time, wherein Vthp represents the critical voltage of the pair of mutually coupled PMOSFET transistors.

12. The method as described in claim 10 further comprises: after step (3), during the sensing period, activating a tri-state buffer to output the data bit based on the voltage at one of the two output nodes; wherein, The sensing circuit further includes the tri-state buffer, with a data input node coupled to one of the two output nodes.

13. The method as claimed in claim 10, wherein step (4) comprises: after step (3), during the sensing period, activating an accelerating transistor to couple the digital voltage rail to the first connection node to charge one of the bit lines to the supply voltage; wherein, The accelerating transistor is coupled between the digital voltage rail and the first connection node.

14. The method as described in claim 10, wherein the switching device is an NMOSFET transistor.

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