Selective etching of silicon-and-germanium-containing materials with reduced under layer loss

Abstract

An exemplary semiconductor processing method may include providing a first etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first silicon and germanium-containing material layer, a second silicon and germanium-containing material layer, and a silicon-containing material layer may be disposed on the substrate. The method may include providing a passivation precursor to the processing region. The method may include contacting the substrate with the first etchant precursor and the passivation precursor. This contact may selectively etch the first silicon and germanium-containing material layer. This contact may form a passivation material on the substrate.

Description

[Technical Field]

[0001] This case claims priority to U.S. Patent Application No. 63 / 552,548, filed on February 12, 2024, entitled “SELECTIVE ETCHING OF SILICON-AND-GERMANIUM-CONTAINING MATERIALS WITH REDUCED UNDER LAYER LOSS”, the entire contents of which are incorporated herein by reference.

[0002] This invention relates to semiconductor processing and apparatus. More specifically, this invention relates to the selective etching of silicon- and germanium-containing materials in vertical structures. [Previous Technology]

[0003] Integrated circuits can be manufactured by processes that create complex patterned material layers on the surface of a substrate. Creating patterned material on a substrate requires controlled methods for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on a surface. It is generally desirable for etching processes to etch one material faster than another to facilitate, for example, pattern transfer processes. This type of etching process is referred to as selective for the first material. Due to the diversity of materials, circuits, and processes, etching processes have been developed to be selective for various materials.

[0004] Based on the materials used in the process, the etching process can be referred to as wet or dry. Wet HF etching preferentially removes silicon oxide, rather than other dielectrics and materials. However, wet processing can be difficult to penetrate some confined trenches and can sometimes deform the remaining material. Dry etching, which generates localized plasma within the substrate processing area, can penetrate more confined trenches and exhibits less deformation of the fragile remaining structure. However, localized plasma can damage the substrate through the arcs generated by their discharge.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These needs, along with other needs, are met by the present invention. [Summary of the Invention]

[0006] An exemplary semiconductor processing method may include providing a first etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first silicon and germanium-containing material layer, a second silicon and germanium-containing material layer, and a silicon-containing material layer may be disposed on the substrate. The method may include providing a passivation precursor to the processing region. The method may include contacting the substrate with the first etchant precursor and the passivation precursor. This contact may selectively etch the first silicon and germanium-containing material layer. This contact may form a passivation material on the substrate.

[0007] In some embodiments, the first silicon and germanium-containing material layer may be characterized by a first germanium concentration. The second silicon and germanium-containing material layer may be characterized by a second germanium concentration. The first germanium concentration may be less than the second germanium concentration. The passivation precursor may be or include a fluorine- and carbon-containing precursor. The passivation precursor may be or include perfluoropentane (C5F12). The method may include forming a plasma effluent of a first etchant precursor, a passivation precursor, or both. The first etchant precursor may be or include a fluorine-containing precursor. The method may include providing an inert gas with the first etchant precursor, the passivation precursor, or both. The passivation precursor may be characterized by a boiling point of less than or about 100 °C. The passivation precursor may be characterized by a vapor pressure of less than or about 100 kPa at 25 °C. The pressure in the processing zone may be maintained at less than or about 30 Torr. The temperature in the processing zone may be maintained at less than or about 150 °C.

[0008] Some embodiments of the present invention may cover semiconductor processing methods. The method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first silicon-and-germanium material layer, a second silicon-and-germanium material layer, and a silicon-containing material layer may be disposed on the substrate. The first silicon-and-germanium material layer may be characterized by a lower germanium concentration than the second silicon-and-germanium material layer. The method may include contacting the substrate with the oxygen-containing precursor. This contact may oxidize at least a portion of the second silicon-and-germanium material layer. The method may include providing a first fluorine-containing precursor to the processing region. The method may include providing a fluorine-and-carbon precursor to the processing region. The method may include contacting the substrate with both the first fluorine-containing precursor and the fluorine-and-carbon precursor. This contact may etch the first silicon-and-germanium material layer relative to the second silicon-and-germanium material layer while preventing etching of the second silicon-and-germanium material layer.

[0009] In some embodiments, the fluorinated and carbon precursor may be or include perfluoropentane (C5F12). The flow rate of the fluorinated and carbon precursor may be less than the flow rate of the first fluorinated precursor. The flow rate of the fluorinated and carbon precursor may be less than or about 1,000 sccm. The method may include forming a plasma effluent of the first fluorinated precursor. This contact may etch the first silicon and germanium material layer with a selectivity greater than or about 40:1 relative to the second silicon and germanium material layer.

[0010] Some embodiments of the present invention cover semiconductor processing methods. The method may include providing a first fluorinated precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first silicon and germanium-containing material layer, a second silicon and germanium-containing material layer, and a silicon-containing material layer may be disposed on the substrate. The first silicon and germanium-containing material layer may be characterized by a lower germanium concentration than the second silicon and germanium-containing material layer. The method may include providing a fluorinated and carbon-containing precursor to the processing region. The method may include contacting the substrate with the first fluorinated precursor and the fluorinated and carbon-containing precursor. This contact may selectively etch the first silicon and germanium-containing material layer while preventing etching of the second silicon and germanium-containing material layer. The method may include providing a second fluorinated precursor and a hydrogen-containing precursor to the processing region. The method may include forming a plasma effluent of the second fluorinated precursor and the hydrogen-containing precursor. The method may include contacting the substrate with the plasma effluent of the second fluorinated precursor and the hydrogen-containing precursor. This contact may etch a portion of the silicon-containing material layer.

[0011] In some embodiments, the flow rate ratio of the first fluorinated precursor to the fluorinated and carbon precursors may be greater than or about 1:1. The fluorinated and carbon precursors may be or include perfluoropentane (C5F12).

[0012] The present invention provides many advantages over conventional systems and techniques. For example, the process can selectively etch one silicon and germanium-containing material relative to another silicon and germanium-containing material. Furthermore, the presence of a passivation precursor can act as a barrier to prevent undesirable etching of the material beneath the silicon and germanium-containing material to be etched. These and other embodiments, as well as their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

Implementation Method

[0022] In the transition to gate-all-around (GAA) transistors, many processing operations are modified from those of the more conventional fin field-effect (FinFET) transistors. Furthermore, as structures continue to shrink in size, the thickness of material layers decreases, while the aspect ratio of memory holes to other structures increases, sometimes significantly.

[0023] During the GAA process, alternating material layers, such as alternating silicon-containing material layers and silicon-and-germanium-containing material layers, are deposited on the substrate. In the formation of the transistor, memory holes or trenches may be formed through the alternating material layers. During the GAA process, silicon-and-germanium-containing materials may be recessed from within the memory holes or trenches to form materials that will serve as nanowires / nanosheets. Subsequent recesses of one or more materials, including another silicon-and-germanium-containing material, may be formed within the recesses and / or memory holes or trenches.

[0024] Due to the similarity of materials in some GAA transistors, selectively removing one material relative to another becomes more difficult. For example, multiple silicon-containing materials, including multiple silicon-and-germanium-containing materials, can be used in GAA processing. In some operations, it is desirable to remove one silicon-and-germanium-containing material, such as silicon-and-germanium-containing nanowires, relative to epitaxial silicon-and-germanium-containing materials and other silicon-containing materials. The prior art has struggled with selectively removing one silicon-and-germanium-containing material relative to another. Non-selective removal can result in undesirable etching of some materials, such as epitaxial silicon-and-germanium-containing materials.

[0025] This invention overcomes these problems by performing selective oxidation prior to etching silicon and germanium-containing materials, such as silicon and germanium-containing nanowires. Selective oxidation preferentially oxidizes silicon and germanium-containing materials characterized by higher germanium concentrations, such as epitaxial silicon and germanium-containing materials. Oxidized silicon and germanium-containing materials are more resistant to etching than unoxidized silicon and germanium-containing materials. Therefore, subsequent etching operations that remove silicon and germanium-containing materials characterized by lower germanium concentrations can selectively remove lower concentration materials relative to higher concentration materials. This invention can also overcome these problems by providing passivation precursors and etchant precursors. Passivation precursors prevent etchant species from reaching materials beneath the silicon and germanium-containing materials to be etched, such as silicon and germanium-containing materials to be retained. Therefore, the etching operation of this invention can successfully remove one silicon and germanium-containing material while retaining another silicon and germanium-containing material and other silicon-containing materials.

[0026] While the remainder of the specification will routinely identify specific etching processes utilizing the disclosed techniques, it will be readily understood that this system and method can be equally applied to etching processes that may occur in the described chambers. Therefore, the invention should not be construed as being so limited to use solely in etching processes or chambers. Furthermore, although exemplary chambers are described to provide the basis for the invention, it will be understood that the invention can be applied to any semiconductor processing chamber that practically permits the described operations.

[0027] Figure 1 shows a top plan view of an embodiment of a processing system 100 for deposition, etching, baking, and curing chambers according to an embodiment. In the figure, a pair of front-opening wafer transfer cassettes (FOUPs) 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed into a low-pressure holding region 106 before being placed into one of the substrate processing chambers 108a-f, which are positioned in series segments 109a-c. A second robotic arm 110 can be used to transfer substrate wafers from the holding region 106 back and forth between the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform various substrate processing operations, including dry etching processes and circulating layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, degassing, orientation, and other substrate processing as described herein.

[0028] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films on a substrate wafer. In one configuration, two pairs of processing chambers, such as 108c-d and 108e-f, may be used to deposit dielectric material on the substrate, and a third pair of processing chambers, such as 108a-b, may be used to etch the deposited dielectric material. In another configuration, all three pairs of chambers, such as 108a-f, may be configured to etch dielectric films on the substrate. Any or more of the described processes may be performed in chambers separate from the manufacturing systems shown in different embodiments. Additional configurations for the deposition, etching, annealing, and curing chambers for dielectric films will be appreciated by way of system 100.

[0029] Figure 2A shows a cross-sectional view of an exemplary processing chamber system 200 with plasma generation zones separated within the processing chamber. During film etching, for example, titanium nitride, tantalum nitride, tungsten, silicon, polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc., processing gases can be flowed into the first plasma zone 215 through the gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in this system and can process the first gas, which then travels through the gas inlet assembly 205. The gas inlet assembly 205 may include two or more distinct gas supply channels, wherein a second channel (not shown) may bypass the RPS 201 (if included).

[0030] A cooling plate 203, a panel 217, an ion suppressor 223, a spray head 225, and a pedestal 265 having a substrate 255 mounted thereon are shown and may each be included according to embodiments. The pedestal 265 may have heat exchange channels through which heat exchange fluid flows to control the temperature of the substrate, and may be operable to heat and / or cool the substrate or wafer during processing operations. The wafer support shallows of the pedestal 265 (which may include aluminum, ceramic, or a combination thereof) may also be resistively heated to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C, using embedded resistance heater elements.

[0031] Panel 217 may be pyramidal, conical, or other similar structures having a narrow apex extending to a wide base. Panel 217 may additionally be flat as shown and include a plurality of through channels for distributing the process gas. Depending on the use of RPS 201, plasma-generating gas and / or plasma-excited species may pass through the plurality of holes in panel 217 (as shown in Figure 2B) for more uniform delivery into the first plasma zone 215.

[0032] An exemplary configuration may include opening the gas inlet assembly 205 into the gas supply region 258, which is separated from the first plasma region 215 by the panel 217, allowing gas / species flow through holes in the panel 217 into the first plasma region 215. Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The panel 217, or the conductive top portion of the chamber, and the spray head 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the panel 217 relative to the spray head 225 and / or the ion suppressor 223. The insulating ring 220 may be positioned between the panel 217 and the spray head 225 and / or the ion suppressor 223, allowing capacitively coupled plasma (CCP) to be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma zone 215 or coupled to the gas inlet assembly 205 to affect the flow of fluid entering this zone via the gas inlet assembly 205.

[0033] The ion suppressor 223 may comprise a plate or other geometry defining a plurality of holes through this structure. These holes are configured to suppress the migration of charged ions away from the first plasma region 215, while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into the activation gas delivery region between the suppressor and the spray head. In embodiments, the ion suppressor 223 may comprise a perforated plate with various hole configurations. These uncharged species may include highly reactive species that can be delivered through the holes with a less reactive carrier gas. As described above, the migration of ion species through the holes can be reduced, and in some cases, completely suppressed. Controlling the number of ion species passing through the ion suppressor 223 can advantageously provide increased control over the gas mixture that is brought into contact with the underlying wafer substrate, thereby increasing the deposition and / or etching characteristics of the gas mixture. For example, adjustments to the ion concentration in the gas mixture can significantly alter its etching selectivity, e.g., SiGex:SiOx etching ratio, SiGex:Si etching ratio, etc. In alternative embodiments where deposition is performed, the equilibrium of the dielectric material can also be altered from conformal deposition to flow deposition.

[0034] A plurality of holes in the ion suppressor 223 may be configured to control the passage of the activating gas, i.e., ions, free radicals, and / or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter relative to the length, and / or the geometry of the holes may be controlled such that the flow of charged ions in the activating gas traveling through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion facing the plasma region 215 and a cylindrical portion facing the spray head 225. The cylindrical portion may be shaped and sized to control the flow of ion species through the spray head 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means of controlling the flow of ion species through the suppressor.

[0035] The ion suppressor 223 can function to reduce or eliminate the number of ionic charged species traveling from the plasma generation region to the substrate. Uncharged neutral and free radical species can still pass through openings in the ion suppressor to react with the substrate. It should be noted that in embodiments, complete elimination of ionic charged species in the reaction region surrounding the substrate may not be performed. In certain examples, ionic species intentionally reach the substrate to perform etching and / or deposition processes. In these examples, the ion suppressor helps to control the concentration of ionic species in the reaction region to a level that facilitates this process.

[0036] The combination of the spray head 225 and the ion suppressor 223 allows plasma to be present in the first plasma region 215 to avoid directly exciting the gas in the substrate processing region 233, while still allowing excited species to travel from the chamber plasma region 215 into the substrate processing region 233. In this way, the chamber can be configured to prevent plasma from contacting the etched substrate 255. This advantageously protects various complex structures and films patterned on the substrate from damage, displacement, or deformation if directly contacted by the generated plasma. Furthermore, when plasma is allowed to contact or approach the substrate surface, the etchability rate of the material increases. Therefore, by maintaining the plasma at the distal end of the substrate, the exposed area of ​​the material is further protected.

[0037] The processing system may further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, ion suppressor 223, spray head 225, and / or stage 265 to generate plasma in the first plasma zone 215 or processing zone 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the processing being performed. This configuration allows for the use of tunable plasma in the performed processing. Unlike remote plasma units, which typically exhibit on / off functionality, tunable plasma may be configured to deliver a specific amount of power to the first plasma zone 215. This allows for the development of specific plasma characteristics, such that precursors are dissociated in a specific manner to enhance the etch profile produced by these precursors.

[0038] Plasma can be ignited in the chamber plasma region 215 above the spray head 225 or in the substrate processing region 233 below the spray head 225. Plasma can be present in the chamber plasma region 215 to generate free radical precursors from the inflow of, for example, fluorine-containing precursors or other precursors. An AC voltage, typically in the radio frequency (RF) range, can be applied between the conductive top portion of the processing chamber (such as panel 217) and the spray head 225 and / or ion suppressor 223 to ignite the plasma in the chamber plasma region 215 during deposition. The RF power supply can generate a high RF frequency of 13.56 MHz, but other frequencies alone or in combination with the 13.56 MHz frequency can also be generated.

[0039] Figure 2B shows a detailed view 253 of the features affecting the distribution of the processing gas through panel 217. As shown in Figures 2A and 2B, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define gas supply zone 258, from which processing gas can be delivered into gas supply zone 258. Gas can fill gas supply zone 258 and flow through holes 259 in panel 217 to first plasma zone 215. Holes 259 can be configured to guide flow in a substantially unidirectional manner, allowing processing gas to flow into processing zone 233, but partially or completely preventing backflow into gas supply zone 258 after passing through panel 217.

[0040] Gas distribution assemblies such as spray heads 225 used in the processing chamber section 200 may be referred to as dual-channel spray heads (DCSH) and are further detailed in the embodiments described in Figure 3. The dual-channel spray head can provide etching processing, allowing for the separation of etchant outside the processing zone 233 to provide limited interaction between the etchant and the chamber components and the etchant itself before it is delivered into the processing zone.

[0041] The spray head 225 may include an upper plate 214 and a lower plate 216. These plates may be coupled to another plate to define a volume 218 between the plates. The coupling of these plates may be to provide a first fluid passage 219 through the upper and lower plates, and a second fluid passage 221 through the lower plate 216. The formed passage may be configured to provide fluid inflow and outflow from the volume 218 through the second fluid passage 221 through the lower plate 216, and the first fluid passage 219 may be fluidly isolated from the volume 218 and the second fluid passage 221 between the plates. The volume 218 may be fluidly inflowed and outflowed through one side of the spray head 225.

[0042] Figure 3 is a bottom view of a spray head 325 used in a processing chamber according to an embodiment. The spray head 325 may correspond to the spray head 225 shown in Figure 2A. The perforations 365, showing a view of the first fluid channel 219, may have a plurality of shapes and configurations to control and influence the flow of precursors through the spray head 225. The small holes 375, showing a view of the second fluid channel 221, may be substantially uniformly distributed above the surface of the spray head, even in the middle of the perforations 365, and compared to other configurations, may help to provide a more uniform mixing of precursors as they leave the spray head.

[0043] The previously discussed chamber can be used to perform exemplary methods including etching methods. Turning to Figure 4, an exemplary operation in method 400 according to an embodiment of the invention is shown. Prior to the first operation of this method, the substrate can be processed in one or more ways before being placed in the processing area of ​​the chamber in which method 400 can be performed. For example, alternating layers of material can be formed on the substrate, and then one or more memory vias or trenches can be formed through the alternating layers. The alternating layers can include any number of materials and can include alternating layers of silicon-containing materials and silicon-and-germanium-containing materials. Although the remainder of the description will discuss silicon-containing materials and silicon-and-germanium-containing materials, any other known material in these two layers can be used to replace one or more of these layers. One material in the alternating layers, such as silicon-and-germanium-containing materials, can be recessed. In the recess, an oxygen-containing material can be formed, followed by a spacer material. In addition, an epitaxial material, such as a second silicon-and-germanium-containing material, can be formed in one or more memory vias or trenches. Some or all of these operations may be performed in the previously described chambers or system tools, or may be performed in different chambers on the same system tool, which may include the chamber in which the operations of method 400 are performed.

[0044] Method 400 may include providing a processing precursor, such as a pretreatment precursor or a pre-etching precursor, to a semiconductor processing chamber in an optional operation 405. In some embodiments, an inert precursor may be provided along with the processing precursor. An exemplary chamber may be the aforementioned chamber 200, which may include one or both of RPS unit 201 or first plasma region 215. Plasma may be formed in optional operation 410, which may form a plasma effluent of the processing precursor. A substrate may contact the processing precursor, or contact the plasma effluent of the processing precursor (if formed) in optional operation 415. Contact in optional operation 415 may remove native oxides present on the first silicon and germanium-containing material layer and the second silicon and germanium-containing material layer on the substrate. Operations for developing the structure may include removing or etching one or more materials. To increase selectivity during removal or etching, method 400 may include providing an oxygen-containing precursor to a processing region in optional operation 420, optionally forming a plasma effluent of the oxygen-containing precursor in optional operation 425, and contacting a substrate with the oxygen-containing precursor or its plasma effluent in optional operation 430. The contact in optional operation 430 may oxidize at least a portion of a second silicon- and germanium-containing material layer, which may be an epitaxial silicon- and germanium-containing material. After a number of oxidations, method 400 may include providing a first etchant precursor to the processing region in operation 435, providing a passivation precursor to the processing region in operation 440, optionally forming a plasma effluent of the first etchant precursor and / or passivation precursor in optional operation 445, and contacting a substrate with the first etchant precursor and the passivation precursor in operation 450. The contact in operation 450 may selectively etch a first silicon- and germanium-containing material layer, which may be silicon- and germanium-containing nanowires in a GAA transistor. This contact may also form a passivation material on the material beneath the first silicon and germanium-containing material layer to be etched. The passivation material prevents pitting corrosion of the material beneath the first silicon and germanium-containing material layer. Method 400 may include providing a second etchant precursor to the processing area in operation 435, optionally forming a plasma effluent of the second etchant precursor in optional operation 455, and optionally contacting the substrate with the second etchant precursor in operation 460. The second etchant precursor can remove a portion of the silicon-containing material, such as silicon-containing material with germanium residue. Reducing and / or removing germanium residue can increase the performance of the final device by improving electron mobility.

[0045] Method 400 may involve the selective oxidation of one silicon and germanium-containing material relative to another silicon and germanium-containing material. Due to the germanium concentration of the material, one silicon and germanium-containing material can be selectively oxidized to a greater extent relative to the other silicon and germanium-containing material. The silicon and germanium-containing material to be oxidized can be characterized by a higher germanium concentration, and therefore can be preferentially oxidized relative to other silicon and germanium-containing materials. By selectively oxidizing one silicon and germanium-containing material relative to another silicon and germanium-containing material, subsequent etching operations can selectively remove silicon and germanium-containing materials that remain unoxidized or less oxidized relative to other silicon and germanium-containing materials. Thus, in GAA transistors, for example, silicon and germanium-containing nanowires with lower germanium content can be selectively etched or released relative to silicon and germanium-containing epitaxial materials with higher germanium content. Method 400 allows for selective oxidation of one silicon and germanium-containing material relative to another silicon and germanium-containing material and subsequent selective removal.

[0046] In method 400, the precursor provided to the processing area in optional operation 405 may include a processing precursor, such as a pretreatment precursor or a pre-etching precursor, and optionally an inert precursor. Example processing precursors may be hydrogen-containing precursors, nitrogen-containing precursors, or combinations thereof, which may flow into the processing area. Hydrogen-containing precursors may be or include, for example, molecular hydrogen (H2), ammonia (NH3), or any other hydrogen-containing precursor used or useful in semiconductor processing. Nitrogen-containing precursors may be or include, for example, molecular nitrogen (N2), ammonia (NH3), or any other nitrogen-containing precursor used or useful in semiconductor processing. In some embodiments, the processing precursor may be provided along with an inert precursor. Inert precursors may be or include, for example, argon, helium, xenon, or other rare, inert, or useful precursors. Inert precursors may be used to dilute the processing precursor or to aid in distributing the processing precursor throughout the processing area.

[0047] If formed in optional operation 410, the plasma effluent (if present) of the treatment precursor and the inert precursor can be generated at a plasma power of less than or about 5,000 W, and can be generated at less than or about 4,750 W, less than or about 4,500 W, less than or about 4,250 W, less than or about 4,000 W, less than or about 3,750 W, less than or about 3,500 W, less than or about 3,250 W, less than or about 3,000 W, less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less.

[0048] In optional operation 415, the plasma effluent of the substrate-accessible processing precursor remains in contact with the substrate for a sufficient period of time to remove native oxides from the silicon and germanium-containing material. In embodiments, the period may be greater than or about 3 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 30 seconds, greater than or about 40 seconds, greater than or about 50 seconds, greater than or about 1 minute, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 5 minutes, or higher. The period may be sufficient to remove greater than or about 85% of the native oxides from the silicon and germanium-containing material, and greater than or about 90%, greater than or about 95%, greater than or about 97%, greater than or about 99%, greater than or about 99.9%, or higher, or all of the native oxides may be removed from the silicon and germanium-containing material.

[0049] In an embodiment, method 400 may include providing an oxygen-containing precursor to a processing area of ​​a semiconductor processing chamber in an optional operation 420. In some embodiments, an inert precursor may be provided along with the oxygen-containing precursor. The oxygen-containing precursor may be or include, for example, molecular oxygen (O2), vapor (H2O), hydrogen peroxide (H2O2), or any other oxygen-containing precursor used or useful in semiconductor processing. The inert precursor may be or include, for example, argon, helium, xenon, or other rare, inert, or useful precursors. The inert precursor may be used to dilute the oxygen-containing precursor, which may further reduce the oxidation rate to control oxidation and oxidation selectivity, or to facilitate the distribution of the oxygen-containing precursor throughout the processing area. Furthermore, the flow rate ratio of the oxygen-containing precursor to the inert precursor (if present) may be adjusted to adjust the oxidation effect and / or oxidation selectivity of the oxygen-containing precursor.

[0050] The flow rates of the oxygen-containing precursor and the inert precursor (if present) are sufficient to selectively oxidize one silicon- and germanium-containing material relative to another silicon- and germanium-containing material. In embodiments, the flow rate of the oxygen-containing precursor to the treatment zone may be greater than or about 1 sccm, and may be greater than or about 10 sccm, greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1,000 sccm, greater than or about 1,500 sccm, greater than or about 2,000 sccm, greater than or about 2,500 sccm, greater than or about 3,000 sccm, greater than or about 3,500 sccm, greater than or about 4,000 sccm, or higher. In addition, the flow rate of the inert precursor that can dilute and / or dispense the oxygen-containing precursor or its plasma effluent may be greater than or about 100 sccm, and may be greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 2,500 sccm, greater than or about 5,000 sccm, greater than or about 7,500 sccm, greater than or about 10,000 sccm, or higher.

[0051] In some embodiments, an oxygen-containing precursor plasma effluent may be generated during optional operation 425. As discussed, the plasma effluent may be generated in the processing area. However, it is contemplated that a plasma effluent without an oxygen-containing precursor may be formed, and plasma-free or thermal oxidation may be performed. For example, when the oxygen-containing precursor is O2 or H2O, the plasma effluent may oxidize all silicon and germanium-containing materials on the substrate. Therefore, subsequent etching to remove one silicon and germanium-containing material relative to another may be an etching that does not etch any oxidized silicon and germanium-containing material. In embodiments forming plasma effluents containing oxygen precursors, plasma effluents containing oxygen precursors and inert precursors (if present) may be generated at plasma power less than or about 5,000 W, and may be generated at less than or about 4,750 W, less than or about 4,500 W, less than or about 4,250 W, less than or about 4,000 W, less than or about 3,750 W, less than or about 3,500 W, less than or about 3,250 W, less than or about 3,000 W, less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less. Compared to pretreatment precursors, plasma effluents from oxygen-containing precursors can be generated at lower plasma power. By generating posttreatment plasma effluents at lower plasma power, oxidation can be better controlled and the impact / damage to the substrate and the materials deposited thereon can be limited.

[0052] Method 400 may include, in an optional operation 430, contacting the substrate with an oxygen-containing precursor or its plasma effluent. This contact may last for a sufficient period to oxidize at least one of a plurality of silicon- and germanium-containing materials on the substrate. In embodiments, the period may be greater than or about 3 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 30 seconds, greater than or about 40 seconds, greater than or about 50 seconds, greater than or about 1 minute, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 5 minutes, or longer. Similarly, the period may be less than or about 5 minutes, less than or about 3 minutes, less than or about 2 minutes, less than or about 1 minute, less than or about 50 seconds, less than or about 40 seconds, less than or about 30 seconds, less than or about 20 seconds, less than or about 10 seconds, less than or about 5 seconds, less than or about 3 seconds, or less.

[0053] By contacting the substrate with an oxygen-containing precursor, germanium and / or silicon in the silicon- and germanium-containing material can bond with oxygen to oxidize a portion of the silicon- and germanium-containing material. Without being limited by any particular theory, it is believed that germanium bonds more readily with oxygen, and silicon- and germanium-containing materials with higher germanium concentrations are more easily oxidized than adjacent silicon- and germanium-containing materials with lower germanium concentrations. Furthermore, it is believed that Si-Ge bonds in silicon- and germanium-containing materials are more easily broken than Si-Si bonds in adjacent silicon-containing materials, and silicon- and germanium-containing materials are more easily oxidized than adjacent silicon-containing materials. Moreover, by operating within the temperature and / or pressure range discussed later, silicon- and germanium-containing materials with higher germanium concentrations can be oxidized more readily.

[0054] In operation 435, method 400 may include providing a first etchant precursor to a processing region of a semiconductor processing chamber. The first etchant precursor may be a halogen-containing precursor or any other precursor capable of selectively etching silicon- and germanium-containing materials. The first etchant precursor may be or include, for example, diatomic fluorine (F2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or any other fluorine-containing precursor used or useful in semiconductor processing.

[0055] In operation 440, method 400 may include providing a passivation precursor to a processing region of a semiconductor processing chamber. The passivation precursor may be provided together with a first etchant precursor. However, it is also contemplated that the passivation precursor and the first etchant precursor may be provided sequentially. The passivation precursor may be a carbon-containing precursor or any other precursor capable of selectively passivating a material beneath the silicon- and germanium-containing material to be etched. More specifically, the passivation precursor may block pitting cavities in a material such as a spacer material (e.g., a low-dielectric-constant material) beneath the silicon- and germanium-containing material to be etched.

[0056] The passivation precursor can be characterized by its boiling point and / or vapor pressure, which promotes the condensation of the passivation precursor as a passivation material in the pitting cavities of the material beneath the silicon and germanium-containing material to be etched. For example, the passivation precursor can be characterized by a boiling point of less than or about 100 °C, such as less than or about 90 °C, less than or about 80 °C, less than or about 70 °C, less than or about 60 °C, less than or about 50 °C, less than or about 45 °C, less than or about 40 °C, less than or about 35 °C, less than or about 30 °C, less than or about 25 °C, less than or about 20 °C, less than or about 15 °C, less than or about 10 °C, less than or about 5 °C, or less. The passivation precursor may be characterized as having a vapor pressure at 25 °C of less than or about 100 kPa, less than or about 95 kPa, less than or about 90 kPa, less than or about 85 kPa, less than or about 80 kPa, less than or about 75 kPa, less than or about 70 kPa, less than or about 65 kPa, less than or about 60 kPa, less than or about 55 kPa, or less. In embodiments, the passivation precursor may be a fluorinated and carbon-containing precursor (i.e., a fluorocarbon compound). The passivation precursor may be or include, for example, perfluoropentane (C5F12), or any other fluorinated and carbon-containing precursor used or useful in semiconductor processing.

[0057] In some embodiments, an inert precursor may be provided along with a first etchant precursor and / or a passivation precursor. The inert precursor may be or include, for example, argon, helium, xenon, or other rare, inert, or useful precursors. The inert precursor may be used to dilute the first etchant precursor and / or the passivation precursor, which may further reduce the etch rate to control etch selectivity, or to facilitate the distribution of the first etchant precursor and / or the passivation precursor throughout the processing area. Furthermore, the flow rate ratio of the first etchant precursor, the passivation precursor, and the inert precursor (if present) may be adjusted to adjust the etch selectivity.

[0058] The flow rate of the first etchant precursor is sufficient to selectively etch another silicon and germanium-containing material relative to one silicon and germanium-containing material. In embodiments, the flow rate of the first etchant precursor to the processing area may be greater than or about 1 sccm, and may be greater than or about 10 sccm, greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1,000 sccm, greater than or about 1,500 sccm, greater than or about 2,000 sccm, greater than or about 2,500 sccm, greater than or about 3,000 sccm, greater than or about 3,500 sccm, greater than or about 4,000 sccm, or higher.

[0059] The flow rate of the passivation precursor is sufficient to passivate the material beneath the silicon- and germanium-containing material to be etched. Furthermore, the flow rate of the passivation precursor can be minimized to reduce any impact on the desired etching. In embodiments, the flow rate of the passivation precursor to the treatment zone may be less than or about 1,000 sccm, and may be less than or about 900 sccm, less than or about 800 sccm, less than or about 700 sccm, less than or about 600 sccm, less than or about 500 sccm, less than or about 400 sccm, less than or about 300 sccm, less than or about 200 sccm, less than or about 100 sccm, less than or about 90 sccm, less than or about 80 sccm, less than or about 70 sccm, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 20 sccm, less than or about 10 sccm, or even smaller.

[0060] Furthermore, the flow rate ratio of the first etchant precursor to the passivation precursor can be maintained to reduce any impact on the desired etching. In embodiments, the flow rate ratio of the first etchant precursor to the passivation precursor can be greater than or about 1:1, and can be greater than or about 1.2:1, greater than or about 1.4:1, greater than or about 1.6:1, greater than or about 1.8:1, greater than or about 2:1, greater than or about 2.5:1, or greater. The relatively low flow rate of the passivation precursor ensures that the passivation material forms to block pitting cavities in the material beneath the silicon and germanium-containing material to be etched, without disrupting the desired etching of the silicon and germanium-containing material. If the flow rate of the passivation precursor relative to the first etchant precursor is too high, the etching rate of the silicon and germanium-containing material will decrease.

[0061] In addition, the flow rate of the inert precursor that can be diluted and / or dispensed as a first etchant precursor, passivation precursor, or plasma effluent thereof may be greater than or about 100 sccm, and may be greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 2,500 sccm, greater than or about 5,000 sccm, greater than or about 7,500 sccm, greater than or about 10,000 sccm, or higher.

[0062] In some embodiments, plasma effluents of a first etchant precursor and / or passivation precursor may be generated during optional operation 445. As discussed, the plasma effluents may be generated in the processing zone. In embodiments, plasma effluents of the first etchant precursor, passivation precursor, and inert precursor (if present) may be generated at a plasma power of less than or about 5,000 W, and may be generated at less than or about 4,750 W, less than or about 4,500 W, less than or about 4,250 W, less than or about 4,000 W, less than or about 3,750 W, less than or about 3,500 W, less than or about 3,250 W, less than or about 3,000 W, less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less.

[0063] Method 400 may include contacting a substrate with a first etchant precursor and a passivation precursor, or their plasma effluent, in operation 450. This contact may last for a sufficient period of time to etch at least one of a plurality of silicon- and germanium-containing materials on the substrate. In embodiments, the period may be greater than or about 3 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 30 seconds, greater than or about 40 seconds, greater than or about 50 seconds, greater than or about 1 minute, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 5 minutes, or higher. Similarly, the period may be less than or about 5 minutes, less than or about 3 minutes, less than or about 2 minutes, less than or about 1 minute, less than or about 50 seconds, less than or about 40 seconds, less than or about 30 seconds, less than or about 20 seconds, less than or about 10 seconds, less than or about 5 seconds, less than or about 3 seconds, or less.

[0064] By contacting the substrate with the first etchant precursor, unoxidized silicon and germanium-containing materials can be selectively removed relative to other materials on the substrate, including oxidized silicon and germanium-containing materials. Without being limited by any particular theory, it is believed that oxidized silicon and germanium-containing materials are more resistant to the first etchant precursor than unoxidized silicon and germanium-containing materials. Therefore, unoxidized silicon and germanium-containing materials can be selectively removed relative to oxidized silicon and germanium-containing materials. Thus, in GAA transistors, unoxidized silicon and germanium-containing materials with lower germanium concentrations, such as SiGe nanowires, can be selectively removed relative to oxidized silicon and germanium-containing materials with higher germanium concentrations, such as epitaxial SiGe materials. Furthermore, a passivation precursor can condense on the material beneath the silicon and germanium-containing material to be etched. The condensation of the passivation precursor can form a passivation material. The passivation material can block pitting cavities (i.e., micropores) in the material beneath the silicon and germanium-containing material.

[0065] In operation 450, another silicon and germanium material layer can be etched relative to a silicon and germanium material layer with a selectivity greater than or about 40:1. For example, an unoxidized silicon and germanium material layer can be etched relative to an oxidized silicon and germanium material layer with a selectivity greater than or about 42:1, such as greater than or about 44:1, greater than or about 46:1, greater than or about 48:1, greater than or about 50:1, greater than or about 52:1, greater than or about 54:1, greater than or about 56:1, greater than 58:1, or greater. In embodiments, the etching rate, such as that of the unoxidized silicon and germanium-containing material layer, may be greater than or about 5.0 Å / s, and may be greater than or about 10.0 Å / s, greater than or about 15.0 Å / s, greater than or about 16.0 Å / s, greater than or about 17.0 Å / s, greater than or about 18.0 Å / s, greater than or about 19.0 Å / s, greater than or about 20.0 Å / s, greater than or about 22.0 Å / s, greater than or about 24.0 Å / s, greater than or about 26.0 Å / s, greater than or about 28.0 Å / s, greater than or about 30.0 Å / s, greater than or about 35.0 Å / s, greater than or about 40.0 Å / s, or greater.

[0066] After selectively etching unoxidized silicon- and germanium-containing materials onto other materials on a substrate, some germanium residue may remain on some surfaces. For example, some germanium residue may be present on silicon-containing materials, such as Si nanowires. If left untreated or not removed from the surface of the silicon-containing material, the residue can affect electron mobility in the final device. Therefore, the presence of germanium residue, such as on silicon-containing materials, can degrade the performance of the final device. The present invention addresses this problem by selectively removing a quantity of silicon-containing material to reduce the presence of germanium residue.

[0067] In optional operation 455, method 400 may include providing a second etchant precursor to a processing region of the semiconductor processing chamber. In some embodiments, a hydrogen-containing precursor and / or an inert precursor may be provided along with the second etchant precursor. The second etchant precursor may be a halogen-containing precursor or any other precursor capable of selectively etching silicon-containing materials. The second etchant precursor may be or include, for example, diatomic fluorine (F2), nitrogen trifluoride (NF3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), xenon difluoride (XeF2), or any other fluorine-containing precursor used or useful in semiconductor processing. The hydrogen-containing precursor may be or include, for example, diatomic hydrogen (H2), ammonia (NH3), hydrocarbons, or any other hydrogen-containing precursor used or useful in semiconductor processing. The inert precursor may be or include, for example, argon, helium, nitrogen, xenon, or other rare, inert, or useful precursors. Inert precursors can be used to dilute the second etchant precursor, which can further reduce the etch rate to control etch selectivity or to facilitate the distribution of the second etchant precursor throughout the processing area. Furthermore, the flow rate ratio of the second etchant precursor to the inert precursor (if present) can be adjusted to modulate etch selectivity.

[0068] The flow rate ratio of the second etchant precursor to the inert precursor (if present) may be sufficient to selectively etch another silicon and germanium-containing material relative to one silicon and germanium-containing material. In embodiments, the flow rate of the second etchant precursor to the processing area may be greater than or about 1 sccm, and may be greater than or about 10 sccm, greater than or about 50 sccm, greater than or about 100 sccm, greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 1,000 sccm, greater than or about 1,500 sccm, greater than or about 2,000 sccm, greater than or about 2,500 sccm, greater than or about 3,000 sccm, greater than or about 3,500 sccm, greater than or about 4,000 sccm, or higher. In addition, the flow rate of the inert precursor that can be diluted and / or dispensed as a second etchant precursor or its plasma effluent may be greater than or about 100 sccm, and may be greater than or about 250 sccm, greater than or about 500 sccm, greater than or about 750 sccm, greater than or about 1,000 sccm, greater than or about 2,500 sccm, greater than or about 5,000 sccm, greater than or about 7,500 sccm, greater than or about 10,000 sccm, or higher.

[0069] In embodiments, the atomic flow ratio of hydrogen to fluorine may be greater than 1:1, greater than or about 1.2:1, greater than or about 1.4:1, greater than or about 1.6:1, greater than or about 1.8:1, greater than or about 2:1, or greater than or about 4:1, or higher. In embodiments, a higher atomic flow ratio of hydrogen to fluorine may increase selectivity. Some precursors may contain both fluorine and hydrogen, wherein all contributing atomic flow ratios are included when calculating the atomic flow ratios described herein. Furthermore, the atomic flow ratio of argon or any other inert material to fluorine may be greater than or about 100:1, greater than or about 150:1, or greater than or about 200:1, or higher.

[0070] In some embodiments, a plasma effluent of a second etchant precursor may be generated during optional operation 460. The plasma effluent may be generated in the processing zone or in the RPS. In embodiments, plasma effluents of the second etchant precursor and hydrogen-containing precursor and / or inert precursor (if present) may be generated at plasma power less than or about 5,000 W, and may be generated at less than or about 4,750 W, less than or about 4,500 W, less than or about 4,250 W, less than or about 4,000 W, less than or about 3,750 W, less than or about 3,500 W, less than or about 3,250 W, less than or about 3,000 W, less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W, less than or about 1,750 W, less than or about 1,500 W, less than or about 1,250 W, less than or about 1,000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less.

[0071] Method 400 may include, in an optional operation 465, contacting the substrate with a second etchant precursor or its plasma effluent. This contact may last for a sufficient period to etch a portion of the silicon-containing precursor onto the substrate. In embodiments, the period may be greater than or about 3 seconds, greater than or about 5 seconds, greater than or about 10 seconds, greater than or about 20 seconds, greater than or about 30 seconds, greater than or about 40 seconds, greater than or about 50 seconds, greater than or about 1 minute, greater than or about 2 minutes, greater than or about 3 minutes, greater than or about 5 minutes, or longer. Similarly, the period may be less than or about 5 minutes, less than or about 3 minutes, less than or about 2 minutes, less than or about 1 minute, less than or about 50 seconds, less than or about 40 seconds, less than or about 30 seconds, less than or about 20 seconds, less than or about 10 seconds, less than or about 5 seconds, less than or about 3 seconds, or shorter. Shorter periods may be preferable to removing only a small amount of silicon-containing material, such as silicon-containing material with germanium residue.

[0072] This contact can etch silicon-containing material less than or about 10 nm to retain the silicon-containing material as much as possible while reducing germanium residue. In an embodiment, this contact can etch silicon-containing material less than or about 9 nm, such as less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, or smaller, such as silicon-containing material between about 2 nm and about 5 nm.

[0073] At the contact of operation 450, a silicon-containing material layer can be etched with a selectivity greater than or about 40:1 relative to any other material on the substrate. For example, the silicon-containing material layer can be etched with a selectivity greater than or about 50:1 relative to any other material on the substrate, such as greater than or about 60:1, greater than or about 70:1, greater than or about 80:1, greater than or about 90:1, greater than or about 100:1, greater than or about 125:1, greater than or about 150:1, or greater.

[0074] After the substrate comes into contact with the second etchant precursor, the surface of the silicon-containing material can be characterized as having a germanium concentration of less than or about 1.5 at.%, and can be characterized as having a germanium concentration of less than or about 1.4 at.%, less than or about 1.3 at.%, less than or about 1.2 at.%, less than or about 1.1 at.%, less than or about 1.1 at.%, less than or about 0.9 at.%, less than or about 0.8 at.%, less than or about 0.7 at.%, less than or about 0.6 at.%, less than or about 0.5 at.%, less than or about 0.4 at.%, less than or about 0.3 at.%, less than or about 0.2 at.%, or less.

[0075] In an embodiment, operations 405-415 may be performed in the same semiconductor processing chamber as operations 420-430, or the substrate may be transferred to a second processing region of a second semiconductor processing chamber to selectively oxidize a silicon- and germanium-containing material on the substrate in operations 420-430. However, the second semiconductor processing chamber may be on the same processing system or host as the semiconductor processing chamber used during operations 405-415, such as processing system 100. Furthermore, operations 435-450 may be performed in the same semiconductor processing chamber as operations 405-415 and / or operations 420-430, or the substrate may be transferred to a third processing region of a third semiconductor processing chamber to selectively etch a silicon- and germanium-containing material on the substrate in operations 435-450. However, the third semiconductor processing chamber may be on the same processing system or host as the semiconductor processing chamber used during operations 405-415 and / or operations 420-430, such as processing system 100. Furthermore, optional operations 455-465 can be performed in the same semiconductor processing chamber as operations 405-415, 420-430, and / or 435-450, or the substrate can be transferred to a fourth processing area of ​​a fourth semiconductor processing chamber to selectively etch silicon-containing material onto the substrate in optional operations 455-465 to reduce and / or remove germanium residue. However, the fourth semiconductor processing chamber can be on the same processing system or host as the semiconductor processing chamber used during operations 405-415, 420-430, and / or 435-450, such as processing system 100. Therefore, contacting the substrate with a pretreatment precursor, contacting the substrate with an oxygen-containing precursor, contacting the substrate with a first etchant precursor, and contacting the substrate with a second etchant precursor can be performed on a single host.

[0076] The processing state also affects the operations performed in method 400 and other etching methods according to the invention. Each operation of method 400 may be performed during a fixed temperature period in some embodiments, while the temperature may be adjusted during different operation periods in some embodiments. For example, in some embodiments, the temperature of the substrate, platform, or chamber may be maintained between about 0 °C and about 500 °C. Temperatures can also be maintained at less than or about 480 °C, less than or about 460 °C, less than or about 440 °C, less than or about 420 °C, less than or about 400 °C, less than or about 380 °C, less than or about 360 °C, less than or about 350 °C, less than or about 340 °C, less than or about 330 °C, less than or about 320 °C, less than or about 310 °C, less than or about 300 °C, less than or about 280 °C, less than or about 260 °C, less than or about 240 °C, less than or about 220 °C, less than or about 200 °C, less than or about 150 °C, less than or about 100 °C, less than or about 75 °C, less than or about 50 °C, less than or about 25 °C, or lower. In embodiments, the temperature may also be maintained at or above 0 °C, or above 25 °C, or above 50 °C, or above 75 °C, or above 100 °C, or above 120 °C, or above 140 °C, or above 150 °C, or above 160 °C, or above 180 °C, or above 200 °C, or above 220 °C, or above 240 °C, or above 260 °C, or above 280 °C, or above 300 °C, or above 320 °C, or above 340 °C, or above 360 ​​°C, or above 380 °C, or above 400 °C, or above 420 °C, or above 440 °C, or above 460 °C, or above 480 °C, or above 500 °C, or higher. Temperature affects the quality of the oxidation process, with higher temperatures allowing for better oxidation of silicon- and germanium-containing materials. Higher temperatures also result in greater reactivity between the etchant precursor and the silicon- and germanium-containing materials. Similarly, lower temperatures can slow down the removal of silicon- and germanium-containing materials due to poor reactivity. However, higher temperatures reduce the effectiveness of passivation precursors. Therefore, in some embodiments, temperatures maintained between about 0 °C and about 150 °C provide better oxidation, increased removal of silicon- and germanium-containing materials, and / or increased effectiveness of passivation precursors.

[0077] The pressure within the chamber also affects the performed operations, and in embodiments, the pressure within the semiconductor processing chamber can be maintained at greater than or about 1 Torr, greater than or about 2 Torr, greater than or about 3 Torr, greater than or about 4 Torr, greater than or about 5 Torr, greater than or about 7.5 Torr, greater than or about 10 Torr, greater than or about 12.5 Torr, greater than or about 15 Torr, greater than or about 17.5 Torr, greater than or about 20 Torr, or greater. Each operation of method 400 can be performed during a fixed pressure period in some embodiments, while in others the pressure can be adjusted during different operation periods. In embodiments, a pressure greater than or about 1 Torr can cause stronger oxidation of one silicon and germanium-containing material relative to another silicon and germanium-containing material. Therefore, lower pressures can cause weaker oxidation, and thus require additional time to achieve sufficient or desired oxidation. However, in order to maintain precise selectivity of oxidation, the pressure in the chamber can also be maintained at less than or about 30 Torr, and can be maintained at less than or about 28 Torr, less than or about 26 Torr, less than or about 24 Torr, less than or about 22 Torr, less than or about 20 Torr, less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, or less.

[0078] Turning to Figures 5A-5D, a cross-sectional view of a structure 500 processed according to an embodiment of the present invention is shown. As illustrated in Figure 5A, structure 500 may include a substrate 505 having a plurality of stacked layers covering a substrate, the substrate 505 being a silicon-containing material, a silicon-and-germanium-containing material, or other substrate material. Alternating material layers may include materials suitable for GAA transistors, such as silicon-containing material 510 alternating with a first silicon-and-germanium-containing material 515. The first silicon-and-germanium-containing material 515 may be or include material to be recessed and / or removed to create nanowires / nanofalves in the GAA transistor. Although only seven layers of material are illustrated, the exemplary structure may include any number of layers. Memory vias or trenches may be defined at the layer level through the stacked structure to the substrate 505. Memory vias or trenches may be defined by sidewalls, which may be formed by alternating layers of silicon-containing material 510 and the first silicon-and-germanium-containing material 515. After the first silicon and germanium-containing material 515 is recessed, an oxygen-containing material 520 and a spacer material 525 may be formed in the recess. As illustrated in Figure 5A, the oxygen-containing material 520 may line the silicon-containing material 510 and the first silicon and germanium-containing material 515 that define the recess. The spacer material 525 may then be deposited in the remaining areas where the first silicon and germanium-containing material 515 was previously present. A second silicon and germanium-containing material 530 may then be formed in memory vias or trenches defined through the stacked structure.

[0079] In an embodiment, the second silicon and germanium-containing material 530, which can be epitaxially grown, can be characterized as having a germanium concentration greater than that of the first silicon and germanium-containing material 515. For example, the first silicon and germanium-containing material 515 can be characterized as having a germanium concentration of less than or about 35 at.%, and can be characterized as having a germanium concentration of less than or about 32.5 at.%, less than or about 30 at.%, less than or about 27.5 at.%, less than or about 25 at.%, less than or about 22.5 at.%, less than or about 20 at.%, less than or about 17.5 at.%, less than or about 15 at.%, or less. Conversely, the second silicon and germanium-containing material 530 can be characterized as having a germanium concentration greater than or about 35 at.%, and can be characterized as having a germanium concentration greater than or about 37.5 at.%, greater than or about 40 at.%, greater than or about 42.5 at.%, greater than or about 45 at.%, greater than or about 47.5 at.%, greater than or about 50 at.%, greater than or about 52.5 at.%, greater than or about 55 at.%, greater than or about 57.5 at.%, greater than or about 60 at.%, or greater. Furthermore, the second silicon and germanium-containing material 530 can be a doped material. In embodiments, the second silicon and germanium-containing material 530 can be doped, for example, with boron.

[0080] Figure 5B may illustrate the structure after some operations, such as those discussed above with respect to Figure 4, have been performed according to the method of the invention. For example, in optional operation 430 of method 400, contacting the substrate with an oxygen-containing precursor may oxidize at least a portion of the second silicon and germanium-containing material layer 535. A portion of the second silicon and germanium-containing material layer 535 may be oxidized silicon and germanium-containing material. A portion of the second silicon and germanium-containing material layer 535 may contact the oxygen-containing material 520 and / or the spacer material 525. As previously discussed with respect to the method of the invention, such as with respect to Figure 4, due to the increased germanium concentration in the second silicon and germanium-containing material layer 530, the second silicon and germanium-containing material layer 530 may be selectively oxidized relative to the first silicon and germanium-containing material layer 515. The spacer material 525 may be porous. Therefore, during subsequent etching to remove the first silicon and germanium-containing material 515, the etchant species can penetrate the spacer material 525 and reach the second silicon and germanium-containing material 530 layer. Since there is no portion of the second silicon and germanium-containing material layer 535 that blocks the etchant species, some of the second silicon and germanium-containing material layer 530 can be etched.

[0081] Figure 5C illustrates the structure after further operations have been performed, such as those described above with respect to Figure 4 according to the invention. An etching operation can be performed to remove the silicon and germanium-containing material 515. This etching removes the first silicon and germanium-containing material 515 to form nanowires / nanofashelves of silicon-containing material 510, which are useful in GAA applications. Due to the presence of selective oxidation and passivation precursors of portions of the second silicon and germanium-containing material layer 535 to block pitting cavities in the material beneath the first silicon and germanium-containing material 515, structure 500 can show minimal or zero etching of the second silicon and germanium-containing material layer 530.

[0082] Figure 5D illustrates the structure after further operations, such as those described above with respect to Figure 4 according to the invention, have been performed. An etching operation may be performed to remove a portion of the silicon-containing material 510. This etching may remove a portion of the silicon-containing material 510 to reduce and / or remove germanium residue from the previously removed first silicon- and germanium-containing material 515 nanowires / nanofibers. A minimal portion of the silicon-containing material 510 may be removed to reduce germanium residue while preserving the silicon-containing material 510 as much as possible.

[0083] In the foregoing description, numerous details have been set forth for the purpose of clarification, providing an understanding of various embodiments of the invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0084] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative architectures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, several well-known processes and elements have not been described to avoid unnecessarily obscuring the invention. Therefore, the foregoing description should not be construed as limiting the scope of the invention. Additionally, methods or processes may be described as sequential or step-by-step, but it will be understood that operations may be performed simultaneously or in a different order than those listed.

[0085] When a numerical range is provided, unless the context explicitly indicates otherwise, each intermediate value, representing the smallest unit of the lower limit between the upper and lower limits of the range, is also explicitly disclosed. Any narrower range between any stated or unstated intermediate value in the stated range and any other stated or intermediate value in the stated range is covered. The upper and lower limits of such smaller ranges may be independently included or excluded in this range, and are subject to any explicitly excluded limit in the stated range. Ranges in which any limit is included, none of the limits are included, or all of the limits are included are also covered in this invention. When a stated range includes one or both of the limits, it also includes ranges that exclude either or both of these included limits.

[0086] When used herein and in the claims of the appended patent, unless the context clearly indicates otherwise, the singular forms “a”, “an” and “the” include the plural references. Thus, for example, “a precursor” includes the plural of precursors, and “the material” includes the equivalents of one or more materials known to the ordinary person, and so on.

[0087] Furthermore, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to indicate the presence of a descriptive feature, integral, component, or operation, but do not exclude the presence or addition of one or more other features, integrals, components, operations, actions, or groups. [Simplified Explanation of the Diagram]

[0013] The nature and advantages of the disclosed technology can be further understood by referring to the rest of the specification and the illustrations.

[0014] Figure 1 shows a top plan view of an embodiment of an exemplary processing system according to an embodiment of the present invention.

[0015] Figure 2A shows an anatomical view of an exemplary treatment chamber according to an embodiment of the present invention.

[0016] Figure 2B shows a detailed view of a portion of the processing chamber illustrated in Figure 2A according to an embodiment of the present invention.

[0017] Figure 3 shows a bottom plan view of an exemplary spray head according to an embodiment of the present invention.

[0018] Figure 4 shows an example operation in a method according to an embodiment of the present invention.

[0019] Figures 5A-5D show cross-sectional views of a substrate processed according to an embodiment of the present invention.

[0020] Several illustrations are included as the subject. It will be understood that the illustrations are for illustrative purposes and are not to be regarded as to scale unless clearly stated otherwise. Furthermore, as the subject, the illustrations are provided to aid understanding and may not include all appearances or information compared to real-world representations, and may include unnecessary or exaggerated material for illustrative purposes.

[0021] In the accompanying drawings, similar parts and / or features may have the same element symbols. Furthermore, various parts of the same type may be distinguished by a letter following the element symbol, which distinguishes similar parts. If only the primary element symbol is used in the specification, this description may apply to any similar parts having the same primary element symbol, regardless of the letter. [Biomaterial Storage]

[0089] Domestic Deposit Information (Please note in order of deposit institution, date, and number) None

[0090] Overseas Deposit Information (Please note in the order of deposit country, institution, date, and number) None

Claims

1. A semiconductor processing method comprising the following steps: providing a first etchant precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, and wherein a first silicon and germanium-containing material layer, a second silicon and germanium-containing material layer, and a silicon-containing material layer are disposed on the substrate; providing a passivation precursor to the processing region; and contacting the substrate with the first etchant precursor and the passivation precursor, wherein the contacting step selectively etches the first silicon and germanium-containing material layer, and wherein the contacting step forms a passivation material on the substrate.

2. The semiconductor processing method as described in claim 1, wherein: The first silicon and germanium-containing material layer is characterized by a first germanium concentration; the second silicon and germanium-containing material layer is characterized by a second germanium concentration; and the first germanium concentration is less than the second germanium concentration.

3. The semiconductor processing method as claimed in claim 1, wherein the passivation precursor comprises a fluorine- and carbon-containing precursor.

4. The semiconductor processing method as described in claim 1, wherein the passivation precursor comprises perfluoropentane (C5F12).

5. The semiconductor processing method as claimed in claim 1, further comprising the steps of: forming a plasma effluent of the first etchant precursor, a plasma effluent of the passivation precursor, or a plasma effluent of the first etchant precursor and the passivation precursor.

6. The semiconductor processing method as claimed in claim 1, wherein the first etchant precursor comprises a fluorine-containing precursor.

7. The semiconductor processing method as claimed in claim 1 further comprises the following steps: providing an inert gas and the first etchant precursor, the passivation precursor, or the first etchant precursor and the passivation precursor.

8. The semiconductor processing method as claimed in claim 1, wherein the passivation precursor is characterized by a boiling point of less than or about 100 °C.

9. The semiconductor processing method as claimed in claim 1, wherein the passivation precursor is characterized by a vapor pressure of less than or about 100 kPa at 25 °C.

10. The semiconductor processing method as claimed in claim 1, wherein a pressure in the processing region is maintained at less than or about 30 Torr.

11. The semiconductor processing method as claimed in claim 1, wherein a temperature in the processing region is maintained at less than or about 150 °C.

12. A semiconductor processing method comprising the steps of: providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, wherein a first silicon-and-germanium material layer, a second silicon-and-germanium material layer, and a silicon-containing material layer are disposed on the substrate, and wherein the first silicon-and-germanium material layer is characterized by a germanium concentration lower than that of the second silicon-and-germanium material layer; contacting the substrate with the oxygen-containing precursor, wherein at least a portion of the second silicon-and-germanium material layer is oxidized; providing a first fluorine-containing precursor to the processing region; providing a fluorine-and-carbon precursor to the processing region; and contacting the substrate with the first fluorine-containing precursor and the fluorine-and-carbon precursor, wherein the first silicon-and-germanium material layer is etched relative to the second silicon-and-germanium material layer while preventing etching of the second silicon-and-germanium material layer.

13. The semiconductor processing method as described in claim 12, wherein the fluorine-containing and carbon precursor comprises perfluoropentane (C5F12).

14. The semiconductor processing method as described in claim 12, wherein the flow rate of the fluorine-containing and carbon precursor is less than the flow rate of the first fluorine-containing precursor.

15. The semiconductor processing method as described in claim 12, wherein the flow rate of the fluorine- and carbon-containing precursor is less than or about 1,000 sccm.

16. The semiconductor processing method as described in claim 12 further comprises the step of: forming a plasma effluent of the first fluorine-containing precursor.

17. The semiconductor processing method as claimed in claim 12, wherein the first silicon and germanium-containing material layer is etched relative to the second silicon and germanium-containing material layer with a selectivity greater than or about 40:

1.

18. A semiconductor processing method comprising the steps of: providing a first fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed within the processing region, wherein a first silicon and germanium-containing material layer, a second silicon and germanium-containing material layer, and a silicon-containing material layer are disposed on the substrate, and wherein the first silicon and germanium-containing material layer is characterized by a germanium concentration lower than that of the second silicon and germanium-containing material layer; providing a fluorine-containing and carbon-containing precursor to the processing region; contacting the substrate with the first fluorine-containing precursor and the fluorine-containing and carbon-containing precursor, wherein the first silicon and germanium-containing material layer is selectively etched while preventing etching of the second silicon and germanium-containing material layer; and providing a second fluorine-containing precursor and a hydrogen-containing precursor to the processing region. The plasma effluents of the second fluorine-containing precursor and the hydrogen-containing precursor are formed; and the substrate is brought into contact with the plasma effluents of the second fluorine-containing precursor and the hydrogen-containing precursor, wherein a portion of the silicon-containing material layer is etched.

19. The semiconductor processing method as claimed in claim 18, wherein the first fluorine-containing precursor has a flow rate ratio of more than or about 1:1 to the fluorine-containing and carbon precursors.

20. The semiconductor processing method as claimed in claim 18, wherein the fluorine-containing and carbon precursor comprises perfluoropentane (C5F12).

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