Time-to-digital conversion device

Abstract

An embodiment of the time-to-digital converter includes a first oscillator configured to output a first clock signal in response to a first event and a second oscillator configured to output a second clock signal in response to a second event. The embodiment further includes a phase detector configured to generate a detection signal based on the phase relationship between the first and second clock signals, and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal, the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal. The count value indicates the time difference between the first and second events.

Description

[Previous Technology]

[0001] Time-to-digital converters, such as time-to-digital converters (TDCs), are configured to convert time information into digital values. In some applications, TDCs, in conjunction with voltage-to-timing converters (VTCs), can be used to sense waveforms on integrated circuit (IC) chips to monitor the power integrity (PI) characteristics of the IC chips. In some applications, TDCs can be used to measure phase noise in phase-locked loops (PLLs). In some applications, TDCs can be used to measure the time-of-flight (ToF) of wireless signals, audio signals, and / or optical signals.

[0002] In some applications involving precise and flexible waveform measurement, time-to-digital converters with resolutions below 100 femtoseconds (fs) and large dynamic ranges can be used. In some applications, the area budget for implementing the time-to-digital converter may limit its resolution and / or dynamic range.

Implementation Method

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of explanation, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, the term "made of" may mean "comprising" or "consisting of." In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not mean one element of A, one element of B, and one element of C.

[0008] Recent advancements in computer technology have led to an increased demand for computing power. For example, artificial intelligence (AI) is now more powerful than ever before, with advanced, large-scale language models containing a vast number of parameters. Training and / or inference operations based on these large language models require significant computing power, increasing the demand for high-performance computing (HPC) devices. Processing circuitry and components in HPC devices, such as central processing units (CPUs), graphics processing units (GPUs), and / or tensor processors (TPUs), face power integrity challenges due to high current consumption. These challenges can be addressed by monitoring the power impedance of the processing circuitry and components.

[0009] In some applications, monitoring power impedance includes monitoring waveforms within the chip or signal delay relative to a reference signal. For example, FIG1A is a block diagram 100A of a first application example for determining clock offset within digital logic 110 in an integrated circuit chip, according to certain embodiments. In FIG1A, two clock signals CLK1 (e.g., a reference signal) and CLK2 (e.g., the monitored signal) output from digital logic 110 are coupled to a time-to-digital converter 120 for comparison. In this example, the time-to-digital converter 120 is configured to generate an output signal TDC_OUT based on the clock signals CLK1 and CLK2, wherein the output signal TDC_OUT represents a value indicating the time difference (e.g., multi-bit digital data) between the clock signals CLK1 and CLK2.

[0010] Furthermore, FIG1B is a block diagram 100B of a second application example for sensing waveform voltage levels in an integrated circuit chip, according to certain embodiments. In FIG1B, the voltage signal VSENSE is detected by a voltage-to-time converter (labeled "VTC") 130. Based on a reference clock signal CLK_REF, the voltage-to-time converter 130 generates a delay signal CLK_DELAY, such that the voltage level of the voltage signal VSENSE is converted into the time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY. In this example, the time-to-digital converter 140 is configured to generate an output signal TDC_OUT based on the reference clock signal CLK_REF and the delay signal CLK_DELAY, wherein the output signal TDC_OUT represents a value indicating the time difference between the reference clock signal CLK_REF and the delay signal CLK_DELAY (e.g., multi-bit digital data).

[0011] In some applications, time-to-digital converters based on Vernier delay line configuration can achieve fine resolution (e.g., less than 100 femtoseconds (fs)), but at the cost of increased delay stages, area, complexity, and thus increased cost.

[0012] This disclosure describes a time-to-digital converter based on the clock cycle difference between two oscillators in one or more embodiments. In some embodiments, the two oscillators are activated in response to two events, and the later-activated clock signal catches up with the earlier-activated clock signal each clock cycle by an increment of the clock cycle difference. In some embodiments, without increasing the number of delay stages, the configuration conforming to one or more embodiments of this application still has fine resolution (e.g., less than 80 femtoseconds) and a measurable range from 0 to 245 picoseconds in the time domain, which in turn improves layout efficiency in integrated circuit wafers, reduces circuit complexity, and lowers manufacturing costs.

[0013] FIG2 is a block diagram of a time-to-digital converter 200 according to some embodiments. The time-to-digital converter 200 in FIG2 is illustrated as a non-limiting example. In some embodiments, some elements of the time-to-digital converter 200 are simplified or omitted in FIG2.

[0014] In FIG. 2, the time-to-digital converter 200 includes a first oscillator 210, a second oscillator 220, a phase detector 230, and a clock counter 240. The first oscillator 210 is configured to receive a first reference signal START1 and a first deceleration control signal SLOW1. The first oscillator 210 is configured to output a first clock signal CKA_M in response to a first event. In some embodiments, the first oscillator 210 is further configured to output a first buffered clock signal CKA_OUT, which is obtained based on the first clock signal CKA_M through a buffer stage of the first oscillator 210. In some embodiments, the first clock signal CKA_M and the first buffered clock signal CKA_OUT have a first clock period T1.

[0015] Furthermore, the second oscillator 220 is configured to receive a second reference signal START2 and a second deceleration control signal SLOW2. The second oscillator 220 is configured to output a second clock signal CKB_M in response to a second event. In some embodiments, the second clock signal CKB_M has a second clock period T2. In some embodiments, the first event occurs before the second event. In some embodiments, the first clock period T1 is greater than the second clock period T2. In some embodiments, the second clock period T2 is at least 100 times the period difference ΔT between the first clock period T1 and the second clock period T2. In some embodiments, the second clock period T2 ranges from 2 nanoseconds (ns) to 6 ns. In some embodiments, the period difference ΔT ranges from 60 femtoseconds (fs) to 100 fs.

[0016] In some embodiments, as a non-limiting example, the first event corresponds to the first reference signal START1 changing or transitioning from a first logic state (e.g., logic low (LOW), or low level in this disclosure) to a second logic state (e.g., logic high (HIGH), or high level in this disclosure). In some embodiments, the second event corresponds to the second reference signal START2 changing or transitioning from a first logic state (e.g., low level) to a second logic state (e.g., high level). In some embodiments, the first oscillator 210 is configured to be deactivated based on the first reference signal START1 being in the first logic state and activated based on the first reference signal START1 being in the second logic state. In some embodiments, the second oscillator 220 is configured to be deactivated based on the second reference signal START2 being in the first logic state and activated based on the second reference signal START2 being in the second logic state.

[0017] In some embodiments, the first clock cycle T1 may be adjusted based on a first deceleration control signal SLOW1, and the second clock cycle T2 may be adjusted based on a second deceleration control signal SLOW2. In some embodiments, the first oscillator 210 and the second oscillator 220 are based on the same hardware configuration. In some embodiments, the first oscillator 210 is a first ring oscillator, including one or more first load capacitors, first load resistors, or first phase interpolators, located between two consecutive inverting stages of the first oscillator 210, and configured to set a first configurable delay of the first oscillator 210. In some embodiments, the second oscillator 220 is a second ring oscillator, including one or more second load capacitors, second load resistors, or second phase interpolators, located between two consecutive inverting stages of the second oscillator 220, and configured to set a second configurable delay of the second oscillator 220. In some embodiments, the first clock cycle T1 may be determined based on the first configurable delay of the first oscillator 210, and the second clock cycle T2 may be determined based on the second configurable delay of the second oscillator 220.

[0018] During operation of the time-to-digital converter 200, the first clock cycle T1 and the second clock cycle T2 are set based on the first deceleration control signal SLOW1 and the second deceleration control signal SLOW2. For example, during operation, the first deceleration control signal SLOW1 is set to a second logic state (e.g., high level), indicating that the first clock cycle T1 corresponds to a slower clock setting of the first oscillator 210 (e.g., setting the first configurable delay to a larger value), while the second deceleration control signal SLOW2 is set to a first logic state (e.g., low level), indicating that the second clock cycle T2 corresponds to a faster clock setting of the second oscillator 220 (e.g., setting the second configurable delay to a smaller value).

[0019] In some alternative embodiments, the first oscillator 210 and the second oscillator 220 are based on different hardware configurations and respectively output clock signals having a first clock period T1 and a second clock period T2. In some embodiments, based on the hardware configuration of the first oscillator 210 and the second oscillator 220, no adjustable delay is available, therefore the first deceleration control signal SLOW1 and / or the second deceleration control signal SLOW2 are omitted.

[0020] The phase detector 230 is configured to generate a detection signal HITB based on the phase relationship between the first clock signal CKA_M and the second clock signal CKB_M. In some embodiments, as a non-limiting example, the detection signal HITB has a first logic state (e.g., low level) indicating that the phase of the first clock signal CKA_M lags behind the phase of the second clock signal CKB_M, and a second logic state (e.g., high level) indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M.

[0021] Clock counter 240 is configured to generate a count value TDC_OUT based on the first clock signal CKA_M when a detection signal HITB indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M. In some embodiments, the count value TDC_OUT indicates the time difference between the first event and the second event. In some embodiments, clock counter 240 is configured to receive and count the clock cycle of the first clock signal CKA_M. In some embodiments, clock counter 240 is configured to receive and count the clock cycle of the first buffered clock signal CKA_OUT. In some other embodiments, clock counter 240 is configured to generate a count value TDC_OUT based on the second clock signal CKB_M instead of the first clock signal CKA_M or the first buffered clock signal CKA_OUT when a detection signal HITB indicates that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M.

[0022] In FIG. 2, clock counter 240 includes clock gating circuit 250 and counter 260. In some embodiments, clock gating circuit 250 is configured to generate a counting clock signal CKC based on a first clock signal CKA_M (or a first buffered clock signal CKA_OUT derived from the first clock signal CKA_M) and a detection signal HITB. In some embodiments, clock gating circuit 250 is configured to generate a counting clock signal CKC having the same frequency and period as the first clock signal CKA_M when the detection signal HITB is in a second logic state (e.g., high level) indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M. In some embodiments, clock gating circuit 250 is configured to set the counting clock signal CKC to a logic state (e.g., the first logic state or low level) when the detection signal HITB is in a first logic state (e.g., low level). In this example, the clock gate circuit 250 includes a clock terminal (depicted by a triangle) configured to receive a first clock signal CKA_M or a first buffered clock signal CKA_OUT, an enable terminal (marked as "EN") configured to receive a detection signal HITB, and an output terminal configured to output a counting clock signal CKC.

[0023] In some embodiments, counter 260 is an N-bit counter, and TDC_OUT is a count value of an N-bit unsigned integer. In some embodiments, N ranges from 6 to 12, or from 8 to 10. In this example, counter 260 includes a clock terminal (depicted by a triangle) configured to receive a counting clock signal CKC, and an output terminal configured to output the count value TDC_OUT.

[0024] In some embodiments, the integrated circuit chip includes one or more digital circuit blocks configured to output various reference signals (e.g., a first reference signal START1 and a second reference signal START2). In some embodiments, the integrated circuit chip further includes a time-to-digital converter 200 configured to output a count value (e.g., a count value TDC_OUT) indicating the time difference between a first event based on a first reference signal and a second event based on a second reference signal.

[0025] FIG3 is a flowchart of process 300 performed by the time-to-digital converter, according to certain embodiments. In some embodiments, process 300 is illustrated based on various operations performed by the time-to-digital converter 200 in FIG2, as a non-limiting example. In FIG3, process 300 includes stages 310 to 355.

[0026] In stage 310, various components of the time-to-digital converter are reset. For example, the phase detector 230, the clock gating circuit 250, and the counter 260 are reset to clear any data or logic state from the previous time-to-digital conversion session. In stage 310, the detection signal HITB is set to disable the clock gating circuit 250, and the counting clock signal CKC is set to prevent the counter 260 from performing any action.

[0027] In stage 315, a first reference signal (e.g., first reference signal START1) changes from a first logic state (e.g., low level) to a second logic state (e.g., high level), and the logic state transition indicates the occurrence of a first event. In stage 320, a first oscillator (e.g., first oscillator 210) outputs a first clock signal (e.g., first clock signal CKA_M) as an oscillation signal in response to the first event. In some embodiments, the first clock signal CKA_M has a first clock period T1.

[0028] At stage 325, based on the presence of the first clock signal CKA_M (as an oscillation signal) and the absence of the second clock signal CKB_M (as an oscillation signal), the phase detector 230 begins to output a detection signal HITB in a first logic state (e.g., low level), indicating that the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, which in turn activates the clock gate circuit 250 and then activates the counter 260.

[0029] At stage 330, a second reference signal (e.g., second reference signal START2) changes from a first logic state (e.g., low level) to a second logic state (e.g., high level), and the logic state transition indicates the occurrence of a second event. In some embodiments, the transition of the logic state of the second reference signal START2 from low to high level is delayed by a time difference Tsense compared to the transition of the logic state of the first reference signal START1 from low to high level. At stage 335, a second oscillator (e.g., second oscillator 220) outputs a second clock signal (e.g., second clock signal CKB_M) as an oscillation signal in response to the second event. In some embodiments, the second clock signal CKB_M has a second clock period T2 equal to (T1 - ΔT). At stage 335, the phase of the second clock signal CKB_M lags behind the phase of the first clock signal CKA_M, therefore the clock gate circuit 250 and the counter 260 remain in the enabled state.

[0030] In stage 340, after Tsense / ΔT cycles, the phase of the second clock signal CKB_M catches up with and leads the phase of the first clock signal CKA_M. In stage 345, in response to the updated phase relationship between the first clock signal CKA_M and the second clock signal CKB_M, the phase detector 230 outputs a detection signal HITB in a second logic state (e.g., high level), indicating that the phase of the first clock signal CKA_M lags behind the phase of the second clock signal CKB_M.

[0031] At stage 350, the detection signal HITB in the second logic state (e.g., high level) further disables the clock gating circuit 250. At stage 350, the clock gating circuit 250 sets the counting clock signal CKC to a fixed logic state so that the counter 260 does not operate. At stage 355, the counter 260 stops. The counter output (e.g., the count value TDC_OUT) is read as the conversion result. In some embodiments, the count value TDC_OUT represents the ratio between the time difference Tsense and the period difference ΔT. In some embodiments, the time difference Tsense is determined based on TDC_OUT × ΔT. In some embodiments, ΔT also represents the time domain resolution of the time-to-digital converter, and the range of count values ​​of the counter 260 corresponds to the measurable range of the time-to-digital converter.

[0032] FIG4A is a circuit diagram of an oscillator 400 according to some embodiments, which is a ring oscillator. In some embodiments, the hardware configuration of the oscillator 400 is a non-limiting example that can be used to implement the first oscillator 210 and / or the second oscillator 220 in FIG2.

[0033] The oscillator 400 includes a first NAND gate 412 as an input stage, a first set of inverters 414, a second set of inverters 415, a third set of inverters 416, a second NAND gate 417, and an inverter 418. The oscillator 400 also includes a buffer circuit 420 after the third set of inverters 416, and a delay circuit 430 between the second set of inverters 415 and the third set of inverters 416. In some embodiments, the buffer circuit 420 includes one or more inverters. In this example, the delay circuit 430 includes a driver stage 432 (containing one or more inverters, such as one inverter in this example) and a third NAND gate 434. In Figure 4A, the first inverter 412, the first set of inverters 414, the second set of inverters 415, the driver stage 432 of the delay circuit 430, the third set of inverters 416, the second inverter 417, and the inverter 418 are sequentially electrically coupled to form a loop with K inverting stages, where K is an odd positive integer. In some embodiments, the signal at the output of the first set of inverters 414 is output by the oscillator 400 as a clock signal CK_M.

[0034] In some embodiments, the first inverter 412 includes a first input configured to receive a feedback clock signal CK_F from the inverter 418, and a second input configured to receive a reference signal START. In some embodiments, in response to the reference signal START being in a first logic state (e.g., low level), the first inverter 412 outputs a second logic state (e.g., high level), thereby effectively disabling the oscillator 400. In some embodiments, in response to the reference signal START being in a second logic state (e.g., high level), the first inverter 412 outputs an inverted version of the feedback clock signal CK_F at its output.

[0035] In some embodiments, the second inverter 417 includes a first input terminal electrically coupled to the output of the third set of inverters 416, and a second input signal configured to receive an enable signal EN. In some embodiments, in response to the enable signal EN being in a first logic state (e.g., low level), the second inverter 417 outputs a second logic state (e.g., high level), thereby effectively disabling the oscillator 400. In some embodiments, in response to the enable signal EN being in a second logic state (e.g., high level), the second inverter 417 outputs an inverted version of the signal from the output of the third set of inverters 416 at its output terminal. In some embodiments, the second inverter 417 is replaced by an inverter, and the enable signal EN is omitted.

[0036] In some embodiments, the buffer circuit 420 is configured to output a buffered clock signal CK_OUT, which has the same frequency and period as the clock signal CK_M. In some embodiments, the buffer circuit 420 provides a greater drive capability for the buffered clock signal CK_OUT than the clock signal CK_M, while minimizing interference to the K inverting stage loops of the oscillator 400.

[0037] In some embodiments, the delay circuit 430 is configured to introduce an adjustable delay to the K inverting stage loops of the oscillator 400. In this example, the third inverting gate 434 is illustrated as a non-limiting example. In some embodiments, a NOR gate is used instead of the third inverting gate 434.

[0038] In this example, the third anti-gate 434 includes a first input (labeled "LOAD") coupled to the output of the driver stage 432, a second input configured to receive the deceleration control signal SLOW, and an output not electrically coupled to other circuitry. In some embodiments, the first input presents a first equivalent load capacitance in response to the deceleration control signal SLOW being in a first logic state (e.g., low level). In some embodiments, the first input presents a second equivalent load capacitance greater than the first equivalent load capacitance in response to the deceleration control signal SLOW being in a second logic state (e.g., high level).

[0039] In an example of the first oscillator 210 based on the oscillator 400, the reference signal START and its corresponding terminal in FIG4A correspond to the first reference signal START1 and its corresponding terminal in FIG2; the clock signal CK_M and its corresponding terminal in FIG4A correspond to the first clock signal CKA_M and its corresponding terminal in FIG2; the buffer clock signal CK_OUT and its corresponding terminal in FIG4A correspond to the first buffer clock signal CKA_OUT and its corresponding terminal in FIG2; and the deceleration control signal SLOW and its corresponding terminal in FIG4A correspond to the first deceleration control signal SLOW1 and its corresponding terminal in FIG2.

[0040] FIG4B is a circuit diagram of the inverted gate 434 of the delay circuit 430 in FIG4A according to some embodiments, as a non-limiting example. In FIG4B, the inverted gate 434 includes a first input terminal 442, which is also labeled "LOAD" in FIG4A. The inverted gate 434 includes a second input terminal 444 configured to receive a deceleration control signal SLOW, and an output terminal 446 not electrically coupled to other circuitry outside the inverted gate 434.

[0041] The reverse gate 434 includes a first P-type transistor 452, a second P-type transistor 454, a first N-type transistor 456, and a second N-type transistor 458. The first drain / source terminals of the first P-type transistor 452 and the second P-type transistor 454 are electrically coupled to a first power node configured to carry a first power supply voltage (e.g., VDD). The second drain / source terminals of the first P-type transistor 452, the second drain / source terminals of the second P-type transistor 454, and the first drain / source terminal of the first N-type transistor 456 are electrically coupled to the output terminal 446 of the reverse gate 434. The second drain / source terminal of the first N-type transistor 456 is electrically coupled to the first drain / source terminal of the second N-type transistor 458. The second drain / source terminal of the second N-type transistor 458 is electrically coupled to a second power node configured to carry a second power supply voltage (e.g., VSS or ground). The gate terminals of the first P-type transistor 452 and the first N-type transistor 456 are electrically coupled to the first input terminal 442 of the inverter 434. The gate terminals of the second P-type transistor 454 and the second N-type transistor 458 are electrically coupled to the second input terminal 444 of the inverter 434.

[0042] In this example, in response to the deceleration control signal SLOW being in the first logic state (e.g., low level), the second P-type transistor 454 is turned on while the second N-type transistor 458 is turned off. The load capacitance observable at the first input terminal 442 is primarily based on the parasitic capacitance (represented by a capacitor with capacitance Cp) between the first input terminal 442 and the output terminal 446. Furthermore, in response to the deceleration control signal SLOW being in the second logic state (e.g., high level), the second P-type transistor 454 is turned off while the second N-type transistor 458 is turned on. The load capacitance observable at the first input terminal 442 is based on the parasitic capacitance (e.g., capacitance Cp) amplified by the Miller effect, which is effective as (1+M) × Cp, where M is the gain from the output terminal 446 to the first input terminal 442.

[0043] In this example, the load difference between the deceleration control signal SLOW in the first logic state and the second logic state is M × Cp. In some embodiments, an oscillator based on an oscillator 400 with a load capacitance Cp and another oscillator based on an oscillator 400 with a load capacitance (1+M) × Cp will have different clock periods, and the difference in clock periods can be determined based on the load difference M × Cp.

[0044] Figure 5 is a circuit diagram of phase detector 500 according to certain embodiments. In some embodiments, phase detector 500 is a non-limiting example of phase detector 230 in Figure 2.

[0045] In FIG. 5, the phase detector 500 includes a D-type inverter 510, a first buffer stage including series-coupled inverters 522 and 524, a second buffer stage including series-coupled inverters 532 and 534, and an output stage including inverter 542. In some embodiments, inverters 522 and 524 are configured to buffer a first clock signal (e.g., first clock signal CKA_M) from a first oscillator (e.g., first oscillator 210), while inverters 532 and 534 are configured to buffer a second clock signal (e.g., second clock signal CKB_M) from a second oscillator (e.g., second oscillator 220).

[0046] In this example, the D-type flip-flop 510 includes a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the D-type flip-flop 510 is configured to receive a first signal from a first buffer stage and corresponding to a first clock signal CKA_M. In some embodiments, the CLK terminal of the D-type flip-flop 510 is configured to receive a second signal based on the inversion of a signal from a second buffer stage and corresponding to the inversion of a second clock signal CKB_M. In some embodiments, the Q terminal of the D-type flip-flop 510 is configured to output a third signal corresponding to a detection signal HITB. In this example, the inverter 542 receives the third signal from the Q terminal of the D-type flip-flop 510 and outputs the detection signal HITB. In some embodiments, the CD terminal of the D-type flip-flop 510 is configured to receive a reset signal RST. When the reset signal RST is in a first logic state (e.g., low level), it has no effect on the operation of the D-type flip-flop 510. However, when the reset signal RST is in a second logic state (e.g., high level), it causes the D-type flip-flop 510 to reset the output of the Q terminal of the D-type flip-flop 510.

[0047] FIG6A is a circuit diagram of a clock gate circuit example 600 according to certain embodiments. In some embodiments, the clock gate circuit 600 is a non-limiting example of the clock gate circuit 250 in FIG2.

[0048] In FIG. 6A, the clock gate circuit 600 includes a first D-type flip-flop 610, a second D-type flip-flop 620, a first buffer stage including inverters 632 and 634 coupled in series, a second buffer stage including inverter 642, and an output stage including inverter 644. In this example, the first D-type flip-flop 610 and the second D-type flip-flop 620 each include a D terminal, a CLK terminal, a Q terminal, and a CD terminal. In some embodiments, the D terminal of the first D-type flip-flop 610 is configured to receive a supply voltage (e.g., VDD) representing a second logic state (e.g., high level). In some embodiments, the CLK terminal of the first D-type flip-flop 610 is configured to receive a signal inverted based on a detection signal HITB. In some embodiments, the CD terminal of the first D-type flip-flop 610 is configured to receive a reset signal RST. When the reset signal RST is in a first logic state (e.g., low level), it has no effect on the operation of the first D-type flip-flop 610. However, when the reset signal RST is in a second logic state (e.g., high level), it causes the first D-type flip-flop 610 to reset the output of its Q terminal. In some embodiments, inverters 632 and 634 are configured to buffer the output signal from the Q terminal of the first D-type flip-flop 610 and provide a buffered output signal (labeled "STOP") to the second D-type flip-flop 620.

[0049] In some embodiments, the D terminal of the second D-type flip-flop 620 is configured to receive a buffered output signal STOP from the inverter 634. In some embodiments, the CLK terminal of the second D-type flip-flop 620 is configured to receive a first buffered clock signal CKA_OUT from a first oscillator (e.g., first oscillator 210). In some embodiments, the CD terminal of the second D-type flip-flop 620 is configured to receive a reset signal RST, which has no effect on the operation of the second D-type flip-flop 620 when the reset signal RST is in a first logic state (e.g., low level), but causes the second D-type flip-flop 620 to reset the output of the Q terminal of the second D-type flip-flop 620 when the reset signal RST is in a second logic state (e.g., high level). In some embodiments, the Q terminal of the second D-type flip-flop 620 is configured to output a signal STOP_R based on the signal STOP and the first buffered clock signal CKA_OUT.

[0050] In this example, inverter 642 receives the signal STOP_R and outputs an inverted signal STOP_B. In some embodiments, inverter 644 includes a first input configured to receive a first buffer clock signal CKA_OUT and a second input configured to receive the signal STOP_B. In some embodiments, in response to signal STOP_B being in a first logic state (e.g., low level), inverter 644 outputs a second logic state (e.g., high level) at its output as a counter clock signal CKC (e.g., a non-oscillating signal). In some embodiments, in response to signal STOP_B being in a second logic state (e.g., high level), inverter 644 outputs the inverted version of the first buffer clock signal CKA_OUT at its output as a counter clock signal CKC (e.g., an oscillating signal).

[0051] In some other embodiments, the first clock signal CKA_M, the second clock signal CKB_M, or the second buffered clock signal based on the second clock signal CKB_M can be used to replace the first buffered clock signal CKA_OUT.

[0052] FIG6B is a circuit diagram based on a variation 650A of the clock gate circuit 600 in FIG6A, according to certain embodiments. In some embodiments, the combination of the second type D flip-flop 620, the inverter 642 and the inverting gate 644 can be replaced by variation 650A.

[0053] In FIG. 6B, variation 650A includes a D-type flip-flop 620A and a gate 646. In this example, the D-type flip-flop 620A includes a D terminal, a CLK terminal, and a Q terminal. In some embodiments, the D terminal of the D-type flip-flop 620A is configured to receive a signal STOP. In some embodiments, the clock terminal of the D-type flip-flop 620A is configured to receive a first buffered clock signal CKA_OUT from a first oscillator (e.g., first oscillator 210). In some embodiments, the Q terminal of the D-type flip-flop 620A is configured to output a signal STOP_R based on the signal STOP and the first buffered clock signal CKA_OUT.

[0054] In Figure 6B, the first input terminal of the gate 646 is configured to receive the signal STOP_R, and the second input terminal of the gate 646 is configured to receive the first buffer clock signal CKA_OUT. In this example, the output terminal of the gate 646 is configured to output the counter clock signal CKC.

[0055] FIG6C is a circuit diagram based on a variation 650B of the clock gate circuit 600 in FIG6A, according to certain embodiments. In some embodiments, the combination of the second type D flip-flop 620, the inverter 642 and the inverting gate 644 can be replaced by variation 650A.

[0056] In FIG. 6C, Variation 650B includes a D-type latch 620B and a gate 646. In this example, the D-type latch 620B includes a D terminal, an EN terminal, and a Q terminal. In some embodiments, the D terminal of the D-type latch 620B is configured to receive a signal STOP. In some embodiments, the EN terminal of the D-type latch 620B is configured to receive a first buffered clock signal CKA_OUT from a first oscillator (e.g., first oscillator 210). In some embodiments, the Q terminal of the D-type latch 620B is configured to output a signal STOP_R based on the signal STOP and the first buffered clock signal CKA_OUT.

[0057] In Figure 6C, the first input terminal of gate 646 is configured to receive the signal STOP_R, and the second input terminal of gate 646 is configured to receive the first buffer clock signal CKA_OUT. In this example, the output terminal of gate 646 is configured to output the counter clock signal CKC.

[0058] FIG7 is a block diagram of counter example 700 according to certain embodiments. In some embodiments, counter 700 is a non-limiting example of counter example 260 in FIG2.

[0059] In Figure 7, the counter 700 includes an N-bit adder 710 and an N-bit clock buffer 720. In some embodiments, the N-bit adder 710 corresponds to an N-bit carry-ripple adder and includes a first N-bit input terminal Ain, a second N-bit input terminal Bin, a carry-in terminal Cin, and an N-bit output terminal S. In some embodiments, the N-bit clock buffer 720 corresponds to a set of N D-type flip-flops and includes an N-bit input terminal D, an N-bit output terminal Q, a clock terminal (depicted by a triangle), and a CD terminal. In some embodiments, the CD terminal of the N-bit clock buffer 720 is configured to reset the binary value of the N-bit output terminal Q based on a reset signal RST. In some embodiments, the N-bit clock buffer 720 is configured to update the binary value of the N-bit output terminal Q with the binary value of the N-bit input terminal D in response to a counter clock signal CKC at the clock terminal.

[0060] In this example, the N-bit output Q of the N-bit clock buffer 720 is configured to carry a count value TDC_OUT, and the first N-bit input Ain of the N-bit adder 710 is configured to receive the count value TDC_OUT from the N-bit output Q of the N-bit clock buffer 720. In this example, the second N-bit input Bin is configured to receive the binary value 0001b, and the carry input Cin is coupled to a supply voltage (e.g., VSS or ground) representing the binary value 0b. In some embodiments, the N-bit output S is configured to output a binary value based on the sum of the binary values ​​of the first N-bit input Ain, the second N-bit input Bin, and the carry input Cin. The N-bit input D of the N-bit clock buffer 720 receives the binary value from the N-bit output S of the N-bit adder 710.

[0061] In operation, in response to the counter clock signal CKC transitioning from a first logic state (e.g., low level) to a second logic state (e.g., high level), the N-bit clock buffer 720 updates the count value TDC_OUT of the N-bit output terminal Q based on the output value of the N-bit adder 710. In response to the updated count value TDC_OUT, the N-bit adder 710 updates the bit value of the N-bit output terminal S by adding the updated count value TDC_OUT (the value of the first N-bit input terminal Ain) to 1 (the value of the second N-bit input terminal Bin). The updated bit value of the N-bit output terminal S will be used to update the count value TDC_OUT of the N-bit output terminal Q the next time the counter clock signal CKC transitions from the first logic state (e.g., low level) to the second logic state (e.g., high level).

[0062] Figures 8A to 8D are signal waveforms and / or digital value diagrams of time-to-digital conversion sessions based on the examples of time-to-digital conversion devices in Figures 2 to 6A and Figure 7, according to certain embodiments.

[0063] Figure 8A includes diagrams 801 to 808. In diagrams 801 to 807, the horizontal axis represents time, and the vertical axis represents the voltage level of various signals. In diagram 808, the horizontal axis represents time, and the vertical axis represents the digital value.

[0064] Figure 801 includes waveform 812, corresponding to the waveform of the reset signal RST in Figures 5, 6A, and 7. Figure 802 includes waveform 822, corresponding to the waveform of the first reference signal START1 in Figure 2, and waveform 824, corresponding to the waveform of the second reference signal START2 in Figure 2. Figure 803 includes waveform 832, corresponding to the waveform of the first clock signal CKA_M in Figures 2 and 5. Figure 804 includes waveform 834, corresponding to the waveform of the second clock signal CKB_M in Figures 2 and 5. Figure 805 includes waveform 836, corresponding to the waveform of the counting clock signal CKC in Figures 2, 6A, and 7. Figure 806 includes waveform 842, corresponding to the waveform of the detection signal HITB in Figures 2, 5, and 6A. Figure 807 includes waveform 844, corresponding to the waveform of the buffered output signal STOP in Figure 6A. Diagram 808 includes waveform 850, which corresponds to the waveform of the count value TDC_OUT in Figures 2 and 7.

[0065] In Figure 8A, the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834), and the counting clock signal CKC (waveform 836) oscillate between a high voltage level (e.g., corresponding to a high-level logic state) and a low voltage level (e.g., corresponding to a low-level logic state) in response to the transition from a low voltage level to a high voltage level by the first reference signal START1 (waveform 822) and the second reference signal START2 (waveform 824). In Figure 8A, the count value TDC_OUT (waveform 850) increases when the phase of the second reference signal START2 lags behind the phase of the first reference signal START1. In Figure 8A, after the detection signal HITB (waveform 842) and the buffered output signal STOP (waveform 844) indicate that the phase of the first reference signal START1 lags behind the phase of the second reference signal START2, the count value TDC_OUT (waveform 850) stops increasing, and the first clock signal CKA_M (waveform 832), the second clock signal CKB_M (waveform 834), and the counting clock signal CKC (waveform 836) remain in a fixed logic state (e.g., represented by a low voltage level).

[0066] The parts within Part A in Figures 801 to 808 are further explained in Figure 8B, and the parts within Part B in Figures 801 to 808 are further explained in Figure 8C.

[0067] Figure 8B is an enlarged view of Part A in Figure 8A. Figure 8B includes figures 801A to 808A, corresponding to the portions of figures 801 to 808 within Part A. In Figure 8B, the same waveforms as in Figure 8A are given the same reference numerals.

[0068] In Figure 8B, before time t0, the reset signal RST (waveform 812) is at a high voltage level (e.g., high level) to reset various elements of the time-to-digital converter (e.g., time-to-digital converter 200), which corresponds to stage 310 in Figure 3. At time t0, the reset signal RST (waveform 812) transitions from a high voltage level (e.g., high level) to a low voltage level (e.g., low level) to allow the time-to-digital converter to operate in response to various other signals.

[0069] At time t1, the first reference signal START1 (waveform 822) transitions from a low voltage level (e.g., low level) to a high voltage level (e.g., high level), corresponding to stage 315 in FIG3. In response to this transition and corresponding to stage 320 in FIG3, the first oscillator (e.g., first oscillator 210) begins to output a first clock signal CKA_M (waveform 832) after an inherent delay, as an oscillation signal transitioning between the low voltage level and the high voltage level. Furthermore, a clock counter (e.g., clock counter 240) is started by the first clock signal CKA_M, as shown by counting the clock signal CKC (waveform 836), and corresponding to stage 325 in FIG3.

[0070] At time t2, the second reference signal START2 (waveform 824) transitions from a low voltage level (e.g., low level) to a high voltage level (e.g., high level), corresponding to stage 330 in Figure 3. The transition of the second reference signal START2 is delayed by a time difference Tsense compared to the transition of the first reference signal START1 (e.g., t2 - t1 = Tsense). In response to the transition of the second reference signal START2 and corresponding to stage 335 in Figure 3, the second oscillator (e.g., second oscillator 220) begins to output a second clock signal CKB_M (waveform 834) after an inherent delay, as an oscillating signal for the transition between the low and high voltage levels.

[0071] In some embodiments, the first clock signal CKA_M has a first clock period T1, and the second clock signal CKB_M has a second clock period T2, where T2 is a period difference ΔT smaller than the first clock period T1. In Figure 8B, the phase of the second clock signal CKB_M begins to lag behind the phase of the first clock signal CKA_M. In Figure 8B, the phase difference between the second clock signal CKB_M and the first clock signal CKA_M decreases by the period difference ΔT for each clock period of either the first clock signal CKA_M or the second clock signal CKB_M. In this example, the counting clock signal CKC (waveform 836) and the first clock signal CKA_M have the same frequency. Therefore, the clock counter calculates the clock period of the counting clock signal CKC, representing the number of clock periods that the first clock signal CKA_M has elapsed.

[0072] FIG8C is an enlarged view of Part B in FIG8A. FIG8C includes figures 801B to 808B corresponding to figures 801 to 808 in Part B. In FIG8C, the same waveforms as in FIG8A are given the same reference numerals.

[0073] In Figure 8C, at time t3, Tsense / ΔT cycles after the first oscillator starts, the phase of the second clock signal CKB_M (waveform 834) catches up with and begins to lead the phase of the first clock signal CKA_M (waveform 832), which corresponds to stage 340 in Figure 3. At time t4, the phase detector (e.g., phase detector 230) detects the change in the phase relationship between the first clock signal CKA_M and the second clock signal CKB_M and outputs a detection signal HITB (waveform 842) that transitions from a high voltage level (e.g., high level) to a low voltage level (e.g., low level), which corresponds to stage 345 in Figure 3.

[0074] In response to the detection signal HITB (waveform 842) transitioning from a high voltage level to a low voltage level, corresponding to stage 350 in Figure 3, the buffered output signal STOP (waveform 844) transitions from a low voltage level to a high voltage level. This, in turn, disables the clock gating circuit (e.g., clock gating circuit 250) of the output counting clock signal CKC (waveform 836). Afterwards, the digital value of the count value TDC_OUT (waveform 850) is read as the conversion result, corresponding to stage 355 in Figure 3.

[0075] Figure 8D is a graph showing the relationship between the digital value of the count value TDC_OUT (waveform 850) and the time difference (e.g., Tsense) between the first reference signal START1 and the second reference signal START2, based on the example in Figure 8A, according to some embodiments. In Figure 8D, the time difference Tsense is represented by the horizontal axis, and the digital value is represented by the vertical axis.

[0076] In this non-limiting example, the time difference Tsesne and the digit value have a linear, proportional relationship, as shown by curve 860. In this example, data point 862 indicates that the count value TDC_OUT has a digit value of 476 when the response time difference Tsesne is 45.2531 picoseconds (ps). In this example, data point 864 indicates that the count value TDC_OUT has a digit value of 2876 when the response time difference Tsesne is 235.4562 ps. Therefore, in this non-limiting example, the resolution of the measurement time difference Tsesne is 79.4 femtoseconds (per digit value).

[0077] FIG. 9A is a circuit diagram of an example 900 of a delay circuit based on a phase interpolator according to some embodiments. In some embodiments, the delay circuit 900 may be used as an alternative embodiment of the delay circuit 430 in FIG. 4A. In FIG. 9A, the delay circuit 900 includes inverters 912 and 914, capacitors 922 and 924, and a phase interpolator 932. The inputs of inverters 912 and 914 are adapted to be electrically coupled to a second set of inverters 415 in FIG. 4A; while the output of the phase interpolator 932 is adapted to be electrically coupled to a third set of inverters 416 in FIG. 4A.

[0078] In Figure 9A, one end of capacitor 922 is coupled to a power node configured to carry a supply voltage (e.g., VSS or ground), and the other end is electrically coupled to the output of inverter 912 and the input of phase interpolator 932. Similarly, one end of capacitor 924 is coupled to a power node configured to carry a supply voltage (e.g., VSS or ground), and the other end is electrically coupled to the output of inverter 912 and the other input of phase interpolator 932. In some embodiments, capacitor 922 has capacitance C1. In some embodiments, capacitor 924 has capacitance C2 when the deceleration control signal SLOW is in a first logic state (e.g., low level), and capacitance C2 + ΔC when the deceleration control signal SLOW is in a second logic state (e.g., high level). In some embodiments, capacitances C1 and C2 are set to be the same or within a 10% variation range. In some embodiments, capacitor 922 is omitted, and capacitance C1 is considered to be zero.

[0079] In FIG. 9A, the signal coupled to the input of the phase interpolator 932 at the output of inverter 912 is labeled PI_IN0; while the signal coupled to the other input of the phase interpolator 932 at the output of inverter 914 is labeled PI_IN1. Furthermore, the signal at the output of the phase interpolator 932 is labeled PI_OUT. In some embodiments, the phase interpolator 932 is configured to determine a first time delay of the signal transition of signal PI_IN1 relative to the signal transition of signal PI_IN0, and output a signal PI_OUT having a signal transition and a second time delay relative to the signal transition of signal PI_IN0. In some embodiments, the second time delay is a fraction of the first time delay.

[0080] FIG9B is a diagram illustrating various signals of the delay circuit 900 in FIG9A according to some embodiments. In FIG9B, time is represented by the horizontal axis. In FIG9B, the signal transition of signal PI_IN1 has a first delay TD1 relative to the signal transition of signal PI_IN0. In FIG9B, the signal transition of signal PI_OUT has a second delay TD2 relative to the signal transition of signal PI_IN0.

[0081] Therefore, the delay circuit 900 can be configured to further reduce the period difference ΔT between the two oscillators without further reducing the difference in the corresponding load capacitance values ​​of the two oscillators. In some embodiments, the period difference ΔT based on the second delay TD2 is in the range of tens of femtoseconds to obtain a result time-to-digital conversion device with finer resolution than that based on the first delay TD1.

[0082] FIG. 10A is a circuit diagram of an example 1000 of a delay circuit based on an adjustable load resistor, according to some embodiments. In some embodiments, the delay circuit 1000 may be used as another alternative embodiment of the delay circuit 430 in FIG. 4A. In FIG. 10A, the delay circuit 1000 includes an inverter 1012, a capacitor 1014, and an adjustable resistor 1016. The input of the inverter 1012 is adapted to be electrically coupled to a second set of inverters 415 in FIG. 4A; while the output node 1018 of the delay circuit 1000 is adapted to be electrically coupled to a third set of inverters 416 in FIG. 4A.

[0083] In Figure 10A, one end of capacitor 1014 is coupled to a power node configured to carry a supply voltage (e.g., VSS or ground), and the other end is electrically coupled to output node 1018. Additionally, one end of adjustable resistor 1016 is electrically coupled to the output of inverter 1012, and the other end is electrically coupled to output node 1018. In some embodiments, the time delay between the input of inverter 1012 and output node 1018 can be determined based on the resistance value of adjustable resistor 1016, wherein a larger resistance value of adjustable resistor 1016 results in a larger delay applied between the second set of inverters 415 and the third set of inverters 416.

[0084] FIG10B is a circuit diagram of an example 1016A of a first adjustable resistor 1016, which can be used as the adjustable resistor 1016 in FIG10A according to some embodiments. The first adjustable resistor 1016A includes a first terminal 1022 and a second terminal 1024, corresponding to the two terminals of the adjustable resistor 1016 in FIG10A. The first adjustable resistor 1016A includes a P-type transistor 1026, an N-type transistor 1028, and a bias generator 1030. The first drain / source terminals of the P-type transistor 1026 and the first drain / source terminals of the N-type transistor 1028 are electrically coupled to the first terminal 1022; while the second drain / source terminals of the P-type transistor 1026 and the second drain / source terminals of the N-type transistor 1028 are electrically coupled to the second terminal 1024.

[0085] In some embodiments, the bias generator 1030 is configured to generate a first bias voltage Vbiasp supplied to the gate terminal of the P-type transistor 1026 and a second bias voltage Vbiasn supplied to the gate terminal of the N-type transistor 1028. In some embodiments, the bias generator 1030 is configured to output appropriate voltage levels at the first bias voltage Vbiasp and the second bias voltage Vbiasn in response to a deceleration control signal SLOW, so as to adjust the resistance value between the first terminal 1022 and the second terminal 1024.

[0086] FIG10C is a circuit diagram of an example 1016B of a second adjustable resistor that can be used as the adjustable resistor 1016 in FIG10A, according to some embodiments. The second adjustable resistor 1016B includes a first terminal 1042 and a second terminal 1044, corresponding to the two terminals of the adjustable resistor 1016 in FIG10A. The second adjustable resistor 1016B includes a first resistor 1046, a second resistor 1048, and a switch 1050. In this example, the second resistor 1048 is electrically coupled between the first terminal 1042 and the second terminal 1044; while one end of the first resistor 1046 is electrically coupled to the second terminal 1044, and the other end is electrically coupled to the switch 1050.

[0087] In Figure 10C, switch 1050 is configured to electrically couple the first resistor 1046 to the first terminal 1042 or electrically decouple the first resistor 1046 from the first terminal 1042 in response to the inversion of the deceleration control signal SLOW (labeled " / SLOW"). Therefore, the resistance between the first terminal 1042 and the second terminal 1044 can be adjusted according to the deceleration control signal SLOW.

[0088] FIG11 is a circuit diagram of oscillators configured to correspond to different clock cycles according to some embodiments. In FIG11, the first oscillator 1100A corresponds to the first oscillator 210 in FIG2, and the second oscillator 1100B corresponds to the second oscillator 220 in FIG2.

[0089] In some embodiments, the first oscillator 1100A is a ring oscillator comprising an inverter 1102A, a first set of inverters 1104A, a second set of inverters 1106A, and a third set of inverters 1110. The first input terminal of the inverter 1102A is electrically coupled to the output terminal of the third set of inverters 1110. The second input terminal of the inverter 1102A is configured to receive a reference signal (e.g., a first reference signal START1). In some embodiments, the signal at the output terminal of the first set of inverters 1104A is used as an output clock signal (e.g., a first clock signal CKA_M).

[0090] In some embodiments, the second oscillator 1100B is a ring oscillator comprising an inverter 1102B, a first set of inverters 1104B, and a second set of inverters 1106B. A first input terminal of the inverter 1102B is electrically coupled to the output terminal of the second set of inverters 1106B. A second input terminal of the inverter 1102B is configured to receive another reference signal (e.g., a second reference signal START2). In some embodiments, the signal at the output terminal of the first set of inverters 1104B is used as an output clock signal (e.g., a second clock signal CKB_M).

[0091] In some embodiments, the hardware configuration of inverter 1102A, the first set of inverters 1104A, and the second set of inverters 1106A matches the hardware configuration of inverter 1102B, the first set of inverters 1104B, and the second set of inverters 1106B. In some embodiments, the third set of inverters 1110 includes M inverting stages. In some embodiments, inverter 1102A, the first set of inverters 1104A, the second set of inverters 1106A, and the third set of inverters 1110 are electrically coupled one after another to form a loop with K+M inverting stages. In some embodiments, inverter 1102B, the first set of inverters 1104B, and the second set of inverters 1106B are also electrically coupled one after another to form a loop with K inverting stages. In some embodiments, K is an odd positive integer, and M is an even positive integer.

[0092] In this example, the additional delay introduced by the third set of inverters 1110 further increases the time period of the first clock signal CKA_M relative to the second clock signal CKB_M. In some embodiments, the first deceleration control signal SLOW1 and / or the second deceleration control signal SLOW2 shown in FIG2 are omitted because the hardware configuration based on the first oscillator 1100A and the second oscillator 1100B cannot provide an adjustable delay.

[0093] FIG12 is a flowchart of a method 1200 for generating a count value indicating the time difference between a first event and a second event, according to some embodiments. In some embodiments, various operations of method 1200 are performed by the time-to-digital converter 200 in FIG2, and reference is made to various embodiments in FIGS. 3 to 11. As shown in FIG12, method 1200 includes blocks 1210 to 1240.

[0094] In block 1210, a first oscillator (e.g., first oscillator 210 in FIG. 2) outputs a first clock signal (e.g., first clock signal CKA_M in FIG. 2) in response to a first event. In some embodiments, the first clock signal has a first clock period. In some embodiments, block 1210 corresponds to the operation of at least stages 315 and 320 in FIG. 3.

[0095] In some embodiments, method 1200 further includes a first oscillator receiving a first reference signal (e.g., the first reference signal START1 in FIG2), wherein a first event corresponds to the first reference signal changing from a first logic state (e.g., low level) to a second logic state (e.g., high level). In some embodiments, method 1200 further includes disabling the first oscillator based on the first reference signal being in the first logic state, and / or enabling the first oscillator based on the first reference signal being in the second logic state.

[0096] In block 1220, a second oscillator (e.g., second oscillator 220 in FIG. 2) outputs a second clock signal (e.g., second clock signal CKB_M in FIG. 2) in response to a second event. In some embodiments, the second clock signal has a second clock period. In some embodiments, the first event occurs before the second event (e.g., time difference Tsense). In some embodiments, the first clock period is greater than the second clock period, and the period difference is ΔT. In some embodiments, block 1220 corresponds to the operation of at least stages 330 and 335 in FIG. 3.

[0097] In some embodiments, method 1200 further includes a second oscillator receiving a second reference signal (e.g., the second reference signal START2 in FIG2), wherein the second event corresponds to the second reference signal changing from a first logic state (e.g., low level) to a second logic state (e.g., high level). In some embodiments, method 1200 further includes disabling the second oscillator based on the second reference signal being in the first logic state, and / or enabling the second oscillator based on the second reference signal being in the second logic state.

[0098] In block 1230, a phase detector (e.g., phase detector 230 in FIG2) generates a detection signal (e.g., detection signal HITB in FIG2) based on the phase relationship between the first clock signal and the second clock signal. In some embodiments, block 1230 corresponds to the operation of at least stages 340 and 345 in FIG3.

[0099] In block 1240, a clock counter (e.g., clock counter 240 in FIG2) generates a count value (e.g., count value TDC_OUT in FIG2) based on a first clock signal and in response to a detection signal indicating that the phase of a second clock signal lags behind the phase of the first clock signal. In some embodiments, block 1240 corresponds to a portion of the operation of at least stages 325 to 345 in FIG3.

[0100] In some embodiments, in order for the clock counter to generate a count value, method 1200 further includes a clock gate circuit of the clock counter (e.g., clock gate circuit 250 in FIG. 2) generating a counting clock signal (e.g., the counting clock signal CKC in FIG. 2) based on a first clock signal and a detection signal. In some embodiments, method 1200 further includes a counter (e.g., counter 260 in FIG. 2) generating a count value based on the counting clock signal. In some embodiments, the counter is an N-bit counter, where N ranges from 6 to 12, or 8 to 10. In some embodiments, the count value is an N-bit unsigned integer.

[0101] In some embodiments, method 1200 further includes configuring a first oscillator, a second oscillator, or both such that the second clock period is at least 100 times the period difference ΔT between the first clock period and the second clock period. In some embodiments, the first oscillator is a first ring oscillator, and the second oscillator is a second ring oscillator. In some embodiments, method 1200 further includes configuring a first configurable delay of the first oscillator based on configuring one or more first load capacitors, first load resistors, or first phase interpolators between successive inverting stages of the first oscillator, as illustrated in the examples of Figures 4A, 4B, and 9A through 10C. In some embodiments, method 1200 further includes configuring a second configurable delay of the second oscillator based on configuring one or more second load capacitors, second load resistors, or second phase interpolators between successive inverting stages of the first oscillator, as illustrated in the examples of Figures 4A, 4B, and 9A through 10C.

[0102] In some aspects, the time-to-digital conversion device includes a first oscillator configured to output a first clock signal in response to a first event and a second oscillator configured to output a second clock signal in response to a second event. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period. The time-to-digital conversion device further includes a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal. The count value indicates the time difference between the first event and the second event.

[0103] In some aspects, a method for generating a count value indicating a time difference between a first event and a second event includes: outputting a first clock signal by a first oscillator in response to the first event, and outputting a second clock signal by a second oscillator in response to the second event. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period. The method further includes: generating a detection signal by a phase detector based on a phase relationship between the first clock signal and the second clock signal, and generating a count value based on the first clock signal by a clock counter in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal.

[0104] In some aspects, an integrated circuit chip includes one or more digital circuit blocks configured to output a first reference signal and a second reference signal, and a time-to-digital converter configured to output a count value indicating a time difference between a first event and a second event. The time-to-digital converter includes a first oscillator configured to output a first clock signal in response to a first event based on the first reference signal, and a second oscillator configured to output a second clock signal in response to a second event based on a second reference signal. The first event occurs before the second event. The first clock signal has a first clock period, the second clock signal has a second clock period, and the first clock period is greater than the second clock period. The time-to-digital converter also includes a phase detector configured to generate a detection signal based on a phase relationship between the first clock signal and the second clock signal, and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal.

[0105] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] Figures 1A and 1B are block diagrams of application examples based on time-to-digital converters, according to certain embodiments. Figure 2 is a block diagram of an example of a time-to-digital converter, according to certain embodiments. Figure 3 is a flowchart of an example of a process executed by a time-to-digital converter, according to certain embodiments. Figure 4A is a circuit diagram of an example of an oscillator, according to certain embodiments. Figure 4B is a circuit diagram of the inverting gate in the delay circuit of Figure 4A, according to certain embodiments. Figure 5 is a circuit diagram of an example of a phase detector, according to certain embodiments. Figure 6A is a circuit diagram of an example of a clock-gated circuit, according to certain embodiments. Figures 6B to 6C are circuit diagrams of variations of the clock-gated circuit in Figure 6A, according to certain embodiments. Figure 7 is a block diagram of an example of a counter, according to certain embodiments. Figures 8A to 8D are diagrams of signal waveforms and / or bit values ​​of a time-to-digital converter session example based on the time-to-digital converters of Figures 2 to 6A and 7, according to certain embodiments. Figures 9A and 9B are diagrams of delay circuit examples based on phase interpolators, according to certain embodiments. Figures 10A and 10C are diagrams of delay circuit examples based on adjustable load resistors, according to certain embodiments. Figure 11 is a circuit diagram of an oscillator configured to correspond to different clock periods, according to certain embodiments. Figure 12 is a flowchart of a method for generating a count value indicating the time difference between a first event and a second event, according to certain embodiments.

Claims

1. A time-to-digital converter, comprising: A first oscillator is configured to output a first clock signal in response to a first event, the first clock signal having a first clock period; A second oscillator, configured to output a second clock signal in response to a second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; a phase detector, configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal; and a clock counter, configured to generate a count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, the count value indicating the time difference between the first event and the second event, wherein the first event corresponds to a first reference signal changing from a first logic state to a second logic state, and the second event corresponds to a second reference signal changing from the first logic state to the second logic state.

2. The time-to-digital conversion device as described in claim 1, wherein, The first oscillator is configured to be deactivated based on the first reference signal being in the first logic state and activated based on the first reference signal being in the second logic state; and the second oscillator is configured to be deactivated based on the second reference signal being in the first logic state and activated based on the second reference signal being in the second logic state.

3. The time-to-digital conversion device as described in claim 1, wherein, The first oscillator is a first ring oscillator, including one or more first load capacitors, first load resistors or first phase interpolators between two consecutive inverting stages of the first oscillator, and configured to set a first configurable delay of the first oscillator; and the second oscillator is a second ring oscillator, including one or more second load capacitors, second load resistors or second phase interpolators between two consecutive inverting stages of the second oscillator, and configured to set a second configurable delay of the second oscillator.

4. The time-to-digital converter as claimed in claim 1, wherein the clock counter comprises: A clock gate circuit is configured to generate a counting clock signal based on the first clock signal and the detection signal; And a counter, configured to generate the count value based on the count clock signal.

5. The time-to-digital conversion device as described in claim 4, wherein, The clock gate control circuit is based on a D-type flip-flop or a D-type latch and has a reverse gate or a gate.

6. The time-to-digital conversion device as described in claim 4, wherein, The counter is an N-bit counter, and N ranges from 6 to 12.

7. The time-to-digital conversion device as claimed in claim 1, wherein, The second clock cycle is at least 100 times the cycle difference between the first clock cycle and the second clock cycle.

8. A method for generating a count value indicating the time difference between a first event and a second event, comprising: A first clock signal is output by a first oscillator in response to the first event, wherein the first clock signal has a first clock period; A second clock signal is output by a second oscillator in response to the second event, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; a detection signal is generated by a phase detector based on the phase relationship between the first clock signal and the second clock signal; and a clock counter generates the count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, wherein the first event corresponds to a first reference signal changing from a first logic state to a second logic state, and the second event corresponds to a second reference signal changing from the first logic state to the second logic state.

9. An integrated circuit chip, comprising: One or more digital circuit blocks are configured to output a first reference signal and a second reference signal; And a time-to-digital converter configured to output a count value indicating the time difference between a first event and a second event, the time-to-digital converter comprising: a first oscillator configured to output a first clock signal in response to the first event based on the first reference signal, the first clock signal having a first clock period; A second oscillator configured to output a second clock signal in response to a second event based on a second reference signal, the second clock signal having a second clock period, the first event occurring before the second event, and the first clock period being greater than the second clock period; a phase detector configured to generate a detection signal based on the phase relationship between the first clock signal and the second clock signal; and a clock counter configured to generate a count value based on the first clock signal in response to the detection signal indicating that the phase of the second clock signal lags behind the phase of the first clock signal, wherein the first event corresponds to the first reference signal changing from a first logic state to a second logic state, and the second event corresponds to the second reference signal changing from the first logic state to the second logic state.

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