Memory cards, memory systems and memory methods

Abstract

A memory card with a new tuning architecture is provided. According to the embodiment, the memory card includes non-volatile memory and a controller. The controller can be connected to a host computer to control the non-volatile memory. The controller is configured such that a first instruction is defined as the sampling timing for the host computer to receive data from the controller, and a first value is defined as tuning mode data sent by the host computer for tuning. When the controller receives the first instruction and the first value is set to the first parameter of the first instruction, it receives the tuning mode data from the host computer. A second value is defined as the tuning mode data sent by the memory card. When the controller receives the first instruction and the second value is set to the first parameter of the first instruction, it sends the tuning mode data to the host computer.

Description

Technical Field

[0001] The embodiments of the present invention relate to memory cards, systems, and methods. Prior Technology

[0002] SD™ memory cards with flash memory are quite common. SD™ memory cards are also known as SD™ cards.

[0003] The SD Association's specifications define a command that tunes the sampling time of data received by the host from the SD™ memory card, enabling the host to correctly read the data from the SD™ memory card. Specifically, this is defined as CMD19 (send tuning block command). Summary of the Invention

[0004] One embodiment of the present invention provides a memory card, system, and method with a novel tuning architecture.

[0005] According to the embodiment, the memory card includes non-volatile memory and a controller. The controller can be connected to a host computer to control the non-volatile memory. The controller is configured such that a first instruction is defined as the sampling timing for the host computer to receive data from the controller, and a first value is defined as tuning mode data sent by the host computer for tuning. When the controller receives the first instruction and the first value is set to the first parameter of the first instruction, it receives the tuning mode data from the host computer. A second value is defined as the tuning mode data sent by the memory card. When the controller receives the first instruction and the second value is set to the first parameter of the first instruction, it sends the tuning mode data to the host computer. Simple Explanation of the Diagram

[0006] [Figure 1] is a diagram showing a structural example of an information processing system that includes a memory card according to the first embodiment and a host that uses the memory card as an external memory device. [Figure 2] is a diagram showing the pin configuration of the connector in an SD Express card. [Figure 3] is a diagram showing a structural example of a memory card according to the first embodiment. [Figure 4] is a diagram showing a structural example of the host of the first embodiment. [Figure 5] is a diagram used to illustrate the basic specifications of CMD19 as defined by the SD Association. [Figure 6] is a diagram used to illustrate an extended example of CMD19. [Figure 7] is a table showing the reference list of the expanded version of CMD19. [Figure 8] is a flowchart showing the order of operations during tuning when the memory card and host are writing data in the first embodiment. [Figure 9] is a diagram illustrating all modes in the range components of the UI to be executed during tuning at the data sampling time. [Figure 10] is a diagram showing a structural example of the host of the second embodiment. [Figure 11] is a flowchart showing the order of operations during tuning when the memory card and host are writing data in the second embodiment. [Figure 12] is a diagram showing a structural example of a memory card according to the third embodiment. [Figure 13] is a diagram showing a structural example of the host in the third embodiment. [Figure 14] is an example of an eye diagram showing the signal waveform of the data line between the memory card and the host in the third embodiment. [Figure 15] is a diagram showing an example of the voltage threshold value of the data signal supported by the memory card in the third embodiment. [Figure 16] is a flowchart showing the sequence of operations when the memory card and the host are tuning the voltage used for data transmission in the third embodiment. [Figure 17] is a diagram showing a structural example of a memory card according to the fourth embodiment. [Figure 18] is a diagram showing a structural example of the host in the fourth embodiment. [Figure 19] is an example of an eye diagram showing the signal waveform of the data line between the memory card and the host in the fourth embodiment. [Figure 20] is a diagram showing an example of the center voltage value of the data signal supported by the memory card in the fourth embodiment. [Figure 21] is a flowchart showing the sequence of operations when the memory card and the host are tuning the voltage used for data transmission in the fourth embodiment. Implementation

[0007] The following describes the implementation method with reference to the drawings.

[0008] (First Embodiment) First, let me describe the first implementation method. Figure 1 is a diagram illustrating a structural example of an information processing system 3 that includes a memory card 1 according to the first embodiment and a host 2 that uses the memory card 1 as an external memory device. The memory card is also called a storage device, or a memory system.

[0009] Memory card 1, for example, is an SD™ memory card. Memory card 1, for example, supports UHS (Ultra High Speed)-I. SD™ memory cards that support UHS-I are also called UHS-I cards.

[0010] Host 2 is an information processing device such as a personal computer, mobile media player, and digital camera.

[0011] The memory card 1 has non-volatile memory 14, memory controller 11, I / O cell 12, and connector 13.

[0012] Non-volatile memory, for example, is NAND flash memory. The memory controller 11 controls the non-volatile memory 14. Furthermore, the memory controller 11 controls communication with the host 2. The memory controller is also commonly referred to as a controller.

[0013] I / O cell 12 works in conjunction with I / O cell 22 of host 2 (described later) to perform the functions of instruction line 32, clock line 33, and data line 31 between memory card 1 and host 2. I / O cell is also called interface driver.

[0014] Connector 13 has pins 1 to 9, which can be assigned to command line 32, clock line 33, and data line 31. For example, data line 31 (DAT0~3) is assigned to pins 7, 8, 9, and 1. Command line 32 is assigned to pin 2. Clock line 33 is assigned to pin 5.

[0015] The host 2 has I / O cells 22 and host controller 21. I / O cell 22 works in conjunction with I / O cell 12 of memory card 1 to form instruction line 32, clock line 33 and data line 31 between memory card 1 and host 2.

[0016] The host controller 21 controls the communication with the memory card 1. Alternatively, one example of memory card 1 shown in Figure 1 is an SD™ memory card that supports UHS-I. The memory card 1 in the first embodiment can also be an SD Express memory card that operates in SD mode.

[0017] Figure 2 shows the pin configuration of connector 13 in SD Express card, i.e., memory card 1-2.

[0018] Memory card 1-2 operates in either SD mode or PCIe mode. In PCIe mode, it uses an interface conforming to the PCI Express™ (PCIe™) specification and a protocol conforming to the NVM Express™ (NVMe™) specification. Therefore, the connector 13 of memory card 1-2, as shown in Figure 2, has pins 10-19 in addition to pins 1-9. Pins 1-9, indicated by the symbol a1 and surrounded by dashed lines, are configured identically to the pins 1-9 of memory card 1 in Figure 1. In SD mode, memory card 1-2 uses only pins 1-9 of the first layer (pins 1-9) and pins 10-19 of the second layer (pins 10-19).

[0019] Figure 3 is a diagram showing a structural example of memory card 1. In addition to the structural elements described above, memory card 1 also has a pattern data memory unit 15. The pattern data memory unit 15 stores tuning pattern data, which is used to tune the sampling timing when host 2 receives data from memory card 1. The tuning pattern data includes bit patterns that would cause the worst eye-opening conditions when using data line 31 to send and receive signals.

[0020] In Figure 3, for ease of explanation, the pattern data memory unit 15 is labeled as a structural element different from the memory controller 11 or the non-volatile memory 14. The pattern data memory unit 15 can be located in the built-in memory of the memory controller 11 or in the non-volatile memory 14.

[0021] Figure 4 is a diagram showing one example of the structure of host 2. In addition to the structural elements already described, the host unit 2 also includes a host CPU 25, a clock unit 23, a sampling clock adjustment unit 24, and a mode data transmission and reception unit 26.

[0022] The host CPU25 will run various programs such as operating system, firmware, and software for multimedia players.

[0023] The clock portion 23 generates a clock signal that is treated as the fundamental frequency of the action of the information processing system 3 .

[0024] The sampling clock adjustment unit 24 , uses the tuning mode data to tune the sampling moment of the data in the case of host 2 reading the data from the memory card 1, or in the case of host 2 writing the data to the memory card. Previously, the tuning of data sampling moments, using CMD19 as defined by the SD Association specification, can only be performed when host2 is reading data from memory card1. Further, with the high speed of memory card 1, it becomes more and more necessary to perform data sampling moment tuning in the case where host 2 writes data to memory card 1; This will be explained later.

[0025] The mode data delivery and reception unit 26 transmits the tuned mode data to, or receives the data from, the memory card 1 .

[0026] Also in Fig. 4 for ease of exposition, the sampling clock adjustment section 24 and the mode data transmission and reception section 26 are labeled as structural elements different from the host controller 21 . The sampling clock adjustment unit 24 and the mode data transmission and reception unit 26 may also be set as a unit within the host controller 21 .

[0027] 5 is a diagram used to illustrate the basic specifications of the CMD19. Host 2 sends CMD 19 to memory card 1 using command line 32 .

[0028] Memory card 1, which receives a message to CMD 19 , sends an outgoing response to CMD 19 (R1) to host 2 using command line 32 . Then after the response, memory card 1 sends the tuned mode data (Data Block) to host 2 using the data line 31 .

[0029] When host 2 receives a message from memory card 1 to tuned mode data, it can tune the sampling moment for the data received from memory card 1 . Specifically, the host controller 21 performs tuning at the sampling moment by sending the mode data to the receiving and receiving part 26 and by means of the sampling clock adjustment part 25 .

[0030] In other words, the CMD19 command is used to request memory card 1 to send out tuning mode information.

[0031] On the other hand, Figure 6 is a diagram used to illustrate an extended example of CMD19. The memory card 1 in the first embodiment, if it receives CMD19, will interpret the various parameters (TD, DDR, CT, TLT, CLT) indicated by the dotted box marked by symbol b1. Figure 7 is a list of parameters of CMD19.

[0032] If the parameter TD is 0, as shown in Figure 5, it indicates that memory card 1 is sending out tuning mode data. TD=0 means using the CMD19 setting according to the basic specifications.

[0033] On the other hand, if the parameter TD is 1, it indicates that host 2 is sending out tuning mode data. Returning to Figure 6, this illustrates CMD19 with parameter TD=1.

[0034] The reason host 2 issues CMD19 with TD=1 is to tune the sampling time when host 2 sends data to memory card 1, so that host 2 can correctly write data to memory card 1. This tuning action is predicated on the fact that when host 2 issues CMD19 with TD=0, it will receive tuning mode data from memory card 1, and the tuning of the sampling time for receiving data from memory card 1 will end. In other words, it is predicated on the premise that host 2 can correctly read the data from memory card 1.

[0035] Host 2 uses instruction line 32 to send CMD19 with the parameter set to TD=1 to memory card 1.

[0036] Memory card 1, upon receiving CMD19 with parameter TD=1, will use command line 32 to send a response (R1) to host 2 in response to CMD19. When CMD19's parameter TD=1, memory card 1 will not send tuning mode data, but will remain in standby until the tuning mode data is sent.

[0037] Once host 2 receives a response (R1) to CMD19, it will use data line 31 to send the tuning mode data (Data Block) to memory card 1. Furthermore, host 2 will send out data (CS) to detect any tuning mode data errors that may occur during the transmission and reception process.

[0038] Therefore, the memory card 1 of the first embodiment can interpret the argument TD of CMD19. In this way, the host 2 can use CMD19 to send tuning mode data to the memory card 1.

[0039] Furthermore, when memory card 1 receives CMD19 with pin TD=1, it stores the tuning mode data sent by host 2, for example, in the internal memory of memory controller 11. Memory card 1 can also store the tuning mode data sent by host 2 in memory other than the internal memory of memory controller 11. For example, memory card 1 can also store the tuning mode data sent by host 2 in non-volatile memory 14. Then, when memory card 1 receives CMD19 with pin TD=0 and is storing the tuning mode data sent by host 2, it sends the stored tuning mode data to host 2. If memory card 1 receives CMD19 with pin TD=0 before receiving CMD19 with pin TD=1, it sends the tuning mode data stored in mode data memory 15 to host 2.

[0040] Therefore, by using CMD19 with argument TD=1, the tuning mode data sent by host 2 to memory card 1 can be received back to host 2 from memory card 1.

[0041] Additionally, the CMD19 parameters (DDR, CT, TLT, CLT) other than TD shown in Figures 6 and 7 will be explained later.

[0042] Next, referring to the flowchart in Figure 8, it will be explained how to tune the data sampling time so that the memory card 1 and the host 2 of the first embodiment can perform writing simultaneously. The premise here is that the tuning of the data writing sampling time has been completed.

[0043] First, host 2 sets CMD19 to transmit tuning mode data to memory card 1 using argument TD (CMD19 with argument TD=0), and sends CMD19 to memory card 1 (S101). Meanwhile, memory card 1 receives CMD19 with argument TD=0 from host 2 (S151). Upon receiving CMD19 with argument TD=0, memory card 1 sends the tuning mode data stored in the mode data memory unit 15 to host 2 (S152). Host 2 then receives and stores the tuning mode data from memory card 1 (S102).

[0044] Next, host 2 sets CMD19 to transmit tuning mode data (CMD19 with TD=1) using argument TD, and sends CMD19 to memory card 1 (S103). On the other hand, memory card 1 receives CMD19 with TD=1 from host 2 (S153). When memory card 1 receives CMD19 with TD=1, it will stand by until host 2 sends the tuning mode data. After host 2 sends CMD19 with pin TD=1, it then sends the tuning mode data obtained and stored from memory card 1 in S102 to memory card 1 (S104). Memory card 1 then receives the tuning mode data from host 2 and stores it (S154).

[0045] Next, host 2 sends CMD19 with pin TD=0 to memory card 1 (S105). Memory card 1 then receives CMD19 with pin TD=0 from host 2 (S155). At this time, memory card 1 holds the tuning mode data sent by host 2, so instead of sending out the tuning mode data stored in the mode data memory unit 15, it sends the tuning mode data received and held from host 2 in S154 to host 2 (S155). On the other hand, host 2 receives the tuning mode data from memory card 1 (S106).

[0046] Host 2 compares the pattern data received from memory card 1 in S106 with the pattern data received from memory card 1 and stored in S102 (S107). As mentioned earlier, this is based on the premise that the tuning at the data writing sampling time has ended; therefore, the pattern data received from memory card 1 and stored in S102 can be used as reference data. Host 2 converts the result of this comparison into, for example, an evaluation value and stores it.

[0047] As shown in Figure 9, host 2 aligns the sampled clock with the clock generated by clock section 23, offsetting it by 1 unit each time according to a specified time unit, and repeatedly executes the processes S103 to S107. CLK_INT is the sampled clock waveform that matches the clock generated by clock section 23. The lower layer CLK_INT, Clock with delay Tap1, is a sampled clock waveform offset by 1 unit from the clock generated by clock section 23. Tap1 represents the offset of 1 unit. The lower layer Clock with delay Tap2 is a sampled clock waveform offset by 2 units from the clock generated by clock section 23. Tap2 represents the offset of 2 units. The same applies to the following layers, with the lower layer being a sampled clock waveform offset by N units from the clock generated by clock section 23. For example, host 2 will execute the processes S103 to S107 until the offset pattern of the sampled clock completely encompasses the UI (unit interval) range of the clock generated by clock section 23. Alternatively, host 2 can also execute the processing of S103~S106 until a certain time exceeds the UI range.

[0048] For the processing of S103 to S107, host 2 determines whether all modes within the UI range have been executed (S108). If there are still unexecuted modes (S108: NO), host 2 will shift the sampling pulse error by 1 unit (S109) and return to S103 to execute the processing of S103.

[0049] If all modes within the UI range have been executed (S108:YES), host 2 will determine the optimal offset of the sampling clock based on the comparison result of S107 and set the sampling point (S110).

[0050] As described above, the memory card 1 of the first embodiment can interpret the CMD19 pin TD. When the pin TD is a predetermined value, it receives tuning mode data from the host 2 and sends the tuning mode data received from the host and kept thereto to the host 2. With this CMD19 expansion, the host 2 can not only read data but also tune the sampling time of the data to be written.

[0051] In this way, the host 2 can perform faster and more accurate reading / writing to the memory card 1 of the first embodiment.

[0052] Regarding the processing of CMD19, sometimes only the rising edge of the clock is used for data transmission, which is called SDR (single-data rate) mode. On the other hand, memory card 1 usually uses both the rising and falling edges of the clock for data transmission, which is called DDR (double-data rate) mode. Therefore, for the memory card of this embodiment, it is sufficient to configure the tuning mode data into two types: a data mode that includes SDR and a data mode that includes DDR.

[0053] As shown in Figures 6 and 7, the DDR pin of CMD19 specifies the tuning mode data for transmitting and receiving signals between memory card 1 and host 2 as either SDR data mode or DDR data mode. For example, pin DDR=0 specifies the tuning mode data for SDR data mode, and pin DDR=1 specifies the tuning mode data for DDR data mode.

[0054] By setting the DDR parameter to the CMD19 parameter, for example, if host 2 is connected to memory card 1 that sends reception data in SDR mode or memory card 1 that sends reception data in DDR mode, CMD19 can be used as the command to send reception mode data, thus achieving the interchangeability of CMD19.

[0055] (Second Implementation) Next, the second embodiment will be described. Here, the same reference numerals are used for structural elements that are the same as in the first embodiment, and repeated descriptions of the same structural elements are omitted.

[0056] Figure 10 is a diagram showing a structural example of the host 2 in the second embodiment. The host 2 in the second embodiment, compared to the host 2 in the first embodiment, further includes a host-side mode data memory unit 27. The host-side mode data memory unit 27, like the mode data memory unit 15 of the memory card 1, stores tuning mode data. The tuning mode data stored in the host-side mode data memory unit 27 may or may not be the same as the tuning mode data stored in the mode data memory unit 15 of the memory card 1. Ideally, the tuning mode data stored in the host-side mode data memory unit 27 is a bit mode created under worse eye-aperture conditions compared to the tuning mode data stored in the mode data memory unit 15 of the memory card 1.

[0057] In the second embodiment, the host 2 stores tuning mode data in the host-side mode data memory unit 27, which differs from the first embodiment. When tuning for data writing, it is not necessary to send the CMD19 signal with pin TD=0 to the memory card 1 as described in the first embodiment, nor is it necessary to retrieve the tuning mode data from the memory card 1. In other words, the host 2 in the second embodiment does not require the process of retrieving tuning mode data from the memory card 1.

[0058] In this way, compared to the first embodiment, the second embodiment can shorten the required time by tuning the sampling time for writing data.

[0059] Furthermore, by using the tuning mode data held by host 2, which is a bit mode created with worse eye opening conditions, more refined tuning can be performed.

[0060] Figure 11 is a flowchart showing the sequence of operations during tuning when the memory card 1 and host 2 are writing data in the second embodiment.

[0061] The differences between this process and the flowchart shown in FIG8 of the first embodiment are as follows: First, the S101 and S102 processes of the host 2 in FIG8, and the S151 and S152 processes of the memory card 1 corresponding to the above processes in FIG8, are omitted. Second, the S104 process of the host 2 in FIG8 is replaced by sending the mode data stored in the mode data memory unit 27 on the host side to the memory card 1 (S121).

[0062] Therefore, in the second embodiment, the host 2 will maintain the tuning mode data, which can shorten the tuning time and enable more precise adjustments.

[0063] (Third Implementation) Next, the third embodiment will be described. Here, the same reference numerals are used for structural elements that are the same as those in the first or second embodiment, and repeated descriptions of the same structural elements are omitted.

[0064] The third implementation is to expand CMD19 so that the voltage used for data transmission can be tuned.

[0065] Figure 12 is a diagram showing a structural example of the memory card 1 according to the third embodiment. The memory card 1 of the third embodiment has a threshold potential control unit 16 compared to the memory card 1 of the first embodiment. Furthermore, in FIG12, for ease of explanation, the threshold potential control unit 16 is labeled as a structural element different from the memory controller 11. The threshold potential control unit 16 may also be provided within the memory controller 11 as a single unit.

[0066] The threshold voltage control unit 16 changes the threshold value of the voltage used for data transmission on the data line 31 between the memory card 1 and the host 2 in response to a request from the host 2. Specifically, the threshold voltage control unit 16 lowers the upper limit value or raises the lower limit value for the voltage threshold value of the data signal transmitted on the data line 31.

[0067] More specifically, the memory card 1 of the third embodiment interprets the parameter TLT of CMD19 shown in Figures 6 and 7, and identifies CMD19 with parameter TLT=1 as the host 2 requesting to change the upper or lower limit value of the voltage threshold of the data signal when using data line 31 to transmit data.

[0068] Figure 13 is a diagram showing a structural example of the host 2 in the third embodiment. In the third embodiment, the host 2 differs from the host 2 in the first embodiment in that the sampling clock adjustment unit 24 is replaced by a threshold potential adjustment unit 28. Furthermore, in FIG13, for ease of explanation, the threshold potential adjustment unit 28 is indicated as a structural element different from the host controller 21. The threshold potential adjustment unit 28 may also be provided within the host controller 21 as a single unit.

[0069] The threshold voltage adjustment unit 28 uses a CMD19 to tune the voltage used for data transmission via the data line 31 between the host 2 and the memory card 1. The tuning performed by the threshold voltage adjustment unit 28 will be explained in detail with reference to Figures 14 and 15.

[0070] Figure 14 is an example of an eye diagram showing the signal waveform of data line 31. In UHS-I, the upper limit minimum value (VOH(min)) of the 1.8V signal threshold is defined as 1.40V, and the lower limit maximum value (VOL(max)) is defined as 0.45V. With this voltage definition, the range is 0.95V.

[0071] Furthermore, for eMMC (embedded multimedia card), the VOH (min) of a 1.2V signal is defined as 0.825V, and the VOL (max) is defined as 0.325V. In the following explanation, considering that SD™ memory cards will also support 1.2V signals in the future, the eMMC specification is used to describe the 1.2V signal.

[0072] In contrast, the memory card 1 of the third embodiment, as shown in Figure 15, supports threshold values ​​for the 1.8V signal, including VOH(min) of 1.40V, as well as 1.38V, 1.36V, and 1.34V. On the other hand, it supports VOL(max) of 0.45V, as well as 0.47V, 0.49V, and 0.51V. If data transmission can be successfully performed using power with VOH(min) = 1.34V and VOL(max) = 0.51V, the amplitude is 0.83. In this case, the slope of the signal rise / fall is gentler, thus suppressing ringing, easing eye opening conditions, and further suppressing electrical power. Furthermore, the memory card 1 has preset initial values ​​of VOH(min) = 1.40V and VOL(max) = 0.45V.

[0073] Furthermore, regarding eMMC, the memory card 1 in the third embodiment, as shown in Figure 15, supports threshold values ​​for the 1.2V signal, VOH(min) in addition to 0.825V, for example, 0.815V, 0.805V, and 0.795V. On the other hand, VOL(max) in addition to 0.325V, also supports 0.335V, 0.345V, and 0.355V.

[0074] Referring to the flowchart in Figure 16, this explains how to tune the voltage so that the memory card 1 and the host 2 in the third embodiment can perform data transfer together. This assumes that tuning for the data writing / reading sampling time has been completed.

[0075] First, host 2 confirms that the data read / write to memory card 1 has been performed correctly (S201). The S201 process can be performed by sending reception tuning mode data via CMD19 with additional TD arguments, but is not limited to this, and can be performed by various methods.

[0076] Next, host 2 sets CMD19 to perform threshold voltage tuning using parameter TLT (parameter TLT=1), and sends CMD19 to memory card 1 (S202). This CMD19 with parameter TLT=1 is sent to memory card 1 via instruction line 32. At this time, host 2, for example, uses the data line to send a value one level lower than the current VOH(min) or one level higher than the current VOL(max) to memory card 1. Host 2 can change VOH(min) and VOL(max) simultaneously, or separately.

[0077] Alternatively, host 2 can also leave the values ​​unspecified, and when memory card 1 receives CMD19 with TLT=1, it will automatically change VOH(min) and VOL(max) by 1 level, for example.

[0078] Memory card 1 receives CMD19 with TLT=1 from host 2 (S251) and changes VOH(min) and VOL(max) (S252). Next, host 2 performs data writing / reading on memory card 1 (S203). Host 2 determines whether there is a problem with the data writing / reading in S203 (S204). The processing of S203 and S204 can also be performed by sending reception tuning mode data through CMD19 with additional TD, but it is not limited to this and can be done by various methods.

[0079] If there are no problems with data writing / reading in S203 (S204: YES), host 2 will determine if there is room to change the values ​​of VOH(min) and VOL(max) (S205). If there is room to decrease the values ​​of VOH(min) and VOL(max) (S205: YES), host 2 will return to S202 and execute a series of processes starting from S202 to investigate whether the values ​​of VOH(min) and VOL(max) can be changed by one level.

[0080] If there is no room to change the values ​​of VOH(min) and VOL(max) (S205:NO), the main unit 2 will end the tuning. Furthermore, when there is a problem with data writing / reading in S203 (S204: NO), host 2 will restore the values ​​of VOH(min) and VOL(max) (S206) and end the tuning. As described above, the memory card 1 in the third embodiment interprets the CMD19 parameter TLT to change the values ​​of VOH(min) and VOL(max). Through this CMD19 expansion, the host 2 can change VOH(min) and VOL(max), thereby tuning the voltage for data transmission.

[0081] Additionally, the CT parameter of CMD19 shown in Figures 6 and 7 specifies either tuning from the initial state or corrective tuning. For example, CT=0 specifies tuning from the initial state, while CT=1 specifies corrective tuning.

[0082] For example, memory card 1 will automatically change VOH(min) and VOL(max) by 1 level each in response to CMD19 with TLT=1. Furthermore, if argument CT=0 is set, it will change by 1 level each time starting from the preset value; or, if argument CT=1 is set, it will change by 1 level each time starting from the current value.

[0083] In this way, each change can start from the preset value, thus shortening the tuning time.

[0084] (Fourth implementation) Next, the fourth embodiment will be described. Here, the same reference numerals are used for structural elements that are the same as those in the first to third embodiments, and repeated descriptions of the same structural elements are omitted.

[0085] In the third embodiment, CMD19 is expanded to allow tuning of the voltage used for data transmission. This tuning involves changing either the upper or lower limit of the voltage threshold, or both. In the fourth embodiment, CMD19 is also expanded to allow tuning of the voltage used for data transmission. This tuning involves changing the center value of the voltage.

[0086] Figure 17 is a diagram showing a structural example of the memory card 1 according to the fourth embodiment. The memory card 1 of the fourth embodiment, compared to the memory card 1 of the third embodiment, has a voltage center value control unit 17, replacing the threshold potential control unit 16. Furthermore, in FIG17, for ease of explanation, the voltage center value control unit 17 is labeled as a structural element different from the memory controller 11. The voltage center value control unit 17 may also be provided within the memory controller 11 as a single unit.

[0087] The voltage center value control unit 17 changes the center value of the voltage used for data transmission on the data line 31 between the memory card 1 and the host 2 in response to a request from the host 2. Specifically, the voltage center value control unit 17 lowers the center value of the voltage of the data signal transmitted on the data line 31.

[0088] More specifically, the memory card 1 of the fourth embodiment interprets the CLT of CMD19 shown in Figures 6 and 7, and identifies CMD19 with CLT=1 as a change in the center value of the voltage used when the host 2 requests to use the data line 31 to transmit data.

[0089] Figure 18 is a diagram showing a structural example of the host 2 in the fourth embodiment. In the fourth embodiment, the host 2 differs from the host 2 in the third embodiment in that the threshold potential adjustment unit 28 is replaced by a voltage center value adjustment unit 29. Furthermore, in FIG18, for ease of explanation, the voltage center value adjustment unit 29 is indicated as a structural element different from the host controller 21. The voltage center value adjustment unit 29 may also be provided within the host controller 21 as a single unit.

[0090] The voltage center value adjustment unit 29 uses the existing CMD19 to tune the voltage used for data transmission via the data line 31 between the host 2 and the memory card 1. The tuning performed by the threshold potential adjustment unit 28 will be explained in detail with reference to Figures 19 and 20.

[0091] Figure 19 is an example of an eye diagram showing the signal waveform of data line 31. For UHS-I, the center value of a 1.8V signal is defined as 0.925V. For example, as shown in the eye diagram on the left side of Figure 19, the upper limit is 1.40V and the lower limit is 0.45V, so the amplitude is 0.95V.

[0092] For eMMC, the center value of a 1.2V signal is defined as 0.575V. For example, as shown in the eye diagram on the right side of Figure 19, the upper limit is 0.825V and the lower limit is 0.45V, so the amplitude is 0.50V.

[0093] In contrast, the memory card 1 in the fourth embodiment supports not only 0.925V as the center value of the 1.8V signal, but also, for example, 0.915V, 0.905V, and 0.895V. If data transmission can be performed smoothly using power with a lower center value, then the fluctuation range can be reduced. In this case, similar to the third embodiment, the slope of the signal rise / fall will be gentler, thus suppressing ringing, easing eye opening conditions, and further suppressing electrical power. In addition, the default initial value of memory card 1 is a center value of 0.925V.

[0094] Furthermore, regarding eMMC, the memory card 1 in the fourth embodiment, as shown in Figure 20, supports not only 0.575V, but also, for example, 0.565V, 0.555V, and 0.545V for the center value of the 1.2V signal. Referring to the flowchart in Figure 21, it is explained how to tune the voltage so that the memory card 1 and the host 2 in the fourth embodiment can perform data transfer together. This assumes that tuning for the data writing / reading sampling time has been completed.

[0095] First, host 2 confirms that the data read / write to memory card 1 has been performed correctly (S301). The S301 process can be performed by sending reception tuning mode data via CMD19 with additional TD arguments, but is not limited to this, and can be performed by various methods.

[0096] Next, host 2 sets CMD19 to perform voltage center value tuning using the parameter CLT (parameter CLT=1), and sends CMD19 to memory card 1 (S302). This CMD19 with parameter CLT=1 is sent to memory card 1 via instruction line 32. At this time, host 2, for example, uses the data line to send a value one level lower than the current center value to memory card 1.

[0097] Alternatively, host 2 can choose not to specify a value, but instead automatically reduce the center voltage value of the data signal by 1 level when memory card 1 receives CMD19 with CLT=1.

[0098] Memory card 1 receives CMD19 (S351) with CLT=1 from host 2 and lowers the voltage center value of the data signal (S352). Next, host 2 performs data writing / reading on memory card 1 (S303). Host 2 determines whether there is a problem with the data writing / reading in S303 (S304). The processing of S303 and S304 can also be performed by sending reception tuning mode data through CMD19 with additional TD, but it is not limited to this and can be done by various methods.

[0099] If there are no problems with data writing / reading in S303 (S304: YES), host 2 will determine if there is room to lower the center voltage value of the data signal (S305). If there is room to lower the center voltage value of the data signal (S305: YES), host 2 will return to S302 and execute a series of processes starting from S302 to investigate whether the center voltage value of the data signal can be lowered by one level.

[0100] If there is no room to reduce the center voltage value of the data signal (S305:NO), the host 2 will end the tuning. Furthermore, when there is a problem with data writing / reading in S303 (S304: NO), host 2 will restore the center voltage value of the data signal (S306) and end the tuning. Therefore, host 2 will execute the processing of S302 to S304 a specified number of times, or until the processing of S303 fails, and then detect the minimum value that the center voltage value of the data signal can be set.

[0101] As described above, the memory card 1 in the fourth embodiment interprets the existing CMD19 pin CLT to reduce the voltage center value of the data signal. Through this CMD19 expansion, the host 2 can reduce the voltage center value of the data signal, thereby tuning the voltage for data transmission.

[0102] Furthermore, the lead CT of CMD19 described in the third embodiment can also be used for tuning in the fourth embodiment. For example, memory card 1 will automatically reduce the voltage center value of the data signal by 1 level in response to CMD19 with CLT=1. Furthermore, if the parameter CT=0 is set, it will reduce the voltage by 1 level from the default value; or, if the parameter CT=1 is set, it will reduce the voltage by 1 level from the current value.

[0103] In this way, just like in the third embodiment, the tuning time can be shortened by starting from a preset value each time. Ideally, as described in the third embodiment, the data transmission voltage is tuned by changing VOH(min) and VOL(max), and as described in the fourth embodiment, the data transmission voltage is tuned by lowering the center value of the data signal voltage. Both are implemented together.

[0104] Several embodiments of the present invention have been described, but these embodiments are merely examples and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention described in the claims and its equivalents.

[0105] 1: Memory card 2: Host 3: Information Processing System 11: Memory controller 12:I / O cell 13: Connector 14: Non-volatile memory 15: Pattern Data Memory Department 16: Threshold Potential Control Unit 17: Voltage Center Value Control Department 21: Host Controller 22:I / O cell 23: Time and Pulse Section 24: Sampling clock adjustment unit 25: Host CPU 26: Model data sent to receiving department 27: Host-side mode data memory unit 28: Threshold Potential Adjustment Section 29: Voltage center value adjustment section 31: Data Line 32: Command Line 33: Clock Circuit

Claims

1. A memory card comprising non-volatile memory and a controller, connectable to a host computer to control the non-volatile memory; wherein the controller is configured to: define a first instruction as a sampling timing for the host computer to receive data from the controller; and define a first value as tuning mode data sent by the host computer for the tuning; wherein when the controller receives the first instruction and the first value is set to the first argument of the first instruction, it receives the tuning mode data from the host computer; and define a second value as the tuning mode data sent by the memory card; wherein when the controller receives the first instruction and the second value is set to the first argument of the first instruction, it sends the tuning mode data to the host computer.

2. The memory card as described in request item 1, wherein, The aforementioned controller is configured such that when the aforementioned controller receives the aforementioned first instruction and the second value is set to the first parameter of the aforementioned first instruction, it determines whether to retain the aforementioned tuning mode data received from the aforementioned host; if it wants to retain the aforementioned tuning mode data received from the aforementioned host, it sends the retained aforementioned tuning mode data to the aforementioned host; if it does not want to retain the aforementioned tuning mode data received from the aforementioned host, it sends the aforementioned tuning mode data stored in the aforementioned memory card to the aforementioned host.

3. The memory card as described in request item 1, wherein, The aforementioned first value is set as the first argument of the aforementioned first instruction, and the aforementioned tuning mode data received from the aforementioned host in accordance with the aforementioned first instruction is, before receiving the aforementioned first instruction, the aforementioned second value is set as the first argument of the aforementioned first instruction, and the aforementioned tuning mode data sent to the aforementioned host in accordance with the aforementioned first instruction.

4. The memory card as described in request item 1, wherein, The aforementioned first value is set as the first argument of the aforementioned first instruction, and the aforementioned tuning mode data received from the aforementioned host in response to the aforementioned first instruction is the aforementioned tuning mode data that the aforementioned host has stored in advance.

5. A memory card comprising a non-volatile memory and a controller, connectable to a host computer to control the non-volatile memory; wherein the controller is configured to define a first instruction as a means of tuning the sampling timing of data received by the host computer from the controller, and a third value as a threshold tuning for the voltage used for data transmission between the controller and the host computer; when the controller receives the first instruction and the third value is set as the second argument of the first instruction, the upper limit or lower limit value of the threshold is changed.

6. The memory card as described in request item 5, wherein, The aforementioned controller is configured such that, in response to the aforementioned first instruction and when the aforementioned third value is set as the second argument of the aforementioned first instruction, it sets the aforementioned upper limit side threshold value to a value second only to the current upper limit value from among the options containing multiple values ​​corresponding to the aforementioned upper limit side threshold value; or, it sets the aforementioned lower limit side threshold value to a value only greater than the current lower limit value from among the aforementioned options containing multiple values ​​corresponding to the aforementioned lower limit side threshold value.

7. A memory card comprising non-volatile memory and a controller, connectable to a host computer to control the non-volatile memory; wherein the controller is configured to define a first instruction as a means of tuning the sampling timing of data received by the host computer from the controller, and a fourth value as a means of tuning the center value of the voltage used for data transmission between the controller and the host computer; when the controller receives the first instruction and the fourth value is set to the third argument of the first instruction, the center value is reduced.

8. A memory system comprising a memory card as described in any one of claims 1 to 4, and a host computer, which can be connected to the memory card; the host computer is configured to perform the following actions: (1) when the first value is set as the first argument of the first instruction, send the first instruction to the memory card and send the tuning mode data to the memory card; (2) when the second value is set as the first argument of the first instruction, send the first instruction to the memory card and receive the tuning mode data from the memory card; (3) compare the tuning mode data sent to the memory card and the tuning mode data received from the memory card; while offsetting the sampling clock, the system is repeatedly executed until the offset width of the sampling clock reaches at least the time length of a unit interval, and then the host computer sets the sampling point for the data to be sent to the memory card.

9. A memory system comprising a memory card as described in claim 5 or 6, and a host computer, which can be connected to the memory card; wherein the host computer is configured to perform the following actions: (1) when the aforementioned third value is set as the first argument of the aforementioned first instruction, send the aforementioned first instruction to the aforementioned memory card; (2) write specified data to the aforementioned memory card and read the aforementioned specified data from the aforementioned memory card; (3) determine whether the aforementioned writing and the aforementioned reading are successful or unsuccessful; execute the operation a specified number of times, or until the aforementioned writing or the aforementioned reading fails, and then detect the minimum value that the aforementioned upper limit threshold can be set and the maximum value that the aforementioned lower limit threshold can be set.

10. A memory system comprising a memory card as described in claim 7 and a host computer, which can be connected to the memory card; wherein the host computer performs the following actions: (1) when the aforementioned fourth value is set to the third argument of the aforementioned first instruction, sending the aforementioned first instruction to the aforementioned memory card; (2) writing specified data to the aforementioned memory card and reading the aforementioned specified data from the aforementioned memory card; (3) determining whether the aforementioned writing and reading are successful or unsuccessful; performing the operation a specified number of times, or until the aforementioned writing or reading fails, and then detecting the minimum value that the aforementioned upper limit center value can be set to.

11. A memory method comprising controlling a memory card, the memory card being connectable to a host and comprising non-volatile memory; defining a first instruction as a sampling timing for tuning the host to receive data from the memory card, and defining a first value as tuning mode data sent by the host for the tuning; wherein when the controller receives the first instruction and the first value is set to the first argument of the first instruction, the tuning mode data is received from the host; and defining a second value as the tuning mode data being sent by the memory card, wherein when the controller receives the first instruction and the second value is set to the first argument of the first instruction, the tuning mode data is sent to the host.

12. A memory method, controlling a memory card, the memory card being connectable to a host and including non-volatile memory; defining a first instruction as a means to tune the sampling timing of data received by the host from the memory card, and defining a third value as a threshold tuning for the voltage used for data transmission between the memory card and the host, wherein when the controller receives the first instruction and the third value is set as the second argument of the first instruction, the upper limit or lower limit value of the threshold value is changed.

13. A memory method, controlling a memory card, the memory card being connectable to a host and including non-volatile memory; defining a first instruction as a means to tune the sampling timing of data received by the host from the memory card, and defining a fourth value as a center value tuning for the voltage used for data transmission between the memory card and the host, wherein when the controller receives the first instruction and the fourth value is set to the third argument of the first instruction, the center value is reduced.

Images