Display device

Abstract

The display device includes: a plurality of pulse output circuits, each outputting a signal to one of two scan lines; and a plurality of inverting pulse output circuits, each outputting an inverted or substantially inverted signal from the signals output by the pulse output circuits to the other of the two scan lines. Each of the plurality of inverting pulse output circuits operates with at least two signals for the operation of the plurality of pulse output circuits. Therefore, the through current generated in the inverting pulse output circuits can be reduced.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display device comprising a shift register in which the transistor system is an n-channel transistor or a p-channel transistor (a transistor of only one conductivity type). Prior Art Conventional display devices are active matrix display devices in which a plurality of pixels arranged in a matrix include individual switches, and each pixel displays an image according to a desired potential (image signal) inputted through the switch. Active-matrix display devices require a circuit (scan line driver circuit) that controls the switching of switches within pixels using the potential of scan lines. A typical scan line driver circuit includes a combination of n-channel and p-channel transistors, but a scan line driver circuit can also be formed using either n-channel or p-channel transistors. Note that the former scan line driver circuit can have lower power consumption than the latter scan line driver circuit. Furthermore, the latter scan line driver circuit can be formed using fewer manufacturing steps than the former scan line driver circuit. When the scan line driver circuit is formed using n-channel transistors or p-channel transistors, the potential output to the scan line varies from the power supply potential output to the scan line driver circuit. Specifically, when the scan line driver circuit is formed using only n-channel transistors, at least one n-channel transistor is disposed between the scan line and the wiring for supplying a high power supply potential to the scan line driver circuit. Consequently, the high potential that can be output to the scan line decreases from the high power supply potential due to the threshold voltage of the at least one n-channel transistor. Similarly, when the scan line driver circuit is formed using only p-channel transistors, the low potential that can be output to the scan line increases from the low power supply potential supplied to the scan line driver circuit. In response to the above problem, a scan line driver circuit formed using an n-channel transistor or a p-channel transistor has been proposed, which can output the power supply potential supplied to the scan line driver circuit to the scan line without change. For example, the scan line driver circuit disclosed in Patent Document 1 includes an n-channel transistor to control the electrical connection between the scan line and a clock signal. The clock signal alternates between a high power supply potential and a low power supply potential at a constant frequency. When the high power supply potential is input to the drain of the n-channel transistor, the potential of its gate can be increased by utilizing capacitive coupling between the gate and its source. Therefore, in the scan line driver circuit disclosed in Patent Document 1, a potential equal to or substantially equal to the high power supply potential can be output from the source of the n-channel transistor to the scan line. The number of switches provided in each pixel of an active-matrix display device is not limited to one. Some display devices include multiple switches in each pixel, and each switch is controlled separately to display an image. For example, Patent Document 2 discloses a display device including two types of transistors (a p-channel transistor and an n-channel transistor) in each pixel, wherein the switching relationships of these transistors are controlled separately by different scan lines. In other words, in order to control the potentials of the two separately provided scan lines, two scan line driver circuits (scan line driver circuit A and scan line driver circuit B) are further provided. In the display device disclosed in Patent Document 2, the separately provided scan line driver circuits output signals having substantially opposite phases to the scan lines. [Reference Document] [Patent Document] [Patent Document 1] Japanese Patent Application No. 2008-122939 [Patent Document 2] Japanese Patent Application No. 2006-106786 Summary of the Invention As disclosed in Patent Document 2, there is also a display device in which a scan line driver circuit outputs a signal that is the inverse or substantially the inverse of a signal output to one of two scan lines to the other of the two scan lines. The scan line driver circuit is formed using n-channel transistors or p-channel transistors. For example, the scan line driver circuit disclosed in Patent Document 1 that outputs a signal to a scan line can output a signal to one of the two scan lines and to an inverter, and the inverter can output a signal to the other of the two scan lines. Note that, in the case where the inverter is formed using an n-channel transistor or a p-channel transistor, a large amount of shoot-through current is generated, resulting in high power consumption of the display device. In view of the above reasons, an embodiment of the present invention aims to reduce the power consumption of a display device including a scan line driver circuit formed using an n-channel transistor or a p-channel transistor when the scan line driver circuit outputs a signal that is an inversion or a substantially inversion of a signal output to one of the two scan lines to the other of the two scan lines. A display device according to one embodiment of the present invention includes: a plurality of pulse output circuits each outputting a signal to one of two scan lines; and a plurality of inverted pulse output circuits each outputting a signal that is an inverse or substantially inverse of the signals output by the pulse output circuits to the other of the two scan lines. Each of the plurality of inverted pulse output circuits operates using a signal for operating the plurality of pulse output circuits. In particular, one embodiment of the present invention is a display device comprising: a plurality of pixels arranged in m columns and n rows (m and n are natural numbers greater than or equal to 4); first to m-th scan lines electrically connected to n pixels arranged in corresponding ones of the first to m-th columns; first to m-th inverted scan lines electrically connected to the n pixels arranged in corresponding ones of the first to m-th columns; and a shift register electrically connected to the first to m-th scan lines and the first to m-th inverted scan lines. The pixels arranged in the k-th column (k is a natural number less than or equal to m) each include a first switch and a second switch, the first switch being turned on by inputting a select signal to the k-th scan line, and the second switch being turned on by inputting the select signal to the k-th inverted scan line. Furthermore, the shift register includes first to m-th pulse output circuits and first to m-th inverted pulse output circuits. The sth (s is a natural number less than or equal to (m-2)) pulse output circuit includes a first transistor. The sth pulse output circuit receives an input pulse (only when s is 1) or a shift pulse output from an (s-1)th pulse output circuit, outputs a selection signal to an sth scan line, and outputs a shift pulse to an (s+1)th pulse output circuit. The first transistor is turned on during a first period, which begins with the input of the pulse or the shift pulse output from the (s-1)th pulse output circuit and ends at the end of the shift period. During the first period, a potential equal to or substantially equal to the potential of a first clock signal input to a drain of the first transistor is output from the source of the first transistor by capacitive coupling between the gate and source of the first transistor. The (s+1)th pulse output circuit includes a second transistor. The (s+1)th pulse output circuit receives a shift pulse from the sth pulse output circuit, outputs a selection signal to the (s+1)th scan line, and outputs a shift pulse to the (s+2)th pulse output circuit. The second transistor is turned on during a second period, which begins when the shift pulse from the sth pulse output circuit is input and ends when the shift period ends. During the second period, a potential that is the same as or substantially the same as a second clock signal input to the drain of the second transistor is output from the source of the second transistor by capacitive coupling between the gate and source of the second transistor. The second pulse output circuit includes a third transistor. The second pulse output circuit receives the shift pulse output from the second pulse output circuit and the second clock signal, and outputs a selection signal to the second inverted scan line. The third transistor is turned off during a third period, which begins when the shift pulse output from the second pulse output circuit is input and ends when the potential of the second clock signal changes. After the third period, the selection signal is output from the source of the third transistor to the second inverted scan line. Another embodiment of the present invention is a display device, wherein the second clock signal input to the sth inverted pulse output circuit in the display device is replaced by a shift pulse output from the (s+1)th pulse output circuit. In a display device according to one embodiment of the present invention, the operation of the inverted pulse output circuits is controlled by at least two signals. This reduces the shoot-through current generated within the inverted pulse output circuits. Furthermore, the signals used to operate the plurality of pulse output circuits are the two signals. This means that the inverted pulse output circuits can operate without generating additional signals. One aspect of the present invention relates to a display device, comprising: a driving circuit and a pixel; the driving circuit comprises: a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor; the first circuit has a function of outputting a first signal to the second circuit; the second circuit has a function of outputting a second signal; one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor; one of the source or drain of the first transistor is electrically connected to the gate of the third transistor; one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor; the gate of the first transistor is electrically connected to a first wiring; the first wiring has a function of supplying a first clock signal; the gate of the second transistor is electrically connected to the gate of the fourth transistor; the potential of the gate of the second transistor is controlled by the first signal; the other of the source or drain of the first transistor and the other of the source or drain of the third transistor are respectively electrically connected to a second wiring; the source of the second transistor or drain and the other of the source or drain of the fourth transistor are electrically connected to the third wiring respectively; the pixel comprises: an EL element, a fifth transistor, a sixth transistor, and a seventh transistor; the fifth transistor has a function of supplying current to the EL element; the sixth transistor has a function of controlling the input of an image signal to the pixel; the fifth transistor and the seventh transistor are electrically connected in series between a power line and the EL element; the power line is electrically connected to the fifth transistor through the seventh transistor; the gate of the seventh transistor is electrically connected to one of the source or drain of the third transistor; the first circuit comprises an eighth transistor; the first signal comprises a signal output by the second clock signal through the eighth transistor; the second circuit comprises a ninth transistor; the second signal comprises a signal output by the third clock signal through the ninth transistor; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have the same polarity. Another aspect of the present invention relates to a display device, comprising: a driving circuit and a pixel; the driving circuit comprises: a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, and a fourth transistor; the first circuit has a function of outputting a first signal to the second circuit; the second circuit has a function of outputting a second signal; one of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor; one of the source or drain of the first transistor is electrically connected to the gate of the third transistor; one of the source or drain of the third transistor is electrically connected to one of the source or drain of the fourth transistor; the gate of the first transistor is electrically connected to a first wiring; the first wiring has a function of supplying a first clock signal; the gate of the second transistor is electrically connected to the gate of the fourth transistor; the potential of the gate of the second transistor is controlled according to the first signal; the other of the source or drain of the first transistor and the other of the source or drain of the third transistor are respectively supplied with a first potential; the source of the second transistor The other of the electrode or drain and the other of the source or drain of the fourth transistor are respectively supplied with a second potential; the pixel comprises: an EL element, a fifth transistor, a sixth transistor, and a seventh transistor; the fifth transistor has a function of supplying current to the EL element; the sixth transistor has a function of controlling the input of an image signal to the pixel; the fifth transistor and the seventh transistor are electrically connected in series between a power line and the EL element; the power line is electrically connected to the fifth transistor through the seventh transistor; the gate of the seventh transistor is electrically connected to one of the source or drain of the third transistor; the first circuit comprises an eighth transistor; the first signal comprises a signal output by the second clock signal through the eighth transistor; the second circuit comprises a ninth transistor; the second signal comprises a signal output by the third clock signal through the ninth transistor; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have the same polarity. Another aspect of the present invention relates to a display device comprising: a pixel, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a capacitor; and an organic electroluminescent element; a first pulse output circuit; a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; an eleventh transistor; and a twelfth transistor; and a second pulse output circuit; a thirteenth transistor; a fourteenth transistor; a fifteenth transistor; and a sixteenth transistor, wherein the gate of the first transistor is electrically connected to the capacitor, wherein one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, and wherein the other of the source and the drain of the second transistor is electrically connected to to one of the source and drain of the first transistor, wherein one of the source and drain of the third transistor is electrically connected to a signal line, wherein the other of the source and drain of the third transistor is electrically connected to the other of the source and drain of the first transistor, wherein one of the source and drain of the fourth transistor is electrically connected to a power supply line, wherein the other of the source and drain of the fourth transistor is electrically connected to the one of the source and drain of the first transistor, wherein one of the source and drain of the fifth transistor is electrically connected to the organic electroluminescent element, wherein the other of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the first transistor, wherein the One of the source and drain of the sixth transistor is electrically connected to the organic electroluminescent element, wherein the gate of the second transistor is electrically connected to the first scan line, wherein the gate of the third transistor is electrically connected to the first scan line, wherein the first pulse output circuit is electrically connected to the first scan line, wherein the gate of the fourth transistor is electrically connected to the second scan line, wherein the gate of the fifth transistor is electrically connected to the second scan line, wherein the second pulse output circuit is electrically connected to the second scan line, wherein one of the source and drain of the seventh transistor is electrically connected to the first scan line, wherein one of the source and drain of the eighth transistor is electrically connected to the first scan line, wherein one of the source and drain of the ninth transistor is electrically connected to the gate of the seventh transistor, wherein one of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the ninth transistor, wherein one of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the ninth transistor, wherein the other of the source and the drain of the eleventh transistor is electrically connected to the other of the source and the drain of the eighth transistor, wherein the gate of the eleventh transistor is electrically connected to the gate of the eighth transistor, wherein one of the source and the drain of the twelfth transistor is electrically connected to the gate of the eighth transistor, wherein the other of the source and the drain of the twelfth transistor has the same potential as the gate of the ninth transistor,One of the source and drain of the thirteenth transistor is electrically connected to the second scan line, one of the source and drain of the fourteenth transistor is electrically connected to the second scan line, one of the source and drain of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor, one of the source and drain of the sixteenth transistor is electrically connected to the gate of the thirteenth transistor, and the other of the source and drain of the sixteenth transistor has the same potential as the other of the source and drain of the fourteenth transistor. Another aspect of the present invention relates to a display device comprising: a pixel, comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a capacitor; and an organic electroluminescent element; a first pulse output circuit; a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; an eleventh transistor; and a twelfth transistor; and a second pulse output circuit; a thirteenth transistor; a fourteenth transistor; a fifteenth transistor; and a sixteenth transistor, wherein the gate of the first transistor is electrically connected to the capacitor, wherein one of the source and the drain of the second transistor is electrically connected to the gate of the first transistor, and wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the first transistor. is electrically connected to one of the source and drain of the first transistor, wherein one of the source and drain of the third transistor is electrically connected to a signal line, wherein the other of the source and drain of the third transistor is electrically connected to the other of the source and drain of the first transistor, wherein one of the source and drain of the fourth transistor is electrically connected to a power supply line, wherein the other of the source and drain of the fourth transistor is electrically connected to the one of the source and drain of the first transistor, wherein one of the source and drain of the fifth transistor is electrically connected to the organic electroluminescent element, wherein the other of the source and drain of the fifth transistor is electrically connected to the one of the source and drain of the first transistor. the other, wherein one of the source and drain of the sixth transistor is electrically connected to the organic electroluminescent element, wherein the gate of the second transistor is electrically connected to a first scan line, wherein the gate of the third transistor is electrically connected to the first scan line, wherein the first pulse output circuit is electrically connected to the first scan line, wherein the gate of the fourth transistor is electrically connected to a second scan line, wherein the gate of the fifth transistor is electrically connected to the second scan line, wherein the second pulse output circuit is electrically connected to the second scan line, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor includes a channel formation region containing silicon, wherein the source of the seventh transistor One of the source and drain of the eighth transistor is electrically connected to the first scan line, wherein one of the source and drain of the ninth transistor is electrically connected to the gate of the seventh transistor, wherein one of the source and drain of the tenth transistor is electrically connected to the other of the source and drain of the ninth transistor, wherein one of the source and drain of the eleventh transistor is electrically connected to the other of the source and drain of the ninth transistor, wherein the other of the source and drain of the eleventh transistor is electrically connected to the other of the source and drain of the eighth transistor, and wherein the gate of the eleventh transistor is electrically connected to the gate of the eighth transistor.One of the source and drain of the twelfth transistor is electrically connected to the gate of the eighth transistor, the other of the source and drain of the twelfth transistor has the same potential as the gate of the ninth transistor, one of the source and drain of the thirteenth transistor is electrically connected to the second scan line, one of the source and drain of the fourteenth transistor is electrically connected to the second scan line, one of the source and drain of the fifteenth transistor is electrically connected to the gate of the thirteenth transistor, one of the source and drain of the sixteenth transistor is electrically connected to the gate of the thirteenth transistor, and the other of the source and drain of the sixteenth transistor has the same potential as the other of the source and drain of the fourteenth transistor. Another aspect of the present invention relates to a display device comprising: a pixel comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first capacitor; and an organic electroluminescent element; and a scan line driver circuit comprising: a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; an eleventh transistor; a twelfth transistor; a thirteenth transistor; and a second capacitor, wherein the gate of the first transistor is electrically connected to the first gate of the first capacitor, wherein the second gate of the first capacitor is electrically connected to the organic electroluminescent element, wherein the source and drain of the second transistor are electrically connected to each other. One of the source and drain of the fourth transistor is electrically connected to a power supply line, wherein the other of the source and drain of the fourth transistor is electrically connected to the source and drain of the first transistor, wherein the first transistor and the second transistor are connected to the gate of the first transistor, wherein the other of the source and drain of the second transistor is electrically connected to the source and drain of the first transistor, wherein the third transistor and the source and drain of the fourth transistor are electrically connected to the signal line, wherein the other of the source and drain of the third transistor is electrically connected to the source and drain of the first transistor, wherein the fourth transistor and the source and drain of the fourth transistor are ... One of the source and drain of the five transistors is electrically connected to the organic electroluminescent element, wherein the other of the source and drain of the fifth transistor is electrically connected to the other of the source and drain of the first transistor, wherein one of the source and drain of the sixth transistor is electrically connected to the organic electroluminescent element, wherein the gate of the fourth transistor is electrically connected to a scan line, wherein one of the source and drain of the seventh transistor is electrically connected to the scan line, wherein one of the source and drain of the eighth transistor is electrically connected to the scan line, wherein the first gate of the second capacitor is electrically connected to the source and drain of the seventh transistor. wherein the second gate of the second capacitor is electrically connected to the gate of the seventh transistor, wherein one of the source and the drain of the ninth transistor is electrically connected to the gate of the seventh transistor, wherein the other of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor, wherein one of the source and the drain of the eleventh transistor is electrically connected to the gate of the eighth transistor, wherein one of the source and the drain of the twelfth transistor is electrically connected to the gate of the eighth transistor, and wherein one of the source and the drain of the thirteenth transistor is electrically connected to the gate of the eleventh transistor. Another aspect of the present invention relates to a display device comprising: a pixel comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first capacitor; and an organic electroluminescent element; and a scan line driver circuit comprising: a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; an eleventh transistor; a twelfth transistor; a thirteenth transistor; and a second capacitor, wherein a gate of the first transistor is electrically connected to a first gate of the first capacitor, wherein a second gate of the first capacitor is electrically connected to the organic electroluminescent element, and wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor. wherein the other of the source and the drain of the second transistor is electrically connected to one of the source and the drain of the first transistor, wherein one of the source and the drain of the third transistor is electrically connected to a signal line, wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein one of the source and the drain of the fourth transistor is electrically connected to a power supply line, wherein the other of the source and the drain of the fourth transistor is electrically connected to the one of the source and the drain of the first transistor, wherein one of the source and the drain of the fifth transistor is electrically connected to the organic electroluminescent element, wherein the source and the drain of the fifth transistor are ... The other of the drains is electrically connected to the source and the other of the drains of the first transistor, wherein one of the source and the drain of the sixth transistor is electrically connected to the organic electroluminescent element, wherein the gate of the fourth transistor is electrically connected to the scan line, wherein one of the source and the drain of the seventh transistor is electrically connected to the scan line, wherein one of the source and the drain of the eighth transistor is electrically connected to the scan line, wherein the first gate of the second capacitor is electrically connected to the one of the source and the drain of the seventh transistor, wherein the second gate of the second capacitor is electrically connected to the gate of the seventh transistor, wherein one of the source and the drain of the ninth transistor is electrically connected to the seventh transistor wherein the other of the source and the drain of the ninth transistor is electrically connected to one of the source and the drain of the tenth transistor, wherein one of the source and the drain of the eleventh transistor is electrically connected to the gate of the eighth transistor, wherein one of the source and the drain of the twelfth transistor is electrically connected to the gate of the eighth transistor, wherein one of the source and the drain of the thirteenth transistor is electrically connected to the gate of the eleventh transistor, wherein a shift pulse is input to the gate of the thirteenth transistor, wherein a clock signal is input to the gate of the tenth transistor, and wherein a power supply potential is supplied to the gate of the ninth transistor and the other of the source and the drain of the seventh transistor. Another embodiment of the present invention is a display device, wherein the scan line driver circuit in the display device includes a pulse output circuit and an inverted pulse output circuit, wherein the inverted pulse output circuit includes the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor, and wherein the pulse output circuit includes the eleventh transistor, the twelfth transistor, and the thirteenth transistor. Another embodiment of the present invention is a display device, wherein the inverted pulse output circuit in the above display device further includes a fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the gate of the eighth transistor, and wherein one of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the ninth transistor. Another aspect of the present invention relates to a display device, comprising: a driving circuit and a pixel; the driving circuit comprising a first pulse output circuit and a second pulse output circuit; the first pulse output circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor; one of the source or drain of the first transistor is electrically connected to a first wiring; the other of the source or drain of the first transistor is electrically connected to a second wiring; the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor; the other of the source or drain of the second transistor is electrically connected to one of the source or drain of the second transistor. The first wiring has a first potential input; the third wiring has a second potential input; the fourth wiring has a first signal input; the fifth wiring has a clock signal input; the pixel includes a fifth transistor, a sixth transistor, and a sixth transistor. a transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a capacitor, and an EL element; one of the source or the drain of the fifth transistor is electrically connected to the EL element; one of the source or the drain of the fifth transistor is electrically connected to one of the source or the drain of the sixth transistor; the other of the source or the drain of the fifth transistor is electrically connected to one of the source or the drain of the seventh transistor; the other of the source or the drain of the fifth transistor is electrically connected to one of the source or the drain of the eighth transistor; the gate of the fifth transistor is electrically connected to the second wiring. The gate of the seventh transistor is electrically connected to the sixth wiring; the other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor; the other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the tenth transistor; the gate of the eighth transistor is electrically connected to the capacitor; the gate of the ninth transistor is electrically connected to the sixth wiring; the other of the source or drain of the tenth transistor is electrically connected to the seventh wiring; the gate of the tenth transistor is electrically connected to the second wiring; the sixth wiring is electrically connected to the second pulse output circuit; and a power supply potential is input to the seventh wiring. Simple diagram description Figure 1 depicts an example configuration of the display device; FIG2A depicts an example configuration of a scan line driver circuit, FIG2B depicts examples of waveforms of various signals, FIG2C depicts terminals of a pulse output circuit, and FIG2D depicts terminals of an inverted pulse output circuit; FIG. 3A depicts an example configuration of a pulse output circuit, FIG. 3B depicts an example operation thereof, FIG. 3C depicts an example configuration of an inverted pulse output circuit, and FIG. 3D depicts an example operation thereof; FIG. 4A depicts an example of a pixel configuration, and FIG. 4B depicts an example of its operation; Figure 5 depicts a variation of the scan line driver circuit; FIG. 6A depicts a variation of a scan line driver circuit, and FIG. 6B depicts examples of waveforms of various signals; Figure 7 depicts a variation of the scan line driver circuit; Figures 8A and 8B depict variations of the scan line driver circuit; Figures 9A and 9B depict variations of the scan line driver circuit; Figures 10A to 10C depict variations of the inverted pulse output circuit; Figures 11A to 11D are cross-sectional views illustrating specific examples of transistors; Figures 12A to 12D are cross-sectional views illustrating specific examples of transistors; Figures 13A and 13B are top views illustrating a specific example of a transistor; and 14A to 14F each depict an example of an electronic device. Implementation Method Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to the following description, and those skilled in the art will readily appreciate that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be limited to the following description of the embodiments. First, a configuration example of a display device according to an embodiment of the present invention will be described with reference to FIG. 1 , FIG. 2A to FIG. 2D , FIG. 3A to FIG. 3D , and FIG. 4A and FIG. 4B . [Configuration example of display device] FIG1 depicts an example configuration of a display device. The display device in FIG1 includes a plurality of pixels 10 arranged in m columns and n rows; a scan line driver circuit 1; a signal line driver circuit 2; a current source 3; m scan lines 4 and m inverted scan lines 5, each electrically connected to a column of pixels 10 and having its potential controlled by the scan line driver circuit 1; n signal lines 6, each electrically connected to a row of pixels 10 and having its potential controlled by the signal line driver circuit 2; and a power supply line 7 having a plurality of branch lines and electrically connected to the current source 3. [Configuration Example of Scan Line Driver Circuit] FIG2A illustrates an example configuration of a scan line driver circuit 1 included in the display device of FIG1. The scan line driver circuit 1 in FIG2A includes wiring for supplying first to fourth clock signals (GCK1 to GCK4) to the scan line driver circuit; wiring for supplying first to fourth pulse width control signals (PWC1 to PWC4); first to mth pulse output circuits 20_1 to 20_m electrically connected to pixels 10 arranged in the first to mth rows via scan lines 4_1 to 4_m; and first to mth inverted pulse output circuits 60_1 to 60_m electrically connected to pixels 10 arranged in the first to mth rows via inverted scan lines 5_1 to 5_m. The first through m-th pulse output circuits 20_1 through 20_m are configured to sequentially output shift pulses during each shift cycle in response to a starting pulse (GSP) for the scan line driver circuit input into the first pulse output circuit 20_1. Specifically, after receiving the starting pulse (GSP) for the scan line driver circuit, the first pulse output circuit 20_1 outputs a shift pulse to the second pulse output circuit 20_2 throughout the entire shift cycle. Subsequently, after receiving the shift pulse output from the first pulse output circuit into the second pulse output circuit 20_2, the second pulse output circuit 20_2 outputs a shift pulse to the third pulse output circuit 20_3 throughout the entire shift cycle. This process is repeated until a shift pulse is input into the m-th pulse output circuit 20_m. Furthermore, the first to mth pulse output circuits 20_1 to 20_m have the function of outputting selection signals to respective scan lines when a shift pulse is input. Note that the selection signal is a signal used to turn on a switch, and the on / off state of the switch is controlled by the potential of the scan line. FIG. 2B illustrates an example of a specific waveform of the aforementioned signal. In particular, the first clock signal (GCK1) for the scan line driver circuit in FIG. 2B periodically alternates between a high level potential (high power supply potential (Vdd)) and a low level potential (low power supply potential (Vss)) and has a duty cycle of approximately 1 / 4. The second clock signal (GCK2) for the scan line driver circuit has a phase shifted by 1 / 4 cycle from the first clock signal (GCK1) for the scan line driver circuit; the third clock signal (GCK3) for the scan line driver circuit has a phase shifted by 1 / 2 cycle from the first clock signal (GCK1) for the scan line driver circuit; and the fourth clock signal (GCK4) for the scan line driver circuit has a phase shifted by 3 / 4 cycle from the first clock signal (GCK1) for the scan line driver circuit. Furthermore, the potential of the first pulse width control signal (PWC1) becomes a high level potential before the potential of the first clock signal (GCK1) for the scan line driver circuit becomes a high level potential, and becomes a low level potential during a period when the potential of the first clock signal (GCK1) for the scan line driver circuit is a high level potential, and the first pulse width control signal (PWC1) has a duty cycle of less than 1 / 4. The second pulse width control signal (PWC2) has a phase shifted from the first pulse width control signal (PWC1) by 1 / 4 cycle; the third pulse width control signal (PWC3) has a phase shifted from the first pulse width control signal (PWC1) by 1 / 2 cycle; and the fourth pulse width control signal (PWC4) has a phase shifted from the first pulse width control signal (PWC1) by 3 / 4 cycle. In the display device shown in FIG2A, the same configuration can be applied to the first through mth pulse output circuits 20_1 through 20_m. Note that the electrical connections between the multiple terminals included in the pulse output circuits vary depending on the pulse output circuit. The specific connections will be described with reference to FIG2A and FIG2C. Each of the first to mth pulse output circuits 20_1 to 20_m has terminals 21 to 27. Terminals 21 to 24 and terminal 26 are input terminals, and terminals 25 and 27 are output terminals. First, let's describe terminal 21. Terminal 21 of the first pulse output circuit 20_1 is electrically connected to a wiring used to supply a starting pulse (GSP) to the scan line driver circuit. Terminals 21 of the second through mth pulse output circuits 20_2 through 20_m are electrically connected to respective terminals 27 of their respective preceding pulse output circuits. Next, terminal 22 will be described. Terminal 22 (a is a natural number less than or equal to m / 4) of the (4a-3) pulse output circuit is electrically connected to a wiring for supplying a first clock signal (GCK1) to the scan line driver circuit. Terminal 22 of the (4a-2) pulse output circuit is electrically connected to a wiring for supplying a second clock signal (GCK2) to the scan line driver circuit. Terminal 22 of the (4a-1) pulse output circuit is electrically connected to a wiring for supplying a third clock signal (GCK3) to the scan line driver circuit. Terminal 22 of the 4a pulse output circuit is electrically connected to a wiring for supplying a fourth clock signal (GCK4) to the scan line driver circuit. Next, terminal 23 will be described. Terminal 23 of the (4a-3) pulse output circuit is electrically connected to a wiring for supplying a second clock signal (GCK2) to the scan line driver circuit. Terminal 23 of the (4a-2) pulse output circuit is electrically connected to a wiring for supplying a third clock signal (GCK3) to the scan line driver circuit. Terminal 23 of the (4a-1) pulse output circuit is electrically connected to a wiring for supplying a fourth clock signal (GCK4) to the scan line driver circuit. Terminal 23 of the 4a pulse output circuit is electrically connected to a wiring for supplying a first clock signal (GCK1) to the scan line driver circuit. Next, terminal 24 will be described. Terminal 24 of the (4a-3) pulse output circuit is electrically connected to a wiring for supplying a first pulse width control signal (PWC1). Terminal 24 of the (4a-2) pulse output circuit is electrically connected to a wiring for supplying a second pulse width control signal (PWC2). Terminal 24 of the (4a-1) pulse output circuit is electrically connected to a wiring for supplying a third pulse width control signal (PWC3). Terminal 24 of the 4a pulse output circuit is electrically connected to a wiring for supplying a fourth pulse width control signal (PWC4). Next, the terminal 25 will be described. The terminal 25 of the x-th pulse output circuit (x is a natural number less than or equal to m) is electrically connected to the scan line 4_x in the x-th column. Next, terminal 26 will be described. Terminal 26 of the yth pulse output circuit (y is a natural number less than or equal to (m-1)) is electrically connected to terminal 27 of the (y+1)th pulse output circuit. Terminal 26 of the mth pulse output circuit is electrically connected to wiring for supplying a stop signal (STP) to the mth pulse output circuit. In the case where the (m+1)th pulse output circuit is provided, the stop signal (STP) for the mth pulse output circuit corresponds to the signal from terminal 27 of the (m+1)th pulse output circuit. Specifically, the stop signal (STP) for the mth pulse output circuit can be supplied to the mth pulse output circuit by providing the (m+1)th pulse output circuit as a dummy circuit or by directly inputting the signal from an external source. The connection relationship of the terminal 27 in each of the pulse output circuits has been described above. Therefore, the above description will be cited. In the display device shown in FIG2A, the same configuration can be applied to the first through mth inverted pulse output circuits 60_1 through 60_m. However, the electrical connection relationship of the plurality of terminals included in the inverted pulse output circuit will vary depending on the inverted pulse output circuit. The specific connection relationship will be described with reference to FIG2A and FIG2D. Each of the first to mth inverted pulse output circuits 60_1 to 60_m has terminals 61 to 63. Terminals 61 and 62 are input terminals, and terminal 63 is an output terminal. First, terminal 61 will be described. Terminal 61 of the (4a-3) inverted pulse output circuit is electrically connected to a wiring for supplying a second clock signal (GCK2) to the scan line driver circuit. Terminal 61 of the (4a-2) inverted pulse output circuit is electrically connected to a wiring for supplying a third clock signal (GCK3) to the scan line driver circuit. Terminal 61 of the (4a-1) inverted pulse output circuit is electrically connected to a wiring for supplying a fourth clock signal (GCK4) to the scan line driver circuit. Terminal 61 of the 4a inverted pulse output circuit is electrically connected to a wiring for supplying a first clock signal (GCK1) to the scan line driver circuit. Next, the terminal 62 will be described. The terminal 62 of the xth inverted pulse output circuit is electrically connected to the terminal 27 of the xth pulse output circuit. Next, the terminal 63 will be described. The terminal 63 of the x-th inverted pulse output circuit is electrically connected to the inverted scan line 5_x in the x-th column. [Configuration example of pulse output circuit] FIG3A shows an example of a configuration of the pulse output circuit shown in FIG2A and FIG2C. The pulse output circuit shown in FIG3A includes transistors 31 to 39. One of the source and drain of the transistor 31 is electrically connected to a wiring supplying a high power supply potential (Vdd) (hereinafter also referred to as a high power supply potential line); and the gate of the transistor 31 is electrically connected to the terminal 21. One of the source and drain of transistor 32 is electrically connected to a wiring for supplying a low power supply potential (Vss) (hereinafter also referred to as a low power supply potential line); and the other of the source and drain of transistor 32 is electrically connected to the other of the source and drain of transistor 31. One of the source and drain of transistor 33 is electrically connected to terminal 22; the other of the source and drain of transistor 33 is electrically connected to terminal 27; and the gate of transistor 33 is electrically connected to the other of the source and drain of transistor 31 and the other of the source and drain of transistor 32. One of the source and drain of transistor 34 is electrically connected to the low power supply potential line; the other of the source and drain of transistor 34 is electrically connected to terminal 27; and the gate of transistor 34 is electrically connected to the gate of transistor 32. One of the source and drain of transistor 35 is electrically connected to the low power supply potential line; the other of the source and drain of transistor 35 is electrically connected to the gate of transistor 32 and the gate of transistor 34; and the gate of transistor 35 is electrically connected to terminal 21. One of the source and drain of transistor 36 is electrically connected to the high power supply potential line; the other of the source and drain of transistor 36 is electrically connected to the gate of transistor 32, the gate of transistor 34, and the other of the source and drain of transistor 35; and the gate of transistor 36 is electrically connected to terminal 26. One of the source and drain of transistor 37 is electrically connected to the high power supply potential line; the other of the source and drain of transistor 37 is electrically connected to the gate of transistor 32, the gate of transistor 34, the other of the source and drain of transistor 35, and the other of the source and drain of transistor 36; and the gate of transistor 37 is electrically connected to terminal 23. One of the source and drain of transistor 38 is electrically connected to terminal 24; the other of the source and drain of transistor 38 is electrically connected to terminal 25; and the gate of transistor 38 is electrically connected to the other of the source and drain of transistor 31, the other of the source and drain of transistor 32, and the gate of transistor 33. One of the source and drain of transistor 39 is electrically connected to the low power supply potential line; one of the source and drain of transistor 39 is electrically connected to terminal 25; and the gate of transistor 39 is electrically connected to the gate of transistor 32, the gate of transistor 34, the other of the source and drain of transistor 35, the other of the source and drain of transistor 36, and the other of the source and drain of transistor 37. Note that in the following description, the node electrically connected to the other of the source and drain of transistor 31, the other of the source and drain of transistor 32, the gate of transistor 33, and the gate of transistor 38 is referred to as node A. Furthermore, the node electrically connected to the gate of transistor 32, the gate of transistor 34, the other of the source and drain of transistor 35, the other of the source and drain of transistor 36, the other of the source and drain of transistor 37, and the gate of transistor 39 is referred to as node B. [Operation Example of Pulse Output Circuit] An example of the operation of the aforementioned pulse output circuit will be described with reference to FIG3B. Specifically, FIG3B depicts the signals input to individual terminals of the second pulse output circuit 20_2, the potentials of the signals output from these individual terminals, and the potentials of nodes A and B when a shift pulse is input from the first pulse output circuit 20_1. Furthermore, FIG3B depicts the signal (Gout3) output from terminal 25 of the third pulse output circuit 20_3, and the signal (SRout3) output from its terminal 27 (the signal input to terminal 26 of the second pulse output circuit 20_2). Note that in FIG3B, Gout represents the signal output from any of the pulse output circuits to the corresponding scan line, and SRout represents the signal output from any of the pulse output circuits to the subsequent-stage pulse output circuit. First, referring to FIG. 3B , the case where the shift pulse is input from the first pulse output circuit 20_1 to the second pulse output circuit 20_2 will be described. During period t1, a high potential (high power supply potential (Vdd)) is input to terminal 21. Therefore, transistors 31 and 35 are turned on. As a result, the potential at node A increases to a high potential (a potential reduced from the high power supply potential (Vdd) by the threshold voltage of transistor 31), and the potential at node B decreases to the low power supply potential (Vss). Consequently, transistors 33 and 38 turn on, and transistors 32, 34, and 39 turn off. As can be seen from the above, during period t1, the signal output from terminal 27 is input to terminal 22, and the signal output from terminal 25 is input to terminal 24. Here, during period t1, both the signal input to terminal 22 and the signal input to terminal 24 are at a low potential (low power supply potential (Vss)). Therefore, in period t1, the second pulse output circuit 20_2 outputs a low-level potential (low power supply potential (Vss)) to the terminal 21 of the third pulse output circuit 20_3 and to the scan line in the second column of the pixel portion. In period t2, the levels of the signals input to these terminals do not change from those in period t1. Therefore, the potentials of the signals output from terminals 25 and 27 do not change; low-level potentials (low power supply potential (Vss)) are output therefrom. During period t3, a high potential (high power supply potential (Vdd)) is input to terminal 24. Note that the potential at node A (the source of transistor 31) increased to a high potential (a potential obtained by reducing the threshold voltage of transistor 31 from the high power supply potential (Vdd)) during period t1. Consequently, transistor 31 is turned off. At this time, the input of the high potential (high power supply potential (Vdd)) to terminal 24 further increases the potential at node A (the gate of transistor 38) by utilizing capacitive coupling between the gate and source of transistor 38 (bootstrapping). Due to this bootstrapping, the potential of the signal output from terminal 25 does not decrease from the high potential (high power supply potential (Vdd)) input to terminal 24. Therefore, during period t3, the second pulse output circuit 20_2 outputs a high potential (high power supply potential (Vdd)) (select signal) to the scan line in the second row of the pixel portion. During period t4, a high-level potential (high power supply potential (Vdd)) is input to terminal 22. As a result, because the potential of node A has already increased due to bootstrapping, the potential of the signal output from terminal 27 does not decrease from the high-level potential (high power supply potential (Vdd)) input to terminal 22. Therefore, during period t4, terminal 27 outputs the high-level potential (high power supply potential (Vdd)) input to terminal 22. In other words, the second pulse output circuit 20_2 outputs a high-level potential (high power supply potential (Vdd)) (shift pulse) to terminal 21 of the third pulse output circuit 20_3. During period t4, the potential of the signal input to terminal 24 remains at a high-level potential (high power supply potential (Vdd)), causing the potential of the signal output from the second pulse output circuit 20_2 to the scan line in the second column of the pixel portion to remain at a high-level potential (high power supply potential (Vdd)) (select signal). Furthermore, a low potential (low power supply potential (Vss)) is input to the terminal 21 to turn off the transistor 35, which does not directly affect the signal output from the second pulse output circuit 20_2 in the period t4. During period t5, a low potential (low power supply potential (Vss)) is input to terminal 24. During this period, transistor 38 remains on. Therefore, during period t5, first pulse output circuit 20_1 outputs a low potential (low power supply potential (Vss)) to the scan line in the second row of the pixel portion. During period t6, the levels of the signals input to these terminals do not change from those during period t5. Therefore, the potentials of the signals output from terminals 25 and 27 do not change either: a low potential (low power supply potential (Vss)) is output from terminal 25, and a high potential (high power supply potential (Vdd) = shift pulse) is output from terminal 27. During period t7, a high potential (high power supply potential (Vdd)) is input to terminal 23. Therefore, transistor 37 turns on. Consequently, the potential at node B increases to a high potential (a potential reduced from the high power supply potential (Vdd) by the threshold voltage of transistor 37), turning on transistors 32, 34, and 39. Consequently, the potential at node A decreases to a low potential (low power supply potential (Vss)), turning off transistors 33 and 38. As can be seen from the above, during period t7, the signals output from terminals 25 and 27 are both at the low power supply potential (Vss). In other words, during period t7, the second pulse output circuit 20_2 outputs the low power supply potential (Vss) to terminal 21 of the third pulse output circuit 20_3 and the scan line in the second column of the pixel portion. [Configuration example of reverse pulse output circuit] FIG3C shows an example of a configuration of the inverted pulse output circuit shown in FIG2A and FIG2D. The inverted pulse output circuit shown in FIG3C includes transistors 71 to 74. One of the source and the drain of the transistor 71 is electrically connected to the high power supply potential line; and the gate of the transistor 71 is electrically connected to the terminal 61. One of the source and drain of transistor 72 is electrically connected to the low power supply potential line; the other of the source and drain of transistor 72 is electrically connected to one of the source and drain of transistor 71; and the gate of transistor 72 is electrically connected to terminal 62. One of the source and drain of transistor 73 is electrically connected to the high power supply potential line; the other of the source and drain of transistor 73 is electrically connected to terminal 63; and the gate of transistor 73 is electrically connected to the other of the source and drain of transistor 71 and the other of the source and drain of transistor 72. One of the source and drain of transistor 74 is electrically connected to the low power supply potential line; the other of the source and drain of transistor 74 is electrically connected to terminal 63; and the gate of transistor 74 is electrically connected to terminal 62. Note that in the following description, a node electrically connected to the other of the source and drain of transistor 71, the other of the source and drain of transistor 72, and the gate of transistor 73 is referred to as node C. [Operation Example of Inverted Pulse Output Circuit] An example of the operation of the inverted pulse output circuit will be described with reference to FIG3D. Specifically, FIG3D depicts the signal input to the second inverted pulse output circuit 20_2, the potential of the signal output therefrom, and the potential of node C during periods t1 to t7 in FIG3B. Note that in FIG3D, the signals input to these terminals are each shown in parentheses. Furthermore, in FIG3D, GBout represents the signal input to any of the inverted scan lines of the inverted pulse output circuit. During periods t1 to t3, a low potential is input to terminals 61 and 62. Therefore, transistors 71, 72, and 74 are off. Consequently, the potential at node C remains at a high potential. Consequently, transistor 73 is on. The potential at node C is higher than the sum of the high power supply potential (Vdd) and the threshold voltage of transistor 73 due to capacitive coupling (bootstrapping) between the gate and source of transistor 73 (the other of the source and drain electrically connected to terminal 63 during periods t1 to t3). As can be seen from the above, during periods t1 to t3, the potential of the signal output from terminal 63 is the high power supply potential (Vdd). That is, during periods t1 to t3, the second inverted pulse output circuit 60_2 outputs the high power supply potential (Vdd) to the inverted scan line in the second row of the pixel portion. During period t4, a high potential (high power supply potential (Vdd)) is input to terminal 62. Consequently, transistors 72 and 74 turn on. Consequently, the potential at node C decreases to a low potential (low power supply potential (Vss)), turning off transistor 73. As can be seen from the above, during period t4, the potential of the signal output from terminal 63 becomes the low power supply potential (Vss). That is, during period t4, the second inverted pulse output circuit 60_2 outputs the low power supply potential (Vss) to the inverted scan line in the second column of the pixel portion. In periods t5 and t6, the levels of the signals input to these terminals do not change from those in period t4. Therefore, the potential of the signal output from terminal 63 does not change; a low-level potential (low power supply potential (Vss)) is output. During period t7, a high potential (high power supply potential (Vdd)) is input to terminal 61, and a low potential (low power supply potential (Vss)) is input to terminal 62. Consequently, transistor 71 turns on, while transistors 72 and 74 turn off. Consequently, the potential at node C decreases to a high potential (the high power supply potential (Vdd) decreases by the threshold voltage of transistor 71), turning on transistor 73. Furthermore, the potential at node C is raised above the sum of the high power supply potential (Vdd) and the threshold voltage of transistor 73 by utilizing capacitive coupling (bootstrapping) between the gate and source of transistor 73. As can be seen from the above, during period t7, the potential of the signal output from terminal 63 becomes the high power supply potential (Vdd). That is, during period t7, the second inverted pulse output circuit 60_2 outputs the high power supply potential (Vdd) to the inverted scan line in the second column of the pixel portion. [Pixel configuration example] FIG4A is a circuit diagram illustrating an example configuration of pixel 10 in FIG1. Pixel 10 in FIG4A includes transistors 11 to 16, capacitor 17, and element 18 comprising an organic material that emits light when excited by a current flowing between a pair of electrodes (hereinafter also referred to as an organic electroluminescent (EL) element). One of the source and the drain of the transistor 11 is electrically connected to the signal line 6 ; and the gate of the transistor 11 is electrically connected to the scan line 4 . One of the source and drain of the transistor 12 is electrically connected to a wiring for supplying a common potential, and the gate of the transistor 12 is connected to the scan line 4. Note that the common potential here is lower than the potential given to the power supply line 7. The gate of the transistor 13 is electrically connected to the scan line 4 . One of the source and drain of transistor 14 is electrically connected to the power supply line 7; the other of the source and drain of transistor 14 is electrically connected to one of the source and drain of transistor 13; and the gate of transistor 14 is electrically connected to the inverting scan line 5. One of the source and drain of transistor 15 is electrically connected to the one of the source and drain of transistor 13 and the other of the source and drain of transistor 14; the other of the source and drain of transistor 15 is electrically connected to the other of the source and drain of transistor 11; and the gate of transistor 15 is electrically connected to the other of the source and drain of transistor 13. One of the source and drain of transistor 16 is electrically connected to the other of the source and drain of transistor 11 and the other of the source and drain of transistor 15; the other of the source and drain of transistor 16 is electrically connected to the other of the source and drain of transistor 12; and the gate of transistor 16 is electrically connected to the inverting scan line 5. One electrode of capacitor 17 is electrically connected to the other of the source and drain of transistor 13 and the gate of transistor 15; the other electrode of capacitor 17 is electrically connected to the other of the source and drain of transistor 12 and the other of the source and drain of transistor 16. The anode of organic EL element 18 is electrically connected to the other of the source and drain of transistor 12, the other of the source and drain of transistor 16, and the other electrode of capacitor 17. The cathode of organic EL element 18 is electrically connected to the wiring for supplying a common potential. Note that the common potential given to the wiring electrically connected to one of the source and drain of transistor 12 may be different from the common potential given to the cathode of organic EL element 18. Hereinafter, the node electrically connected to the other of the source and drain of transistor 13, the gate of transistor 15, and the one electrode of capacitor 17 is referred to as node D. The node electrically connected to one of the source and drain of transistor 13, the other of the source and drain of transistor 14, and the one of the source and drain of transistor 15 is referred to as node E. The node electrically connected to the other of the source and drain of transistor 11, the other of the source and drain of transistor 15, and the one of the source and drain of transistor 16 is referred to as node F. The node electrically connected to the other of the source and drain of transistor 12, the other of the source and drain of transistor 16, the other electrode of capacitor 17, and the anode of organic EL element 18 is referred to as node G. [Pixel Operation Example] An example of the pixel operation described above will be described with reference to FIG4B. Specifically, FIG4B depicts the potentials of scan line 4_2 and inverted scan line 5_2 arranged in the second column of the pixel portion during periods t1 to t7 in FIG3B and FIG3D, as well as the image signal input to signal line 6. In FIG4B, the signals input to the wiring are each shown in parentheses. Furthermore, in FIG4B, "DATA" represents the image signal. During periods t1 and t2, the select signal is not input to scan line 4_2, and the select signal is input to the inverted scan line 5_2. Consequently, transistors 11, 12, and 13 are off, and transistors 14 and 16 are on. Consequently, a current corresponding to the gate potential of transistor 15 (the potential of node D) is supplied from the power supply line to organic EL element 18. In other words, pixel 10 displays an image based on the image signal held in capacitor 17. Note that during periods t1 and t2, the image signal (data_1) for the pixels arranged in the first row is input from signal line driver circuit 2 to signal line 6. During period t3, a selection signal is input to scan line 4_2. Consequently, transistors 11, 12, and 13 are turned on, resulting in a short circuit between one electrode of capacitor 17 and signal line 6, and between one electrode of capacitor 17 and power supply line 7. Consequently, the image signal held in capacitor 17 is lost (initialized). During period t4, the selection signal is not input to the inverted scan line 5_2. Therefore, transistors 14 and 16 are off. Furthermore, the image signal (data_2) for the pixels arranged in the second row is input to signal line 6. Therefore, node F has a potential corresponding to the image signal (data_2). Note that during period t4, nodes D and E have a potential corresponding to the sum of the potential of the image signal (data_2) and the threshold voltage of transistor 15 (hereinafter referred to as the data potential). This is because when nodes D and E have a potential higher than the data potential, transistor 15 turns on, and the potentials of nodes D and E decrease to the data potential. Furthermore, even when the potential of node F changes to a potential corresponding to the image signal (data_2) after transistors 14 and 16 are turned off and transistor 15 is turned off (after nodes D and E have a potential equal to the sum of the potential of node F and the threshold voltage of transistor 15), the potential of node D changes due to the capacitive coupling between nodes D and F. Therefore, in this case, the potentials of nodes D and E also decrease to the data potential. In period t4, due to the short circuit between the node G and the wiring for supplying the common potential through the transistor 12, the potential of the node G becomes the common potential. Therefore, in period t4, the voltage supplied to the capacitor 17 is equal to the difference between the data potential (the potential of the node D) and the common potential (the potential of the node G). In periods t5 and t6, the selection signal is not input to the scan line 4_2. Therefore, the transistors 11, 12, and 13 are turned off. During period t7, a select signal is input to the inverted scan line 5_2. Consequently, transistors 14 and 16 are turned on. It is known that the drain current in the saturation region of a transistor is proportional to the square of the potential difference between the transistor's threshold voltage and the voltage between the transistor's gate and source. Here, the voltage between the gate and source of transistor 15 becomes the voltage applied to capacitor 17 (the difference between the data voltage (the sum of the potential corresponding to the image signal (data_2) and the threshold voltage of transistor 15) and the common potential). Therefore, the drain current in the saturation region of transistor 15 is proportional to the square of the difference between the potential corresponding to the image signal (data_2) and the common potential. In this case, the drain current in the saturation region of transistor 15 is independent of the transistor's threshold voltage. Note that the potential of node G changes so that the same current as the current generated in transistor 15 flows to organic EL element 18. Here, when the potential of node G changes, the potential of node D changes due to capacitive coupling through capacitor 17. Therefore, even when the potential of node G changes, transistor 15 can supply a constant current to organic EL element 18. Through the above operations, the pixel 10 can display an image according to the image signal (data_2). [Display Device Disclosed in This Specification] In the display device disclosed in this specification, the operation of the inverted pulse output circuit is controlled by at least two signals. This reduces the shoot-through current generated within the inverted pulse output circuit. Furthermore, the signals used to operate the plurality of pulse output circuits are used as the two signals. This means that the inverted pulse output circuit can operate without generating additional signals. [Example of Change] The above-described display device is one embodiment of the present invention. The present invention also includes display devices having a structure different from that of the above-described display device. The following describes another embodiment of the present invention. Note that the present invention also includes display devices having any of the following multiple elements shown as examples of another embodiment of the present invention. [Variations of Display Device] As an example of a display device, a display device including an organic EL element in each pixel (hereinafter also referred to as an EL display device) has been described. However, the display device of the present invention is not limited to an EL display device. For example, the display device of the present invention may be a display device that displays images by controlling the alignment of liquid crystals (a liquid crystal display device). [Variations of Scan Line Driver Circuit] Furthermore, the configuration of the scan line driver circuit included in the display device is not limited to that shown in FIG. 2A . For example, any of the scan line driver circuits shown in FIG. 5 , FIG. 6A , and FIG. 7 may be used as the scan line driver circuit included in the display device. The scan line driver circuit 1 in FIG. 5 differs from the scan line driver circuit 1 in FIG. 2A in that terminal 61 of the y-th inverted pulse output circuit 60_y (y is a natural number less than or equal to (m-1)) is electrically connected to terminal 27 of the (y+1)-th pulse output circuit, and terminal 61 of the m-th inverted pulse output circuit 60_m is electrically connected to a wiring for supplying a stop signal (STP) to the m-th pulse output circuit. The scan line driver circuit 1 in FIG. 5 can also output signals similar to those output by the scan line driver circuit 1 in FIG. 2A to the scan lines and inverted scan lines. In the scan line driver circuit 1 of FIG. 2A , a high-level potential is input to terminal 61 of the inverted pulse output circuit with a shorter period than that of the scan line driver circuit 1 of FIG. 5 . That is, transistor 71 included in the inverted pulse output circuit is turned on during a shorter period (see FIG. 2A , 2B , and 2D , as well as FIG. 3C ). Therefore, even when the gate potential of transistor 73 included in the inverted pulse output circuit decreases due to leakage current generated in transistor 72 or the like, the potential can be increased. This reduces the probability that the inverted pulse output circuit will output a potential lower than the high power supply potential (Vdd) to the corresponding inverted scan line. On the other hand, in the scan line driver circuit 1 of FIG. 5 , the parasitic capacitance of the wiring for supplying the first to fourth clock signals (GCK1 to GCK4) of the scan line driver circuit can be lower than that of the scan line driver circuit 1 of FIG. 2A . Therefore, the scan line driver circuit 1 of FIG. 5 has lower power consumption than the scan line driver circuit 1 of FIG. 2A . The scan line driver circuit 1 in FIG. 6A differs from the scan line driver circuit 1 in FIG. 2A in that it operates with two clock signals and two pulse width control signals for the scan line driver circuit. Consequently, the connection relationship between the pulse output circuit and the inverted pulse output circuit is also different (see FIG. 6A ). In particular, the scan line driver circuit 1 in FIG. 6A includes wiring for supplying a fifth clock signal (GCK5) to the scan line driver circuit, wiring for supplying a sixth clock signal (GCK6) to the scan line driver circuit, wiring for supplying a fifth pulse width control signal (PWC5), and wiring for supplying a sixth pulse width control signal (PWC6). FIG6B illustrates an example of specific waveforms of the signals in FIG6A . The fifth clock signal (GCK5) for the scan line driver circuit in FIG6B periodically alternates between a high level (high power supply potential (Vdd)) and a low level (low power supply potential (Vss)) and has a duty cycle of approximately 1 / 2. Furthermore, the sixth clock signal (GCK6) for the scan line driver circuit has a phase shifted by 1 / 2 cycle from the fifth clock signal (GCK5) for the scan line driver circuit. The fifth pulse width control signal (PWC5) reaches a high level before the fifth clock signal (GCK5) for the scan line driver circuit reaches a high level, and reaches a low level during the period when the fifth clock signal (GCK5) for the scan line driver circuit is at a high level. The fifth pulse width control signal (PWC5) has a duty cycle of less than 1 / 2. The sixth pulse width control signal (PWC6) has a phase shifted by 1 / 2 cycle from the fifth pulse width control signal (PWC5). The scan line driver circuit 1 in FIG. 6A can also output signals similar to those output from the scan line driver circuit 1 in FIG. 2A to the scan lines and the inverted scan lines. Note that in the scan line driver circuit 1 of FIG. 2A , the parasitic capacitance of the wiring used to supply the first to fourth clock signals (GCK1 to GCK4) of the scan line driver circuit can be lower than that of the scan line driver circuit 1 of FIG. 6A . Therefore, the scan line driver circuit 1 of FIG. 2A has lower power consumption than the scan line driver circuit 1 of FIG. 6A . On the other hand, in the scan line driver circuit 1 in FIG. 6A , the number of signals necessary for the operation of the scan line driver circuit can be smaller than that in the scan line driver circuit 1 in FIG. 2A . The scan line driver circuit 1 in FIG. 7 differs from the scan line driver circuit 1 in FIG. 2A in that it operates without a pulse width control signal. Therefore, the connection relationship between the pulse output circuit and the inverted pulse output circuit is also different (see FIG. 7 ). In the scan line driver circuit 1 shown in Figure 7, the selection signal output from the pulse output circuit to the corresponding scan line is the same signal as the shift pulse output to the subsequent pulse output circuit. Therefore, the signal output from the pulse output circuit to the scan line (the potential of the scan line) and the signal output from the inverted pulse output circuit to the inverted scan line (the potential of the inverted scan line) have opposite phases. The scan line driver circuit 1 shown in Figure 7 can be used as a scan line driver circuit included in a display device. Note that in the scan line driver circuit 1 of FIG. 2A , the interval between the period for outputting the selection signal to the scan line in the y-th column and the period for outputting the selection signal to the scan line in the (y+1)-th column is wider than that in the scan line driver circuit 1 of FIG. Therefore, even when any of the first to fourth clock signals (GCK1 to GCK4) for the scan line driver circuit is delayed or has a blunted waveform, the scan line driver circuit 1 of FIG. 7 can accurately input image signals to the pixels, compared to the scan line driver circuit 1 of FIG. 6A . On the other hand, in the scan line driver circuit 1 in FIG. 7 , the number of signals necessary for the operation of the scan line driver circuit can be smaller than that in the scan line driver circuit 1 in FIG. 2A . [Example of variation of pulse output circuit] The configuration of the pulse output circuit included in the scan line driver circuit is not limited to that shown in FIG. 3A. For example, any of the pulse output circuits shown in FIG. 8A and 8B or FIG. 9A and 9B can be used as the pulse output circuit included in the scan line driver circuit. Furthermore, the pulse output circuit in FIG. 8A has a configuration in which a transistor 50 is added to the pulse output circuit in FIG. 3A . One of the source and drain of transistor 50 is electrically connected to a high power supply potential line; the other of the source and drain of transistor 50 is electrically connected to the gate of transistor 32, the gate of transistor 34, the other of the source and drain of transistor 35, the other of the source and drain of transistor 36, the other of the source and drain of transistor 37, and the gate of transistor 39; and the gate of transistor 50 is electrically connected to a reset terminal (Reset). Note that a high potential can be input to the reset terminal during the vertical flyback period of the display device, and a low potential can be input to the reset terminal during periods other than the vertical flyback period. Thus, the potentials of the respective nodes of the pulse output circuit can be initialized, thereby preventing malfunction. The pulse output circuit in FIG. 8B has a configuration in which transistor 51 is added to the pulse output circuit in FIG. 3A . One of the source and drain of transistor 51 is electrically connected to the other of the source and drain of transistor 31 and the other of the source and drain of transistor 32; the other of the source and drain of transistor 51 is electrically connected to the gate of transistor 33 and the gate of transistor 38; and the gate of transistor 51 is electrically connected to a high power supply potential line. Note that transistor 51 is turned off during periods when node A has a high potential (periods t1 to t6 in FIG. 3B ). Therefore, the configuration in which transistor 51 is added can interrupt the electrical connection between the gate of transistor 33 and the gate of transistor 38, and between the other of the source and drain of transistor 31 and the other of the source and drain of transistor 32 during periods t1 to t6. Therefore, the load during the bootstrap period in the pulse output circuit can be reduced in the period included in the period t1 to t6. The pulse output circuit in FIG. 9A has a configuration in which transistor 52 is added to the pulse output circuit in FIG. The other of the source and drain of transistor 52 is electrically connected to the gate of transistor 33 and the other of the source and drain of transistor 51; the other of the source and drain of transistor 52 is electrically connected to the gate of transistor 38; and the gate of transistor 52 is electrically connected to the high power supply potential line. In a similar manner to the above, transistor 52 can be used to reduce the load during the bootstrap period in the pulse output circuit. The pulse output circuit in Figure 9B has a configuration in which transistor 51 is removed from the pulse output circuit depicted in Figure 9A, and transistor 53 is added to the pulse output circuit depicted in Figure 9A. One of the source and drain of transistor 53 is electrically connected to the other of the source and drain of transistor 31, the other of the source and drain of transistor 32, and the source and drain of transistor 52. The other of the source and drain of transistor 53 is electrically connected to the gate of transistor 33; and the gate of transistor 53 is electrically connected to a high power supply potential line. In a similar manner to the above, transistor 53 can be used to reduce the load during the bootstrap period in the pulse output circuit. Furthermore, the effects of false pulses generated in the pulse output circuit on the switching of transistors 33 and 38 can be reduced. [Variation example of reverse pulse output circuit] The configuration of the inverted pulse output circuit included in the scan line driver circuit is not limited to that shown in FIG. 3C . For example, any of the inverted pulse output circuits shown in FIG. 10A to FIG. 10C can be used as the inverted pulse output circuit included in the scan line driver circuit. The inverted pulse output circuit in FIG10A has a configuration in which capacitor 80 is added to the inverted pulse output circuit in FIG3C. One electrode of capacitor 80 is electrically connected to the other of the source and drain of transistor 71, the other of the source and drain of transistor 72, and the gate of transistor 73; and the other electrode of capacitor 80 is electrically connected to terminal 63. Note that capacitor 80 prevents changes in the potential of the gate of transistor 73. Furthermore, the inverted pulse output circuit in FIG3C can have a smaller circuit area than the inverted pulse output circuit in FIG10A. The inverted pulse output circuit in Figure 10B has a configuration in which transistor 81 is added to the inverted pulse output circuit in Figure 10A. One of the source and drain of transistor 81 is electrically connected to the other of the source and drain of transistor 71 and the other of the source and drain of transistor 72. The source and drain of transistor 81 are electrically connected to the gate of transistor 73 and one electrode of capacitor 80. The gate of transistor 81 is electrically connected to the high power supply potential line. Note that transistor 81 prevents the breakdown of transistors 71 and 72. In particular, in the inverted pulse output circuit in Figure 3C, the potential of node C changes significantly due to the bootstrapping, causing the voltage between the source and drain of transistors 71 and 72 (particularly, between the source and drain of transistor 72) to change significantly, leading to the breakdown of transistors 71 and 72. In contrast, in the inverted pulse output circuit of FIG. 10B , when the gate potential of transistor 73 is increased by the bootstrap, transistor 81 is turned off, so that the potential of node C does not significantly change due to the bootstrap. Consequently, changes in the voltage between the source and drain of transistors 71 and 72 can be reduced. Furthermore, the inverted pulse output circuit of FIG. 3C or FIG. 10A can have a smaller circuit area than the inverted pulse output circuit of FIG. 10B . The inverted pulse output circuit in FIG10C has a configuration in which the wiring electrically connected to one of the source and drain of transistor 73 is changed from the high power supply potential line in the inverted pulse output circuit in FIG3C to a wiring for supplying the power supply potential (Vcc). Here, the power supply potential (Vcc) is higher than the low power supply potential (Vss) and lower than the high power supply potential (Vdd). Furthermore, this change reduces the probability of changes in the potential output from the inverted pulse output circuit to the corresponding inverted scan line. Furthermore, the aforementioned crash can be prevented. Furthermore, in the inverted pulse output circuit in FIG3C , the number of power supply potentials required for the inverted pulse output circuit's operation can be reduced compared to the inverted pulse output circuit in FIG10C . [Example of pixel changes] The configuration of the pixels included in the above-described display device is not limited to that shown in FIG. 4A . For example, although the pixel in FIG. 4A is formed using only n-channel transistors, the present invention is not limited to this configuration. That is, in a display device according to one embodiment of the present invention, the pixels can selectively be formed using only p-channel transistors, or a combination of n-channel and p-channel transistors. Note that, as depicted in FIG. 4A , when the transistors provided in the pixels are of only one conductivity type, the pixels can be highly integrated. This is because, in the case where the transistors are given different conductivity types by implanting impurities into the semiconductor layer, a gap (margin) must be provided between the n-channel transistors and the p-channel transistors. In contrast, in the case where the pixels are formed using transistors of only one conductivity type, this gap is not necessary. [Specific example of transistor] Specific examples of transistors included in the scan line driver circuit will be described below with reference to Figures 11A to 11D and Figures 12A to 12D. Note that any of the transistors described below can be included in both the scan line driver circuit and the pixel. The channel formation region of the transistor can be formed using any semiconductor material; for example, a semiconductor material containing a Group 14 element such as silicon or silicon germanium, a semiconductor material containing a metal oxide, or the like can be used. Furthermore, any of these semiconductor materials can be amorphous or crystalline. Furthermore, any oxide semiconductor material can be used, but preferably, an oxide semiconductor containing at least one selected from In, Ga, Sn, and Zn is used. For example, In-Sn-Zn-O as the main oxide is preferably used as the oxide semiconductor because it can produce a transistor with high field-effect mobility and high reliability. This rule can also be applied to the following oxides: four-component metal oxides such as In-Sn-Ga-Zn-O as the main oxide; such as In-Ga-Zn-O as the main oxide (also known as IGZO), In-Al-Zn-O as the main oxide, Sn-Ga-Zn-O as the main oxide, Al-Ga-Zn-O as the main oxide, Sn-Al-Zn-O as the main oxide, In-Hf-Zn-O as the main oxide, In-La-Zn-O as the main oxide, In-Ce-Zn-O as the main oxide, In-Pr-Zn-O as the main oxide, In-Nd-Zn-O as the main oxide, In-Pm-Zn-O as the main oxide, In-Sm-Zn-O as the main oxide, In-Eu-Zn-O as the main oxide, In-Gd-Zn-O as the main oxide a three-component metal oxide mainly composed of In-Tb-Zn-O, In-Dy-Zn-O, In-Ho-Zn-O, In-Er-Zn-O, In-Tm-Zn-O, In-Yb-Zn-O, or In-Lu-Zn-O; a two-component metal oxide mainly composed of In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, or In-Ga-O; a single-component metal oxide mainly composed of In-O, Sn-O, or Zn-O; and the like. Figures 11A to 11D and Figures 12A to 12D illustrate a specific example of a transistor in which a channel is formed in an oxide semiconductor. Note that Figures 11A to 11D and Figures 12A to 12D illustrate a specific example of a bottom-gate transistor, but a top-gate transistor can also be used as the transistor. Furthermore, Figures 11A to 11D and Figures 12A to 12D illustrate a specific example of a staggered transistor, but a coplanar transistor can also be used as the transistor. Figures 11A to 11D are cross-sectional views illustrating the steps used to fabricate a transistor (a so-called channel-etched transistor). First, a conductive film is formed on the substrate 400, which is a substrate having an insulating surface, and then, the gate electrode layer 401 is provided by a photolithography step using a mask. A glass substrate that can be mass-produced is preferably used as substrate 400. A glass substrate having a strain point of 730°C or higher when subjected to a high temperature heat treatment in a later step can be used as the glass substrate for substrate 400. For example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass can be used for substrate 400. An insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The base layer has the function of preventing diffusion of impurity elements from the substrate 400 and may be formed using a single layer or a stacked layer structure of one or more of a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, and a silicon nitride oxide layer. Silicon oxynitride refers to silicon in which the oxygen content is higher than the nitrogen content; for example, silicon oxynitride contains 50 to 70 atomic percent oxygen, 0.5 to 15 atomic percent nitrogen, 25 to 35 atomic percent silicon, and 0 to 10 atomic percent hydrogen. Furthermore, silicon oxynitride refers to silicon in which the nitrogen content is higher than the oxygen content; for example, silicon oxynitride contains 5 to 30 atomic percent oxygen, 20 to 55 atomic percent nitrogen, 25 to 35 atomic percent silicon, and 10 to 25 atomic percent hydrogen. Note that the above ranges are measured using a Rutherford backscattering spectrometer (RBS) or a hydrogen forward scattering spectrometer (HFS). Furthermore, the total percentage of these constituent elements does not exceed 100 atomic percent. The gate electrode layer 401 can be formed using a single layer or stacked layer structure of at least one of the following materials: Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, their nitrides, oxides, and alloys thereof. Alternatively, an oxide or oxynitride containing at least In and Zn can be used. For example, In-Ga-Zn-ON can be used as the primary material. Next, a gate insulating layer 402 is formed on the gate electrode layer 401. After the gate electrode layer 401 is formed, the gate insulating layer 402 is formed by sputtering, evaporation, plasma chemical vapor deposition (PCVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or the like without exposure to air. Preferably, the gate insulating layer 402 is an insulating film that can release oxygen through heat treatment. Releasing oxygen by heat treatment means that the amount of oxygen released converted into oxygen atoms is greater than or equal to 1.0×10 18 atoms / cm 3 , preferably greater than or equal to 3.0×10 20 atoms / cm 3 , as determined by thermal desorption spectrometry (TDS). The following shows a method in which the amount of oxygen released is measured by converting it into oxygen atoms using TDS analysis. The amount of gas released during TDS analysis is proportional to the integrated value of the spectrum. Therefore, the amount of gas released can be calculated from the ratio between the integrated value of the measured spectrum and the reference value of a standard sample. The reference value of the standard sample represents the ratio of the density of a predetermined atom contained in the sample to the integrated value of the spectrum. For example, the number of oxygen molecules (NO2) released from an insulating film can be obtained based on the TDS analysis results of a standard sample of a silicon wafer containing a predetermined density of hydrogen and the TDS analysis results of the insulating film according to equation (1). Here, all spectra with a mass number of 32 obtained by TDS analysis are assumed to be generated from oxygen molecules. CH3OH, which is a gas with a mass number of 32, is not considered under the assumption that it cannot exist. Furthermore, oxygen molecules containing isotopes of oxygen atoms, that is, oxygen atoms with a mass number of 17 or 18, are not considered because the proportion of such molecules in nature is very small. In Equation 1, NH2 is the value obtained by converting the number of hydrogen atoms released from a standard sample into a density. SH2 is the integrated value of the spectrum when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is set to NH2 / SH2. SO2 is the integrated value of the spectrum when the insulating film is subjected to TDS analysis. α is a coefficient that affects the spectral intensity in TDS analysis. For details of Equation 1, refer to Japanese Patent Application No. H06-275697. Note that the amount of oxygen released from the insulating film described above was measured using a silicon wafer containing 1×1016 atoms / cm3 of hydrogen as a standard sample using a thermal desorption spectrometer EMD-WA1000S / W manufactured by ESCO Ltd. Furthermore, in TDS analysis, oxygen is partially detected as oxygen atoms. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that because the above α includes the ionization rate of oxygen molecules, the number of released oxygen atoms can also be estimated by estimating the number of released oxygen molecules. Note that NO2 is the number of oxygen molecules released. When converted into oxygen atoms, the amount of oxygen released is twice the number of oxygen molecules released. In the above structure, the film in which oxygen is released by heat treatment may be oxygen-excess silicon oxide (SiO x (X>2)). In oxygen-excess silicon oxide (SiO x (X>2)), the number of oxygen atoms per unit volume is greater than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are measured using Rutherford backscattering spectrometry. The supply of oxygen from the gate insulating layer 402 to the oxide semiconductor film reduces the interface state density therebetween, thereby preventing carriers from being trapped at the interface between the oxide semiconductor film and the gate insulating layer 402, resulting in little degradation of the electrical characteristics of the transistor. Furthermore, in some cases, charges may be generated due to oxygen vacancies in the oxide semiconductor film. Typically, some of the oxygen vacancies in the oxide semiconductor film function as donors, leading to the release of electrons, i.e., carriers. Consequently, the threshold voltage of the transistor may shift negatively. To prevent this, sufficient oxygen, preferably an excess amount of oxygen, is supplied from the gate insulating layer 402 to the oxide semiconductor film in contact with the gate insulating layer 402, thereby reducing the oxygen vacancies in the oxide semiconductor film that may cause the threshold voltage to shift negatively. Preferably, the gate insulating layer 402 should be sufficiently flat to facilitate crystal growth of the oxide semiconductor film. The gate insulating layer 402 may be formed in a single layer or stacked layer structure using at least one of the following materials: silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cerium oxide, tantalum oxide, and magnesium oxide. The gate insulating layer 402 is preferably formed by sputtering in an oxygen atmosphere at a substrate heating temperature greater than or equal to room temperature and less than or equal to 200°C, preferably greater than or equal to 50°C and less than or equal to 150°C. Note that a gas may be added to the oxygen atmosphere; in this case, the percentage of oxygen gas is 30 volume percent or higher, preferably 50 volume percent or higher, and more preferably 80 volume percent or higher. The thickness of the gate insulating layer 402 ranges from 100 nm to 1000 nm, preferably from 200 nm to 700 nm. A lower substrate heating temperature during film formation, a higher percentage of oxygen gas in the film formation atmosphere, or a thicker gate insulating layer 402 results in a large amount of oxygen being released during the heat treatment performed on the gate insulating layer 402. The hydrogen concentration in the film can be further reduced by sputtering than by PCVD. Note that the gate insulating layer 402 may have a thickness greater than 1000 nm, but should have a thickness that does not reduce productivity. Then, an oxide semiconductor film 403 is formed on the gate insulating layer 402 by sputtering, evaporation, PCVD, PLD, ALD, MBE, or similar methods. FIG11A is a cross-sectional view after the above steps. The oxide semiconductor film 403 has a thickness ranging from 1 nm to 40 nm, preferably from 3 nm to 20 nm. In particular, when the transistor has a channel length of 30 nm or less and the oxide semiconductor film 403 has a thickness of approximately 5 nm, short channel effects can be suppressed and stable electrical characteristics can be obtained. In particular, a transistor in which In—Sn—Zn—O is used as a main material in the oxide semiconductor film 403 can have high field-effect mobility. A transistor in which a channel is formed in an oxide semiconductor film containing In, Sn, and Zn as main components can have advantageous characteristics by forming the oxide semiconductor film while heating the substrate, or by performing heat treatment after forming the oxide semiconductor film. Note that the main component refers to an element contained in the composition at 5 atomic percent or more. By systematically heating the substrate after forming an oxide semiconductor film primarily composed of In, Sn, and Zn, the field-effect mobility of the transistor can be improved. Furthermore, the transistor's threshold voltage can be positively shifted, rendering the transistor normally off. To reduce the off-state current of the transistor, the oxide semiconductor film 403 is formed using a material having a bandgap of 2.5 eV or greater, preferably 2.8 eV or greater, and more preferably 3.0 eV or greater. Using a material having a bandgap within this range for the oxide semiconductor film 403 can reduce the off-state current of the transistor. In the oxide semiconductor film 403, it is preferable to reduce the concentration of hydrogen, alkali metals, alkaline earth metals, and the like so that the impurity concentration is extremely low. This is because these impurities contained in the oxide semiconductor film 403 form energy levels that lead to recombination in the energy gap, thereby increasing the off-state current of the transistor. The hydrogen concentration in the oxide semiconductor film 403 measured by secondary ion mass spectrometry (SIMS) is lower than 5×1019cm-3, preferably lower than or equal to 5×1018cm-3, more preferably lower than or equal to 1×1018cm-3, and still more preferably lower than or equal to 5×1017cm-3. Furthermore, the concentrations of alkali metals in the oxide semiconductor film 403 measured by SIMS are as follows: The sodium concentration is lower than or equal to 5×10 16 cm -3 , preferably lower than or equal to 1×10 16 cm -3 , and more preferably lower than or equal to 1×10 15 cm -3 . Similarly, the lithium concentration is lower than or equal to 5×10 15 cm -3 , preferably lower than or equal to 1×10 15 cm -3 . Similarly, the potassium concentration is lower than or equal to 5×10 15 cm -3 , preferably lower than or equal to 1×10 15 cm -3 . As the oxide semiconductor film 403, an oxide semiconductor film (also called a c-axis aligned crystalline oxide semiconductor film (CAAC-OS film)) including crystals (also called c-axis aligned crystals (CAAC)) can be used. The crystal system is aligned along the c-axis and has a triangular or hexagonal atomic arrangement when viewed from the ab plane, the top surface, or the interface. In the crystal, metal atoms are arranged in layers along the c-axis, or metal atoms and oxygen atoms are arranged in layers along the c-axis, and the direction of the a-axis or b-axis changes in the ab plane (the crystal is twisted about the c-axis). In a broad sense, CAAC refers to a non-single crystal phase having a triangular, hexagonal, equilateral triangular, or regular hexagonal atomic arrangement when viewed perpendicular to the ab plane, wherein metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner, when viewed perpendicular to the c-axis. Note that nitrogen may replace a portion of the oxygen contained in CAAC. The CAAC-OS film is non-single-crystal, but this does not mean that the CAAC-OS film is composed solely of amorphous components. Although the CAAC-OS film includes crystallized portions (crystalline portions), in some cases, the boundaries between one crystalline portion and another are not distinct. The c-axis of the crystalline portions included in the CAAC-OS film can be oriented in a direction (for example, perpendicular to the surface of the substrate on which the CAAC-OS film is formed or the top surface of the CAAC-OS film). Optionally, the normal to the ab plane of each crystalline portion included in the CAAC-OS film can be oriented in a certain direction (for example, perpendicular to the surface of the substrate on which the CAAC-OS film is formed or the top surface of the CAAC-OS film). As an example of the CAAC-OS film, there is an oxide film formed in a film shape and having a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the surface of the film or the surface of the substrate on which the CAAC-OS film is formed, and wherein when the cross-section of the film is observed, metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner. The oxide semiconductor film 403 is preferably formed by sputtering in an oxygen atmosphere at a substrate heating temperature of 100°C to 600°C, more preferably 150°C to 550°C, and more preferably 200°C to 500°C. The thickness of the oxide semiconductor film 403 is from 1 nm to 40 nm, more preferably from 3 nm to 20 nm. The higher the substrate heating temperature during film formation, the lower the impurity concentration in the resulting oxide semiconductor film 403. Furthermore, the atoms in the oxide semiconductor film 403 are arranged, and their density increases, facilitating the formation of crystals or CAACs. Furthermore, because an oxygen atmosphere is used for film formation, unnecessary atoms such as rare gas atoms are not incorporated into the oxide semiconductor film 403, facilitating the formation of crystals or CAACs. Note that a mixed gas atmosphere containing oxygen and rare gases may be used. In this case, the percentage of oxygen is 30 volume percent or higher. Preferably, it is 50 volume percent or higher, and more preferably, 80 volume percent or higher. The thinner the oxide semiconductor film 403, the lower the short-channel effect of the transistor. However, if the oxide semiconductor film 403 is too thin, the oxide semiconductor film 403 is significantly affected by interface scattering, thereby potentially reducing field-effect mobility. When forming the oxide semiconductor film 403 using a sputtering method using a film primarily composed of In—Sn—Zn—O, an In—Sn—Zn—O target having an atomic ratio of In:Sn:Zn of 2:1:3, 1:2:2, 1:1:1, or 20:45:35 is preferably used. When the oxide semiconductor film 403 is formed using an In—Sn—Zn—O target having such a composition ratio, crystals or CAAC can be easily formed. Next, a first heat treatment is performed. This first heat treatment is performed in a reduced-pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. This first heat treatment can reduce the impurity concentration in the oxide semiconductor film 403. FIG11B is a cross-sectional view after the above step. Preferably, the first heat treatment is performed by completing the heat treatment in a reduced-pressure atmosphere or an inert atmosphere, then changing the atmosphere to an oxidizing atmosphere while maintaining the temperature, and further performing the heat treatment. Heat treatment performed in a reduced-pressure atmosphere or an inert atmosphere effectively reduces the impurity concentration in the oxide semiconductor film 403 and, at the same time, generates oxygen vacancies. Therefore, heat treatment in an oxidizing atmosphere is performed to reduce the generated oxygen vacancies. In addition to heating the substrate during film formation, performing the first heat treatment on the oxide semiconductor film 403 can significantly reduce the level of impurities in the film. Consequently, the field-effect mobility of the transistor can be increased to a value close to the ideal field-effect mobility described later. Note that oxygen ions may be implanted into the oxide semiconductor film 403, and impurities such as hydrogen may be released from the oxide semiconductor film 403 by heat treatment, so that the oxide semiconductor film 403 may be crystallized simultaneously with the heat treatment or by heat treatment performed later. Instead of the first heat treatment, the oxide semiconductor film 403 can be selectively crystallized by laser beam irradiation. Alternatively, laser beam irradiation can be performed during the first heat treatment, allowing the oxide semiconductor film 403 to be selectively crystallized. Laser beam irradiation is performed in an inert atmosphere, an oxygen atmosphere, or a reduced-pressure atmosphere. A continuous wave laser beam (hereinafter referred to as a CW laser beam) or a pulsed laser (hereinafter referred to as a pulsed laser beam) can be used for this laser beam irradiation. For example, a gas laser beam such as an Ar laser beam, a Kr laser beam, or an excimer laser beam can be used; a laser beam emitted from a medium using single crystal or polycrystalline YAG, YVO4, forsterite (Mg2SiO4), YAlO3, or GdVO4 doped with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta; a solid-state laser beam such as a glass laser beam, a ruby laser beam, an alexandrite laser beam, or a Ti:sapphire laser beam; or a vapor laser beam emitted from one or both of copper vapor and gold vapor. The oxide semiconductor film 403 can be crystallized by irradiation with the first harmonic of the laser beam or any of the second to fifth harmonics of the first harmonic of the laser beam. Note that the laser beam used for irradiation preferably has energy greater than the band gap of the oxide semiconductor film 403. For example, a laser beam emitted by a KrF, ArF, XeCl, or XeF excimer laser can be used. Note that the laser beam can be a linear laser beam. Note that laser beam irradiation may be performed multiple times in different situations. For example, it is preferable that the first laser beam irradiation be performed in a rare gas atmosphere or a reduced pressure atmosphere, and the second laser beam irradiation be performed in an oxidizing atmosphere, because in this case, high crystallinity can be obtained and oxygen vacancies in the oxide semiconductor film 403 can be reduced at the same time. Next, the oxide semiconductor film 403 is processed into an island shape by a photolithography step or a similar step to form an oxide semiconductor film 404. Next, a conductive film is formed over the gate insulating layer 402 and the oxide semiconductor film 404, and then a photolithography step or a similar step is performed to form the source electrode 405A and the drain electrode 405B. The conductive film can be formed by sputtering, evaporation, PCVD, PLD, ALD, MBE, or a similar method. Similar to the gate electrode layer 401, the source electrode 405A and the drain electrode 405B can be formed using a single layer or stacked layer structure of at least one of the following materials: Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W; their nitrides; their oxides; and their alloys. Next, an insulating film 406 serving as a top insulating film is formed by sputtering, evaporation, PCVD, PLD, ALD, MBE, or a similar method. FIG11C is a cross-sectional view after the above steps. The insulating film 406 can be formed by a method similar to the method for forming the gate insulating layer 402. A protective insulating film (not shown) may be formed to be stacked on the insulating film 406. Preferably, the protective insulating film has a property of preventing oxygen from passing through even when heat treatment for one hour is performed at, for example, 250° C. to 450° C., preferably, 150° C. to 800° C. When a protective insulating film having such properties is provided around the insulating film 406, oxygen released from the insulating film 406 during the heat treatment can be prevented from diffusing outside the transistor. Since the oxygen is retained within the insulating film 406 in this manner, a decrease in the field-effect mobility of the transistor can be prevented, variations in the threshold voltage can be reduced, and reliability can be improved. The protective insulating film can be formed by a single layer or stacked layer structure using at least one of the following materials: silicon oxide nitride, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cerium oxide, tantalum oxide, and magnesium oxide. After forming the insulating film 406, a second heat treatment is performed. FIG11D is a cross-sectional view after the above step. The second heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere at a temperature of 150°C to 550°C, preferably 250°C to 400°C. This second heat treatment releases oxygen from the gate insulating layer 402 and the insulating film 406 and reduces oxygen vacancies in the oxide semiconductor film 404. Furthermore, the interface state density between the gate insulating layer 402 and the oxide semiconductor film 404, and between the oxide semiconductor film 404 and the insulating film 406, can be reduced, resulting in reduced variations in the threshold voltage of the transistor and increased transistor reliability. The transistor including the oxide semiconductor film 404 subjected to the first and second heat treatments has high field-effect mobility and low off-state current. Specifically, the off-state current per micrometer of channel width can be 1×10-18 A or less, 1×10-21 A or less, or 1×10-24 A or less. Preferably, the oxide semiconductor film 404 is non-single-crystalline. This is because, if oxygen vacancies are generated in the completely single-crystalline oxide semiconductor film 404 by transistor operation or external light or heat, carriers in the oxygen vacancies are generated in the oxide semiconductor film 404 due to the absence of oxygen between the crystal lattices to repair the oxygen vacancies; thus, the threshold voltage of the transistor shifts in a negative direction. The oxide semiconductor film 404 preferably has crystallinity. For example, a polycrystalline oxide semiconductor film or a CAAC-OS film is preferably used as the oxide semiconductor film 403. Through the above steps, the transistor depicted in FIG. 11D can be manufactured. A transistor having a structure different from that of the transistor described above will be described with reference to Figures 12A to 12D. Note that Figures 12A to 12D are cross-sectional views depicting the manufacturing steps of a so-called etch-stop transistor (also known as a channel-blocking transistor or a channel-protecting transistor). The transistor system depicted in Figures 12A to 12D differs from the transistor depicted in Figures 11A to 11D in that an insulating film 408 serving as an etching stopper is provided. Therefore, descriptions identical to those of Figures 11A to 11D will be omitted below, and the above description will be referenced. Through the above steps, the structure depicted in the cross-sectional views in Figures 12A and 12B can be obtained. The insulating film 408 in FIG12C can be formed in a manner similar to that of the gate insulating layer 402 and the insulating film 406. That is, as the insulating film 408, it is preferable to use an insulating film in which oxygen is released by heat treatment. The insulating film 408 serving as an etching stopper film can prevent the oxide semiconductor film 404 from being etched in a photolithography step or the like for forming the source electrode 405A and the drain electrode 405B. After forming the insulating film 406 in FIG. 12D , a second heat treatment is performed to release oxygen from the insulating film 408 and the insulating film 406. This further increases the effectiveness of reducing oxygen vacancies in the oxide semiconductor film 404. Furthermore, the interface state density between the gate insulating layer 402 and the oxide semiconductor film 404, and between the oxide semiconductor film 404 and the insulating film 408, can be reduced, resulting in reduced variations in the threshold voltage of the transistor and increased transistor reliability. Through the above steps, the transistor depicted in FIG. 12D can be manufactured. The scan line driver circuit and the pixel may include any of the transistors depicted in FIG11D and FIG12D. For example, a configuration in which the transistor system is used as transistor 11 in FIG4A will be described with reference to FIG13A and FIG13B. Specifically, FIG13A is a top view of the case in which the transistor depicted in FIG11D is used as transistor 11, and FIG13B is a top view of the case in which the transistor depicted in FIG12D is used as transistor 11. Note that the cross-section taken along line C1-C2 in FIG13A is FIG11D, and the cross-section taken along line C1-C2 in FIG13B is FIG12D. In each of the transistors depicted in Figures 13A and 13B, a portion of the wiring used as signal line 6 in Figure 4A is used as one of the source and drain of transistor 11, and a portion of the wiring used as scan line 4 is used as the gate of transistor 11. In this manner, a portion of these wirings provided in the display device can be used as transistor terminals. [Various electronic devices including liquid crystal display devices] Examples of electronic devices each including the liquid crystal display device disclosed in this specification will be shown below with reference to Figures 14A to 14F. FIG14A depicts a laptop computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, and the like. FIG14B depicts a personal digital assistant (PDA) including a main body 2211 having a display portion 2213, an external interface 2215, operation buttons 2214, and the like. A stylus 2212 for operation is included as an accessory. Figure 14C depicts an e-book reader 2220, an example of electronic paper. E-book reader 2220 includes two housings: housing 2221 and housing 2223. Housings 2221 and 2223 are connected by a hinge 2237, along which e-book reader 2220 can be opened and closed. This structure allows e-book reader 2220 to be used as a book. Display unit 2225 is incorporated into housing 2221, and display unit 2227 is incorporated into housing 2223. Display unit 2225 and display unit 2227 can display one image or different images. In a configuration where the display units display different images, for example, the right display unit (display unit 2225 in FIG. 14C ) can display text, while the left display unit (display unit 2227 in FIG. 14C ) can display an image. Furthermore, in FIG. 14C , the housing 2221 is provided with an operating unit and the like. For example, the housing 2221 is provided with a power supply 2231, operating keys 2233, a speaker 2235, and the like. The operating keys 2233 can be used to turn pages. Note that a keyboard, pointing device, or the like can also be provided on the surface of the housing on which the display unit is provided. Furthermore, external connection terminals (headphone terminals, USB terminals, terminals that can connect to various cables such as AC adapters and USB cables, or the like), a recording medium insertion portion, and the like can be provided on the back or side surfaces of the housing. Furthermore, the e-book reader 2220 can function as an electronic dictionary. The e-book reader 2220 can be configured to transmit and receive data wirelessly. Through wireless communication, desired book information or the like can be purchased and downloaded from an e-book server. It should be noted that electronic paper can be applied to devices in a wide variety of fields as long as the devices can display information. For example, in addition to e-book readers, electronic paper can be used for posters, advertisements in transportation vehicles such as trains, displays on various cards such as credit cards, and the like. Figure 14D depicts a mobile phone. The mobile phone includes two housings: housings 2240 and 2241. Housing 2241 is provided with a display panel 2242, a speaker 2243, a microphone 2244, an indicator device 2246, a camera lens 2247, external connection terminals 2248, and the like. Housing 2240 is provided with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, and the like. An antenna is integrated into housing 2241. Display panel 2242 has a touch panel function. Multiple operation keys 2245, displayed as images, are depicted by dotted lines in FIG. 14D . Note that the mobile phone includes a boost circuit to increase the voltage output from solar cell 2249 to the voltage required for each circuit. Furthermore, in addition to the above structure, the mobile phone may include a contactless IC chip, a small recording device, or the like. The display orientation of display panel 2242 can be appropriately changed depending on the mode of use. Furthermore, camera lens 2247 is located on the same surface as display panel 2242, allowing it to be used as a video phone. Speaker 2243 and microphone 2244 can be used for video calling, recording and playing sounds, etc., as well as voice calling. Furthermore, housings 2240 and 2241, in the unfolded state as depicted in FIG. 14D , can be slid so that one housing overlaps the other; thus, the size of the mobile phone can be reduced, making it more portable. External connection terminal 2248 can be connected to an AC adapter or various cables such as a USB cable, enabling charging and data communication for the mobile phone. Furthermore, large amounts of data can be stored and transferred by inserting a recording medium into external memory slot 2250. Furthermore, in addition to the functions described above, infrared communication, television reception, or similar functions can also be provided. FIG14E depicts a digital camera including a main body 2261, a display portion (A) 2267, an eyepiece 2263, an operation switch 2264, a display portion (B) 2265, a battery 2266, and the like. FIG14F depicts a television set. In a television set 2270, a display portion 2273 is incorporated into a housing 2271. The display portion 2273 can display images. Here, the housing 2271 is supported by a stand 2275. The television set 2270 can be operated using the operating switches on the housing 2271 or a separate remote controller 2280. Channels and volume can be controlled using the operating keys 2279 of the remote controller 2280, thereby controlling the image displayed on the display unit 2273. Furthermore, the remote controller 2280 may include a display unit 2277 on which information outputted by the remote controller 2280 can be displayed. Note that the television set 2270 is preferably equipped with a receiver, a modem, and the like. Conventional television broadcasts can be received by the receiver. Furthermore, when the television set is connected to a communication network via a modem, either wired or wirelessly, it can perform one-way (from transmitter to receiver) or two-way (between transmitter and receiver, or between receivers) data communication. This application is based on Japanese Patent Application No. 2011-108318 filed in the Japan Patent Office on May 13, 2011, the entire contents of which are incorporated herein by reference. 1: Scan line driver circuit 2: Signal line driver circuit 3: Current Source 4: Scan line 5: Inverted scan line 6:Signal line 7: Power supply line 10: Pixels 11~16,31~39: Transistors 17,80:Capacitor 18: Organic EL element 20: Pulse output circuit 21~27,61~63: terminal 60: Inverse pulse output circuit 400:Substrate 401: Gate electrode layer 402: Gate insulation layer 403, 404: Oxide semiconductor film 405A: Source electrode 405B: Drain electrode 406,408:Insulating film 2201,2211,2261: Main body 2202,2221,2241,2223,2240,2271: Shell 2203,2213,2265,2267,2273,2277,2225,2227: Display unit 2204:Keyboard 2212:Pointed pen 2214: Operation button 2215: External Interface 2220: E-book reader 2231:Power supply 2233,2245,2279: Operation keys 2235,2243: Speaker 2237: shaft 2242: Display Panel 2244:Microphone 2246:Indicator device 2247:Camera lens 2248: External connection terminal 2249:Solar Cell 2250: External memory slot 2263: Eyepiece 2264: Operation switch 2266:Battery 2270:TV 2275: Platform 2280: Remote Control

Claims

1. A display device comprising: a driving circuit and pixels; the driving circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor; one of the source or drain of the first transistor is electrically connected to a first wiring; the other of the source or drain of the first transistor is electrically connected to a second wiring and to one of the source or drain of the second transistor; the other of the source or drain of the second transistor is electrically connected to a third wiring; one of the source or drain of the third transistor is electrically connected to the gate of the first transistor and to one of the source or drain of the fourth transistor; the gate of the third transistor is electrically connected to the fourth wiring; the other of the source or drain of the fourth transistor is electrically connected to the third wiring; the gate of the fourth transistor is electrically connected to the gate of the second transistor; the first wiring input has a first potential; the third wiring input has a second potential; the fourth wiring input has a first clock signal. The pixel includes an EL element, a capacitor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; one of the sources or drains of the fifth transistor is electrically connected to the EL element and to one of the sources or drains of the sixth transistor; the other source or drain of the fifth transistor is electrically connected to one of the sources or drains of the seventh transistor and to one of the sources or drains of the eighth transistor; the gate of the fifth transistor is electrically connected to the second wiring; the gate of the seventh transistor is electrically connected to the sixth wiring; the other source or drain of the eighth transistor is electrically connected to one of the sources or drains of the ninth transistor and to one of the sources or drains of the tenth transistor; the gate of the eighth transistor is electrically connected to the capacitor; the gate of the ninth transistor is electrically connected to the sixth wiring; the other source or drain of the tenth transistor is electrically connected to the seventh wiring. The gate of the tenth transistor is electrically connected to the second wiring; the sixth wiring is electrically connected to the pulse output circuit; and the seventh wiring has a power supply potential input.

2. A display device, comprising: a driving circuit and pixels; the driving circuit including a first transistor, a second transistor, a third transistor, and a fourth transistor; one of the source or drain of the first transistor is electrically connected to a first wiring; the other of the source or drain of the first transistor is electrically connected to a second wiring and to one of the source or drain of the second transistor; the other of the source or drain of the second transistor is electrically connected to a third wiring; one of the source or drain of the third transistor is electrically connected to the gate of the first transistor and to one of the source or drain of the fourth transistor; the gate of the third transistor is electrically connected to the fourth wiring; the other of the source or drain of the fourth transistor is electrically connected to the third wiring; the gate of the fourth transistor is electrically connected to the gate of the second transistor; the first wiring input has a first potential; the third wiring input has a second potential; the fourth wiring input has a first clock signal. The pixel includes an EL element, a capacitor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; one of the sources or drains of the fifth transistor is electrically connected to the EL element and is also electrically connected to one of the sources or drains of the sixth transistor; the other source or drain of the fifth transistor is electrically connected to one of the sources or drains of the seventh transistor and is also electrically connected to one of the sources or drains of the eighth transistor. The gate of the fifth transistor is electrically connected to the second wiring; the other of the source or drain of the seventh transistor is electrically connected to the fifth wiring; the gate of the seventh transistor is electrically connected to the sixth wiring; the other of the source or drain of the eighth transistor is electrically connected to one of the source or drain of the ninth transistor, and also electrically connected to one of the source or drain of the tenth transistor. The gate of the eighth transistor is electrically connected to one of the sources or drains of the ninth transistor, and is also electrically connected to the capacitor; the gate of the ninth transistor is electrically connected to the sixth wiring; the other of the sources or drains of the tenth transistor is electrically connected to the seventh wiring; the gate of the tenth transistor is electrically connected to the second wiring; the fifth wiring has a first signal input; the sixth wiring is electrically connected to the pulse output circuit; and the seventh wiring has a power supply potential input.

Images