Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a substrate including a junction field-effect transistor (FET) region; a well region located in the substrate and adjacent to the FET region; a source region located in the well region; a FET doped region located in the FET region and including: a first doped region; and a second doped region located below the first doped region, wherein a dopant concentration in the first doped region is less than a dopant concentration in the second doped region; and a gate structure above the FET region.

Claims

1. A semiconductor device, comprising: A substrate includes a junction field-effect transistor (FET) region; a well region located in the substrate and adjacent to the FET region; a source region located in the well region; a FET doped region located in the FET region and including: a first doped region; and a second doped region contacting a lower surface of the first doped region but not contacting the well region, wherein a dopant concentration in the first doped region is less than a dopant concentration in the second doped region; and a gate structure above the FET region.

2. The semiconductor device as claimed in claim 1, wherein the junction field-effect transistor doped region has a higher dopant concentration than the substrate.

3. The semiconductor device as claimed in claim 1, wherein the first doped region and the well region have an overlapping portion.

4. The semiconductor device as claimed in claim 3, wherein a horizontal width of the overlapping portion is about 0.05 μm to about 0.10 μm.

5. The semiconductor device as claimed in claim 1, wherein a horizontal width of an upper surface of the junction field-effect transistor region is about 0.5 μm to about 1.0 μm.

6. A method for manufacturing a semiconductor device, comprising: A plurality of well regions are formed in a substrate, wherein the substrate has a junction field-effect transistor region located between the well regions; A plurality of source regions are formed in the well regions respectively; an implantation process is performed into the junction field-effect transistor region to form a junction field-effect transistor doped region, the junction field-effect transistor doped region having a higher dopant concentration than the substrate, and comprising: a first doped region; and a second doped region, contacting a lower surface of the first doped region but not contacting the well regions, wherein the dopant concentration of the first doped region is less than the dopant concentration of the second doped region; and a gate structure is formed above the junction field-effect transistor region.

7. The method as described in claim 6, wherein a dopant performing the implantation process and a dopant in the junction field-effect transistor region have the same conductivity type.

8. The method as described in claim 6 further comprises: forming a mask layer over the substrate before performing the implantation process, the mask layer having an opening, wherein the opening overlaps the well areas; and removing the mask layer after performing the implantation process.

9. The method as described in claim 6, wherein a dopant concentration of the substrate is less than the dopant concentration of the first doped region and the dopant concentration of the second doped region.

Images