Reconstructed semiconductor die evaluation and power delivery

Abstract

This invention describes methods, systems, and apparatus for reconstructing semiconductor die evaluation and power delivery. A semiconductor device can be formed based on a reconstructed wafer of an operable die, supporting an improved architecture for power delivery. In some instances, a first side of an interface block can be bonded to one or more volatile memory stacks. An evaluation procedure can be performed by probing one or more conductive pads on a second side of the interface block. The second side of the interface block can then be bonded to a first side of a host chip, and the host chip is operable to control one or more functions of the interface block and the one or more volatile memory stacks. In some instances, a redistribution layer can be formed over the second side of the host chip to provide a power interface for the semiconductor device.

Description

Technical Field

[0001] This technical field relates to the evaluation of reconstructed semiconductor grains and power transmission. Prior Technology

[0002] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, and any of these states can be stored within the memory cell. To store information, a memory device can write (e.g., program, set, assign) states to memory cells. To access the stored information, a memory device can read (e.g., sense, detect, retrieve, determine) the states from memory cells. Summary of the Invention

[0003] A method for manufacturing a semiconductor device is described. The method may include: bonding a first side of an interface block to one or more volatile memory stacks; performing an evaluation procedure on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; bonding the second side of the interface block to a first side of a host chip, at least in part based on performing the evaluation procedure; the host chip being operatively coupled to the interface block and controlling a function of the one or more volatile memory stacks; and forming a redistribution layer over the second side of the host chip opposite to the first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the semiconductor device.

[0004] A semiconductor device is described. The semiconductor device may include: an interface block including a logic circuit system for operating one or more memory arrays; one or more volatile memory stacks, etc., coupled to a first side of the interface block, each of a group of semiconductor dies including at least one of the one or more memory arrays; a host chip coupled to a second side of the interface block opposite to the first side of the interface block, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks; and a redistribution layer above the first side of the host chip opposite to the second side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the semiconductor device, the second side of the host chip being coupled to the first side of the interface block.

[0005] Describes a product formed by a process. The product can be formed by: bonding a first side of an interface block to one or more volatile memory stacks; performing an evaluation process on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; bonding the second side of the interface block to a first side of a host chip, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks, at least in part based on performing the evaluation process; and forming a redistribution layer over the second side of the host chip opposite to the first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the product.

[0006] A method for manufacturing a semiconductor device is described. The method may include: bonding a second side of an interface block to a first side of one or more volatile memory stacks, the interface block including a logic circuit system for operating one or more memory arrays of the one or more volatile memory stacks; performing an evaluation procedure on the interface block and the one or more volatile memory stacks by detecting one or more first conductive pads on a first side of the interface block opposite to the second side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; and forming a redistribution layer over the first side of the interface block opposite to the second side of the interface block, the redistribution layer including one or more second conductive pads operable to couple the interface block to a host chip.

[0007] Describe a semiconductor device. The semiconductor device may include: an interface block including a logic circuit system for operating one or more memory arrays; one or more volatile memory stacks, etc., bonded to a second side of the interface block; each semiconductor die of a group of semiconductor dies including at least one of the one or more memory arrays; and one or more first conductive pads, etc., formed on a first side of the interface block opposite to the second side of the interface block, the one or more first conductive pads providing an evaluation interface for the interface block and the one or more volatile memory stacks. Simple Explanation of the Diagram

[0008] Figure 1 illustrates one example of a system that supports the reconstruction of semiconductor die evaluation and power delivery, based on examples disclosed herein.

[0009] Figure 2 illustrates one example of a system that supports the reconstruction of semiconductor die evaluation and power delivery, based on examples disclosed herein.

[0010] Figure 3 illustrates one example of an architecture that supports reconstructed semiconductor die evaluation and power delivery, based on examples disclosed herein.

[0011] Figures 4 through 13 illustrate example operations of a semiconductor device for forming a semiconductor die evaluation and power delivery system, based on examples disclosed herein.

[0012] Figure 14 illustrates one example of a system for reconstructing semiconductor die evaluation in a supported stacked memory architecture, based on examples disclosed herein.

[0013] Figures 15 and 16 illustrate flowcharts illustrating one or more methods for supporting the reconstruction of semiconductor die evaluation and power delivery based on examples disclosed herein. Implementation

[0014] This patent application claims priority to U.S. Patent Application No. 63 / 572,720, filed April 1, 2024, entitled "Reconstructed Semiconductor Die Evaluation and Power Delivery," and U.S. Patent Application No. 19 / 090,263, filed March 25, 2025, entitled "Reconstructed Semiconductor Die Evaluation and Power Delivery," each of which is assigned to its assignee, and the entire contents of each of which are expressly incorporated herein by reference.

[0015] Some semiconductor systems (e.g., memory systems, processor systems, semiconductor devices) may include a stack of semiconductor components (e.g., semiconductor dies) that may contain one or more memory dies (e.g., array dies, volatile memory dies) or one or more memory die stacks (e.g., volatile memory stacks) stacked with a logic die (e.g., an interface block), the logic die being operable to access a group of memory arrays distributed across one or more memory dies. This stacked architecture may be implemented as part of a high-bandwidth memory (HBM) system or a tightly coupled dynamic random access memory (TCDRAM) system, and other instances, and may support memory-centric logic solutions, such as graphics processing units (GPUs), and other implementations. In some instances, an HBM system may include one or more memory dies coupled (e.g., bonded, stacked) to a logic die. In some instances, a TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled, directly coupled) to one or more processors (e.g., one or more host chips) such as a GPU or other host device, as part of a physical memory map accessible to the processor. A logic die may contain various components such as interface blocks (e.g., memory interface blocks, interface circuit systems), logic blocks, controllers, processors, and other components. A semiconductor component (e.g., a semiconductor cell, a semiconductor subsystem) (such as a logic die) may be formed as a single die with associated circuit systems, or may be formed as a die having multiple die portions (e.g., relatively small dies, each containing a subset of a logic cell), such die portions may be referred to as "chiplets" (e.g., logic chiplets), and other instances.

[0016] Semiconductor systems (such as semiconductor devices comprising one or more memory stacks (e.g., dynamic random access memory (DRAM) stacks, memory dies), one or more interface blocks (e.g., logic blocks, logic dies), and one or more host chips (e.g., GPUs)) can be manufactured via one or more wafer-to-wafer bonding steps. In wafer-to-wafer bonding, a first wafer of a plurality of first dies can be bonded to a second wafer of a plurality of second dies (e.g., via fusion bonding or hybrid bonding). However, such bonding techniques can be associated with a relatively low device yield (e.g., a relatively high yield loss). For example, in some cases, operable dies (e.g., good dies, dies that operate according to a performance expectation) can be bonded to defective dies (e.g., bad dies, dies that fail to operate according to a performance expectation), which may result in both dies being rejected (e.g., discarded). Therefore, some good dies can be discarded as part of a process, thereby reducing manufacturing yield and increasing waste. In addition, some semiconductor devices may be associated with relatively high heat generation and the corresponding manufacturing processes may not support efficient heat dissipation (e.g., based on one of the architectures of a semiconductor device).

[0017] According to one or more examples described herein, a semiconductor device (e.g., an HBM system, a heterogeneous semiconductor device) can be formed (e.g., manufactured) based on a wafer reconstructed from a die that meets an evaluation procedure (e.g., a die as a known good die (KGD)). That is, some dies can be separated from one or more first wafers (e.g., diced from one or more first wafers), tested to determine whether the die is KGD, and the KGD dies are assembled together to form a second wafer. Additionally, a semiconductor device manufacturing method can be improved to support more efficient power delivery to the semiconductor device (e.g., based on the placement of a host chip relative to one or more heat sinks). In some examples, a first side (e.g., the side opposite a substrate material) of an interface block (e.g., a logic die, a known good logic die) can be bonded to one or more memory stacks (e.g., known good memory dies, DRAM stacks, TCDRAM stacks). The interface block may also be formed with one or more conductive pads (e.g., probe pads) on a second side of one of the interface blocks (e.g., the side containing a substrate material), which can support the execution of one or more evaluation procedures for the interface block and one or more memory stacks.

[0018] Based on the execution of one or more evaluation procedures, the second side of the interface block can then be bonded to a first side (e.g., the side opposite a substrate material) of a host chip (e.g., a known good host die, a GPU, one or more host devices), and the host chip can be operated to couple with the interface block and control one or more functions of the interface block and one or more memory stacks. In some instances, a redistribution layer (RDL) (e.g., a power distribution layer, a relatively low-resistance power distribution network) can be formed over a second side of the host chip (e.g., the side containing a substrate material, the side opposite the first side). The RDL may include a set of conductive signal lines providing a power delivery interface for the semiconductor device. By forming the semiconductor device according to one or more of the examples described herein, a relatively small number of dies can be rejected, which can improve manufacturing yield. In addition, by forming an RDL over a host chip, the semiconductor device can operate with improved thermal distribution, which can increase the lifetime of the semiconductor device and improve device reliability and performance.

[0019] In addition to its applicability to memory systems as described herein, techniques for reconstructing semiconductor die evaluation and power delivery can typically be implemented to improve the sustainability of various electronic devices and systems. As the use of electronic devices becomes more widespread, energy consumption and hazardous emissions associated with their production and operation are also increasing. Furthermore, the amount of waste associated with electronic device disposal (e.g., e-waste) can also cause environmental problems. Implementing the techniques described herein can mitigate the impacts related to electronic devices by reducing waste materials during production and by reducing semiconductor component degradation based on improved heat dissipation. This can help extend the lifespan of electronic devices, thereby reducing e-waste, and other benefits.

[0020] The features of the invention are illustrated and described in the background context of the system and architecture. The features of the invention are further illustrated and described in the background context of an architecture, illustrative operation, and flowchart of semiconductor device formation.

[0021] Figure 1 illustrates one example of a system 100 supporting reconstructed semiconductor die evaluation and power delivery according to examples disclosed herein. System 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an internet-connected device, a vehicle controller, a system-on-a-chip (SoC) or other fixed or portable electronic system, and other examples. System 100 includes a host system 105, a memory system 110, and one or more channels 115 coupling the host system 105 and the memory system 110 (e.g., to support a communicative coupling). System 100 may include any number of memory systems 110 coupled to the host system 105. In some examples, system 100 may be formed as a single device (e.g., a single assembly package, a single heterogeneous package, a single co-design package, a single system technology co-optimized package).

[0022] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, application processing circuitry, one or more processing components) that use memory to execute programs (e.g., applications, functions, operations). Any or more of these components may be referred to as a processor 125 or included within the processor 125. The processor 125 may include at least one of one or more processing elements that can be co-located or distributed, including a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an instance of a SoC or one of its components, as well as other instances.

[0023] In some instances, system 100 or host system 105 may include an input component, an output component, or a combination thereof. An input component may include a sensor, a microphone, a keyboard, another processor (e.g., on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with system 100 via one or more peripheral components, and other examples. An output component may include a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with system 100 via one or more peripheral components, and other examples.

[0024] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functions of an external memory controller (e.g., a host system memory controller), which may be referred to as a host system controller 120 or included within the host system controller 120. For example, a host system controller 120 may issue commands or other communications for operating the memory system 110, such as write commands, read commands, configuration communications, or other operation communications. In some instances, the host system controller 120, or the associated functions described herein, may be implemented by or may be part of the processor 125. For example, a host system controller 120 may be hardware, instructions (e.g., software, firmware), or a combination thereof implemented by the processor 125 or other components of the host system 105. In various instances, a host system 105 or a host system controller 120 may be referred to as a host.

[0025] Memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by system 100. Memory system 110 may include a memory system controller 140 and one or more memory devices 145 operable to store data (e.g., memory packages, memory chips, portions of a memory chip). Memory system 110 can be configured to operate with different types of host systems 105 and can respond to commands from host system 105 (e.g., from a host system controller 120). For example, memory system 110 (e.g., a memory system controller 140) may receive a write command instructing memory system 110 to write one of the data received from host system 105, or a read command instructing memory system 110 to provide data stored in a memory device 145 to host system 105, or a re-read command instructing memory system 110 to re-store one of the data re-stored in a memory device 145, as well as other types of commands and operations.

[0026] A memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions supporting the memory system 110 in performing various operations, and is operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 is operable to communicate with one or more of a host system controller 120, one or more memory devices 145, or a processor 125. In some embodiments, the memory system controller 140 may cooperate with the host system controller 120, a local controller 150 of a memory device 145, or any combination thereof to control the operation of the memory system 110. Although an instance of memory system controller 140 is depicted as a separate component of memory system 110, in some instances, the functionality of memory system 110 may be implemented by at least one of a processor 125, a host system controller 120, one or more local controllers 150, or any combination thereof.

[0027] Each memory device 145 may include a local controller 150 (e.g., a logic controller, an interface controller, one or more processors) and one or more memory arrays 155. A memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array, an array of one or more semiconductor components), wherein each memory cell is operable to store data (e.g., as one or more stored bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, DRAM cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, NOR memory cells, and NAND memory cells, or any combination thereof.

[0028] A local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of a memory device 145. In some instances, the local controller 150 may be operable to communicate with a memory system controller 140 (e.g., to receive or transmit data or commands, or both). In some instances, a memory system 110 may not include a memory system controller 140 and a local controller 150, or a host system controller 120 may perform the functions of one of the memory system controllers 140 described herein. In some instances, the local controller 150 or a memory system controller 140, or both, may include a decoding component operable to access the address of a memory array 155, a sensing component for sensing the state of memory cells in the memory array 155, a writing component for writing state to memory cells in the memory array 155, or various other components operable to support the described operations of a memory system 110.

[0029] A host system 105 (e.g., a host system controller 120) and a memory system 110 (e.g., a memory system controller 140) may use one or more channels 115 to transmit information (e.g., data, commands, control information, configuration information). Each channel 115 may be an example of a transmission medium carrying information, and each channel 115 may include one or more signal paths (e.g., a transmission medium, an electrical conductor, a conductive path) between terminals (e.g., nodes, pins, contacts) associated with components of system 100. A terminal may be an example of a conductive input or output point of a device of system 100, and a terminal may operate as part of a channel 115. In some embodiments, at least one channel 115 between a host system 105 and a memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). To support communication via channel 115, a host system 105 (e.g., a host system controller 120) and a memory system 110 (e.g., a memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating the received signals, or an encoder for encoding or modulating the signals to be transmitted, and other components that support communication via channel 115, which may be included in a respective interface portion of their respective systems.

[0030] A channel 115 is dedicated to conveying one or more types of information, and channel 115 may include unidirectional channels, bidirectional channels, or both. For example, channel 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some instances, a channel 115 may be configured to provide power from one system to another (e.g., from host system 105 to memory system 110 according to a regulated voltage). In some instances, at least a subset of channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard) that supports the configured operation of a host system 105 and a memory system 110 and their interaction.

[0031] In some instances, at least a portion of system 100 may implement a stacked die architecture in which multiple semiconductor die entities are communicatively coupled (e.g., direct coupling, bonding). For example, one or more semiconductor dies (e.g., a single memory die, a stack of multiple memory dies) may be used to form at least one of the memory arrays 155 of a memory device 145, and these semiconductor dies may be stacked on top of another semiconductor die (e.g., a logic die) that includes at least a portion of a local controller 150. In some instances, a semiconductor die or die assembly may include at least a portion or all of a local controller 150 and at least a portion or all of a memory system controller 140, and this semiconductor die or die assembly may be coupled to one or more memory dies or a stack of one or more memory dies. According to these and other examples, the circuitry for accessing one or more memory arrays 155 (e.g., the circuitry for a memory system 110) may be distributed across multiple semiconductor dies in a stack (e.g., a stack of one of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., examples of memory interface blocks, first interface circuitry), and one or more second dies may include corresponding second interface blocks configured to access one or more memory arrays 155 of the second die, each coupled to a first interface block of the first die. In some examples, the system may include a controller for each set of one or more first interface blocks (e.g., at least a portion of a memory controller, an interface controller, a host interface controller, and a memory system controller 140) to support access operations (e.g., accessing one or more memory arrays 155) via that set of first interface blocks. In some instances, this controller may be located in a first die that is the same as the first interface block. In some instances, a plurality of semiconductor dies of a memory system 110 or a system 100 (e.g., an HBM system containing a configuration of a memory system 110, or a TCDRAM system containing a configuration of a memory system 110 and a host system 105) may include one or more array dies coupled to (e.g., a configuration containing the host system 105, or another die containing the host system 105) a logic die stack, the logic die including an interface block operable to access a set of memory arrays 155 distributed across one or more second dies.

[0032] Some systems 100 can be fabricated via one or more wafer-to-wafer bonding steps (e.g., blind wafer-to-wafer bonding steps, where unevaluated dies of two or more wafers are bonded together). Some wafer-to-wafer bonding techniques can be associated with a relatively high yield loss. Furthermore, some fabrication processes of a system 100 may not support structures for efficient heat dissipation. According to one or more examples described herein, a system 100 or at least a portion thereof can be formed based on a reconstructed wafer from a KGD (Known Gain Disposal). Additionally, the fabrication method of system 100 can be modified to support increased heat dissipation of system 100. For example, an interface block (e.g., a reconstructed wafer of the interface block) can be bonded to one or more memory stacks (e.g., memory device stack 145). The interface block can be formed with one or more probe pads, which can support the execution of one or more evaluation procedures. Next, the interface block can be bonded to a host chip (e.g., a host system 105), and the host chip is operable to couple with the interface block and control one or more functions of the interface block and one or more memory stacks. In some instances, the channel 115 providing coupling of the host system 105 to the memory system 110 may be a hybrid bonding pad. In some instances, an RDL may be formed over the host chip to provide power to the system 100 via the host chip. These techniques can improve the manufacturing yield of a semiconductor device and improve the ability of the manufactured semiconductor device to dissipate heat efficiently.

[0033] Figure 2 illustrates an example of a system 200 (e.g., a semiconductor system, a system coupled semiconductor dies, an HBM system, a TCDRAM system) supporting reconstruction of semiconductor die evaluation and power delivery according to examples disclosed herein. System 200 illustrates an example of a die 205 (e.g., die 205-a, a semiconductor die, a logic die, a processor die, a host die, a logic unit) coupled to one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, semiconductor dies, memory dies, array dies, memory cells). A die 205 or a die 240 may be formed using a respective semiconductor substrate (e.g., a substrate of a crystalline semiconductor material such as silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride), or a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG), silicon-on-sapphire (SOS)), or epitaxial semiconductor material formed on another substrate, and other examples. Although the illustrated example of system 200 includes two dies 240, a system 200 according to the described technology may include any number or more dies 240 coupled to a die 205 (e.g., 8, 12, 16 or more dies 240), and other dies in a stack or other coupled layout. Furthermore, although the non-limiting examples of system 200 herein are described generally in accordance with their suitability for memory systems, memory subsystems, memory devices or combinations thereof, examples of system 200 are not limited thereto. For example, the embodiments of the present invention can also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem for applications such as data collection, data processing, data storage, networking, communications, power, artificial intelligence, system-on-a-chip, control, telemetry, sensing and monitoring, digital entertainment or any combination thereof.

[0034] System 200 illustrates an example of an interface circuitry system implemented (e.g., partitioned between the semiconductor dies) in a plurality of semiconductor dies (e.g., a direct-coupled die stack) between a host and memory (e.g., via a host interface, via a physical host interface). For example, die 205-a may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 containing an interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, and die 240-a-2 containing an interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an instance of memory array 155 and may contain memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR or NAND memory cells, or any combination thereof.

[0035] Although an instance of system 200 is illustrated as having an interface block 245 contained in each die 240, according to the described technology, a die 240 may contain any number of interface blocks 245, each coupled to one or more memory arrays 250 of its own group, and each coupled to an interface block 220 of a die 205. Therefore, an interface circuitry system of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., for communication) to one or more interface blocks 245 of a die 240 (e.g., outside die 205). In some instances, a coupling combination of interface block 220 and interface block 245 (e.g., via a bus associated with one or more channels (such as one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof)) may contain or be referred to as a data path associated with one or more memory arrays 250 of their respective groups.

[0036] In some implementations (e.g., a TCDRAM implementation), a die 205 may include a host processor 210. A host processor 210 may be an instance of a host system 105, or a portion thereof (e.g., a processor 125, a host system controller 120, or both). The host processor 210 may be configured to perform operations implementing storage on the memory array 250 (e.g., to support an application or other function of the host system 105 that may request access to the memory array 250). For example, the host processor 210 may receive data read from the memory array 250, or may transfer data to be written to the memory array 250, or both (e.g., depending on an application or other operation of the host processor 210). Additionally or alternatively, a host processor 210 may be located outside of a die 205 (e.g., in an HBM implementation), such as in another semiconductor die or other component coupled to die 205 via one or more contacts 212 (e.g., externally accessible terminals of die 205) (e.g., communicatively coupled, directly coupled, bonded, coupled via another intermediary component).

[0037] A host processor 210 can be configured to communicate (e.g., transmit, receive) with interface block 220 via a host interface 216 (e.g., a physical host interface), which can implement the configuration of channel 115. In some instances, a host interface 216 can provide a communicative coupling between the physical or functional boundaries of a host system 105 and a memory system 110. For example, the host processor 210 can be configured to communicate access communications (e.g., control communications, access command communications, data communications, configuration communications) via a host interface 216 to support access operations (e.g., read operations, write operations) and other operations on memory array 250. Although an instance of system 200 includes a single host interface 216, a system according to the described technology may include any number or multiple host interfaces 216 for accessing the memory array 250 of the system.

[0038] In some instances, a respective host interface 216 may be coupled between a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2) and a respective controller 215. A controller 215 may be an example of a control circuitry system (e.g., a memory controller circuitry system, a host interface control circuitry system) associated with a host system 105, and may be associated with a respective instance implementing one or more forms of a host system controller 120 or a memory system controller 140 or a combination thereof. For example, a controller 215 may be operable to respond to instructions (e.g., requests, commands) from a host processor 210 to access one or more memory arrays 250 to support a function or application of the host processor 210, transmit associated commands (e.g., for one or more interface blocks 220) to access one or more memory arrays 250, and communicate data (e.g., write data, read data) with the host processor 210, as well as other functions.

[0039] In some instances, one or more controllers 215 may be implemented in a single die 205 (e.g., the same die containing one or more interface blocks 220), regardless of whether a host processor 210 is contained in or outside the die 205. In other instances, the controller 215 or associated circuitry or functionality may be implemented outside the die 205 (e.g., in another die not shown, coupled to the respective interface block 220 via respective terminals of the respective host interfaces 216), and the die 205 may be in the same or a different die than the one containing the host processor 210. An interface block 220 may be operated via a single controller 215 or by one or more of a group of controllers 215 (e.g., according to a controller multiplexing scheme). In some other instances, one or more controllers 215 may be contained within the host processor 210 (e.g., as a memory interface of the host processor 210, or as a memory interface of a host system 105).

[0040] While in some instances a controller 215 may be directly coupled to one or more interface blocks 220 (not shown), in other instances a controller 215 (e.g., a host interface 216) may be coupled to a group of interface blocks 220 via a logic block 225 (e.g., a logic circuitry for a channel group, a logic circuitry for a host interface 216, a multiplexing circuitry). For example, logic block 225 may be coupled to interface block 220-a-1 via bus 223-a-1 and to interface block 220-a-2 via bus 223-a-2. A controller 215 and one or more corresponding interface blocks 220 can communicate (e.g., collaborate) via a logic block 225 using a host interface 216 to perform one or more operations (e.g., scheduling operations, access operations, operations initiated by a host processor 210) associated with accessing a set of corresponding memory arrays 250.

[0041] In some instances, a logic block 225, a controller 215, or a host interface 216, or a combination thereof, may be associated with a "channel group" corresponding to one of a plurality of memory arrays 250 (e.g., for parallel or otherwise coordinated access to the plurality of memory arrays 250). For example, this channel group may be associated with a plurality of memory arrays 250 accessed via a single interface block 245, or a plurality of memory arrays 250 accessed via one of the respective interface blocks 245, or a plurality of memory arrays 250 accessed via one of the respective interface blocks 220, any of which may be associated with communications via a single logic block 225, via a single host interface 216, or via a single controller 215. Such and other configurations for implementing one or more channel groups in a system can support various techniques for parallel and high-bandwidth data transfer, memory management operations, repair and replacement techniques, or power and heat distribution, as well as other techniques utilizing the described coupling of components and interfaces in multiple semiconductor dies (e.g., according to a high-bandwidth memory configuration of system 200, according to a tightly coupled configuration of system 200). In some instances, these techniques can be implemented in a manner transparent to other aspects of the host interface 216 or a host system 105 (e.g., at or using a logic block 225).

[0042] In some instances, a host interface 216 may include one or more signal paths for each group of logical blocks 225 or interface blocks 220, such that the host processor 210 can communicate with each logical block 225 or interface block 220 via the signal path of its corresponding group (e.g., selected according to one of the corresponding groups to perform an access operation via one of the logical blocks 225 or interface blocks 220 selected by the host processor 210). Additionally or alternatively, a host interface 216 may be contained in multiple logic blocks 225 (not shown) or interface blocks 220 sharing one or more signal paths, and a logic block 225, an interface block 220, or a host processor 210, or any of these, may interpret, ignore, respond to, or suppress responses to communications via the shared signal paths of the host interface 216 based on a logical indication (e.g., an addressing indication associated with logic block 225 or interface block 220, an interface enable signal, or an interface select signal, which may be provided by the host processor 210, the corresponding logic block 225, or the corresponding interface block 220 depending on the direction of the communication).

[0043] In some instances, a host processor 210 may determine to access an address (e.g., a logical address of a memory array 250, a physical address of a memory array 250, an address of a logical block 225, an address of an interface block 220, or an address of a host interface 216, responding to an application of the host processor 210 or an application supported by the host processor 210), and determine which controller 215 to transmit the access message for accessing the address to (e.g., a controller 215, logical block 225, or interface block 220 corresponding to the address). In some instances, the address may be associated with a column memory cell of the memory array 250, a row memory cell of the memory array 250, or both. The host processor 210 may transmit access signals (e.g., one or more access signals, one or more access commands) to the determined controller 215, which may then transmit the access signals to the corresponding logic block 225 or interface block 220. The corresponding interface block 220 may then transmit the access signals to the coupled interface block 245 to access (e.g., a corresponding memory array 250) the determined address.

[0044] A die 205 may also include a logic block 230 (e.g., a common logic block, a central logic block, a common logic circuit system, an evaluation circuit system, a memory system configuration circuit system, a memory system management circuit system). The logic block 230 may be configured to communicate (e.g., transmit, receive) with the logic blocks 225, interface blocks 220, or both of the die 205. In some cases, a logic block 230 may be configured to communicate information (e.g., commands, instructions, indications, data) with one or more logic blocks 225 or interface blocks 220 to facilitate the operation of the system 200. For example, a logic block 230 may be configured to transmit configuration communications (e.g., initialization communications, evaluation communications, mapping communications), which may be received by logic block 225 or interface block 220 to support the configuration of logic block 225 or interface block 220, or (e.g., via respective interface blocks 245) operate other states of die 240. A logic block 230 may be coupled to each logic block 225 and each interface block 220 via a respective bus 231. In some instances, such buses may each contain one or more signal paths of their respective groups, such that a logic block 230 can communicate with each logic block 225 or each interface block 220 via the signal paths of its respective group. Additionally or alternatively, such buses may contain one or more signal paths (not shown) shared among multiple logic blocks 225 or interface blocks 220.

[0045] In some implementations, a logic block 230 may be configured to communicate (e.g., transmit, receive) with a host processor 210 via (e.g., via a bus, via a contact 212 for a host processor 210 external to a die 205), such that logic block 230 can support an interface between the host processor 210 and logic block 225 or interface block 220. For example, a host processor 210 may be configured to transmit initialization messages (e.g., power-on commands) or other configuration or operation messages, which may be received by logic block 230 to support the initialization, configuration, evaluation, or other operations of logic block 225 or interface block 220. Additionally or alternatively, in some embodiments, a logic block 230 may be configured to communicate (e.g., transmit, receive) with a component external to system 200 via a contact 234, which may be an externally accessible terminal of die 205, such that logic block 230 can support bypassing an interface of host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and with one or more dies 240 or memory arrays 250 (e.g., to perform a self-test operation for access to memory array 250). In some instances, during manufacturing, assembly, verification, or other operations associated with system 200 (e.g., for operation independent of a host processor before coupling with host processor 210, without implementing host processor 210), such embodiments may support evaluation, configuration, or other operations of system 200 via one or more contacts 234 accessible at a physical interface of system 200. Additionally or alternatively, a logic block 230 may implement one or more states of a controller 215. For example, a logic block 230 may contain or operate as one or more controllers 215, and may perform operations attributable to a controller 215.

[0046] In some instances, individual signals can be routed between a die 205 and one or more dies 240. For example, each interface block 220 can be coupled to at least one respective bus 221 of die 205 and one respective bus 246 of die 240, these buses being configured to communicate with a corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 can be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 can be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some instances, a die 240 may include a bus, such as a bus 255, that bypasses the operating circuitry of the die 240 (e.g., bypasses an interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via a bus 255-a-1 of die 240-a-1, with bus 255-a-1 bypassing interface block 245 of die 240-a-1. These techniques can be extended to interconnects in more than two dies 240 (e.g., for interconnects via respective buses 255 of multiple dies 240). In some embodiments, at least a portion of bus 221, bus 246, or bus 255, or any combination thereof, may include one or more conductors in a redistribution layer (RDL) of a respective die (e.g., above or below a semiconductor substrate of the die). Additionally or alternatively, in some embodiments, at least a portion of bus 221, bus 246, or bus 255, or any combination thereof, may include vias formed through one or more semiconductor substrates of a respective die (e.g., as one or more through-silicon vias (TSVs)).

[0047] The respective signal paths of buses 221, 246 and 255 can be coupled from one die to another via various contact configurations at the surface of the interfacing die (e.g., exposed contacts, the metal surface of the respective die). For example, bus 221-a-1 can be coupled to bus 246-a-1 via a contact 222-a-1 of die 205-a (e.g., on one of its surfaces) and a contact 247-a-1 of die 240-a-1; bus 221-a-2 can be coupled to bus 255-a-1 via a contact 222-a-2 of die 205 and a contact 256-a-1 of die 240-a-1; bus 255-a-1 can be coupled to bus 246-a-2 via a contact 257-a-1 of die 240-a-1 and a contact 247-a-2 of die 240-a-2, and so on. Although each individual bus is depicted as having a single line coupled via a single contact, it should be understood that each signal path of a given bus can be associated with a respective contact to support individual communicative coupling of each signal path of the given bus. In some instances, a bus 255 may traverse a portion of a die 240 (e.g., in a plane direction, along a direction different from a thickness direction, in a waterfall configuration, or in a stepped configuration), which may support a configuration of contacts 222 along a surface of a die 205 and one of other contacts coupled to interface blocks 245 of different dies 240 along a stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along a thickness direction).

[0048] Interconnection of interfacing contacts can be supported by various technologies. For example, in a hybrid bonding embodiment, interfacing contacts can be coupled by fusing one of their conductive materials (e.g., conductive materials) (e.g., without solder or other intermediary materials between the contacts). A hybrid bond can be an example of combining a dielectric bond (SiOx) with an embedded metal (Cu) to form a permanent bond for the interconnect. Hybrid bonding can achieve smaller bond pitch, higher memory cell density, improved communication above the conductive line, improved power distribution, and other benefits. Under one assembly condition, coupling of die 205-a to die 240-a-1 may involve fusing one conductive material of contact 222-a-2 with one conductive material of contact 256-a-1, and coupling of die 240-a-1 to die 240-a-2 may involve fusing one conductive material of contact 257-a-1 with one conductive material of contact 247-a-2, and so on. In some instances, this coupling may include invalid fusion of one of the contacts (e.g., a non-communicative coupling, a physical coupling), such as fusion of one of the contacts 260-a-1 and 256-a-2, neither of which is coupled to the operating circuitry of the die 240-a-1 or 240-a-2. In some instances, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260, which may not be operatively coupled to an interface block 245 or an interface block 220), or this coupling may be a byproduct of the repetition of components that may be operative or ineffective in various configurations (e.g., where for a die 240 having a common configuration of contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between an interface block 245 and an interface block 220).

[0049] In some instances, the fusion of one of the conductive materials between the dies (e.g., between contacts) may be accompanied by the fusion of one of the other materials at one or more surfaces of the interfacing dies. For example, under an assembly condition, the coupling of die 205 to die 240-a-1 may involve the fusion of a dielectric material 207 (e.g., a non-conductive material) of die 205-a to a dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 to die 240-a-2 may involve the fusion of a dielectric material 242 of die 240-a-1 to a dielectric material 242 of die 240-a-2. In some instances, such dielectric materials may comprise oxides, nitrides, carbides, oxynitrides, oxycarbonoxides, or other conversions or doping of a substrate material (e.g., a semiconductor substrate material) or other materials of die 205 or die 240, as well as other materials that may support this fusion. However, coupling between grains 205 and 240 can be implemented using other techniques, such as solder, adhesive, thermal interface materials and other intermediate materials or combinations thereof.

[0050] In some instances, dies 240 may be coupled into a stack (e.g., forming a "cube" or other configuration of one of the dies 240), and one or more of such stacks may subsequently be coupled to a die 205 (e.g., in a stack-to-wafer bonding configuration). In some instances, one or more dies 240 of each group may be coupled to each die 205 of a plurality of dies 205 formed in a wafer (e.g., before dicing the wafer of the die 205, in a wafer-to-wafer bonding configuration, in a stack-to-wafer bonding configuration), and the dies 205 of the wafers coupled to each of their respective groups of dies 240 may be separated from each other (e.g., by at least dicing the wafer of the die 205, by monolithization). In some other instances, after the die 205 is separated from the wafer of the die 205, one or more dies 240 of each group may be coupled to a respective die 205 (e.g., in a wafer-to-wafer bonding configuration). In some other instances, each of the groups of one or more wafers comprising a plurality of dies 240 may be coupled into a stack (e.g., in a wafer-to-wafer bonding configuration). In various instances, such techniques may subsequently separate the stack of dies 240 from the coupled wafer, or the wafer stack having dies 240 may be coupled to another wafer comprising a plurality of dies 205 (e.g., in a second wafer-to-wafer bonding configuration), after which the system 200 may be separated from the coupled wafer. In some other instances, in addition to those for forming the system 200, wafer-to-wafer coupling techniques may be implemented by stacking one or more wafers of dies 240 (e.g., sequentially) on top of one wafer of dies 205 prior to separation into the system 200.

[0051] Buses 221, 246, and 255 may be implemented to provide a configured communication (e.g., a coordinated communication, a logical communication, a modulated communication, a digital communication) between an interface block 220 and a corresponding interface block 245. This may involve various modulation or encoding techniques via a transport interface block (e.g., via a driver component of the transport interface block). In some instances, this communication may be supported (e.g., in coordination with signal transmission) by clock signals transmitted via the respective buses (e.g., accompanying). For example, the buses may be configured to transmit one or more clock signals transmitted by interface block 220 for reception by interface block 245 (e.g., to trigger signal reception by a latch or other receiving component of interface block 245 to support timing operation of interface block 245). Additionally or alternatively, the bus may be configured to transmit one or more clock signals transmitted by interface block 245 for reception by interface block 220 (e.g., to trigger signal reception by a latch or other receiving component of interface block 220 to support timing operation of interface block 220). These clock signals may be associated with communications of various types of communications, such as control communications, command communications, data communications, or any combination thereof (e.g., one-way communications, two-way communications, deterministic communications). For example, a bus may include one or more signal paths for transmitting a data bus (e.g., one or more data channels, a DQ bus, via a data interface of an interface block) based on one or more corresponding clock signals (e.g., data clock signals), or for transmitting one or more signal paths for transmitting a control bus (e.g., a command / address (C / A) bus, via a command interface of an interface block) based on one or more clock signals (e.g., control clock signals), or any combination thereof.

[0052] Interface block 220, interface block 245, logic block 225, and logic block 230 may each contain circuitry (communication circuitry, multiplexing circuitry, processing circuitry, controller circuitry, logic circuitry, physical components, hardware) in various configurations (e.g., hardware configuration, logic configuration, software configuration, or instruction configuration), which support the functionality allocated to their respective blocks for accessing or otherwise operating a corresponding set of memory arrays 250. For example, interface block 220 may contain circuitry configured to perform a first subset of operations supporting access to memory array 250, and interface block 245 may contain circuitry configured to perform a second subset of operations supporting access to memory array 250. In some instances, interface block 220, interface block 245, and logic block 225 may support functional partitioning or distribution across multiple dies (e.g., die 205 and at least one die 240) associated with a memory system controller 140, a local controller 150, or both. In some implementations, a logic block 230 may be configured to coordinate or configure the operation of interface block 220, interface block 245, logic block 225, or a combination thereof, and may support the implementation of one or more modes of a memory system controller 140. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or a controller 215, or operations performed without commands from host processor 210 or a controller 215 (e.g., operations determined or initiated by a logic block 225, operations determined or initiated by an interface block 220, operations determined or initiated by an interface block 245, operations determined or initiated by a logic block 230), or various combinations thereof.

[0053] In some implementations, system 200 may include one or more examples of non-volatile storage devices (e.g., non-volatile storage device 235 of a die 205, non-volatile storage devices 270 of one or more dies 240, or combinations thereof). In some instances, a logic block 230, logic block 225, interface block 220, interface block 245, or combinations thereof may be configured to communicate with one or more examples of non-volatile storage devices. For example, where applicable, a logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more examples of non-volatile storage devices via one or more buses (not shown) or respective contacts (not shown), each of which may include one or more signal paths operable to transmit communications (e.g., command communications, data communications). In some instances, a logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, can configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of the non-volatile storage device. Additionally or alternatively, in some instances, a logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, can be written with information (e.g., configuration information, evaluation information) to be stored in one or more instances of the non-volatile storage device. In some instances, this non-volatile storage device may include fuses, antifuses, or other types of one-time programmable storage elements, or any combination thereof.

[0054] In some embodiments, system 200 may include one or more sensors (e.g., one or more sensors 237 of a die 205, one or more sensors 275 of a die 240, or a combination thereof). In some embodiments, a logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements from one or more sensors of system 200. For example, a logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more sensors via one or more buses (not shown) or respective contacts (not shown). These sensors may include temperature sensors, current sensors, voltage sensors, counters, or other types of sensors. In some instances, a logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, can be configured with one or more operations based on the output of one or more sensors. For example, a logic block 230 can be configured with one or more operations of logic block 225 or interface block 220 based on signals (e.g., indications, data) received from one or more sensors. Additionally or alternatively, a logic block 225 or an interface block 220 can generate access signals for transmission to a corresponding interface block 245 based on one or more sensors.

[0055] In some instances, a circuit system comprising logic block 225, interface block 220, interface block 245, or a logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least partially by doped portions of a substrate of a respective die. In some instances, a substrate of die 205 may have characteristics (e.g., material, material properties, physical shape, or size) different from those of a substrate of die 240. Additionally or alternatively, in some instances, a transistor formed from a substrate of die 205 may have characteristics (e.g., manufacturing characteristics, performance characteristics, physical shape, or size) different from those of a transistor formed from a substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0056] In some instances, interface block 220 may support the layout of one or more components within interface block 220. For example, the layout may include paired components for sharing an access port (e.g., a command port, a data port). Additionally, in some instances, the layout may support an interface for a controller 215 (e.g., a host interface 216) that differs from the interface for an interface block 245 (e.g., via bus 221). For example, a host interface 216 may be synchronous and have separate channels for read and write operations, while one of the interfaces between interface block 220 and one or more interface blocks 245 may be asynchronous and support read and write operations using the same channel. In some instances, a deterministic timing (e.g., a deterministic timing between a controller 215 and a logic block 225 or one or more interface blocks 220) may be used to implement communication between a host interface 216. This deterministic timing may be associated with a configured timing between a first signal and a response second signal. In some instances, a timing different from that of a host interface 216 (e.g., based on a different clock frequency, based on a timing offset, such as a phase offset) may be used to implement communication between an interface block 220 and one or more interface blocks 245. This timing may be deterministic or non-deterministic.

[0057] A die 240 may include one or more cells 265 (e.g., modules) that are separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of the cells 265. Although each die 240 of system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described technology may include any number of cells 265, which may be arranged in various patterns (e.g., groups of one or more cells 265 along a column direction, groups of one or more cells 265 along a row direction, and other patterns). Each cell 265 may include at least a circuit system of a respective interface block 245, and (a plurality of) memory arrays 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the respective interface block 245. In some instances, where applicable, each cell 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., associated with a respective interface block 245 of a cell 265 of a different die 240), which may support varying degrees of stackability or modularity in or via cells 265 of other dies 240. Although instances of the nonvolatile storage device 270 and sensor 275 are depicted external to cell 265, in some other instances, the nonvolatile storage device 270, sensor 275, or both may be additionally or alternatively included in cell 265.

[0058] In some instances, interface block 220 may include circuitry configured to receive a first access command message (e.g., from a host processor 210, from a controller 215, from a logic block 225, via a host interface 216, via one or more contacts 212 from a host processor 210 or controller 215 outside a die 205, based on a request from a host application), and to transmit a second access command message to (e.g., in response to) the received first access command message to (e.g., coupled to) the respective interface block 245. Interface block 245 may correspondingly include circuitry configured to receive a second access command message from its respective interface block 220, and in some instances to access (e.g., in response to) the received second access command message to one or more memory arrays 250. In various instances, the first access command message may include an access command associated with an operation type (e.g., a read operation, a write operation, a rewrite operation, a memory management operation), which may be associated with an indication of one or more addresses (e.g., a logical address, a physical address) of the memory array 250. In some instances, the first access command message may include an indication of a logical address associated with the memory array 250, and the circuitry of an interface block 220 may be configured to generate a second access command message indicating a physical address associated with the memory array 250 (e.g., a column address, a row address, using a logic-to-entity (L2P) table, or other mapping or computational functionality of the interface block 220).

[0059] In some instances, to support write operations of system 200, the circuitry of interface block 220 can be configured (e.g., from a host processor 210, from a controller 215, from a logic block 225) to receive a first data message associated with a first access command message, and to transmit a second data message (e.g., associated with a second access command message) based on the received first access command message and the first data message. Interface block 245 can be configured accordingly to receive the second data message, and to write data to one or more memory arrays 250 (e.g., according to an address indicated by one associated with the first access command message) based on the received second access command message and the second data message. In some instances, interface block 220 may include an error control function (e.g., an error detection circuitry, an error correction circuitry, error correction code (ECC) logic, an ECC engine) that supports interface block 220 in generating a second data message based on performing an error control operation using the received first data message (e.g., detecting or correcting an error in the first data message, determining that it is to be transmitted in the second data message and written to one or more corresponding bits along with the data).

[0060] In some instances, to support read operations of system 200, the circuitry of interface block 245 can be configured to read data from memory array 250 based on a received second access command message, and transmit a first data message based on the read data. Interface block 220 can be correspondingly configured to receive the first data message, and transmit a second data message based on the received first data message (e.g., to a host processor 210, to a controller 215, to a logic block 225). In some instances, interface block 220 may include an error control functionality that supports interface block 220 in generating a second data message based on performing an error control operation using the received first data message (e.g., detecting or correcting an error in the first data message, which may involve calculations involving one or more co-occurring bits received with the first data message).

[0061] In some instances, access command messages and other messages transmitted to interface block 245 may be generated based on various determination or generation techniques configured at interface block 220 or logic block 225 (e.g., based on an access command message received from a host processor 210, a start message received from a host processor 210, without receiving or otherwise independently of messages from a host processor 210). In some instances, such techniques may involve communication or other coordination with a logic block 230, a logic block 225, a host processor 210, one or more controllers 215, one or more examples of non-volatile storage devices, one or more sensors, or any combination thereof. These technologies can support the configuration of interface block 220 or logic block 225 for access operations and other operations performed on memory array 250 via a respective interface block 245. For example, interface block 220 or logic block 225 may include evaluation circuitry, access configuration circuitry, communication circuitry, scheduling circuitry, repair circuitry, regeneration circuitry, error control circuitry, adverse access (e.g., hammer) mitigation circuitry, and other circuitry operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0062] In some instances, the functionality of a die 205 can be implemented by forming a semiconductor unit (e.g., a semiconductor system) having multiple semiconductor die portions (e.g., semiconductor wafers, relatively small semiconductor dies), and each die portion may contain a respective portion of a circuit system associated with the die 205. For example, a unit 280 may represent a portion of a circuit system component contained in a die portion (e.g., contained in a wafer), and the die portion may contain an integer multiple of units 280. In some instances, each semiconductor die portion of a semiconductor unit may contain different respective portions of a circuit system. As a non-limiting example, a semiconductor unit (e.g., having the functionality of a die 205) may be formed from one or more first die portions having one or more units 280-a-1 and one or more second die portions having one or more units 280-a-2. One or more units 280-a-1 may include one or more interface blocks 220, a logic block 225 or any combination thereof, and one or more units 280-a-2 may include a host processor 210, one or more controllers 215, a logic block 230 or any combination thereof.

[0063] Some systems 200 can be fabricated via one or more wafer-to-wafer bonding steps (e.g., blind wafer-to-wafer bonding steps, where unevaluated dies of two or more wafers are bonded together). Some wafer-to-wafer bonding techniques can be associated with a relatively high yield loss. Furthermore, some fabrication processes of a system 200 (or a portion thereof) may not support structures for efficient heat dissipation. According to one or more examples described herein, a system 200 can be formed based on a reconstructed wafer from a KGD (Known Gain Disposal). Additionally, fabrication methods can be modified to support increased heat dissipation for the system 200. For example, a reconstructed wafer of an interface block (e.g., a die 205 containing one or more interface blocks 220) can be bonded to a reconstructed wafer of one or more memory stacks (e.g., one or more die stacks 240). The interface blocks can be formed with one or more probe pads, which can support the execution of one or more evaluation procedures. Next, the interface block can be bonded to a host chip (e.g., a host system external to die 205), and the host chip can be operated to couple with the interface block and control one or more functions of the interface block and one or more memory stacks. In some instances, an RDL can be formed on top of the host chip to provide power to system 200 via the host chip. These techniques can improve the manufacturing yield of a semiconductor device and improve the ability of the manufactured semiconductor device to dissipate heat efficiently.

[0064] Figure 3 illustrates one example of an architecture 300 that supports reconstructed semiconductor die evaluation and power delivery, as illustrated in the examples disclosed herein. Architecture 300 may include an interface block 305 (e.g., interface logic, a logic chip, a die 205, an interface block 220, a logic layer), one or more memory stacks 345 (e.g., TCDRAM, memory device 145) (each memory stack 345 includes one or more memory chips 340 (e.g., memory chips 340-a and 340-b, die 240, DRAM die, memory array die, local controller 150, memory array 155)), a host chip 310 (e.g., a GPU, a host system 105, a host die, a host processor 210, a unit 280), a substrate 315 (e.g., a dummy layer, a silicon layer), and one or more pads 320 (e.g., solder contacts), which may represent or include instances of the respective components as described herein (including references to Figures 1 and 2). Although Figure 3 illustrates a non-limiting example architecture 300, architecture 300 may include any number of memory stacks 345, interface blocks 305, host chips 310, and pads 320.

[0065] In some cases, architecture 300 may be formed (e.g., manufactured) via one or more wafer-to-wafer bonding steps. As an example, a first wafer may include multiple interface blocks 305 and may be bonded to a second wafer that may include one of memory stacks 345 and a third wafer that includes multiple host chips 310. After bonding, the respective assemblies (e.g., a bonded combination of an interface block 305, one or more memory stacks 345, and one host chip 310) may be diced for individual packaging. However, in some cases, a wafer may include operable dies (e.g., good dies) and defective dies (e.g., bad dies, inoperable dies, faulty dies), and this wafer-to-wafer bonding may occur without performing an evaluation procedure on the respective wafers. Therefore, in some cases, one or more good dies (e.g., an operable interface block 305) may be bonded to one or more bad dies (e.g., a bad host chip 310), which may result in the rejection and discarding of some good dies. Therefore, such manufacturing techniques may result in reduced manufacturing yield and increased waste due to the rejection of good dies (e.g., bonded to defective dies). Furthermore, an architecture 300 may be formed such that one or more memory stacks 345 are located above the interface block 305 and the host chip 310. This architecture 300 may be associated with a relatively high heat concentration (e.g., at the host chip 310 and interface block 305), which may lead to device degradation and reduced performance.

[0066] According to one or more examples described herein (e.g., including references to Figures 4 through 13), an architecture 300 (e.g., a semiconductor device, an HBM system, a TCDRAM system, a heterogeneous semiconductor device) can be formed (e.g., manufactured) based on a wafer reconstructed from a known good interface block 305 (e.g., a known good host chip 310, a known good memory stack 345) and assembled with one or more first wafers (e.g., diced from one or more first wafers) to form a reconstructed wafer. In some instances, "dicing" can refer to the process in which one or more dies are separated from a wafer of one of the dies (e.g., via sawing, laser dicing, scribing, breaking, etching, or other separation techniques) to form an individual die wafer. In some instances, a "reconstructed wafer" may refer to a wafer comprising multiple dies (e.g., wafers, die portions) previously diced from other wafers and reassembled (e.g., aggregated, combined) based on a dielectric material (e.g., a dielectric silicon oxide interstitial filler material). Therefore, a reconstructed wafer may contain a relatively large proportion of KGD compared to one or more original formed wafers from which it was diced. Thus, the individual components of architecture 300 can be verified as KGD before being bonded to other components. Consequently, the described examples provide a manufacturing process based on the bonding of multiple reconstructed wafers, which can increase (e.g., architecture 300) a manufacturing yield.

[0067] Furthermore, one or more examples as described herein (e.g., including references to Figures 4 through 13) can support an improved capability for efficient heat dissipation of the architecture 300, resulting in improved device performance. For example, a semiconductor device can be formed such that one or more memory stacks 345 are formed below interface block 305 and host chip 310 is formed above interface block 305, which can support improved heat distribution (e.g., based on the host chip 310 being relatively closer to a substrate material or other heat sink element). Additionally, interface block 305, host chip 310, and one or more memory stacks 345 can be formed with one or more conductive pads (e.g., probe contacts) to provide an evaluation interface for verifying the operability of interface block 305, host chip 310, and one or more memory stacks 345, or any combination thereof. These conductive pads can support intermediate evaluation procedures during a formation process. By forming semiconductor devices according to one or more of the examples described herein, such as systems of architecture 300, a more testable design and increased efficient heat dissipation can be achieved, which may result in improved manufacturing yield, reduced waste, and improved device performance and reliability.

[0068] Some examples and operations described herein can be described with reference to the various sides of a respective component (e.g., an interface block 305, a host chip 310, a memory stack 345, a memory chip 340, or another component). For example, one side of a component may be referred to as a "back side" or a "front side". A "back side" of a component may refer to a side that is the same as a substrate material (e.g., a silicon substrate) (e.g., a substrate used for mechanical support during formation) on which the component is formed. A "front side" of a component may refer to a side opposite to the substrate material on which the component is formed (e.g., opposite to the back side).

[0069] Figures 4 through 13 illustrate examples of operations for forming a semiconductor device 400 (e.g., a heterogeneous device, a heterogeneous semiconductor system, a heterogeneous HBM system, a heterogeneous TCDRAM system) using reconstructed semiconductor die evaluation in a stacked memory architecture, as disclosed herein. For example, Figures 4 through 13 may illustrate a series of operations that can support the manufacture of a system 100 or a portion thereof, a system 200 or a portion thereof, or another device as described herein, which can increase device yield and improve device reliability during manufacturing. Reference can be made to the x-direction, y-direction, and z-direction diagrams of coordinate system 401. The operations illustrated in and described with reference to Figures 4 to 13 can be performed by a manufacturing system (such as a semiconductor fabrication system configured to perform additive operations (e.g., deposition, epitaxy, bonding), subtractive operations (e.g., etching, grooving, planarization, polishing), modification operations (e.g., oxidation, doping, reaction, conversion), and supporting operations (e.g., masking, patterning, photolithography, alignment), as well as other operations supporting the described techniques). In some instances, portions of the semiconductor device 400 illustrated with the same pattern may be formed of the same or similar materials, and portions illustrated with different patterns may be formed of different materials.

[0070] Figure 4 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a first set. For example, the first set of operations may include forming one or more memory stacks 445 (e.g., TCDRAM, die stack 240, memory device 145). In some instances, at least six memory stacks 445 may be present. In some other instances, at least eight memory stacks 445 may be present. Each of the memory stacks 445 may each include one or more memory wafers 440 (e.g., die 240, DRAM wafer including one or more memory arrays) positioned (e.g., formed) on a carrier material 402 (e.g., including a sacrificial silicon material 416 and one or more dielectric materials 422). Although Figure 4 illustrates a non-limiting example in which each memory stack 445 includes a memory chip 440-a (e.g., a first-core DRAM) and a memory chip 440-b (e.g., a second-core DRAM), each memory stack 445 may include any number of memory chips 440, and any number of memory stacks 445 may be formed on carrier material 402. Each memory stack 445 may be formed using wafer-to-wafer bonding, wafer-to-wafer bonding, or wafer-to-wafer bonding. In some instances, wafer-to-wafer bonding may be used when the distance between the pads between two memory chips (e.g., memory chips 440-a and 440-b) is extremely small. Each memory chip 440 may be formed having a respective substrate material 404 (e.g., a silicon substrate) and each having one or more dielectric materials 406. In Figure 4, a memory chip 440-a may include a respective substrate material 406-a and a memory chip 440-b may include a respective substrate material 406-b. One or more dielectric materials 406 may include one or more layers of silicon oxide, one or more layers of silicon carbide nitrate, or other dielectric materials, which may be formed around a circuit system (such as a transistor (e.g., CMOS) cell circuit system). In some instances, one or more dielectric materials 406 may be a mid-stage (MOL) or back-end (BEOL) dielectric layer.

[0071] In some instances, forming one or more memory stacks 445 may include forming a plurality of vias 408 through one side (e.g., a back side) of each memory stack 445 (e.g., each memory chip 440 of each memory stack 445) (which is the same side as its respective substrate material 404 (e.g., a substrate material 404-a)). Forming vias 408 may include forming a plurality of corresponding cavities and depositing a conductive material (e.g., copper) in each of the cavities. In some instances, a single or dual damascene process may be used to form the vias 408. Alternatively, a via-to-live (VL) process or a via-to-middle (VM) process may be used to form such a plurality of vias 408. Each memory chip 440 may further include one or more conductive pads 410 (e.g., hybrid bonding pads, copper material), which may support bonding (e.g., wafer-to-wafer hybrid bonding based on alignment of one or more alignment features 414) to one or more other memory chips 440. In some instances, one or more memory stacks 445 may be bonded to other components (e.g., an interface block) based on vias 408, one or more conductive pads 410, or both. Each via 408 may provide an interface (e.g., an electronic coupling) for the circuitry 412 (e.g., interconnect circuitry, back-end process (BEOL) circuitry) of each memory chip 440.

[0072] In some instances, the side of one or more memory stacks 445 opposite to a substrate material 404 (e.g., a front side) (e.g., the side of the memory chip 440-a of one or more memory stacks 445) may be bonded to a carrier material 402 (e.g., before bonding with other components). In some instances, one or more memory stacks 445 may be bonded (e.g., stacked to a wafer by fusion bonding) to one or more dielectric materials 422 (e.g., comprising a dielectric silicon oxide material, a silicon carbide nitrate material, or both). Furthermore, in some instances, bonding one or more memory stacks 445 to the carrier material 402 may be performed by fusion bonding. Bonding may be based on aligning one or more alignment features 420 of the carrier material 402 with one or more alignment features 414 of the memory chip 440. One or more memory stacks 445 may be placed on a carrier material 402, which can facilitate the handling of a very thin substrate volatile memory (e.g., memory chips 440-a and 440-b).

[0073] Figure 5 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a second set. For example, the second set of operations may include forming (e.g., depositing) one or more dielectric materials 502 (e.g., silicon oxide interstitial material) between the memory stacks 445 of one or more memory stacks 445. The dielectric materials 502 may be formed after bonding one or more memory stacks to a carrier material 402 (e.g., a sacrificial carrier). In some instances, forming one or more dielectric materials 502 may be part of a reconstruction of a known good memory wafer 440 (e.g., KGD, TCDRAM reconstruction). Additionally, the dielectric materials 502 may include one or more alignment features 508 to support alignment with other components (e.g., an interface block).

[0074] The second set of operations may further include forming one or more conductive pads 504 (e.g., hybrid bonding pads formed of a copper material) in one side (e.g., a back side) of each memory chip 440 (e.g., each memory chip 440-b, each top memory chip 440). Forming one or more conductive pads 504 may include planarizing one or more substrate materials 404 of one or more memory stacks 445 (e.g., removing a portion of substrate material 404) (e.g., removing a portion of substrate material 404-b). One or more conductive pads 504 may be coupled to one or more vias 408 (e.g., in a formed TSV, conductive pad 504-a may be coupled to a via 408-a and conductive pad 504-b may be coupled to a via 408-b). In some instances, bonding one or more memory stacks 445 to other components (e.g., an interface block) may be based on one or more conductive pads 504.

[0075] Figure 6 illustrates a portion of a semiconductor device 400 following one or more third set of manufacturing operations. For example, the third set of operations may include forming an interface block 605. Interface block 605 may include a logic circuitry configurable to operate one or more memory arrays of one or more memory stacks 445. Interface block 605 may include a substrate material 602 (e.g., an interface logic silicon substrate) and one or more dielectric materials 604 (e.g., comprising one or more layers of silicon oxide, one or more layers of silicon carbide nitrate, or other dielectric materials). The substrate material 602, the one or more dielectric materials 604, or both may include (or be formed around) circuitry such as circuitry 606 (e.g., interconnect circuitry, BEOL circuitry), transistor circuitry (e.g., CMOS circuitry), and other circuitry. Interface block 605 may be formed to include one or more conductive pads 608 (e.g., hybrid bonding pads) on a first side (e.g., a front side) opposite to the substrate material 602.

[0076] Forming interface blocks 605 can be based on a wafer reconstruction process, which may include forming a first wafer of one of a plurality of interface blocks 605. Each interface block 605 may be tested to determine whether it is defective (e.g., based on failure to meet one or more performance expectations) or operable (e.g., based on meeting one or more performance expectations). The first wafer may be diced to separate defective interface blocks 605 from operable interface blocks 605. Each interface block 605 of the semiconductor device 400 may be selected for reconstruction based on the determination that the interface blocks 605 are operable. In some instances, a second wafer containing one of operable interface blocks 605 may be formed based on combining selected interface blocks 605.

[0077] In some instances, a first side (e.g., the front side) of interface block 605 (e.g., a KGD interface logic chip) may be bonded (e.g., via a wafer-to-wafer front-to-back hybrid bonding, via a wafer-to-wafer front-to-back hybrid bonding) to one or more memory stacks 445 (e.g., the back side), which is the same side as one of the substrate materials 404 of the memory stacks 445. Unlike in FIG3, the circuitry and layout for one or more memory stacks 445 may be designed to enable communication between the front side of interface block 605 and the back side of volatile memory stacks 445, wherein the circuitry and layout for one or more memory stacks 345 may be designed to enable communication between the back side of interface block 305 and the front side of volatile stacks 345. Bonding may be based on one or more conductive pads 608, one or more conductive pads 504, or both. The interface block 605 may include forming a plurality of vias 610 (e.g., TSVs, formed by forming cavities and depositing a conductive material such as copper) through a second side (e.g., a back side) of the interface block 605, which is the same side as the substrate material 602. The interface block 605 may further include forming one or more conductive pads 612 (e.g., contacts formed of an aluminum material, an aluminum RDL) on the second side of the interface block 605. The vias 610 may be coupled to a respective conductive pad 612 and a respective circuit system 606 (e.g., providing an interface therebetween). In some instances, the one or more conductive pads 612 may be coupled to the vias 610 via (e.g., formed prior to the one or more conductive pads 612) one or more respective tungsten contacts. Interface block 605 may further include one or more contacts 614 (e.g., aluminum contacts to support coupling between one or more conductive pads 608 and one of their respective circuit systems 606) and one or more alignment features 616 (e.g., to support alignment with one or more memory stacks 445). Although the example of semiconductor device 400 shows two memory stacks 445 bonded to interface block 605, semiconductor device 400 may include any number of memory stacks 445 bonded to any number of interface blocks 605 (e.g., at least one interface block 605 coupled to at least eight memory stacks 445).

[0078] In some instances, the third set of operations may further include forming (e.g., depositing) one or more dielectric materials 618 (e.g., silicon oxide interstitial filler material) around the interface block 605 (e.g., which may electrically insulate the interface block 605). These instances may be applied when the interface block 605 is bonded to an individual wafer of one or more memory stacks 445 (e.g., not formed as part of a rebuilt wafer). Additionally or alternatively, bonding the interface block 605 to one or more memory stacks 445 may be based on forming a second wafer (e.g., a rebuilt wafer), and one or more dielectric materials 618 may be associated with the reconstruction of the second wafer.

[0079] The third set of operations may further include performing one or more evaluation procedures on the interface block 605 and one or more memory stacks 445. The evaluation procedures may be based on probing one or more conductive pads 612 on the second side (e.g., the back side) of the interface block 605 (e.g., using one or more probes 620 or other evaluation circuitry). The evaluation procedures may be performed based on bonding the interface block 605 to one or more memory stacks 445. Therefore, this evaluation step (e.g., a first evaluation) can increase the manufacturing yield of one of the semiconductor devices 400 by verifying the operability of the package (e.g., the bonding combination of one or more memory stacks 445 and the interface block 605) before performing further manufacturing operations.

[0080] Figure 7 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a fourth group. For example, the fourth group of operations may include forming one or more dielectric materials 702. The one or more dielectric materials 702 may comprise one or more layers of silicon oxide, one or more layers of silicon carbide nitrate, or other dielectric materials. The one or more dielectric materials 702 may be formed (e.g., in a z-direction) over one side (e.g., a back side) of the interface block 605, which is the same side as one of the substrate materials 602 of the interface block 605. The one or more dielectric materials 702 may be formed having one or more conductive pads 704 (e.g., hybrid bonding pads). One or more conductive pads 704 can be performed as a multi-step process (e.g., a dual damascene process), wherein one or more first cavities are formed at a first depth (e.g., for one or more vias 706), and one or more second cavities are formed at a second depth (e.g., for one or more surfaces of the conductive pads 704), and both the first and second cavities are concurrently filled with a conductive material (e.g., copper). One or more dielectric materials 702 may also include one or more alignment features 708 to support alignment with other components. In some instances, interface blocks 605 (e.g., the back side of interface blocks 605) may be bonded to other components (e.g., a host chip) based on one or more conductive pads 704, one or more alignment features 708, or both.

[0081] In some instances, the fourth set of operations may further include forming an RDL (not shown) over one or more dielectric materials 702 (e.g., following a similar fabrication operation to one of the RDLs described herein (including references to Figures 10 and 11)). This RDL may include one or more conductive pads operable to couple the interface block to a power delivery network (e.g., including one or more relatively low-resistance vias), a host chip, or any combination thereof. In some instances, after the fifth set of fabrication operations, the semiconductor device 400 may be ready for packaging, which may include separating (e.g., dicing) multiple semiconductor devices 400 (e.g., formed on the same carrier) from each other. That is, the semiconductor device 400 may be packaged for delivery without additional fabrication operations (e.g., without being bonded to a host chip, the semiconductor device 400 may not include a GPU). These methods enable the separate fabrication of the interface block 605 and combinations of one or more memory stacks 445, as well as other external components (e.g., a host system).

[0082] Figure 8 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a fifth group. For example, the fifth group of operations may include forming a host chip 805. The host chip 805 may include a GPU operable to control the interface block 605, one or more memory stacks 445, or one of the functions of both. The interface block 605 may include a substrate material 802 (e.g., a GPU silicon substrate) and one or more dielectric materials 804 (e.g., comprising one or more layers of silicon oxide, one or more layers of silicon nitrate, or other dielectric materials). The substrate material 802, one or more dielectric materials 804, or both may include (or be formed around) circuitry such as circuitry 806 (e.g., interconnect circuitry, BEOL circuitry), transistor circuitry (e.g., CMOS circuitry), and other circuitry. The host chip 805 may be formed to include one or more conductive pads 808 (e.g., hybrid bonding pads) on a first side (e.g., a front side) opposite to the substrate material 802.

[0083] The formation of host chip 805 can be based on a wafer reconstruction process, which may include forming a first wafer of one of a plurality of host chips 805. Each host chip 805 may be tested to determine whether it is defective (e.g., based on failure to meet one or more performance expectations) or operable (e.g., based on meeting one or more performance expectations). The first wafer may be diced to separate defective host chips 805 from operable host chips 805. Each host chip 805 of the semiconductor device 400 may be selected for reconstruction based on the determination that the host chip 805 is operable. In some instances, a second wafer containing one of operable host chips 805 may be formed based on the combination of selected host chips 805.

[0084] In some instances, one side (e.g., a back side) of an interface block 605 that is the same side as a substrate material 602 can be bonded (e.g., via wafer-to-wafer front-to-back hybrid bonding, via wafer-to-wafer front-to-back hybrid bonding) to a first side (e.g., a front side) of a host chip 805 (e.g., a KGD host chip). In some instances, if a wafer-to-wafer configuration is used, one or more dielectric materials 604 or one or more dielectric materials 804, or both, can span the entire semiconductor device 400. Alternatively, if a wafer-to-wafer configuration is used, one or more dielectric materials 604 can span the length of the interface block 605 and one or more dielectric materials 804 can span the length of the host chip 805. Bonding can be based on one or more conductive pads 808, one or more conductive pads 704, or both. Forming a host wafer 805 may include forming a plurality of vias 810 (e.g., TSVs, through which a conductive material such as copper is deposited and a cavity is formed) through a second side (e.g., a back side) of the host wafer 805, which is the same side as the substrate material 802. Forming a host wafer 805 may further include forming one or more conductive pads 812 (e.g., contacts formed of an aluminum material, an aluminum RDL) on the second side of the host wafer 805. The vias 810 may be coupled to a respective conductive pad 812 and a respective circuit system 806 (e.g., providing an interface therebetween). In some instances, the one or more conductive pads 812 may be coupled to the vias 810 via (e.g., formed prior to the one or more conductive pads 812) one or more respective tungsten contacts. The host chip 805 may further include one or more contacts 814 (e.g., aluminum contacts to support coupling between one or more conductive pads 808 and one of their respective circuit systems 806) and one or more alignment features 816 (e.g., to support alignment with interface block 605). That is, one or more conductive pads 808 and one or more conductive pads 704 (e.g., hybrid bonding copper pads) may be surrounded by two aluminum layers (e.g., containing one or more contacts 814 and one or more conductive pads 612). In some embodiments, vias 810 of the host chip 805 may be aligned with vias 610 of the interface block 605.

[0085] In some instances, the fifth set of operations may further include forming (e.g., depositing) one or more dielectric materials 818 (e.g., silicon oxide interstitial filler material) around the host chip 805 (e.g., which can electrically insulate the host chip 805). These instances may be applied when the host chip 805 is bonded to an individual chip of the interface block 605 (e.g., not formed as part of a reconstructed wafer). Additionally or alternatively, bonding the host chip 805 to the interface block 605 may be based on the formation of a second wafer (e.g., a reconstructed wafer), and one or more dielectric materials 818 may be associated with the reconstruction of the second wafer. Thus, based on the fifth set of operations, both an interface block 605 and a host chip 805 (e.g., stacked in a front-to-back configuration) may be stacked on top of one or more memory stacks 445 (e.g., also stacked in a front-to-back configuration).

[0086] In some instances, interface block 605 and host chip 805 (e.g., a die in a logic device stack) may have the same lateral dimensions (e.g., the same length along one width direction of semiconductor device 400). These identical dimensions facilitate wafer-to-wafer integration. In some alternative instances, interface block 605 and host chip 805 may have different lateral dimensions (e.g., different respective lengths along one width direction of semiconductor device 400). In these instances, one or more dielectric materials (e.g., silicon oxide) may be located on the side of any die (e.g., interface block 605, host chip 805) having a relatively smaller lateral dimension than the other die.

[0087] The fifth set of operations may further include performing one or more evaluation procedures on the host chip 805, interface block 605, one or more memory stacks 445, or any combination thereof. The one or more evaluation procedures may be based on probing one or more conductive pads 812 on a second side (e.g., the back side) of the host chip 805 (e.g., using one or more probes 820 or other evaluation circuitry). Evaluation procedures may be performed based on bonding the host chip 805 to the interface block 605. Therefore, this intermediate evaluation step (e.g., a second evaluation) may further increase the manufacturing yield of one of the semiconductor devices 400 by verifying the operability of the package (e.g., the bonding combination of the host chip 805, interface block 605, and one or more memory stacks 445) before performing additional manufacturing operations.

[0088] Figure 9 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a sixth group. For example, the sixth group of operations may include forming one or more dielectric materials 902. The one or more dielectric materials 902 may comprise one or more layers of silicon oxide, one or more layers of silicon carbide nitrate, or other dielectric materials. The one or more dielectric materials 902 may be formed (e.g., in a z-direction) over one side (e.g., a back side) of the host wafer 805, which is the same side as a substrate material 802 of the host wafer 805. The one or more dielectric materials 902 may be formed having one or more conductive pads 904 (e.g., hybrid bonding pads). One or more conductive pads 904 can be performed as a multi-step process (e.g., a dual damascene process), wherein one or more first cavities are formed at a first depth (e.g., for one or more vias 906), and one or more second cavities are formed at a second depth (e.g., for one or more surfaces of the conductive pads 904), and both the first and second cavities are concurrently filled with a conductive material (e.g., copper). One or more dielectric materials 902 may also include one or more alignment features 908 to support alignment with other components (e.g., an RDL wafer). In some instances, the host wafer 805 (e.g., the back side of the host wafer 805) can be bonded to other components (e.g., one or more conductive signal lines of an RDL wafer) based on the formation of one or more dielectric materials 902, one or more conductive pads 904, one or more alignment features 908, or any combination thereof.

[0089] Figure 10 illustrates a portion of a semiconductor device 400 following one or more seventh group manufacturing operations. For example, the seventh group of operations may include forming an RDL 1005 (e.g., an RDL wafer, an RDL die) on one side (e.g., a back side) of a host wafer 805 that is the same side as the substrate material 802. The RDL 1005 may include a substrate material 1002 (e.g., an RDL silicon substrate) and one or more dielectric materials 1004 (e.g., comprising one or more layers of silicon oxide, one or more layers of silicon nitrate, or other dielectric materials). The RDL 1005 may be formed with one or more conductive pads 1006 (e.g., hybrid bonding pads) on the side of the RDL 1005 opposite to the substrate material 1002 (e.g., a front side).

[0090] RDL 1005 may include a plurality of conductive signal lines 1008 (e.g., RDL landing pads formed of a copper material). The plurality of conductive signal lines 1008 may provide a power interface for the semiconductor device 400 (e.g., a relatively low-resistance power delivery network). RDL 1005 may further include one or more alignment features 1010 (e.g., to support bonding alignment with the host wafer 805). In some instances, the side of RDL 1005 opposite to the substrate material 1002 (e.g., the front side) may be bonded (e.g., via wafer-to-wafer front-to-back hybrid bonding) to one side of the host wafer 805, which is the same side as the substrate material 802 (e.g., the back side). Bonding may be based on one or more conductive pads 1006, one or more conductive pads 904, one or more alignment features 1010, one or more alignment features 908, or any combination thereof.

[0091] Figure 11 illustrates a portion of a semiconductor device 400 following one or more eighth group manufacturing operations. For example, the eighth group operation may include forming a plurality of vias 1105 (e.g., power through-dielectric vias (TDVs)). Forming vias 1105 may include removing carrier material 402 located beneath one side (e.g., a front side) of one or more memory stacks 445 (e.g., thus exposing the front side of one or more memory stacks 445). Forming the plurality of vias 1105 may further include forming a plurality of cavities extending through a bottom surface of one or more dielectric materials 502 (e.g., a bottom surface of the semiconductor device 400) to a conductive signal line 1008 and depositing a conductive material (e.g., copper) within the cavities. Thus, vias 1105 may extend from the bottom surface of the semiconductor device 400 to the conductive signal line 1008, and the plurality of vias 1105 may be coupled to the conductive signal line 1008 (e.g., a power TDV may land on RDL 1005). Multiple vias 1105 may extend through one or more dielectric materials (e.g., multiple different dielectric layers) of the semiconductor device 400 along one or more memory stacks 445, interface blocks 605, and host chip 805 in a height direction (e.g., the z-direction). Specifically, the multiple vias 1105 may extend through one or more dielectric materials 502, 618, 702, 818, 902, and 1004. In some embodiments, the vias 1105 may be located in a peripheral region of the semiconductor device 400. The vias 1105 may also have a radius (e.g., other dimensions) large enough to support power transmission. In some embodiments, the vias 1105 may be formed using a post-via process or a mid-via process.

[0092] As described herein, in some alternative embodiments (not shown), the host chip 805 may be omitted from the semiconductor device 400, and RDL 1005 may be formed over the interface block 605 and one or more dielectric materials 702 (e.g., directly over one or more dielectric materials 702). In these embodiments, a plurality of vias 1105 may be formed extending along one or more memory stacks 445 and the interface block 605 (e.g., and through one or more dielectric materials 502, one or more dielectric materials 618, and one or more dielectric materials 702).

[0093] Figure 12 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a ninth group. For example, the ninth group of operations may include forming a plurality of contacts 1205 (e.g., front side) on one or more memory stacks 445 opposite to the substrate material 404 (e.g., a front side). Each contact 1205 may be coupled to a respective memory stack 445 (e.g., to a respective contact 418, a contact 1205-b of a memory stack 445) or to a respective via 1105 (e.g., a contact 1205-a). In some instances, one or more contacts 1202 (e.g., front tungsten contacts for TCDRAM) may couple one or more contacts 1205 (e.g., contact 1205-b) to one or more contacts 418 of one or more memory stacks 445.

[0094] In some instances, the ninth set of operations may include performing one or more evaluation procedures on one or more memory stacks 445, interface blocks 605, host wafers 805, or any combination thereof. The one or more evaluation procedures may be based on (e.g., using one or more probes 1204 or other evaluation circuitry) probing (e.g., on the front side of one or more memory stacks 445) one or more contacts 1205. Therefore, this intermediate evaluation step (e.g., a third evaluation) may further increase the manufacturing yield of one of the semiconductor devices 400 by verifying the operative combination of the package (e.g., host wafers 805, interface blocks 605, one or more memory stacks 445, and RDL 1005) before performing additional manufacturing operations.

[0095] Figure 13 illustrates a portion of a semiconductor device 400 following one or more manufacturing operations in a tenth group. For example, the tenth group operation may include forming one or more pads 1305 (e.g., µ-bumps, electrical contacts). Each pad 1305 may include a solder material 1302 coupled to a conductive material 1304 (e.g., copper). One or more pads 1305 may be formed (e.g., along a z-direction) below a bottom surface of the semiconductor device 400 (e.g., below the bottom surface of dielectric material 502, below the front side of one or more memory stacks 445). In some instances, forming one or more pads 1305 may include forming a substrate material 1306 (e.g., polyimide material) above the front side of one or more memory stacks 445 and above contacts 1205 (e.g., a polyimide layer may be positioned adjacent to the memory device). Next, one or more cavities may be formed through at least a portion of the substrate material 1306 to reach one or more contacts 1205. A conductive material 1304 may be deposited within one or more cavities, and a solder material 1302 may be formed over the conductive material 1304. In some embodiments, a second conductive material 1308 (e.g., tungsten) may be formed between the conductive material 1304 and one or more contacts 1205. Therefore, a plurality of vias 1105 may be coupled to a first set of pads 1305 (e.g., pads 1305-a), and each memory stack 445 may be coupled to a second set of pads 1305 (e.g., pads 1305-b). That is, the front side of one or more memory chips 440 (e.g., memory dies) may be coupled to one or more pads 1305 via a tungsten contact (e.g., the second conductive material 1308).

[0096] After the tenth set of manufacturing operations, the semiconductor device 400 can be prepared for packaging, which may include separating (e.g., dicing) multiple semiconductor devices 400 from each other (e.g., forming on the same carrier). According to the technology described with reference to Figures 4 through 13, the semiconductor device 400 may include a heterogeneous integration of a power distribution network (e.g., via 1105), an RDL 1005 (e.g., an RDL silicon wafer), a host chip 805 (e.g., a GPU), an interface block 605 (e.g., interface logic), and one or more memory stacks 445 (e.g., TCDRAM stacks). That is, the semiconductor device 400 may include one or more vias 1105, which are coupled to the RDL 1005 to provide power to the semiconductor device 400. For example, each of the vias 1105 may span between a pad of the RDL 1005 and a pad coupled to a solder pad. In some instances, a via 1105 may have a relatively wide diameter near one or more pads 1305 and a relatively narrow diameter near an RDL 1005. The RDL 1005 may be bonded to the back side of one of the host wafers 805, and the front side of one of the host wafers 805 may be bonded to the back side of one of the interface blocks 605. Additionally, the front side of one of the interface blocks 605 may be bonded to the back side of one or more memory stacks 445, and the front side of one or more memory stacks 445 may be coupled to one or more pads 1305. Thus, the semiconductor device 400 may support an interface block 605 that supports multiple memory stacks 445 (e.g., a logic device stack may support multiple memory device stacks). In some instances, the semiconductor device 400 may be a multi-bond integrated assembly in which one or more memory stacks 445 (e.g., a first stack) are stacked using wafer-on-wafer bonding, and interface block 605 and host chip 805 (e.g., a second stack of a logic die and a GPU die) may also be stacked using wafer-on-wafer bonding or stack-on-wafer (SoW) bonding. Alternatively, one or more memory stacks 445 (e.g., a first stack) may be placed on interface block 605 and host chip 805 (e.g., a second stack) via wafer-on-wafer bonding or stack-on-wafer (SoW) bonding.

[0097] One or more of the techniques described herein can be used to support increased manufacturing yield for wafers associated with components of semiconductor device 400 (e.g., HBM devices, TCDRAM devices). For example, the techniques described herein can perform intermediate evaluation prior to a bonding process, which can reduce the likelihood of good-to-bad die bonding. Additionally, the described techniques can support re-bonding of wafers, which can further increase manufacturing yield and reduce waste based on an increased number of good-to-good die combinations. Furthermore, by forming one or more vias 1105 and RDL 1005, semiconductor device 400 can support increased heat reduction (e.g., increased heat dissipation capacity). For example, based on RDL 1005 and multiple vias 1105 (e.g., power delivery networks), a host chip 805 can be positioned relatively closer to a substrate of semiconductor device 400 (e.g., and / or one or more heat sink elements), which can mitigate heat transfer to other components of semiconductor device 400. Therefore, by applying one or more of the techniques described herein, the yield and improved lifespan and reliability of semiconductor devices 400 can be increased.

[0098] Although some of the described techniques are described in the background content of memory systems, the techniques described herein can be implemented in other semiconductor systems that implement heterogeneous semiconductor components (e.g., dies associated with different functions including different logic functions, different storage or processing functions, or any combination thereof) (including heterogeneous semiconductor components interconnected within a layer, between layers, or any combination thereof). Furthermore, although a non-limiting example of the semiconductor device 400 is illustrated as a heterogeneous integration of one of two memory stacks 445, an interface block 650, a host chip 805, an RDL 1005, and two vias 1105, it should be understood that the techniques described herein can be applied to any configuration including any combination of one or more memory stacks 445, one or more interface blocks 605, one or more host chips 805, one or more RDLs 1005, and one or more vias 1105 (e.g., six memory stacks 445, one interface block 605, one host chip 805, and one RDL 1005).

[0099] Figure 14 illustrates an example of a semiconductor device 500 formed using the techniques described herein. The semiconductor device 500 is integrated with an example of a memory stack 1 to 1 to 6. For example, the semiconductor device 500 includes an RDL 520 (e.g., labeled PDN / RDL Si), a host chip 515 (e.g., labeled GPU), an interface block 510 (e.g., labeled IF logic (MIB)), and a memory stack 505 (e.g., labeled TCDRAM). The memory stack 505 may be an example of a memory stack 345 and one or more memory stacks 445 as described with reference to Figures 3 to 13. The interface block 510 may be an example of an interface block 305 and an interface block 605 as described with reference to Figures 3 to 13. The host chip 515 may be an example of a host chip 310 and a host chip 805 as described with reference to Figures 3 to 13. RDL 520 may be an example of one of the RDL 1005 as described with reference to Figures 3 to 13.

[0100] Although the semiconductor device 500 exhibits a specific configuration of memory stack 505, interface block 510, host chip 515, and RDL 520, various combinations of components are within the scope of this invention. For example, the techniques described herein can be used to form a semiconductor device integrating memory stacks from 1 to 1 to 1 to Z, where Z represents the number of memory stacks 505 in the semiconductor device and Z can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, etc. In some instances, the techniques described herein can be used to form semiconductor devices integrating memory stacks from 1 to 1 to Y to 6, where Y represents the number of interface blocks 510 in the semiconductor device and Y can be 1, 2, 3, 4, 5, 6, etc. In some instances, the techniques described herein can be used to form semiconductor devices integrating memory stacks from 1 to X to 1 to 6, where X represents the number of host chips 515 in the semiconductor device and X can be 1, 2, 3, 4, 5, 6, etc. In some instances, the techniques described herein can be used to form semiconductor devices integrating memory stacks from W to 1 to 1 to 6, where W represents the number of RDLs 520 in the semiconductor device and W can be 1, 2, 3, 4, 5, 6, etc.

[0101] The techniques described herein can be used to form other configurations of semiconductor devices. In some instances, the techniques described herein can be used to form a semiconductor device integrating memory stacks from W to X to Y to Z, where W represents the number of RDL 520s in the semiconductor device, X represents the number of memory stacks 505 in the semiconductor device, Y represents the number of interface blocks 510 in the semiconductor device, and Z represents the number of host chips 515 in the semiconductor device. Different configurations of the semiconductor device may include (but are not limited to): 1 to 1 to 2 to 2, 1 to 1 to 2 to 4, 1 to 1 to 2 to 8, 1 to 1 to 2 to 10, 1 to 1 to 2 to 12, 1 to 1 to 2 to 14, 1 to 1 to 2 to 16, etc.; or 1 to 1 to 3 to 3, 1 to 1 to 3 to 9, 1 to 1 to 3 to 12, 1 to 1 to 3 to 15, etc.; or 1 to 1 to 4 to 4, 1 to 1 to 4 to 8, 1 to 1 to 4 to 12. 1 to 1 to 4 to 16; or 1 to 1 to 6 to 12, 1 to 1 to 6 to 18, 1 to 1 to 6 to 24; or 1 to 1 to 8 to 8, 1 to 1 to 8 to 16, 1 to 1 to 8 to 24, 1 to 1 to 8 to 32; or 1 to 2 to 2 to 4, 1 to 2 to 2 to 8, 1 to 2 to 2 to 10, 1 to 2 to 2 to 12, 1 to 2 to 2 to 14, 1 to 2 to 2 to 16; or 1 to 3 to 3 to 9, 1 to 3 to 3 to 12, 1 to 3 to 6 to 12, 1 to 3 to 3 to 15; or 1 to 2 to 4 to 4, 1 to 2 to 4 to 8, 1 to 2 to 4 to 12, 1 to 2 to 4 to 16; or 1 to 2 to 6 to 12, 1 to 2 to 6 to 18, 1 to 2 to 6 to 24; or 1 to 3 to 6 to 12, 1 to 3 to 6 to 18, 1 to 3 to 6 to 24, etc.; or 1 to 2 to 8 to 8, 1 to 2 to 8 to 16, 1 to 2 to 8 to 24, 1 to 2 to 8 to 32, etc.; or 1 to 4 to 8 to 8, 1 to 4 to 8 to 16, 1 to 4 to 8 to 24, 1 to 4 to 8 to 32, etc.; or 2 to 2 to 8 to 8, 2 to 2 to 8 to 16, 2 to 2 to 8 to 24, 2 to 2 to 8 to 32, etc. Other numerical combinations of components may also be formed using the techniques described herein.

[0102] Figure 15 shows a flowchart illustrating a method 1500 for supporting reconstruction of semiconductor die evaluation and power delivery according to examples disclosed herein. The operation of method 1500 can be implemented by a manufacturing system or its components as described herein. For example, the operation of method 1500 can be performed by a manufacturing system as described with reference to Figures 1 through 14. In some instances, a manufacturing system may execute a set of instructions to control the functional elements of a device to perform the described functions. Alternatively or additionally, the manufacturing system may use dedicated hardware to perform the described functions.

[0103] In 1505, the method may include attaching one side of an interface block to one or more volatile memory stacks.

[0104] In 1510, the method may include performing an evaluation procedure on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side opposite a first side of the interface block, at least in part based on attaching the interface block to one or more volatile memory stacks.

[0105] In 1515, the method may include at least in part based on performing an evaluation procedure to attach a second side of an interface block to a first side of a host chip, the host chip being operable to communicatively couple with the interface block and control the functionality of one or more volatile memory stacks.

[0106] In 1520, the method may include forming a redistribution layer over a second side of a host chip opposite to a first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for a semiconductor device.

[0107] In some instances, such as one described herein, the device may perform one or more methods, such as method 1500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing the invention:

[0108] Specimen 1: A method, apparatus, or non-transitory computer-readable medium comprising any combination of operations, features, circuitry, logic, components, or instructions for: attaching a first side of an interface block to one or more volatile memory stacks; performing an evaluation procedure on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on attaching the interface block to the one or more volatile memory stacks; attaching the second side of the interface block to a first side of a host chip, at least in part based on performing the evaluation procedure, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks; and forming a redistribution layer over the second side of the host chip opposite to the first side of the host chip, the redistribution layer comprising a plurality of conductive signal lines providing a power interface for the semiconductor device.

[0109] State 2: The method, apparatus or non-transitory computer-readable medium of State 1 further includes any combination of operations, features, circuitry, logic, components or instructions for forming the one or more volatile memory stacks positioned on a carrier material and for attaching one first side of each volatile memory stack to the carrier material before attaching the first side of the interface block to the one or more volatile memory stacks.

[0110] State 3: A method, apparatus, or non-transitory computer-readable medium as in State 2, wherein forming the one or more volatile memory stacks includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for forming a plurality of vias through each volatile memory stack to a second side opposite to the first side of each volatile memory stack, wherein the first side of the interface block is coupled to the one or more volatile memory stacks at least partially based on the plurality of vias.

[0111] State 4: The method, apparatus, or non-transitory computer-readable medium of State 3 further includes any combination of operations, features, circuitry, logic, components, or instructions for forming a dielectric material between the volatile memory stacks of the one or more volatile memory stacks and forming one or more second conductive pads in the second side of each volatile memory after the first side of the one or more volatile memory stacks is bonded to the carrier material, wherein the one or more second conductive pads are coupled to at least one first set of vias of the plurality of vias, and wherein the first side of the interface block is bonded to the one or more volatile memory stacks at least partially based on the one or more second conductive pads.

[0112] Format 5: A method, apparatus or non-transitory computer-readable medium of any of Formats 1 to 4, further comprising operations, features, circuitry, logic, components or instructions or any combination thereof for forming the interface block, the interface block comprising one or more second conductive pads on the first side of the interface block, wherein the first side of the interface block is bonded to the one or more volatile memory stacks at least partially based on the one or more second conductive pads.

[0113] State 6: A method, apparatus or non-transitory computer-readable medium as in State 5, further comprising any combination of operations, features, circuitry, logic, components or instructions, or the like, for forming a plurality of vias through the second side of the interface block prior to performing the evaluation procedure, wherein the plurality of vias are coupled to the one or more conductive pads.

[0114] State 7: A method, apparatus, or non-transitory computer-readable medium of any of States 5 to 6, wherein forming the interface block includes operation, features, circuitry, logic, components, or instructions, or any combination thereof, for: forming a first wafer comprising one of a plurality of interface blocks including the interface block; testing the plurality of interface blocks to determine whether each interface block is defective; and dicing the first wafer to separate defective interface blocks from operable interface blocks.

[0115] State 8: A method, apparatus, or non-transitory computer-readable medium as in State 7, further comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for selecting the interface block at least in part based on determining that the interface block is operable, and for forming a second wafer comprising one of the operable interface blocks including the interface block, at least in part based on selecting the interface block, wherein the interface block is bonded to the one or more volatile memory stacks at least in part based on forming the second wafer.

[0116] Format 9: A method, apparatus or non-transitory computer-readable medium of any of Formats 1 to 8, further comprising an operation, feature, circuit system, logic, component or instruction or any combination thereof for forming a second dielectric material over the second side of the interface block, the second dielectric material comprising one or more second conductive pads, wherein the second side of the interface block is bonded to the first side of the host chip at least partially based on the one or more second conductive pads.

[0117] Format 10: A method, apparatus or non-transitory computer-readable medium of any of Formats 1 to 9, further comprising any combination of operations, features, circuit systems, logic, components or instructions for forming the host chip, the host chip including one or more second conductive pads on the first side of the host chip, wherein the second side of the interface block is bonded to the first side of the host chip at least partially based on the one or more second conductive pads.

[0118] Sample 11: The method, apparatus, or non-transitory computer-readable medium of Sample 10 further includes any combination of operations, features, circuit systems, logic, components, or instructions for: forming a plurality of vias through the second side of the host chip, the plurality of vias being coupled to one or more third conductive pads; and performing a second evaluation procedure on the host chip, the interface block, the one or more volatile memory stacks, or any combination thereof by probing the one or more third conductive pads.

[0119] Sample 12: A method, apparatus or non-transitory computer-readable medium of any of Samples 10 to 11, wherein forming the host chip includes operation, features, circuitry, logic, components or instructions or any combination thereof for: forming a first wafer comprising one of a plurality of host chips including the host chip; testing the plurality of host chips to determine whether each host chip is defective; and dicing the first wafer to separate defective host chips from operable host chips.

[0120] Version 13: The method, apparatus or non-transitory computer-readable medium of Version 12 further includes operations, features, circuitry, logic, components or instructions, or any combination thereof, for selecting the host chip at least in part based on determining that the host chip is operable and for forming a second wafer comprising one of the operable host chips including the host chip, at least in part based on selecting the host chip, wherein the interface block is attached to the host chip at least in part based on forming the second wafer.

[0121] Sample 14: A method, apparatus or non-transitory computer-readable medium of any of Samples 1 to 13, further comprising any combination of operations, features, circuit systems, logic, components or instructions for: forming a second dielectric material over the second side of the host chip, the second dielectric material comprising one or more second conductive pads; and at least in part based on the formation of the second dielectric material, connecting the one or more second conductive pads to the plurality of conductive signal lines.

[0122] Specimen 15: A method, apparatus or non-transitory computer-readable medium of any of Specimens 1 to 14, further comprising operations, features, circuitry, logic, components or instructions or any combination thereof for forming a plurality of vias extending from a bottom surface of a dielectric material to the plurality of conductive signal lines, the dielectric material extending along a height direction of one or more volatile memory stacks, the interface block and the host chip, the plurality of vias being coupled to the plurality of conductive signal lines.

[0123] Version 16: A method, apparatus, or non-transitory computer-readable medium as in Version 15, wherein forming the plurality of vias includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: removing a carrier material located below a first side of one or more volatile memory stacks; forming a plurality of cavities extending from the bottom surface of the dielectric material through the dielectric material to the plurality of conductive signal lines; and depositing a conductive material within the plurality of cavities.

[0124] Sample 17: A method, apparatus, or non-transitory computer-readable medium of any of Samples 15 to 16, further comprising an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for forming a plurality of contacts coupled to each of the one or more volatile memory stacks and the plurality of vias, and for performing a second evaluation procedure on the one or more volatile memory stacks, the interface block, the host chip, or any combination thereof by probing at least one of the plurality of contacts.

[0125] Specimen 18: A method, apparatus or non-transitory computer-readable medium of any of Specimens 15 to 17, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for forming a plurality of pads below the bottom surface of the dielectric material, wherein each of the plurality of vias is coupled to a first set of pads of one of the plurality of pads, and wherein each volatile memory stack is coupled to a second set of pads of one of the plurality of pads.

[0126] Sample 19: A method, apparatus, or non-transitory computer-readable medium as described in any of Samples 1 to 18, wherein the interface block includes a logic circuit system configurable to operate one or more memory arrays of the one or more volatile memory stacks; the one or more volatile memory stacks include one or more DRAM chips including the one or more memory arrays; and the host chip includes a graphics processing unit operable to control the functions of the interface block, the one or more volatile memory stacks, or both.

[0127] Figure 16 shows a flowchart illustrating a method 1600 for supporting reconstruction of semiconductor die evaluation and power delivery according to examples disclosed herein. The operation of method 1600 can be implemented by a manufacturing system or its components as described herein. For example, the operation of method 1600 can be performed by a manufacturing system as described with reference to Figures 1 through 14. In some instances, a manufacturing system may execute a set of instructions to control the functional elements of a device to perform the described functions. Alternatively or additionally, the manufacturing system may use dedicated hardware to perform the described functions.

[0128] In 1605, the method may include attaching a second side of one of an interface block to a first side of one or more volatile memory stacks, the interface block including a logic circuitry system for operating one or more memory arrays of one or more volatile memory stacks.

[0129] In 1610, the method may include performing an evaluation procedure on the interface block and the one or more volatile memory stacks by probing one or more first conductive pads on a first side opposite a second side of the interface block, at least in part based on bonding the interface block to one or more volatile memory stacks.

[0130] In 1615, the method may include forming a redistribution layer over a first side of an interface block opposite to a second side of the interface block, the redistribution layer including one or more second conductive pads operable to couple the interface block to a host chip.

[0131] In some instances, such as one of the devices described herein, the device may perform one or more methods, such as method 1600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing the invention:

[0132] Sample 20: A method, apparatus, or non-transitory computer-readable medium comprising any combination of operations, features, circuitry, logic, components, or instructions for: attaching a second side of an interface block to a first side of one or more volatile memory stacks, the interface block including logic circuitry for operating one or more memory arrays of the one or more volatile memory stacks; performing an evaluation procedure on the interface block and the one or more volatile memory stacks by detecting one or more first conductive pads on a first side of the interface block opposite to the second side of the interface block, at least in part based on attaching the interface block to the one or more volatile memory stacks; and forming a redistribution layer over the first side of the interface block opposite to the second side of the interface block, the redistribution layer including one or more second conductive pads operable to couple the interface block to a host chip.

[0133] State 21: A method, apparatus or non-transitory computer-readable medium as in State 20, further comprising operations, features, circuitry, logic, components or instructions or any combination thereof for forming the interface block, the interface block comprising one or more third conductive pads on the first side of the interface block, wherein the first side of the interface block is bonded to the one or more volatile memory stacks at least partially based on the one or more third conductive pads.

[0134] State 22: A method, apparatus or non-transitory computer-readable medium as in State 21, wherein forming the interface block includes operation, features, circuitry, logic, components or instructions or any combination thereof for: forming a first wafer comprising one of a plurality of interface blocks including the interface block; testing the plurality of interface blocks to determine whether each interface block is defective; and dicing the first wafer to separate defective interface blocks from operable interface blocks.

[0135] It should be noted that the descriptions of the states described herein are possible implementations, and the operations and steps may be reconfigured or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods may be combined.

[0136] Describe a device. The following provides an overview of one of the states of the device as described herein:

[0137] Sample 23: A semiconductor device comprising: an interface block including a logic circuit system for operating one or more memory arrays; one or more volatile memory stacks, etc., coupled to a first side of the interface block, each of a group of semiconductor dies including at least one of the one or more memory arrays; a host chip coupled to a second side of the interface block opposite to the first side of the interface block, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks; and a redistribution layer above the first side of the host chip opposite to the second side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the semiconductor device, the second side of the host chip being coupled to the first side of the interface block.

[0138] State 24: The semiconductor device of State 23 further includes: a plurality of vias extending from a bottom surface of a dielectric material to the plurality of conductive signal lines, the dielectric material extending along a height direction of one or more volatile memory stacks, the interface block and the host chip, the plurality of vias being coupled to the plurality of conductive signal lines.

[0139] State 25: The semiconductor device of State 24 further includes: a plurality of bonding pads, which are located below the bottom surface of the dielectric material, wherein each of the plurality of vias is coupled to a first group of bonding pads of the plurality of bonding pads, and wherein each volatile memory stack is coupled to a second group of bonding pads of the plurality of bonding pads.

[0140] State 26: A semiconductor device of any one of States 23 to 25, wherein the interface block includes: one or more conductive pads, such that are in the first side of the interface block, wherein the one or more volatile memory stacks are bonded to the first side of the interface block at least in part based on the one or more conductive pads.

[0141] Type 27: A semiconductor device of any one of Types 23 to 26, wherein the interface block includes: a plurality of vias extending through the first side of the interface block and coupled to one or more conductive pads, wherein the host chip is at least partially bonded to the second side of the interface block based on the plurality of vias.

[0142] State 28: A semiconductor device of any one of States 23 to 27, wherein the one or more volatile memory stacks include: a plurality of vias, wherein in each volatile memory of the one or more volatile memory stacks, a first volatile memory of one volatile memory stack is coupled to a second volatile memory at least in part through the plurality of vias.

[0143] Type 29: A semiconductor device of any one of Types 23 to 28, wherein the host chip includes: a plurality of vias extending through the first side of the host chip, wherein the host chip is coupled to the plurality of conductive signal lines at least in part based on the plurality of vias.

[0144] Type 30: A semiconductor device of any one of types 23 to 29, wherein: the one or more volatile memory stacks include one or more DRAM chips including one or more memory arrays; and the host chip includes a graphics processing unit operable to control the interface block, the one or more volatile memory stacks, or both.

[0145] Describe a device. The following provides an overview of one of the states of the device as described herein:

[0146] Sample 31: A product formed by one of the following processes: bonding a first side of an interface block to one or more volatile memory stacks; performing an evaluation process on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; bonding the second side of the interface block to a first side of a host chip, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks, at least in part based on performing the evaluation process; and forming a redistribution layer over the second side of the host chip opposite to the first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the product.

[0147] Describe a device. The following provides an overview of one of the states of the device as described herein:

[0148] Sample 32: A semiconductor device comprising: an interface block including a logic circuit system for operating one or more memory arrays; one or more volatile memory stacks, etc., bonded to a second side of the interface block, each of a group of semiconductor dies including at least one of the one or more memory arrays; and one or more first conductive pads, etc., formed above a first side of the interface block opposite to the second side of the interface block, the one or more first conductive pads providing an evaluation interface for the interface block and the one or more volatile memory stacks.

[0149] State 33: A semiconductor device as in State 32, wherein the interface block includes: one or more conductive pads, which are in the first side of the interface block, wherein the one or more volatile memory stacks are bonded to the first side of the interface block at least partially based on the one or more conductive pads.

[0150] State 34: A semiconductor device of any one of States 32 to 33, wherein the one or more volatile memory stacks include: a plurality of vias, wherein in each volatile memory of the one or more volatile memory stacks, a first volatile memory of one volatile memory stack is coupled to a second volatile memory at least in part through the plurality of vias.

[0151] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof, can represent the data, instructions, commands, information, signals, bits, or communication symbols cited in the foregoing description. Some diagrams may depict a signal as a single signal; however, a signal may represent a bus of signals, wherein the bus may have various bit widths.

[0152] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports signal flow between them. Components are considered electronically connected (e.g., conductive contact, connection, coupling) if any electrical path (e.g., conductive path) exists between them that can readily support signal flow (e.g., charge, current, voltage) between them. Based on the operation of a device involving connected components, a conductive path between electronically connected (e.g., conductive contact, connection, coupling) components can be an open circuit or a closed circuit. A conductive path between connected components can be a direct conductive path between components or an indirect conductive path involving intermediate components (such as switches, transistors, or other components). In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt signal flow between connected components for a period of time.

[0153] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a component isolates two components, it can initiate a change that prevents signals from flowing between other components using a previously permitted conductive path.

[0154] The term "coupling" (e.g., "electrical coupling") can refer to a condition that moves from an open-circuit relationship between components that currently cannot transmit signals between components (e.g., via a conductive path) to a closed-circuit relationship between components that can transmit signals between components (e.g., via a conductive path). When a component (such as a controller) couples other components together, the component can initiate a change that allows signals to flow between other components via a conductive path that previously did not allow signals to flow.

[0155] The terms "layer" and "level" can refer to an organization of a geometry (e.g., relative to a substrate) (e.g., a single layer, a sheet). Each layer or level can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or level can be a three-dimensional structure in which two dimensions are greater than a third dimension, such as a thin film. Layers or levels can contain different elements, components, or materials. In some instances, a layer or level can consist of two or more sublayers or sublevels.

[0156] One of the switching components discussed herein (e.g., a transistor) may be a field-effect transistor (FET) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate; in some instances, this may cause the channel to become conductive. A switching component may be an example of an n-type FET or a p-type FET.

[0157] The descriptions presented herein, as well as the illustrative configurations described with accompanying drawings, do not represent all instances that can be implemented or are within the scope of the invention claims. Specific details are included to provide an understanding of the described techniques. However, these techniques may be practiced without such specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid confusion with the concepts of the described instances.

[0158] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by adding one or more dashes and additional markings after the reference label to differentiate them. If only the first reference label is used in the specification, the description applies to any similar component having the same first reference label, regardless of any additional reference labels.

[0159] The functions described herein can be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Due to the nature of software, the functions described herein can be implemented using software executed by a processing system, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can be physically located at various locations, including portions distributed to enable the implementation of functions at different physical locations.

[0160] The interpretive blocks and modules described herein can be implemented or executed using one or more processors (such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. A processor may be an instance of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0161] As used herein, the word "or," as used in the scope of the invention claim, or in a list of items (for example, a list of items beginning with a phrase such as "...at least one of..." or "...one or more of..."), indicates a comprehensive list such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0162] As used herein, the article "a" preceding a noun included in the claims of this invention is open-ended and is understood to refer to "at least one" or "one or more" of those nouns. Therefore, the terms "a," "at least one," "one or more," and "at least one of one or more" are interchangeable. For example, if a claim lists "a component" performing one or more functions, each of the individual functions may be performed by a single component or by any combination of components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a particular characteristic or performing a particular function. Subsequent use of the terms "the" or "said" to refer to a component introduced by the article "a" may refer to any or all of the one or more components. For example, the use of the article "a" to refer to one component can be understood as meaning "one or more components," and the subsequent reference to "the component" in the claims of the invention can be understood as equivalent to referring to "at least one of the one or more components." Similarly, the subsequent use of the terms "the" or "said" to refer to one component introduced as "one or more components" can refer to any or all of the one or more components. For example, the subsequent reference to "the one or more components" in the claims of the invention can be understood as equivalent to referring to "at least one of the one or more components."

[0163] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of a computer program from one location to another. A non-transitory storage medium can be any available media accessible by a computer, or a combination of media. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a computer or a processor.

[0164] Descriptions and drawings are provided to enable those skilled in the art to make or use the invention. Those skilled in the art will understand that various modifications of the invention are possible, and that the techniques disclosed herein can be applied to other variations without departing from the scope of the invention. Therefore, the invention is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0165] 100: System 105: Host System 110: Memory System 115: Channel 120: Host System Controller 125: Processor 140: Memory System Controller 145: Memory Device 150: Local controller 155: Memory Array 200: System 205-a: Grain 207: Dielectric Materials 210: Host Processor 212: Contact element 215: Controller 216: Host Interface 220-a-1: Interface Block 220-a-2: Interface Block 221-a-1: Busbar 221-a-2: Busbar 222-a-1: Contact element 222-a-2: Contact element 223-a-1: Busbar 223-a-2: Busbar 225: Logical Block 230: Logical Block 234: Contact element 235: Non-volatile storage devices 237: Sensor 240-a-1: Grain 240-a-2: Grain 242: Dielectric materials 245-a-1: Interface Block 245-a-2: Interface Block 246-a-1: Busbar 246-a-2: Busbar 247-a-1: Contact element 247-a-2: Contact element 250-a-1: Memory Array 250-a-2: Memory Array 255-a-1: Busbar 256-a-1: Contact element 256-a-2: Contact element 257-a-1: Contact element 257-a-2: Contact element 260-a-1: Contact element 265-a-1: Unit 265-a-2: Unit 280-a-1: Unit 280-a-2: Unit 300: Architecture 305: Interface Block 310: Mainframe chip 315:Substrate 320: solder pad 340-a: Memory chip 340-b: Memory chip 345: Memory Stacking 400: Semiconductor Devices 401: Coordinate System 402: Carrier material 404: Substrate material 404-a: Substrate material 404-b: Substrate material 406-a: Substrate material 406-b: Substrate material 408: Through hole 408-a: Through hole 408-b: Through hole 410: Conductive pad 412: Circuit System 414: Alignment Feature 416: Sacrificial Silicon Material 418: Contacts 420: Alignment of feature section 422: Dielectric materials 440-a: Memory chip 440-b: Memory chip 445: Memory Stacking 500: Semiconductor Devices 502: Dielectric material 504: Conductive pad 504-a: Conductive pad 504-b: Conductive pad 505: Memory Stacking 508: Alignment Feature 510: Interface Block 515: Mainframe chip 520: Relay Layer (RDL) 602: Substrate material 604: Dielectric material 605: Interface Block 606: Circuit System 608: Conductive pad 610: Through hole 612: Conductive pad 614: Contacts 616: Alignment Feature 618: Dielectric Materials 620: Probe 702: Dielectric material 704: Conductive pad 706: Through hole 708: Alignment Feature 802: Substrate material 804: Dielectric material 805: Mainframe chip 806: Circuit System 808: Conductive pad 810: Through hole 812: Conductive pad 814: Contacts 816: Alignment of Feature Section 818: Dielectric Materials 820: Probe 902: Dielectric material 904: Conductive pad 906: Through hole 908: Alignment Feature 1002: Substrate material 1004: Dielectric materials 1005: Relay Layer (RDL) 1006: Conductive pad 1008: Conductive signal line 1010: Alignment Feature 1105: Through hole 1202: Contact element 1204: Probe 1205: Contact element 1205-a: Contact element 1205-b: Contact element 1302: Welding material 1304: Conductive material 1305-a: Solder pad 1305-b: solder pad 1306: Substrate material 1308: Second conductive material 1500: Method 1505: Operation 1510: Operation 1515: Operation 1520: Operation 1600: Method 1605: Operation 1610: Operation 1615: Operation

Claims

1. A method for manufacturing a semiconductor device, comprising: A first side of an interface block is bonded to one or more volatile memory stacks; an evaluation procedure is performed on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on the bonding of the interface block to the one or more volatile memory stacks; the second side of the interface block is bonded to a first side of a host chip, the host chip being operable to communicatively couple with the interface block and control one function of the one or more volatile memory stacks, at least in part based on the performance of the evaluation procedure; and a redistribution layer is formed over the second side of the host chip opposite to the first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the semiconductor device.

2. The method of request item 1, further comprising: Forming a stack of one or more volatile memory cells positioned on a carrier material; And before attaching the first side of the interface block to the one or more volatile memory stacks, attaching one first side of each volatile memory stack to the carrier material.

3. The method of claim 2, wherein forming the stack of one or more volatile memory modules includes: A plurality of vias are formed through a second side of each volatile memory stack opposite to the first side of each volatile memory stack, wherein the first side of the interface block is coupled to the one or more volatile memory stacks at least partially based on the plurality of vias.

4. The method of claim 3, further comprising: After bonding the first side of the one or more volatile memory stacks to the carrier material, a dielectric material is formed between each volatile memory stack of the one or more volatile memory stacks; and one or more second conductive pads are formed in the second side of each volatile memory, wherein the one or more second conductive pads are coupled to at least one first set of vias of the plurality of vias, and wherein the first side of the interface block is bonded to the one or more volatile memory stacks at least partially based on the one or more second conductive pads.

5. The method of claim 1, further comprising: The interface block is formed, the interface block including one or more second conductive pads on the first side of the interface block, wherein the first side of the interface block is bonded to the one or more volatile memory stack at least partially based on the one or more second conductive pads.

6. The method of claim 5, further comprising: Prior to performing the evaluation procedure, a plurality of vias are formed through the second side of the interface block, wherein the plurality of vias are coupled to one or more conductive pads.

7. The method of request item 5, wherein forming the interface block includes: Form a first wafer comprising one of a plurality of interface blocks containing the interface block; test the plurality of interface blocks to determine whether each interface block has defects; And the first wafer is cut to separate the defective interface block from the operable interface block.

8. The method of claim 7, further comprising: The interface block is selected at least in part based on the determination that the interface block is operable; and a second wafer is formed at least in part based on the selection of the interface block, including one of the operable interface blocks containing the interface block, wherein the interface block is bonded to the one or more volatile memory stacks at least in part based on the formation of the second wafer.

9. The method of claim 1, further comprising: A second dielectric material is formed above the second side of the interface block, the second dielectric material including one or more second conductive pads, wherein the second side of the interface block is bonded to the first side of the host chip at least partially based on the one or more second conductive pads.

10. The method of claim 1, further comprising: The host chip is formed, the host chip including one or more second conductive pads on the first side of the host chip, wherein the second side of the interface block is bonded to the first side of the host chip at least partially based on the one or more second conductive pads.

11. The method of claim 10, further comprising: Forming a plurality of vias through the second side of the host chip, the plurality of vias being coupled to one or more third conductive pads; and performing a second evaluation procedure on the host chip, the interface block, the one or more volatile memory stacks, or any combination thereof by probing the one or more third conductive pads.

12. The method of claim 10, wherein forming the host chip includes: Forming a first wafer comprising one of a plurality of host chips containing the host chip; testing the plurality of host chips to determine whether each host chip has defects; and dicing the first wafer to separate the defective host chip from the operable host chip.

13. The method of claim 12, further comprising: The host chip is selected at least in part based on the determination that the host chip is operable; and a second wafer is formed at least in part based on the selection of the host chip, comprising one of the operable host chips including the host chip, wherein the interface block is bonded to the host chip at least in part based on the formation of the second wafer.

14. The method of claim 1, further comprising: A second dielectric material is formed above the second side of the host chip, the second dielectric material including one or more second conductive pads; and the one or more second conductive pads are coupled to the plurality of conductive signal lines at least in part based on the formation of the second dielectric material.

15. The method of claim 1, further comprising: A plurality of vias are formed extending from the bottom surface of one of the dielectric materials to the plurality of conductive signal lines. The dielectric material extends along the height direction of one or more volatile memory stacks, the interface block, and the host chip. The plurality of vias are coupled to the plurality of conductive signal lines.

16. The method of claim 15, wherein forming the plurality of vias comprises: Remove the carrier material located below the first side of one or more volatile memory stacks; A plurality of cavities are formed extending from the bottom surface of the dielectric material through the dielectric material to the plurality of conductive signal lines; and a conductive material is deposited in the plurality of cavities.

17. The method of claim 15, further comprising: Forming a plurality of contacts coupled to each of the one or more volatile memory stacks and the plurality of vias; and performing a second evaluation procedure on the one or more volatile memory stacks, the interface block, the host chip, or any combination thereof by probing at least one of the plurality of contacts.

18. The method of claim 15, further comprising: A plurality of bonding pads are formed below the bottom surface of the dielectric material, wherein each of the plurality of vias is coupled to a first group of bonding pads of the plurality of bonding pads, and wherein each volatile memory stack is coupled to a second group of bonding pads of the plurality of bonding pads.

19. As in request item 1, wherein: The interface block includes a logic circuit system configurable to operate one or more memory arrays of the one or more volatile memory stacks; the one or more volatile memory stacks include one or more dynamic random access memory (DRAM) chips containing the one or more memory arrays; and the host chip includes a graphics processing unit operable to control the functions of the interface block, the one or more volatile memory stacks, or both.

20. A semiconductor device comprising: An interface block that includes a logic circuit system for operating one or more memory arrays; One or more volatile memory stacks are bonded to a first side of the interface block, and each semiconductor die of a group of semiconductor dies includes at least one of the one or more memory arrays; a host chip is bonded to a second side of the interface block opposite to the first side of the interface block, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks; and a redistribution layer is placed over the first side of the host chip opposite to the second side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the semiconductor device, the second side of the host chip being bonded to the first side of the interface block.

21. The semiconductor device of claim 20, further comprising: A plurality of vias extend from the bottom surface of one of the dielectric materials to the plurality of conductive signal lines, the dielectric material extending along the height direction of one or more volatile memory stacks, the interface block and the host chip, the plurality of vias being coupled to the plurality of conductive signal lines.

22. The semiconductor device of claim 21, further comprising: A plurality of solder pads are located below the bottom surface of the dielectric material, wherein each of the plurality of vias is coupled to a first group of solder pads of the plurality of solder pads, and wherein each volatile memory stack is coupled to a second group of solder pads of the plurality of solder pads.

23. The semiconductor device of claim 20, wherein the interface block includes: One or more conductive pads, such as those in the first side of the interface block, wherein the one or more volatile memory stacks are bonded to the first side of the interface block at least in part based on the one or more conductive pads.

24. The semiconductor device of claim 20, wherein the interface block includes: A plurality of vias, which extend through the first side of the interface block and are coupled to one or more conductive pads, wherein the host chip is at least partially bonded to the second side of the interface block based on the plurality of vias.

25. The semiconductor device of claim 20, wherein the one or more volatile memory stacks include: A plurality of vias, wherein in each of the volatile memory cells of one or more volatile memory stacks, a first volatile memory cell of one volatile memory stack is coupled to a second volatile memory cell at least in part based on the plurality of vias.

26. The semiconductor device of claim 20, wherein the host chip comprises: A plurality of vias extending through the first side of the host chip, wherein the host chip is at least partially coupled to the plurality of conductive signal lines based on the plurality of vias.

27. The semiconductor device as claimed in claim 20, wherein: The one or more volatile memory stacks include one or more dynamic random access memory (DRAM) chips containing one or more memory arrays; and the host chip includes a graphics processing unit operable to control the interface block, the one or more volatile memory stacks, or one of the functions of both.

28. A product formed by one of the following processes: bonding a first side of an interface block to one or more volatile memory stacks; performing an evaluation process on the interface block and the one or more volatile memory stacks by probing one or more conductive pads on a second side of the interface block opposite to the first side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; bonding the second side of the interface block to a first side of a host chip, the host chip being operable to communicatively couple with the interface block and control a function of the one or more volatile memory stacks, at least in part based on performing the evaluation process; and forming a redistribution layer over the second side of the host chip opposite to the first side of the host chip, the redistribution layer including a plurality of conductive signal lines providing a power interface for the product.

29. A method for manufacturing a semiconductor device, comprising: A second side of an interface block is bonded to a first side of one or more volatile memory stacks, the interface block including a logic circuit system for operating one or more memory arrays of the one or more volatile memory stacks; an evaluation procedure is performed on the interface block and the one or more volatile memory stacks by detecting one or more first conductive pads on the first side of the interface block opposite to the second side of the interface block, at least in part based on bonding the interface block to the one or more volatile memory stacks; and a redistribution layer is formed over the first side of the interface block opposite to the second side of the interface block, the redistribution layer including one or more second conductive pads operable to couple the interface block to a host chip.

30. The method of claim 29, further comprising: The interface block is formed, the interface block including one or more third conductive pads on the first side of the interface block, wherein the first side of the interface block is bonded to the one or more volatile memory stack at least partially based on the one or more third conductive pads.

31. The method of request 30, wherein forming the interface block includes: Form a first wafer comprising one of a plurality of interface blocks containing the interface block; test the plurality of interface blocks to determine whether each interface block has defects; And the first wafer is cut to separate the defective interface block from the operable interface block.

32. A semiconductor device comprising: An interface block that includes a logic circuit system for operating one or more memory arrays; One or more volatile memory stacks are bonded to a second side of one of the interface blocks, each of a set of semiconductor chips includes at least one of the one or more memory arrays; and one or more first conductive pads are formed on a first side of the interface block opposite to the second side of the interface block, the one or more first conductive pads providing an evaluation interface for the interface block and the one or more volatile memory stacks.

33. The semiconductor device of claim 32, wherein the interface block includes: One or more conductive pads, such as those in the first side of the interface block, wherein the one or more volatile memory stacks are bonded to the first side of the interface block at least in part based on the one or more conductive pads.

34. The semiconductor device of claim 32, wherein the one or more volatile memory stacks include: A plurality of vias, wherein in each of the volatile memory cells of one or more volatile memory stacks, a first volatile memory cell of one volatile memory stack is coupled to a second volatile memory cell at least in part based on the plurality of vias.

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