Memory structure, memory device and operating method thereof

Abstract

The memory device includes a plurality of memory cells. Each memory cell includes a first memory cell. The first memory cell includes a first transistor and a first charge-well transistor. The first transistor is coupled to a first storage node and is used to transmit a first write bit line signal to the first storage node based on a first write word line signal. The first charge-well transistor is used to generate a first current signal based on a threshold voltage level of the first charge-well transistor and a voltage level of the first storage node.

Claims

1. A memory device comprising a plurality of memory cells, the memory cells including a first memory cell, the first memory cell comprising: a first transistor coupled to a first storage node and configured to transmit a first write bit line signal to the first storage node according to a first write word line signal; a first charge trap transistor configured to generate a first current signal according to a threshold voltage level of the first charge trap transistor and a voltage level of the first storage node; a source structure extending in a first direction; a drain structure extending in the first direction and separated from the source structure; and a first gate structure surrounding each of the source structure and the drain structure and configured to operate with the source structure and the drain structure as the first charge trap transistor.

2. The memory device as claimed in claim 1, wherein the first transistor is turned on to perform a write operation when the voltage level of the first write word line signal is greater than the critical voltage level of the first transistor, and the first transistor is turned off to perform a read operation or maintain the logic state of the first memory cell when the voltage level of the first write word line signal is less than the critical voltage level of the first transistor.

3. The memory device as claimed in claim 2, wherein a first terminal of the first charge trap transistor is used to receive a first read word line signal, and a second terminal of the first charge trap transistor is used to receive a first read bit line signal, wherein when the first memory cell maintains the logic state, the voltage level of the first read word line signal is equal to the voltage level of the first read bit line signal, and when the first memory cell performs the read operation, the voltage level of the first read word line signal is different from the voltage level of the first read bit line signal.

4. The memory device as claimed in claim 2, wherein when a first logic value is written to the first memory cell, the voltage level of the first write bit line signal is equal to the voltage level of the first write word line signal, when a second logic value is written to the first memory cell, the voltage level of the first write bit line signal is different from the voltage level of the first write word line signal, and the first logic value is different from the second logic value.

5. The memory device as claimed in claim 1, wherein the memory cells further include a second memory cell, the second memory cell comprising: a second transistor coupled to a second storage node and configured to transmit a second write bit line signal to the second storage node according to the first write word line signal; and a second charge trap transistor configured to generate a second current signal, wherein the first memory cell and the second memory cell are further configured to add the first current signal and the second current signal together.

6. The memory device as claimed in claim 5 further comprises: a first semiconductor structure extending in a second direction; a second semiconductor structure extending in the second direction and separated from the first semiconductor structure in the first direction; and a second gate structure extending in the first direction and surrounding each of the first semiconductor structure and the second semiconductor structure, wherein the second gate structure and the first semiconductor structure are configured to operate as the first transistor, and the second gate structure and the second semiconductor structure are configured to operate as the second transistor.

7. The memory device as claimed in claim 6 further comprises: a third semiconductor structure coupled to the first semiconductor structure and having a first length in the second direction; and a fourth semiconductor structure coupled to the second semiconductor structure, having a second length greater than the first length in the second direction and isolated from the third semiconductor structure in the first direction, wherein the third semiconductor structure and the fourth semiconductor structure are respectively used to transmit the first write bit line signal and the second write bit line signal.

8. The memory device as claimed in claim 1, wherein the memory cells further include a second memory cell, the second memory cell comprising: a second transistor coupled to a second storage node and configured to transmit the first write bit line signal to the second storage node according to a second write word line signal; and a second charge trap transistor configured to generate a second current signal, wherein the first memory cell and the second memory cell are further configured to add the first current signal and the second current signal together.

9. The memory device as claimed in claim 8 further comprises: a first semiconductor structure extending in a second direction; and a second semiconductor structure extending in the second direction and separated from the first semiconductor structure in the second direction; And a second gate structure, extending upward on a third side, and surrounding the first semiconductor structure; And a third gate structure extending upward in the third direction, surrounding the second semiconductor structure, and separated from the second gate structure in the first direction, wherein the second gate structure and the first semiconductor structure are configured to operate as the first transistor, and the third gate structure and the second semiconductor structure are configured to operate as the second transistor.

10. The memory device as claimed in claim 9 further includes: a conductive structure extending in the first direction for transmitting the first write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

11. A memory structure comprising: a source structure extending in a first direction; a drain structure extending in the first direction and separated from the source structure; a first gate structure surrounding each of the source structure and the drain structure and configured to operate with the source structure and the drain structure as a first charge trap transistor; a first semiconductor structure extending in a second direction and coupled to the first gate structure; and a second gate structure separated from the first gate structure in the second direction, surrounding the first semiconductor structure and configured to operate with the first semiconductor structure as a first transistor.

12. The memory structure as claimed in claim 11 further comprises: a third gate structure surrounding each of the source structure and the drain structure and configured to operate with the source structure and the drain structure as a second charge trap transistor; and a second semiconductor structure extending in the second direction, separated from the first semiconductor structure in the first direction, and coupled to the third gate structure.

13. The memory structure as claimed in claim 12, wherein the second gate structure further surrounds the second semiconductor structure and is used to operate with the second semiconductor structure as a second transistor, and the drain terminal of the second transistor is coupled to the gate terminal of the second charge trap transistor.

14. The memory structure as claimed in claim 13 further comprises: a third semiconductor structure coupled to the first semiconductor structure and having a first length in the second direction; and a fourth semiconductor structure coupled to the second semiconductor structure and having a second length in the second direction, wherein the first length is less than the second length.

15. The memory structure as claimed in claim 14 further comprises: a first oxide structure having a third length in the second direction; and a second oxide structure having the first length in the second direction and used to isolate the third semiconductor structure and the fourth semiconductor structure from each other, wherein the first oxide structure, the third semiconductor structure, the second oxide structure and the fourth semiconductor structure are arranged sequentially in the first direction.

16. The memory structure as claimed in claim 12 further comprises: a fourth gate structure, separated from the second gate structure in the first direction, surrounding the second semiconductor structure and configured to operate with the second semiconductor structure as a second transistor, wherein each of the second gate structure and the fourth gate structure extends in a third direction, and the first direction, the second direction and the third direction are perpendicular to each other.

17. The memory structure as claimed in claim 16 further includes: a conductive structure extending in the first direction for transmitting a write bit line signal to each of the first semiconductor structure and the second semiconductor structure.

18. A method of operating a memory device, comprising: writing a first input bit into a first storage node; storing a first weighted bit via a first charge trap transistor coupled to the first storage node; generating a first current signal flowing through the first charge trap transistor based on the first input bit and the first weighted bit; and operating a source structure, a drain structure, and a first gate structure as the first charge trap transistor, wherein the source structure extends in a first direction, the drain structure extends in the first direction and is separate from the source structure, and the first gate structure surrounds each of the source structure and the drain structure.

19. The method of operation as described in claim 18 further comprises: turning on a first transistor by a write word line signal to transmit a first write bit line signal to the first storage node; and turning on a second transistor by the write word line signal to transmit a second write bit line signal to a second storage node, wherein the second storage node is different from the first storage node.

20. The method of operation as described in claim 18 further comprises: turning on a first transistor by a first write word line signal to transmit a write bit line signal to the first storage node; and turning on a second transistor by a second write word line signal to transmit the write bit line signal to a second storage node, wherein the second storage node is different from the first storage node.

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