A method of forming transistor interconnects on top of a semiconductor device substrate

Abstract

A scalable diffusion coupling device includes: a processing chamber for growing a diffusion material on a wafer; wherein the processing chamber includes a heatable base plate heated to a specified temperature, and a substrate is placed on the heatable base plate; a heatable top plate includes a second heating mechanism, wherein the heatable top plate is configured to move vertically along an x-axis and a x-major axis to apply mechanical pressure to the substrate positioned on the heatable base plate, and wherein when the heatable top plate applies the mechanical pressure, the pressure in the processing chamber is maintained at less than 10⁻³ Torr, wherein the first heating mechanism and the second heating mechanism are independently adjustable, or wherein the entire processing chamber is heatable, and wherein the device is a modified or unmodified commercial bonding or thermoforming tool.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0002] This case asserts priority to U.S. Patent Application No. US 18 / 674,085, filed on May 24, 2024.The relevant U.S. applications include: U.S. Patent Application No. 18 / 607,380, filed March 15, 2024, entitled "GRAPHENE BEOL INTEGRATION INTERCONNECTION STRUCTURES"; U.S. Patent Application No. 18 / 527,043, filed December 1, 2023, entitled "LARGE-AREA WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL INTERCALATION DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHEN"; and U.S. Patent Application No. 17 / 863,232, filed July 12, 2022. U.S. Patent Application No. 17 / 857,954, filed July 5, 2022, entitled "Low-Temperature / Beol-Compatible Highly Scalable Grapene Synthesis Tool," and U.S. Provisional Application No. 63 / 218,498, filed July 6, 2021, entitled "Wafer-Scalle CMOS-Compatible Grapene Synthesis Tool," and U.S. Provisional Application No. 63 / 441,766, filed January 27, 2023, entitled "Wafer-Scalle CMOS-Compatible Grapene Synthesis Tool." Date, Invention Title: LARGE-AREA / WAFER-SCALE CMOS-COMPATIBLE 2D-MATERIAL DOPING TOOLS, PROCESSES, AND METHODS, INCLUDING DOPING OF SYNTHESIZED GRAPHENE, Two-dimensional material intercalation doping in large-area / wafer-scale CMOS compatible processes, including doping tools, processes and methods for doping to synthesize graphene.The entire contents of the aforementioned application are incorporated herein by reference. [Previous Technology]

[0003] Atoms in a "material stack" can form "diffusion couples" due to solid-state diffusion. This phenomenon can be used to synthesize high-quality thin films at relatively low temperatures. This technology can be utilized in a wide range of applications, including microelectronics, optoelectronics, bioelectronics, and quantum computing. However, to achieve this solid-state diffusion-assisted thin film growth, especially on large "wafer-scale" substrates (e.g., 150 mm, 200 mm, 300 mm, etc.) within a reasonable growth time, it is necessary to design and manufacture novel devices, or utilize existing commercial (current or past) devices, with minor or major modifications, to obtain a device that can uniformly apply various temperatures and pressures across the entire surface area of ​​a semiconductor wafer or any other substrate to form diffusion couples. The core component of such a device is a reactor. The reactor must not only be able to support the large-area substrate as described above, but also must provide a chemical purging environment, near-zero temperature inhomogeneity heating of the large-area substrate, and a mechanism to apply relatively high (e.g., up to 1000 psi, etc.) and uniform mechanical pressure to the diffusion couples. It should be noted that in some cases, the aforementioned mechanical pressure can be applied using atmospheric pressure.

[0004] In the emerging field of atomically thin two-dimensional (2D) materials, particularly graphene or multilayer graphene (MLG) (essentially single or multiple atomic layers of carbon atoms arranged in a hexagonal lattice), thin films must be synthesized directly on the desired substrate (usually a dielectric or metal) without a transfer step. This is because transferring thin films to a substrate is widely considered infeasible and cost-inefficient in the mainstream electronics (i.e., CMOS) industry. The graphene / MLG layers mentioned here are the material of choice for many back-end-of-line (BEOL) processes (wafer manufacturing steps after the formation of active components such as transistors and diodes), especially for on-chip interconnects. However, BEOL interconnects must be synthesized under a strict thermal budget of <500 °C to avoid any damage to the underlying active components (e.g., transistors, diodes, etc.) and / or the underlying interconnect layers and layered structures, which may contain, for example, aluminum, copper, cobalt, ruthenium, alloys of the above materials, or two-dimensional low dielectric constant (low k value material) insulating materials, and processed at a low softening / diffusion temperature, although this processing temperature may be increased to above 500 °C for ease of processing.

[0005] Significant progress has been made in the latest technological developments for synthesizing graphene / MLG at BEOL-compatible temperatures, enabling the application of diffusion couples in graphene / MLG growth. During synthesis, a layer of carbon source (e.g., in the form of powder, slurry, or amorphous carbon film) deposited on a sacrificial metal film (e.g., nickel) distributed on a SiO2 / Si substrate forms a diffusion couple. Experts have demonstrated that high-quality graphene / MLG can be grown by applying appropriate mechanical pressure (65-85 ps) to this carbon source at relatively low temperatures (<450 °C), although this is only applicable to relatively small (1-2 inch) substrates. Therefore, to enable the application of this technology in mainstream CMOS manufacturing, diffusion couple generation devices capable of scaling up (to 150 / 200 / 300 mm) need to be designed and manufactured. This technology / device can also be extended to substrates of various geometries and configurations, as well as other applications that inherently require low thermal budgets (<500 °C).

[0006] Furthermore, this invention proposes a method for synthesizing large-area, single-layer to multi-layer graphene using controlled pressure and temperature. The hardware device proposed in this invention can simultaneously apply temperature and pressure to a given carbon source material and a multilayer stacked metal matrix.

[0007] Key components of the hardware may include at least one mechanical pressure head and at least one heater (integrated in the process / reaction chamber or within the pressure head) to raise the temperature of the substrate above room temperature.

[0008] Commercially available tools such as wafer bonding tools, hot pressing-based isostatic pressing systems, hot isostatic pressing heads (HIPs), hot press containers, or similar mechanisms may be used. [Summary of the Invention]

[0009] One aspect of the present invention is to provide a scalable diffusion coupling device comprising: a processing chamber for growing a diffusion material on a wafer; wherein the processing chamber includes a heatable base plate heated to a specified temperature and a substrate placed on the heatable base plate; a heatable top plate including a second heating mechanism, wherein the heatable top plate is configured to be movable along an x-axis; and an x-axis that is movable vertically for applying mechanical pressure to the substrate positioned on the heatable base plate, wherein while the heatable top plate applies the mechanical pressure, the pressure in the processing chamber is maintained below 10⁻³ Torr, wherein the first heating mechanism and the second heating mechanism are independently adjustable, or wherein the processing chamber can be heated as a whole (including the top plate and the base plate), and the diffusion coupling device is a commercial bonding tool or other existing thermoforming / autoclave, which may be modified or unmodified.

Implementation Method

[0012] The systems, methods, and manufacturing tools disclosed in this invention are all for the synthesis of highly scalable graphene compatible with low temperature / BEOL. Other devices suitable for this invention include various commercially available tools, such as wafer bonding tools, hot-press-based isostatic pressing systems, hot isostatic pressing (HIP) machines, autoclaves, etc. The following description is intended to enable those skilled in the art to understand, and to make and use, various embodiments of the invention. The descriptions of specific devices, techniques, and applications are provided by way of example only. Various modifications to the embodiments described in this specification will be apparent to those skilled in the art. Furthermore, the general principles defined in this specification can be applied to other examples and applications without departing from the spirit and scope of the various embodiments.

[0013] The terms "an embodiment," "an example," or similar expressions used in this specification refer to specific technical features, structures, or characteristics described in the description of that embodiment, which may be included in at least one embodiment of the present invention. Therefore, the terms "in an embodiment," "in one embodiment," and similar expressions appearing throughout the specification may, but do not necessarily, indicate the same embodiment.

[0014] Furthermore, the technical features, structures, or characteristics of the present invention described in this specification can be combined in any suitable manner in one or more embodiments. Numerous specific details, such as programming, software modules, user selection, online transactions, database queries, database structures, hardware modules, hardware circuits, and hardware wafers, will be provided in the following description to enable the reader to fully understand the embodiments of the present invention. However, those skilled in the art will recognize that the present invention can be implemented without one or more of these specific details, or using other alternative methods, components, materials, etc. In another aspect, to avoid obscuring various aspects of the invention, well-known structures, materials, or operations are not shown or described in detail.

[0015] The schematic flowcharts included in this specification are generally referred to as logic flowcharts. Therefore, the sequence and labeled steps depicted are merely illustrative of one embodiment of the presented method. The shown method may be understood as being functionally, logically, or effectively equivalent to one or more other steps of the method, or a portion thereof. Furthermore, the format and symbols used in this specification are merely for interpreting the logical steps of the method and should not be construed as limiting the scope of the method. While various arrows and lines may be used in the flowcharts, it should be understood that such arrows and lines are not intended to limit the scope of the corresponding method. In fact, some arrows or other lines may also be used to indicate the logical flow of the method. For example, an arrow may indicate a period of waiting or monitoring not shown in the diagram between two steps listed in the depicted method. Furthermore, the order in which a particular method occurs may or may not strictly adhere to the order of the corresponding steps shown.

[0016] Definition

[0017] Back-to-Line Process (BEOL): refers to the second part of the IC manufacturing process. In this part, interconnects and other circuit elements are formed on the wafer (e.g., metallization layer) and between and on individual devices (mainly transistors) isolated by in-layer and / or inter-layer insulators.

[0018] Complementary Metal-Oxide-Semiconductor (CMOS): is a metal-oxide-semiconductor field-effect transistor (MOSFET) process that uses complementary and multiple electrically symmetrical p-type and n-type MOSFET pairs to implement at least logic functions.

[0019] Grain boundary (GB): refers to the interface between two grains and / or microcrystals in a polycrystalline material.

[0020] Graphene: It is an allotrope of carbon, consisting of a single layer of atoms arranged in a two-dimensional honeycomb lattice.

[0021] Graphene nanoribbons (GNR): are graphene strips with a width of less than about one hundred (100) nm.

[0022] Graphite: It is a layered crystalline form of elemental carbon, in which the atomic arrangement and covalent bonding form a hexagonal structure within the layers.

[0023] Intercalation doping: Intercalation refers to the reversible insertion of molecules or ions between layers of a compound (e.g., potassium ions inserted between graphite layers). Doping involves adding impurities to a material. Dopants (impurity ions) integrate into the material's crystal lattice. N-type dopants donate electrons to the material, while P-type dopants accept electrons from it. Doping alters the carrier density, thereby changing the material's electronic properties.

[0024] Intercalation dopants: There are many references available. Specifically, information on graphene can be found in recent studies by Kaustav Banerjee et al.; for example, J. Jiang, Jae Hwan Chu, and Kaustav Banerjee, “CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI,” IEDM 2018, pp. 34.5.1-4, 799-802; and J. Jiang et al., “Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects,” Nano Letters, Vol. 17, No. 3, pp. 1482-1488, 2017.

[0025] Piezoelectricity: is the electric charge that accumulates in certain solid materials in response to applied mechanical stress.

[0026] Resistance Temperature Detector (RTD): A sensor that measures temperature by monitoring the change in resistance of a conductor with temperature. An RTD element can be formed from a thin wire wound around a heat-resistant ceramic or glass core, but other structures can also be used.

[0027] Silicon dioxide: It is an oxide of silicon and an insulator with the chemical formula SiO2.

[0028] Wafer: A thin sheet of semiconductor (e.g., silicon, germanium) used to manufacture integrated circuits, etc.

[0029] Examples of a highly scalable graphene synthesis tool compatible with low temperature / BEOL.

[0030] First, it should be noted that the following exemplary embodiments are all based on graphene sources. However, graphene sources are merely examples. Other carbon sources (including carbon-supported compounds) may be used in other exemplary embodiments.

[0031] Figure 1 shows an example top view of the graphene processing and transfer chamber used in a carbon source synthesis tool 100 according to several embodiments of the present invention. Note that in other exemplary embodiments, other diffusion materials (other elements in the periodic table suitable for specific diffusion metals and diffusion applications) besides carbon sources may be used. The carbon source synthesis tool 100 may be a low-temperature / BEOL compatible scalable graphene (and / or other carbon source) synthesis tool. The carbon source synthesis tool 100 includes a transfer chamber 102. The transfer chamber 102 is used to load a wafer / substrate. The wafer may be of various sizes (e.g., 300 mm, 200 mm, 150 mm, etc.). An operator / user may place the wafer / substrate in the transfer chamber 102. The transfer chamber 102 is then closed and sealed. The pressure in the transfer chamber 102 is adjusted to be the same as the pressure in the processing chamber 104. Once the pressure is equal, the wafer / substrate is pushed into the processing chamber 104. Note that the wafer / substrate may be returned to the transfer chamber 102 after the deposition and other manufacturing methods related to the present invention have been performed.

[0032] It should be noted that in some process embodiments of the present invention, two or more wafers / substrates are present at each location within the processing chamber (i.e., one wafer / substrate is located on top of another wafer / substrate, which in turn is located on top of yet another wafer / substrate, and so on. And typically (but not necessarily), the "top surface" of the wafer / substrate to be processed faces outward, i.e., towards the individual pressure plate / pressure disc). In this state, heat and compression acceleration can be applied simultaneously to the two or more wafers / substrates, thereby synthesizing graphene on all wafers / substrates.

[0033] The processing chamber 104 and the transfer chamber 102 are connected via a slit valve 106. The slit valve 106 opens when the pressure in the two chambers is equal.

[0034] Processing chamber 104 is the main chamber (or reactor) for growing graphene (and / or other carbon materials) on a wafer and / or applying temperature and pressure to form diffusion couples on the desired surface, ultimately forming high-quality graphene. A substrate with a size slightly larger than 300 mm is located in processing chamber 104 (e.g., see heating base plate 208). Processing chamber 104 is equipped with a heater system. A heating top plate or top disk is also located in processing chamber 104 (e.g., see heating top plate 206). The heating top disk also has its own heating mechanism (e.g., see heating power supply 202). In this design, the base plate used to carry the wafer and the heating top disk can be heated separately or simultaneously. For example, the base plate can be heated, but the top disk can be kept at a temperature close to room temperature (or vice versa). The pad surface (covering the heating disk) can be made of graphite, but other materials such as aluminum nitride, quartz, silicon carbide coated graphite, etc., can also be used. Several other materials with similar functions are also available. Generally, any material that can provide good heat transfer and pressure distribution can be used in this invention. The flatness and surface finish of the gasket are key factors in ensuring proper heat and pressure distribution.

[0035] The mechanical / turbine pump 108 can be used to control the pressure in the processing chamber 104 and / or the transfer chamber 102. The mechanical pump can be used to reduce the pressure in the processing chamber 104 (e.g., 10⁻³ Torr). The turbo pump can be a more powerful pump for further reducing the pressure (e.g., 10⁻⁷ Torr). During diffusion couple operation, low pressure is required to remove any impurities from the chamber.

[0036] The electrical control device 110 can be used to operate the carbon source synthesis tool 100. The electrical control device 110 may include a computer processor and software system. The user can input commands and view the status of various operations of the carbon source synthesis tool 100.

[0037] Figure 2 shows an exemplary schematic diagram of the internal components of a processing chamber 104 according to several embodiments of the present invention. The wafer transfer chamber 214 shown in the figure illustrates the back-and-forth transfer of a wafer between the processing chamber 104 and the transfer chamber 102. A heating chassis 208 can be fixed in place and can be heated to a specific temperature (e.g., 500°C). A heating power supply 212 can keep the heating chassis 208 in a heated state. The heating result can maintain a temperature uniformity of ±3°C (and / or near-zero non-uniformity) across the entire heating chassis 208. A heating top plate 206 can move up and down along the x-axis and x-major axis. The heating top plate 206 has an independent heating source (e.g., heating power supply 202). The heating top plate 206 can be operated using a hydraulic cylinder 204, a motor, etc. The heating top plate 206 can be moved to provide mechanical pressure to the wafer surface. For example, this pressure can be 50 to 125 psi or higher. The wafer is placed on the upper surface of the heating chassis 208. While the heated top plate 206 applies mechanical pressure to the diffusion couple, the chamber pressure is maintained at a low value. The chamber pressure can be, for example, 10⁻⁶ to 10⁻⁷ torr to prevent contamination of the growth process. The chamber pressure can be regulated using a mechanical pump / turbopump 216 and related devices, sensors, and software.

[0038] The following describes an exemplary operation of the processing chamber 104. The processing chamber 104 can be used to deposit / grow a majority layer (e.g., a single-layer or few-layer graphene (FLG) structure, or a multilayer graphene (MLG) structure). To grow graphene, a carbon / graphene source is first deposited on a nickel film (e.g., with a thickness of 100 nm). The graphene source (and / or other carbon source) can be: graphite powder, a liquid / slurry form of a solvent containing graphite, or an amorphous carbon layer already deposited on nickel. Other forms are also possible. The nickel film can be deposited first using different deposition methods and tools, and then the carbon source can be deposited on the top surface of the nickel. The thickness of the nickel or other diffused layer can be, for example, about 50 nm, about 75 nm, about 100 nm, about 150 nm, about 200 nm, about 250 nm, about 300 nm, etc. The applied mechanical pressure splits the carbon / graphene source into carbon atoms, which then diffuse through nickel and recombine on the other side of the nickel film to form a dielectric layer on the top surface of the target substrate (e.g., a silicon wafer). Once the required number of graphene layers have been formed, the nickel film and any remaining carbon source can be removed.

[0039] Figure 3 shows a flowchart of an example graphene synthesis tooling process 300 according to several embodiments of the present invention. The graphene synthesis tooling process 300 can be used to operate the carbon source synthesis tool 100 or any other apparatus / device disclosed or suggested in this specification. The graphene synthesis tooling process 300 can grow graphene at relatively low temperatures (e.g., 300-450°C). It should be noted that thermal budget compatibility with CMOS / BEOL is achieved as long as the operating temperature of the processing chamber 104 is below ~450°C. BEOL is a process step that occurs after the front-end transistor has been fabricated. After the transistor is formed on the wafer by the manufacturing process, subsequent process steps should be performed within a thermal budget of approximately 450°C to avoid transistor damage and various possible consequences leading to short circuits and reliability issues.

[0040] When synthesizing graphene using the graphene synthesis tool process 300, the number of graphene layers formed can be controlled by adjusting the process parameters. The graphene synthesis tool process 300 can directly grow graphene on the top surface of any substrate (e.g., dielectric / Si substrate, metal substrate, etc.). The graphene synthesis tool process 300 can also synthesize graphene into a thin / very few-layer coating on a metal substrate.

[0041] More specifically, in step 302, the graphene synthesis tooling process 300 can achieve low-temperature (e.g., <450°C) growth of graphene films compatible with CMOS / BEOL thermal budgets. In step 304, the graphene synthesis tooling process 300 can perform direct synthesis (i.e., transfer-free) of graphene on various substrates. In step 306, the graphene synthesis tooling process 300 can achieve controlled thicknesses from single layers to multiple layers.

[0042] An exemplary tool for low-temperature / BEOL-compatible, highly scalable graphene synthesis

[0043] Figure 7 shows an exemplary side view of a commercial bonding tool 700. According to some embodiments of the invention, the tool can serve as a graphene processing chamber for carbon source synthesis, as well as other functions. The commercial bonding tool 700 may include a bottom heater 705, a bottom bonding pressure plate 710, or a heatable chamber. The wafer to be bonded 715 (hereinafter referred to as the "synthesis substrate" in this document and references), bonding jig 720, mechanical clamp 725, spacer 730, top heater 740, and bonding pressure 750 (hereinafter referred to as synthesis acceleration pressure).

[0044] The bottom heater 705 and the top heater 740 can be controlled individually or can heat the entire chamber, typically with a maximum temperature set at 500°C. They can also be heated in series. The specific approach depends on engineering, design, and logistical requirements. Radial temperature control can also be provided to promote a more uniform final bonding or synthesis result. The bonding pressure (provided at least by the bonding pressurization 750) can typically reach 200 kN, and radial pressure regulation can be incorporated into the pressure-bearing surfaces and the applied pressure. This pressure regulation capability can help control the synthesis acceleration and the uniformity of the synthesis acceleration.

[0045] Implementation of the bonding method may include the following steps: loading the wafer / substrate 715 to be bonded into a commercial bonding tool 700, providing temperature equilibration to achieve the desired overall conditions, aligning one wafer to another (depending on the required processing type; for example, control to millimeter-level accuracy, sometimes to nanometer-level), possibly repeating the alignment / equilibration steps, performing soft bonding by applying a small bonding pressure 750, checking for alignment deviations, then applying bonding pressure 750 at full pressure at the desired temperature for the required duration, and cooling the synthesized wafer / substrate under the desired overall conditions. These cooling conditions affect the final wafer-to-wafer stack stress and the alignment uniformity of the entire wafer / substrate 715 (wafer-to-wafer alignment in the bonding case).

[0046] If this bonding apparatus is applied to a carbon source synthesis process, taking a single-wafer process as an example, an exemplary implementation may include the following steps: Preparing a wafer / substrate 715. The preparation method may use a method described in this specification and the patents listed in the references to deposit a material layer onto the wafer / substrate 715 to create a wafer / substrate 715 suitable for a carbon source synthesis process. In the above case, the wafer / substrate 715 is usually singular, but the number still depends on engineering and machine design and other considerations. The wafer / substrate 715 is loaded into a commercial bonding tool 700. Temperature equilibration is then provided to achieve the desired overall conditions. For a single-wafer synthesis process, the aforementioned time-consuming alignment procedure is not required. Therefore, time is saved. The required synthesis pressure 750 is provided at the desired temperature for the required time. The processed synthesized wafer / substrate 715 is cooled to the desired temperature conditions. When applied to this synthesis process, the required time is much shorter than that required for most bonding processes.

[0047] It should be noted that in some process embodiments of the present invention, two or more wafers / substrates can be placed at each location (i.e., one wafer / substrate is placed on top of another wafer / substrate, which in turn is placed on top of yet another wafer / substrate, and so on. And typically (but not necessarily) the "top surface" of the wafer / substrate to be processed faces the individual pressure plate / pressure disk). In this state, heat acceleration and compression acceleration can be applied simultaneously to the two or more wafers / substrates, thereby synthesizing graphene on all wafers / substrates. Therefore, in some aspects of the present invention, this feature is similar to the bonding process, mainly referring to "stacking" two wafers in a bonding apparatus, aligning them, and then bonding them.

[0048] The commercial bonding tool 700 may include a device and software (not shown) for aligning two wafers 715 (or composite substrates, which may be two or more). Alignment may be achieved mechanically, optically, or a combination of both. For example, this alignment function may be used to composite the required number of layers, such as FLG / MLG layers, on multiple wafers / substrates.

[0049] The commercial bonding tool 700 may also include apparatus and software for performing wafer-to-wafer, die-to-wafer, or die-to-die bonding processes. The synthesis of carbon sources (e.g., FLG / MLG) may also be performed on the aforementioned substrate and structure, as well as other parts.

[0050] The commercial bonding tool 700 (and other tools / apparatus / machines mentioned or suggested in this specification) may be modified to make the bonding tool usable as an intercalation doping tool. Details regarding the relevant processes are described in detail in the aforementioned U.S. Patent Application No. 18 / 527,043, which is cited herein, as well as in other technical documents.

[0051] Figure 8A shows an exemplary side view of a commercial isostatic pressing sintering apparatus 800, which, according to some embodiments of the present invention, can be used as a graphene processing chamber for carbon source synthesis, as well as other functions. The isostatic pressing sintering apparatus 800 may include an upper punch / pressure head 810, a heating / pressurizing chamber mold / model 820, and a lower punch / pressure head 830.

[0052] The upper punch / pressure head 810 may include an integrated or non-integrated upper heater (not shown). The lower punch / pressure head 830 may also include an integrated or non-integrated lower heater (not shown). The upper and lower heaters can be controlled independently, typically with a maximum temperature set to 500°C, or they can be heated in series. The specific implementation depends on engineering, design, and logistical requirements. Radial temperature control may also be provided to promote a more uniform final bonding or synthesis result. The upper punch / pressure head 810 and lower punch / pressure head 830 can be activated to apply pressure to the powder sample 850 using, for example, hydraulic methods, helical levers, etc., to form a disc-shaped sample 870, the power used depending on engineering, cost, speed, and design considerations.

[0053] With appropriate modifications, the process can be changed to place the wafer / substrate above the punch / pressure head 830, where a carbon source is already prepared above the wafer / substrate, or a separate carbon source (e.g., powder sample 850) is provided in the chamber. Graphene can then be synthesized on the wafer / substrate in the manner described above. Radial temperature control can also be incorporated to promote a more uniform final sintering or synthesis result. The pressure of the sintering / synthesis pressurization 860 (which can be provided at least via the sintering / synthesis pressurization 860) can typically reach 1000 kN. Radial pressure adjustments can also be designed in this step based on surface parameters and the applied force. This pressure regulation capability helps control the synthesis acceleration and its uniformity.

[0054] The shape of the heating / pressurizing chamber mold / model 820 may include a circle that conforms to or is slightly larger than the required substrate. The shape of the heating / pressurizing chamber mold / model 820 may also include a rectangle or other shapes to fit the shape of the required substrate. The volume of the heating / pressurizing chamber mold / model 820 may be modified due to engineering and process considerations; for example, providing space for the use of a gaseous carbon (or doped) source.

[0055] An isostatic pressing sintering apparatus 800 applied in an exemplary isostatic pressing sintering process may include initial conditions (a) 880. Here, a powder sample 850 may be loaded into a heating / pressurizing chamber mold / model 820, which may be heated for temperature acceleration, and then an upper punch / pressurizer 810 is activated and moved toward a lower punch / pressurizer 830 to press the sample, thereby reducing the volume of the processing chamber and compressing the powder sample 850. Of course, this compression of the initial volume may generate heat, and therefore it may be necessary to remove the heat from the chamber of the apparatus to maintain temperature uniformity and / or to apply the resulting heat to accelerate any desired reactions and phase transitions. In step (b) 882, a sintering / synthesis pressurization 860 may apply pressure and move the upper punch / pressurizer 810 toward the lower punch / pressurizer 830, thereby reducing the chamber volume and compressing the material therein. Step (c) 884 shows the exemplary final position reached by the upper punch / pressure head 810, at which point the device 800 has created the disk-shaped sample 870, as shown in step (d) 886.

[0056] If a commercial or research-grade isostatic pressing (OSP) apparatus (e.g., exemplary OSP sintering apparatus 800) is used in an exemplary graphene synthesis process, the process may include initial conditions (a) 880. In this process, a wafer / substrate (not shown) may be loaded into a heating / pressurizing chamber mold / model 820 and placed on a lower punch / pressurizer 830 within the processing chamber. The lower punch / pressurizer 830 is then heated for thermal acceleration, followed by moving an upper punch / pressurizer 810 toward the lower punch / pressurizer 830 to reduce the volume of the processing chamber and compress the powder sample 850. As described above and in the combined references herein, the wafer / substrate may include a carbon source material / layer disposed on top of a diffusion material (e.g., Ni), which may be disposed above a dielectric material (e.g., an intermetallic dielectric layer, silicon oxide, a low-k material, etc.). A 2D or 3D stack / circuit may also be configured below the dielectric material. The carbon source for graphene synthesis can be supplied in various forms, such as gaseous hydrocarbons, distributed in the processing chamber and located above the wafer / substrate. Of course, heat may be generated during the initial volume compression process, and it may be necessary to remove the heat from the device chamber to maintain temperature uniformity and / or to apply the resulting heat to accelerate any desired reactions and phase changes. In step (b) 882, sintering / synthesis pressurization 860 can apply pressure to move the upper punch / pressurization head 810 toward the lower punch / pressurization head 830, thereby further reducing the chamber volume, compressing the carbon source material, and promoting diffusion through the diffusion layer to form graphene on the dielectric surface in this embodiment. Step (c) shows an exemplary final position of the upper punch / pressurization head 810. Finally, as shown in step (d), the disk-shaped sample 870 formed in the device 800 is a wafer / substrate, with the remaining carbon source distributed on top of a diffusion layer (e.g., nickel), which is located above the newly formed MLG. The MLG, as for the MLG, is located above the exemplary dielectric of the wafer / substrate.

[0057] Figure 8B shows an exemplary side view of another commercial and research isostatic pressing sintering apparatus 899. The possible configuration shown in the figure is extremely common. Reference URLs are included in the figure. Such machines can also be used to simultaneously provide temperature and pressure acceleration for graphene synthesis processes. Furthermore, they can be used not only for wafer-to-wafer bonding, wafer-level graphene synthesis, and wafer-level intercalation doping, but also for grain-to-wafer and grain-to-grain bonding, as well as graphene synthesis and intercalation doping of similar sizes.

[0058] Figure 9 shows an exemplary side view of a commercial / research hot isostatic pressing (HIP) apparatus 900. According to some embodiments of the invention, this apparatus can be used as a graphene processing chamber as a carbon source synthesis tool, and in other applications. The HIP apparatus 900 may include a pressure gauge 910, an inlet valve 912, an inlet port 914, a nut 916, a pressure relief valve 918, a temperature measuring tube 920, an outlet port 922, a container cap 924, and a pressure vessel 926. The HIP apparatus 900 utilizes high-pressure gas to provide the compressive acceleration required for graphene formation, while utilizing heat supplied to the substrate and the processing chamber pressure vessel 926 to provide thermal acceleration.

[0059] The processing chamber pressure vessel 926 may include an integrated or non-integrated heater (not shown). The vessel cover 924 may include an integrated or non-integrated lower heater (not shown). The heaters of the pressure vessel 926 and the vessel cover 924 can be independently controlled, typically with a maximum temperature set to 500°C, or heated in series, depending on engineering, design, and logistical requirements. Radial (relative to wafer / substrate) temperature control may also be provided to promote a more uniform final synthesis result. An inlet valve 912 may be activated to supply gas pressure to the processing chamber pressure vessel 926 via an inlet port 914, thereby promoting and accelerating graphene synthesis, or other synthesis processes.

[0060] The present invention can be applied by making appropriate modifications to the HIP device 900. In use, a wafer / substrate can be loaded into the processing chamber pressure vessel 926, with a carbon source provided above the wafer / substrate or supplied into the chamber; for example, at least a portion of the carbon source comprises a pressurized gas containing carbon components. The process of synthesizing graphene on the wafer / substrate can be carried out as described in this specification and the cited references. Radial temperature control can also be provided to promote a more uniform final synthesis result. Gas pressure can create an impact force on the wafer / substrate, typically up to 10,000 kN, and as a gas, its radial pressure gradient should be close to zero, even if it is close to a liquid phase. Hydraulic pressure generated by a liquid can also be utilized in this type of machine, with appropriate modifications to handle this viscous gas, which can be referred to as a liquid. This handling capability can help control the synthesis acceleration and the uniformity of the synthesis acceleration.

[0061] The pressure vessel 926 may include a circular shape that conforms to or is slightly larger than the desired substrate. The shape of the pressure vessel 926 may include rectangles, etc., to match the desired substrate shape, but is not necessarily so. Furthermore, the gas pressure application of this system enables simpler and more practical single-pass multi-wafer processing, and corresponding processing chamber / pressure vessel 926 configurations. Based on engineering and process considerations, the internal shape of the processing chamber / pressure vessel 926 and the configuration of the gas distribution manifolds that may exist therein may need to be modified. For example, modified to use a gaseous carbon (or doped) source.

[0062] If a commercial or research-grade HIP device (e.g., the HIP device 900 of this embodiment) is applied to an exemplary graphene synthesis process, the process may include a set of initial conditions. In this step, a wafer / substrate (not shown) is loaded into a processing chamber pressure vessel 926, the vessel is heated to accelerate the temperature, and then a valve 912 is opened and the required gas is supplied via an inlet 914 for compression. As described earlier in this specification and in the references cited, the wafer / substrate may include a carbon source material / layer located above a diffusion material (e.g., Ni). The diffusion material may be located above a dielectric material (e.g., an intermetallic dielectric layer, silicon oxide, a low-k material, etc.). A 2D or 3D stack / circuit may be configured below the dielectric material. The carbon source for graphene synthesis may also be supplied in various forms, such as gaseous hydrocarbons, distributed in the processing chamber above the wafer / substrate. Of course, this compression process may generate heat, which may need to be removed from the chamber to maintain temperature uniformity and / or the resulting heat may be used to accelerate any desired reaction. The pressure within the processing chamber pressure vessel 926 may include pressures above nominal atmospheric pressure, such as approximately 2 Bar, approximately 5 Bar, approximately 10 Bar, approximately 50 Bar, approximately 100 Bar, and so on. The construction and support of the processing chamber pressure vessel 926 to provide a safe tool is a well-known technique in the art. The resulting pressure can be used to compress the carbon source material and promote carbon diffusion via a diffusion layer (typically nickel), thereby forming graphene on an exemplary dielectric surface.

[0063] There are many other possible configurations described above. Such machines can also be used to simultaneously accelerate the graphene synthesis process with both temperature and pressure. They can also be applied to two-dimensional materials, such as the intercalation doping of MLG structures.

[0064] Figure 10 shows an exemplary view of an alternative commercial and research Hot Pressure Vessel (HPV) device 1000 design. According to some embodiments of the invention, the device can utilize a graphene processing chamber as a carbon source synthesis tool and provide other functionalities. The HPV device 1000 may include a temperature controller 1012, a pressure controller 1014, a protective shell 1016, a vacuum pump 1018, a pressure sensor 1022, a water-cooled / heated chamber 1024, and a hydraulic pump 1026 for flange lifting. The HPV device 1000 utilizes high-pressure gas to provide the compression acceleration required for graphene formation, while using heat supplied to the substrate and the water-cooled / heated chamber 1024 of the processing chamber to provide temperature acceleration.

[0065] These machines have many possible configurations. They can also be used (with or without modification) to simultaneously provide temperature and pressure acceleration for the graphene synthesis process. They can also be applied to two-dimensional materials, such as intercalation doping of MLG structures.

[0066] Exemplary Example

[0067] An exemplary embodiment of the present invention may begin with wafer (e.g., Si / SiO2) preparation, followed by deposition of a catalyst metal film, such as a nickel film. The morphology of the catalyst film may be adjusted during or after deposition (e.g., using an annealing step, etc.) to meet specific application requirements. A uniformly distributed carbon source is then deposited on the top surface of the nickel film. A pressure of 65 to 85 psi is then applied to the carbon source. A disk with a diameter slightly larger than the wafer diameter of 300 mm can be used for pressure application. The substrate (wafer) may be heated to 300 °C to 450 °C. After the pressure is applied, some carbon elements diffuse into the nickel film. This carbon source / Ni / SiO2 / Si structure can act as a diffusion couple. The carbon atoms recombine on the other side of the nickel film (e.g., the side facing SiO2) to form a single layer, few layers, or multiple layers of graphene.

[0068] Various process steps can then be performed (e.g., removing the remaining graphite, removing the metal catalyst (Ni) layer, etc.).

[0069] If SiO2 is not used, the substrate can be made of copper or other metals (e.g., cobalt, ruthenium, molybdenum, tungsten, or metal alloys), or low dielectric constant (low k) materials, such as porous silica or silsesquioxane (HSQ) or black diamond, or even any patterned substrate formed of metals and dielectrics. In this embodiment, applicable modifications may also include forming a sacrificial layer of amorphous carbon between Ni and Cu. This prevents Ni and Cu from forming an alloy. In other embodiments of the invention, the aforementioned other metals may in particular include: Co, Ni, Ru (as a substrate and / or catalyst), molybdenum, etc., or may be metal compounds.

[0070] The thickness of the substrate and the catalyst (e.g., 100 nm, etc.) can also be set. The required number of graphene layers (i.e., their thickness) can be a function of the Ni thickness and other process parameters (including time, temperature, pressure, and the grain size of the catalyst film).

[0071] The substrate wafer can be 300mm or 200mm, or smaller / larger (450mm). Provided process compatibility is met, a temperature controller can be used to maintain the temperature between room temperature (~25 °C) and 500 °C, or any higher. Graphite powder can be dispersed uniformly or in a pre-patterned manner. A jig (disc) can be used to apply downward pressure to uniformly distributed graphite. Other carbon-containing compounds can also be used as alternatives.

[0072] The pressure applied to the substrate to form the diffusion couple can be applied mechanically, for example using an instrument with a clamp, or by any non-contact method, such as using gas pressure (1 bar to several thousand bar), to increase the ambient pressure of the substrate. A single substrate can be processed at a time, or multiple substrates can be processed in batches. Furthermore, the gas can be ordinary air, a specific gas such as Ar or N2, or a mixture of multiple gases. As shown and suggested in this specification, many commercial and research machines / appliances can successfully perform the disclosed graphene synthesis process; for example, commercial bonding tools 700, isostatic pressing sintering apparatus 800, hot isostatic pressing (HIP) apparatus 900, and hot autoclave (HPV) apparatus 1000, etc.

[0073] The application of heat can come from any source capable of generating temperature on the substrate. In several embodiments of the invention, the upper punch / pressure head and / or lower punch / pressure head are both heatable devices. In some embodiments of the invention, the upper punch / pressure head and / or lower punch / pressure head may be non-heatable, but use another heat source, such as the pressure chamber wall, etc.

[0074] Exemplary systems and methods for migrating deposited material to the surface of a substrate via diffusion couples deposited on the substrate.

[0075] The exemplary systems and methods of the present invention can facilitate the migration of deposited material through diffusion pairs deposited on a substrate to the substrate surface. This method provides many advantages for material deposition.

[0076] Figure 4 illustrates an example process 400 according to several embodiments of the present invention for causing deposited material to migrate through a diffusion coupler deposited on a substrate to the surface of the substrate. Process 400 may use a reactor system to induce one or more diffusion materials to migrate through the diffusion coupler to the substrate by performing the following steps. In step 402, process 400 may apply a specific pressure to induce one or more diffusion materials to migrate through the diffusion coupler to the substrate. In step 404, process 400 may apply a temperature to induce one or more diffusion materials to migrate through the diffusion coupler to the substrate.

[0077] Figure 5 illustrates another exemplary process 500 according to several embodiments of the present invention for migrating deposited material through diffusion couplers deposited on a substrate to the surface of the substrate. Process 500 provides the ability to deposit materials that may not be deposited directly using conventional methods. For example, past techniques did not provide a method for synthesizing graphene directly on silicon. Process 500 can fulfill this requirement. It should be noted that the present invention can be customized to alter the particle size and other material structures of the deposited material by appropriately changing the structure of the diffusion couplers and / or the process conditions.

[0078] In step 502, process 500 deposits a diffusion couple onto a substrate using several methods, including the most common method, and then deposits a material of unspecified form onto the substrate on the top surface of the diffusion couple. This step may be referred to in this specification as the preparation of a substrate or a layered substrate.

[0079] In step 504, process 500 places the layered substrate in a high-pressure and high-temperature environment for a period of time, the pressure and temperature range of which are as described above.

[0080] In step 506, process 500 may apply heat, especially by means of resistance heating, radiation heating, gas heating, etc.

[0081] In step 508, pressure may be applied in process 500. This step may be achieved in particular by means of mechanical devices, air pressure, flexible membranes, liquid pressure, etc.

[0082] Application example: Reactors that can be pressurized mechanically and heated directly.

[0083] Figure 6 illustrates an exemplary process 600 according to several embodiments of the present invention, which uses top and bottom heaters to pressurize a substrate with uniform pressure and temperature. The aforementioned carbon source synthesis tool 100 can be modified and / or otherwise applied to implement this exemplary embodiment. First, the substrate is placed on a base (e.g., a disk) using tools typical of the manufacturing apparatus industry. The base has the capability to directly contact and heat the substrate. Note that the material used for this contact may vary depending on the appropriate padding material used. Next, a movable top heater (embedded in the disk) is moved downwards, pressurizing the substrate while heating it. When the process is complete, the substrate is removed from the reactor (e.g., the processing chamber of Figure 2 above).

[0084] In step 602, the application surfaces of the top heater and the bottom heater are made parallel to the substrate and sufficiently compliant to avoid damaging the substrate. To achieve this, sufficient clearance and play as well as compliance can be provided to the top heater mechanism, and if necessary, a compliance layer can be provided to the application surface in step 604 as a means of implementation.

[0085] In step 606, the reactor may also be equipped with means for placing the substrate under vacuum and exposing the substrate to other gases, such as N2, Ar, He, etc., to optimize the process. Therefore, the reactor may be equipped with a vacuum pump, gas lines, and gas control panel to ensure that the substrate can be placed in various environments.

[0086] In step 608, the reactor may be connected to means that can transport a substrate into and out of the reactor. For example, if wafers are to be processed, the reactor may be attached to one side of a transfer chamber. The transfer chamber is equipped with a wafer transport robot that operates under high vacuum. In several examples of the invention, a slit valve may be provided to isolate the reactor from the rest of the system. Multiple reactors may be connected to a transfer chamber to achieve higher throughput or productivity. Reactors for depositing diffusion couples, such as sputtering and CVD chambers, may also be provided, including source material connected to the transfer chamber. This allows a material layer to be formed on the substrate, and the final material to be deposited on the same system.

[0087] In step 610, process 600 provides field sensors (e.g., equipped in a reactor, etc.) to ensure proper pressure and temperature distribution so that the deposited material migrates through the diffusion couple in optimal condition. For example, pressure sensors can be used on the base steps to calibrate and monitor pressure. Pressure can also be monitored by monitoring the current consumed by the motor applying pressure between the surfaces, using a flexure embedded in the base liner material or similar as a strain gauge, and other methods. Similarly, temperature can be monitored using thermocouples and RTDs mounted in the base, using IR sensors, phosphorus-based sensors, etc.

[0088] In step 612, process 600 provides software control to ensure that process parameters are applied appropriately in the correct order and duration.

[0089] Another reactor configuration will be described below. This reactor is used to apply other forms of heat and pressure to a substrate. It should be noted that the configuration described is only one of many available configurations. Alternative configurations may include, but are not limited to: - A heating film subjected to high pressure (e.g., gas or hydraulic pressure); - A clamshell configuration providing high-temperature and high-pressure heated N2, Ar, or other similar gases; - A mass-production reactor with the same characteristics as described above; - A clamshell configuration, but using a combination of the heating substrate and the method of applying pressure to the substrate as described above. For example, high-temperature and high-pressure gases may be introduced; high pressure may be introduced, and the substrate may be heated by a bottom heater, while the high-temperature gas is heated by the bottom heater, simultaneously performing the pressurization function and maintaining the temperature; - A quartz body having a substrate placed on a base, using high-pressure gas to perform induction heating and pressure loading; - An array of lamps may also be configured in the quartz body for final temperature control.

[0090] For example, the reactor described above allows materials to be deposited via diffusion couples, as in the aforementioned embodiment of depositing graphene onto a silicon wafer via a nickel layer. The deposition method using diffusion couples can be applied to a wider range of deposited and diffused materials.

[0091] The following description shows several operating ranges of the system of the present invention, as well as the range of parameters such as material structure and composition required to obtain optimal process results.

[0092] As previously described, the method of the present invention enables a material to migrate through a diffusion couple, thereby depositing the material onto a substrate. This result would be impossible using other conventional deposition methods in the prior art (e.g., because graphene is difficult to grow directly on Si or SiO2). The system disclosed in this invention achieves the growth of graphene on Si / SiO2 by applying pressure and temperature to a carbon source deposited on a Ni layer. This Ni layer is a material layer deposited on a Si wafer or similar material.

[0093] It should be noted that the reactor can be implemented as a batch reactor and / or a single-substrate (wafer) reactor. It is worth noting that if a single-substrate configuration is used, finer substrate-to-substrate process control can be achieved compared to a batch reactor. A method for batch growth using only a single-wafer architecture can also be achieved by placing a stack of wafers between two heaters.

[0094] Conclusion

[0095] Although several embodiments of the present invention have been described above with reference to specific examples, various modifications and variations can be made to these embodiments without departing from the spirit and scope of the various embodiments. Therefore, this patent specification and drawings should be considered illustrative in nature and not intended to limit the scope of the invention. [Simplified Explanation of the Diagram]

[0010] The content of this invention will become clearer from the following detailed description and with reference to the accompanying drawings. In the drawings, the same elements may be represented by the same element symbols. Figure 1 shows an exemplary top view of a graphene processing and transfer chamber of a graphene synthesis tool according to several embodiments of the present invention. Figure 2 shows an exemplary schematic diagram of the internal components of a processing chamber according to several embodiments of the present invention. Figure 3 shows a process flow diagram of a graphene synthesis tool according to several embodiments of the present invention. Figure 4 shows an example high-order flow diagram of a method according to several embodiments of the present invention, in which deposited material migrates (e.g., diffuses) to the surface of a substrate by passing through a diffusion couple metal deposited on a substrate (e.g., a Si wafer) to form a diffusion couple. Figure 5 shows another example high-order flow diagram of a method according to several embodiments of the present invention, in which deposited material migrates to the surface of a substrate by passing through a diffusion couple metal deposited on a substrate to a substrate surface. Figure 6 shows an example high-order flow diagram according to several embodiments of the present invention, in which a top heater and a bottom heater are used to pressurize and heat the substrate at uniform pressure and temperature. Figure 7 shows an exemplary side view of a commercial bonding tool, which, according to some embodiments of the present invention, can be applied to a graphene processing chamber as a carbon source synthesis tool or for other applications. Figure 8A shows an exemplary side view of a commercial isostatic pressing (IPS) sintering apparatus, which, according to some embodiments of the invention, can be used as a graphene processing chamber for carbon source synthesis tools or for other applications. Figure 8B shows an exemplary side view of other commercial and research IPS sintering apparatuses. Figure 9 shows an exemplary side view of a commercial / research hot isostatic pressing (HIP) apparatus, which, according to some embodiments of the invention, can be used as a graphene processing chamber for carbon source synthesis tools. Figure 10 shows an exemplary perspective view of an alternative commercial and research hot autoclave (HPV) apparatus design, which, according to some embodiments of the invention, can be used as a graphene processing chamber for carbon source synthesis tools or for other applications.

[0011] The above figures are representative and are not intended to exhaustively list all specific embodiments of the present invention.

Claims

1. A method for forming transistor interconnects over a semiconductor device substrate, the method comprising: A semiconductor device substrate is provided, comprising a CMOS transistor and an interlayer dielectric, wherein the interlayer dielectric is located above the CMOS transistor and comprises SiO2 (silicon dioxide); a metal catalyst layer is deposited on the interlayer dielectric, wherein the metal catalyst layer comprises Ni (nickel), Co (cobalt), Ru (ruthenium), or Mo (molybdenum); a diffusion material comprising carbon is deposited on the metal catalyst layer; the semiconductor device substrate is then loaded into a processing chamber, wherein the processing chamber includes a heatable base plate heated to a specified temperature, wherein the specified temperature is greater than 50°C and less than 450°C; the semiconductor device substrate is placed on the heatable base plate, wherein the processing chamber includes a heatable top plate configured to move vertically to apply mechanical pressure to the semiconductor device substrate on the heatable base plate, wherein the mechanical pressure is applied... The mechanical pressure is greater than 30 psi and less than 1000 psi; and graphene is subsequently formed, wherein the graphene is distributed at the interface between the interlayer dielectric and the metal catalyst layer, and wherein the processing chamber is part of a modified or unmodified commercial tool or device, and wherein the modified or unmodified commercial tool or device is a bonding tool, or a hot pressing tool, or an isostatic pressing sintering device, or a hot isostatic pressing (HIP) device, or a hot autoclave (HPV) device.

2. According to the method of request item 1, where, The diffusion material includes amorphous carbon.

3. According to the method of request item 1, where, The graphene includes high-quality graphene material, wherein the high quality is characterized by a Raman spectral G / D ratio greater than 1.

0.

4. According to the method of request item 1, where, The semiconductor device substrate includes a single-crystal, polycrystalline, or amorphous structure, which includes the semiconductor elements silicon or germanium, or a combination of these elements.

5. According to the method of request item 1, where, During the application of this mechanical pressure, the air pressure in the processing chamber is maintained at less than 10⁻⁶ Torr.

6. According to the method of request item 1, where, The processing chamber is supplied with pressurized gas, wherein the pressurized gas includes nitrogen, helium, argon, or carbon, or a combination thereof.

7. According to the method of request item 1, where, The processing chamber has a gas pressure greater than 30 psi, and the gas pressure impacts the semiconductor device substrate.

8. A method for forming transistor interconnects over a semiconductor device substrate, the method comprising: A semiconductor device substrate is provided, comprising a CMOS transistor and an interlayer dielectric, wherein the interlayer dielectric is located above the CMOS transistor and comprises SiO2 (silicon dioxide); a metal catalyst layer is deposited on the interlayer dielectric, wherein the interlayer dielectric comprises SiO2 (silicon dioxide); wherein the metal catalyst layer comprises Ni (nickel), Co (cobalt), Ru (ruthenium), or Mo (molybdenum); a diffusion material comprising carbon is deposited on the metal catalyst layer; the semiconductor device substrate is then loaded into a processing chamber, wherein the processing chamber includes a heatable base plate heated to a specified temperature; the semiconductor device substrate is placed on the heatable base plate, wherein the processing chamber includes a heatable top plate configured to move vertically to apply mechanical pressure to the semiconductor device substrate on the heatable base plate. The mechanical pressure is applied while the pressure in the processing chamber is maintained at less than 10⁻³ Torr; and graphene is subsequently formed, wherein the graphene is distributed at the interface between the interlayer dielectric and the metal catalyst layer, wherein the processing chamber is part of a modified or unmodified commercial tool or apparatus, and wherein the modified or unmodified commercial tool or apparatus is a bonding tool, or a hot pressing tool, or an isostatic pressing sintering apparatus, or a hot isostatic pressing (HIP) apparatus, or a hot autoclave (HPV) apparatus, and wherein the heatable top plate applies a mechanical pressure of 30 psi to 1000 psi to the substrate.

9. According to the method in request item 8, where, The diffusion material includes amorphous carbon.

10. According to the method in request item 8, where, The graphene includes high-quality graphene material, wherein the high quality is characterized by a Raman spectral G / D ratio greater than 1.

0.

11. According to the method in request item 8, where, The semiconductor device substrate includes a single-crystal, polycrystalline, or amorphous structure, which includes the semiconductor elements silicon or germanium, or a combination of these elements.

12. According to the method in request item 8, where, The diffusion material includes amorphous carbon, wherein the graphene includes high-quality graphene material, and wherein the high quality is characterized by a Raman spectral G / D ratio greater than 1.

0.

13. According to the method in request item 8, where, The heated top plate applies the mechanical pressure while the processing chamber is first evacuated and then an inert gas is introduced, wherein the inert gas includes nitrogen, helium, argon, or a combination thereof.

14. According to the method in request item 8, where, The specified temperature is greater than 50°C and less than 450°C.

15. According to the method in request item 8, where, The processing chamber has a gas pressure greater than 30 psi, and the gas pressure impacts the semiconductor device substrate.

16. A method for forming transistor interconnects on top of a semiconductor device substrate, the method comprising: A semiconductor device substrate is provided, comprising a CMOS transistor and an interlayer dielectric, wherein the interlayer dielectric is located above the CMOS transistor and comprises SiO2 (silicon dioxide); a metal catalyst layer is deposited on the interlayer dielectric, wherein the metal catalyst layer comprises Ni (nickel), Co (cobalt), Ru (ruthenium), or Mo (molybdenum); a diffusion material is deposited on the metal catalyst layer, wherein the diffusion material comprises carbon; the semiconductor device substrate is then loaded into a processing chamber, wherein the processing chamber includes a heatable base plate heated to a specified temperature; the semiconductor device substrate is placed on the heatable base plate, wherein the processing chamber includes a heatable top plate configured to move vertically to apply mechanical pressure to the semiconductor device substrate on the heatable base plate, an inert gas is introduced into the processing chamber while the mechanical pressure is applied, wherein the inert gas comprises nitrogen, helium, or argon, or a combination thereof. The mechanical pressure is greater than 30 psi and less than 1000 psi; and graphene is subsequently formed, wherein the graphene is distributed at the interface between the interlayer dielectric and the metal catalyst layer, and wherein the processing chamber is part of a modified or unmodified commercial tool or device, wherein the modified or unmodified commercial tool or device is a bonding tool, or a hot pressing tool, or an isostatic pressing sintering device, or a hot isostatic pressing (HIP) device, or a hot autoclave (HPV) device, and wherein the diffusion material comprises amorphous carbon.

17. According to the method of request item 16, where, The processing chamber has a gas pressure greater than 30 psi, and the gas pressure impacts the semiconductor device substrate.

18. According to the method of request item 16, where, The specified temperature is greater than 50°C and less than 450°C.

19. According to the method of request item 16, where, The graphene comprises high-quality graphene material, wherein the high quality is characterized by a Raman spectral G / D ratio greater than 1.0.

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