Program-verify techniques in a memory device

Abstract

The memory device includes a memory block having a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings. The memory device also includes a circuit system configured to program the memory cells of a selected word line among the plurality of word lines into a plurality of data states in a plurality of programming loops, the programming loops including programming pulses and verification operations. During at least one of the verification operations, the circuit system is configured not to lock a set of the plurality of NAND strings. The set of NAND strings includes at least some of the fully programmed memory cells of the selected word line, such that conductivity is achieved through the NAND strings in the set during sensing.

Description

Technical Field

[0001] This disclosure is largely about a procedural verification technique for mitigating the impact of CELSRC rebound. Prior Technology

[0002] Semiconductor memory is widely used in various electronic devices, such as cell phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery pack).

[0003] NAND memory devices include a chip having a plurality of memory blocks, each of which includes an array of memory cells arranged in a plurality of word lines. Programming the memory cells of a word line to retain data typically occurs in a plurality of programming loops, each of which includes a control gate that applies programming pulses to the word line and a verification operation for sensing threshold voltages of the programmed memory cells. Data is sensed during both the programming operation and subsequent read operations. Continuous improvement of sensing technology is still needed to enhance the reliability of sensing operations. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for performing a programmed operation in a memory device. The method proceeds to the following steps: preparing a memory block comprising a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings. The method proceeds to the following steps: programming the memory cells of a selected word line among the plurality of word lines into a plurality of data states in a plurality of programming loops. The programming loops include programming pulses and verification operations. In at least one of the programming loops, during the verification operation, the method proceeds to the following step: not locking a set of the plurality of NAND strings. The set of NAND strings includes at least some of the programmed memory cells of the selected word line, such that conductivity is achieved through the NAND strings in the set during sensing.

[0005] According to another aspect of this disclosure, the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

[0006] According to yet another aspect of this disclosure, the step of not locking the NAND string of the set so that the NAND string of the set is conductive during sensing occurs during the programming of the plurality of later data states.

[0007] According to another aspect of this disclosure, the plurality of stylized data states includes seven stylized data states, and the plurality of subsequent data states includes three of the seven stylized data states.

[0008] According to a further aspect of this disclosure, the NAND strings in the set include the NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

[0009] According to a further embodiment of this disclosure, the memory device further includes a source line, which is set to approximately zero volts (0 V) during sensing.

[0010] According to a further embodiment of this disclosure, the method further includes the step of applying a verification voltage to the selected word line during the verification operation of at least one of the programmed loops.

[0011] Another aspect of this disclosure relates to a memory device comprising a memory block having a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings. The memory device also includes a circuitry configured to program the memory cells of a selected word line among the plurality of word lines into a plurality of data states in a plurality of programming loops, the programming loops including programming pulses and verification operations. During at least one of the verification operations, the circuitry is configured not to lock a set of the plurality of NAND strings. The set of NAND strings includes at least some of the fully programmed memory cells of the selected word line, such that conductivity is achieved through the NAND strings in the set during sensing.

[0012] According to another aspect of this disclosure, the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

[0013] According to yet another aspect of this disclosure, the circuit system is configured to not lock the plurality of NAND strings in the set during the programming of the plurality of late data states.

[0014] According to another aspect of this disclosure, the plurality of stylized data states includes seven stylized data states, and the plurality of subsequent data states includes three of the seven stylized data states.

[0015] According to a further aspect of this disclosure, the NAND strings in the set include the NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

[0016] According to a further embodiment of this disclosure, the memory device further includes a source line, wherein during sensing, the circuitry sets the source line to approximately zero volts (0 V).

[0017] According to another aspect of this disclosure, during the verification operation of at least one of these programmed loops, the circuit system applies a verification voltage to the selected word line.

[0018] Another aspect of this disclosure relates to a device comprising a memory block having a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings. The device also includes a programming component for programming the memory cells of a selected word line among the plurality of word lines into a plurality of data states during a plurality of programming loops including programming pulses and verification operations. During at least one of the verification operations, the programming component is configured not to lock a first set of the plurality of NAND strings, the first set of NAND strings including at least some of the fully programmed memory cells of the selected word line. The programming component is also configured to conduct electricity through the first set of NAND strings and through a second set of NAND strings including the fully programmed memory cells of the selected word line.

[0019] According to another aspect of this disclosure, the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

[0020] According to another example of this disclosure, the programming component is configured to not lock the plurality of NAND strings of the set during the programming of the plurality of late data states.

[0021] According to a further aspect of this disclosure, the plurality of stylized data states includes seven stylized data states, and the plurality of subsequent data states includes three of the seven stylized data states.

[0022] According to a further aspect of this disclosure, the first set of NAND strings includes NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

[0023] According to a further embodiment of this disclosure, the device further includes a source line, and during sensing, the programming component sets the source line to approximately zero volts (0 V). Simple Explanation of the Diagram

[0024] The following description will be more detailed with reference to the exemplary embodiments depicted in the accompanying drawings. It should be understood that these drawings merely depict exemplary embodiments of the present disclosure and should therefore not be considered as limiting its scope. This disclosure is described and explained with additional specificity and detail using the accompanying drawings, in which: [Figure 1A] is a block diagram of an example memory device; [Figure 1B] is a block diagram of the example control circuit; [Figure 1C] is a block diagram of an example circuit system of the memory device in Figure 1A; [Figure 2] A block depicting the memory cells in an example two-dimensional configuration of the memory array in Figure 1A; [Figure 3A] and [Figure 3B] depict cross-sectional views of an instance of a floating gate memory cell in a NAND string; [Figure 4A] and [Figure 4B] depict cross-sectional views of an instance charge-capture memory cell in a NAND string; [Figure 5] An example block diagram depicting the sensing block SB1 of Figure 1; [Figure 6A] is a perspective view of a block of a set in the three-dimensional configuration of the memory array example in Figure 1; [Figure 6B] A cross-sectional view depicting a portion of one of the blocks in Figure 6A; [Figure 6C] A drawing depicting the diameter of the memory vias in the stack shown in Figure 6B; [Figure 6D] A close-up view depicting the stacked region 622 of Figure 6B; [Figure 7A] A top view depicting an example of the stacked word line layer WL0 of Figure 6B; [Figure 7B] A top view depicting the top dielectric layer DL116 of an example stack of Figure 6B; [Figure 8] Depicts the threshold voltage distribution of a page of memory cells, programmed as one bit per memory cell (SLC); [Figure 9] Depicts the threshold voltage distribution of a page of memory cells, programmed as a three-bit per memory cell (TLC); [Figure 10] shows the waveform of the voltage applied to the select word line during the instance programming operation; [Figure 11] is a schematic diagram illustrating the selection of a NAND string during a typical sensing operation; [Figure 12] is a plot of the sensing node voltage versus time during an illustrative sensing operation; [Figure 13] is a schematic diagram of an instance memory block comprising multiple NAND strings during a sensing operation; [Figure 14] is a schematic diagram illustrating the voltage applied to a plurality of word lines in a memory block during an exemplary negative sensing operation; [Figure 15] is a schematic diagram illustrating the voltage applied to a plurality of word lines in a memory block during an exemplary positive sensing operation; [Figure 16] is a plot of the threshold voltage distribution of two sets of memory cells programmed into data states, wherein one set of memory cells is programmed using positive sensing during the verification operation, and the other set is programmed using negative sensing during the verification operation; [Figure 17A] is a plot of the threshold voltage distribution of a plurality of memory cells programmed into three sub-cells (TLC) per memory cell during the programming of the S6 data state according to a type of programming operation; [Figure 17B] is a plot of the critical voltage distribution of multiple memory cells that have been programmed into TLC during the read operation of the S6 data state; [Figure 18] is a flowchart of steps including a programmable memory device according to an exemplary embodiment of the present disclosure; [Figure 19A] is a plot of the threshold voltage distribution of a plurality of memory cells of a TLC during the programming operation of the S6 data state according to an exemplary embodiment; and [Figure 19B] is a plot of the threshold voltage distribution of multiple memory cells that have been programmed into TLC during the read operation of the S6 data state. Implementation

[0025] This disclosure relates primarily to program verify technology, whereby certain NAND strings coupled to a programmed memory cell are not locked during sensing. This allows the CELSRC bounce that occurs during positive sensing to exhibit a more consistent pattern during both verification and read operations. This consistency improves the overall reliability of data programmed into the memory cell. These techniques will be discussed in further detail below.

[0026] Figure 1A is a block diagram of an example memory device 100 configured to program memory cells in word lines of memory blocks according to the sensing technology disclosed herein. Memory die 108 includes a memory structure 126 of memory cells, such as a memory cell array, a control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable by word lines via column decoder 124 and by bit lines via row decoder 132. Read / write circuitry 128 includes multiple sensing blocks SB1, SB2, ..., SBp (sensing circuitry) and allows parallel reading or programming of a page of memory cells. Generally, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Instructions and data are transferred between host 140 and controller 122 via data bus 120, and between controller and one or more memory chips 108 via line 118.

[0027] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 may include one or more memory cell arrays comprising a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed on (but not within) a single substrate (such as a wafer), without an intermediate substrate. The memory structure 126 may include any type of non-volatile memory, which is monolithically formed in one or more solid layers of memory cell arrays having active regions disposed on a silicon substrate. The memory structure 126 may be located in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0028] The control circuit system 110 works in conjunction with the read / write circuit 128 to perform memory operations on the memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

[0029] For example, a storage area 113 may be provided for programming parameters. Programmable parameters may include programming voltage, programming voltage bias, location parameters indicating the location of memory cells, contact connector thickness parameters, verification voltage, and / or the like. Location parameters may indicate the location of memory cells within the entire NAND string array, the location of memory cells within a specific NAND string group, the location of memory cells on a specific plane, and / or the like. Contact connector thickness parameters may indicate the thickness of the contact connector, the substrate or material contained within the contact connector, and / or the like.

[0030] On-chip address decoder 114 provides an address interface between addresses used by the host or memory controller and hardware addresses used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to word lines and bit lines during memory operation. It may include drivers for word lines, SGS and SGD transistors, and source lines. In one method, a sensing block may include bit line drivers. The SGS transistor system includes a select gate transistor at the source terminal of the NAND string, and the SGD transistor system includes a select gate transistor at the drain terminal of the NAND string.

[0031] In some embodiments, some components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit system 110, state machine 112, decoder 114 / 132, power control module 116, sensing blocks SBb, SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0032] The control circuit 150 may include a programming circuit 151 configured to perform programming and verification operations on a set of memory cells, wherein the set of memory cells includes memory cells assigned to represent one of a plurality of data states and memory cells assigned to represent another of the plurality of data states; the programming and verification operations include a plurality of programming and verification iterations; and in each programming and verification iteration, the programming circuit programs a selected word line, and then applies a verification signal to the selected word line. The control circuit 150 may also include a counting circuit 152 configured to obtain a count of memory cells that have passed the verification test for the data state. The control circuit 150 may also include a determination circuit 153 configured to determine whether the programming operation is complete based on the amount by which the count exceeds a threshold.

[0033] For example, Figure 1B is a block diagram of the example control circuit 150, which includes a programming circuit 151, a counting circuit 152, and a decision circuit 153.

[0034] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, an error-correction code (ECC) engine 245, and a locking engine 246. The ECC engine can correct several read errors caused by an excessively high upper tail of the Vt distribution. However, in some cases, there may be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0035] Multiple storage devices 122a, 122b contain code such as an instruction set, and processor 122c is operable to execute the instruction set to provide the functionality described herein. Alternatively or additionally, processor 122c may access the code from storage device 126a of memory structure 126 (such as a reserved area of ​​memory cells in one or more word lines). For example, the code may be used by controller 122 to access memory structure 126, such as for programming, read, and erase operations. The code may include boot code and control code (e.g., an instruction set). The boot code is software that initializes controller 122 and enables controller 122 to access memory structure 126 during startup or start-up. The code may be used by controller 122 to control one or more memory structures 126. Upon power-up, processor 122c retrieves the code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. After the control code is loaded into RAM 122b, it is executed by processor 122c. The control code includes drivers for performing basic tasks, such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0036] Typically, control codes may include instructions for performing the functions described herein (including the steps in the flowcharts discussed further below) and providing voltage waveforms (including the voltage waveforms discussed further below). For example, as shown in Figure 1C, control circuitry 110, controller 122, control circuitry 150, and / or any other circuitry are configured / programmed to perform programmed operations using unique NAND string locking technology. In step 160, data states S1 to Sn-1 do not require programming using unique locking technology. In step 161, during the verification of data states Sn to S7, all memory cells Er to Sn-1 are not locked (conductive) except for one of those data states. These techniques will be discussed in further detail below.

[0037] In one embodiment, the host computer is a computing device (e.g., a laptop, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming one or more processors to perform the methods described herein. The host computer may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with one or more processors.

[0038] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0039] Semiconductor memory devices include: volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Different types of memory devices can have different configurations. For example, flash memory devices can be configured as NAND or NOR.

[0040] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements (such as antifuse or phase-change materials) and optional control elements (such as diodes or transistors). Further as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as float gates, conductive nanoparticles, or charge storage dielectric materials.

[0041] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. As a non-limiting example, a flash memory device (NAND memory) configured as NAND generally contains memory elements connected in series. An example of a NAND series includes a set of memory cells and SG transistors connected in series.

[0042] NAND memory arrays can be configured such that the array consists of multiple memory strings, where a string comprises multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, in a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located within and / or on the substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0043] In a two-dimensional memory structure, semiconductor memory elements are disposed in a single plane or a single memory device level. Generally, in a two-dimensional memory structure, the memory elements are disposed in a plane extending substantially parallel to the main surface of the substrate supporting the memory elements (e.g., in an xy-direction plane). The substrate may be a wafer on which a layer of memory elements is formed, or it may be a carrier substrate attached to such memory elements after their formation. As a non-limiting example, the substrate may include semiconductors such as silicon.

[0044] Memory elements can be arranged in an ordered array (such as in multiple columns and / or rows) within a single memory device level. However, memory elements can be arranged irregularly or non-orthogonally. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0045] The three-dimensional memory array is configured such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to the main surface of the substrate, and the x and y directions are substantially parallel to the main surface).

[0046] As a non-limiting example, a three-dimensional memory structure can be vertically configured as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array can be configured as multiple vertical rows (e.g., rows extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction)), each row having multiple memory elements. The rows can be configured in two dimensions, for example, in the xy-plane, thereby producing a three-dimensional configuration of memory elements with multiple vertically stacked elements on a memory plane. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

[0047] As a non-limiting example, in a three-dimensional NAND string array, memory elements can be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements can be coupled together to form a vertical NAND string spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0048] Generally, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are generally formed on the layers of the underlying memory device levels of the array. However, the layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared or have an intermediary layer between the memory device levels.

[0049] Furthermore, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels together. The substrate can be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Further, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate wafers and then packaged together to form a stacked wafer memory device.

[0050] Figure 2 illustrates memory blocks 200 and 210 of memory cells in an example two-dimensional configuration of the memory array 126 of Figure 1. The memory array 126 may include a plurality of such blocks 200 and 210. Each example block 200 and 210 includes several NAND strings and individual bit lines, such as BL0, BL1, ... shared between blocks. One end of each NAND string is connected to a drain-side select gate (SGD), and the control gate of the drain-side select gate is connected via a common SGD line. The other end of the NAND string is connected to a source-side select gate (SGS), which is in turn connected to a common source line 220. One hundred and twelve word lines (e.g., WL0 to WL111) extend between the SGS and the SGD. In some embodiments, a memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines without user data can also be used in memory arrays adjacent to selected transistors or between certain data word lines. These dummy word lines can protect edge data word lines from certain edge effects.

[0051] A non-volatile memory system with a floating gate, such as the type shown in Figures 3A and 3B, can be provided in a memory array. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in Figures 4A and 4B, the charge-capturing memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric material formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between the conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are captured and stored in a confined region within the nitride. This stored charge then detectably alters a portion of the cell channel's threshold voltage. The cell is erased by injecting a hot hole into the nitride. A similar cell can be provided in a gate-divided configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0052] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where the ONO dielectric layer extends across the channel between source and drain diffusion. The charge for one data bit is located in the dielectric layer adjacent to the drain, and the charge for the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is achieved by reading the binary states of the spatially separated charge storage regions within the dielectric separately. Other types of non-volatile memory are also known.

[0053] Figure 3A illustrates a cross-sectional view of example floating gate memory cells 300, 310, and 320 in a NAND string. In this figure, the bit lines or NAND string direction enters the page, and the word lines direction is from left to right. As an example, word line 324 spans the NAND string extension including respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell 300, 310, and 320 is located in a different individual NAND string. An inter-poly dielectric (IPD) layer 328 is also shown. The control gates 302, 312, and 322 are part of the serial number lines. Figure 3B provides a cross-sectional view along the contact line connector 329.

[0054] Control gates 302, 312, and 322 surround float gates 304, 314, and 321, increasing the surface contact area between control gates 302, 312, and 322 and float gates 304, 314, and 321. This results in higher IPD capacitance, leading to a higher coupling ratio and making programming and erasing easier. However, as the size of NAND memory devices shrinks, the spacing between adjacent cells 300, 310, and 320 becomes smaller, so there is almost no space between two adjacent float gates 302, 312, and 322 to accommodate control gates 302, 312, and 322 and the IPD layer 328.

[0055] As an alternative, as shown in Figures 4A and 4B, planar or planar memory cells 400, 410, and 420 have been developed, in which control gates 402, 412, and 422 are planar or planar; that is, they do not surround the float gate, and their only contact with the charge storage layer 428 is above it. In this case, there are no advantages to having a tall float gate. Instead, the float gate becomes thinner. Furthermore, the float gate can be used to store charge, or a thin charge-trapping layer can be used to trap charge. This method avoids the problem of ballistic electron transport, where electrons can pass through the float gate after tunneling through the tunnel oxide during programming.

[0056] Figure 4A depicts a cross-sectional view of example charge-trapping memory cells 400, 410, and 420 in a NAND string. The view is in the word line direction of memory cells 400, 410, and 420, which include flat control gates and charge-trapping regions, as two-dimensional examples of memory cells 400, 410, and 420 in the memory cell array 126 of Figure 1. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, unlike the floating-gate MOSFET technology which uses a conductor such as doped polysilicon to store electrons. As an example, word line 424 extends across a NAND string including individual channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are IPD layer 428, charge trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge trapping layer 404, 414, and 421 extends continuously within its respective NAND string. The flat configuration of the control gate can be made thinner than a floating gate. Additionally, memory cells can be placed more compactly together.

[0057] Figure 4B illustrates a cross-sectional view of the structure of Figure 4A along the contact line connector 429. The NAND string 430 includes an SGS transistor 431, instance memory cells 400, 433, ..., 435, and an SGD transistor 436. Channels in the IPD layer 428 of the SGS transistor 431 and SGD transistor 436 allow communication between the control gate layer 402 and the floating gate layer. For example, the control gate layer 402 and the floating gate layer may be polysilicon, and the tunnel oxide layer may be silicon oxide. The IPD layer 428 may be a stack of nitride (N) and oxide (O), such as in an N—O—N—O—N configuration.

[0058] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0059] Figure 5 illustrates an example block diagram of the sensing block SB1 of Figure 1. In one approach, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, example sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different individual sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and handled by individual processors in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with the set of sensing circuits and latches. The sensing circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sensing circuit to set a precharge voltage. In one possible approach, the voltage is provided independently to each sensing circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage is provided to each sensing circuit simultaneously. The sensing circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code executable by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, and 553b associated with the sensing circuits 550a, 551a, 552a, and 553a; setting bit values ​​in the latches; and providing voltages for setting precharge levels in the sensing nodes of the sensing circuits 550a, 551a, 552a, and 553a. Further examples of the sensing circuit controller 560 and the sensing circuits 550a, 551a, 552a, and 553a are provided below.

[0060] In some embodiments, a memory cell may include a flag register comprising a set of latches storing flag bits. In some embodiments, the number of flag registers may correspond to the number of data states. In some embodiments, one or more flag registers may be used to control the type of verification technique used when verifying a memory cell. In some embodiments, the output of the flag bits may modify associated logic of the device, such as an address decoding circuitry, to select a specified cell block. Batch operations (e.g., erase operations) may be performed using flags set in flag registers or combinations of flag registers and address registers, such as in implicit addressing or alternatively by direct addressing using only address registers.

[0061] Figure 6A is a perspective view of a set of blocks 600 in an example three-dimensional configuration of the memory array 126 of Figure 1. The substrate contains example blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (storage elements) and a peripheral region 604 having circuitry used by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuitry may include a voltage driver 605, which can be connected to the control gates of blocks BLK0, BLK1, BLK2, and BLK3. In one method, the control gates at a common height in blocks BLK0, BLK1, BLK2, and BLK3 are commonly driven. The substrate 601 may also carry the circuitry beneath blocks BLK0, BLK1, BLK2, and BLK3, as well as one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in a central region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuit system. Each block BLK0, BLK1, BLK2, BLK3 contains a stacked area of ​​memory cells, where alternating stacked levels represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposing layered sides, from which vertical contacts extend upwards to the upper metal layer to form connections with the conductive paths. Although four blocks BLK0, BLK1, BLK2, BLK3 are illustrated as an example, two or more blocks extending in the x and / or y directions may also be used.

[0062] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0063] Figure 6B illustrates an example cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, and BLK3 in Figure 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers, in addition to the data word line layers (word lines) WL0 to WL111, also include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. Further, the region of the stack 610 containing NAND strings NS1 and NS2 is shown. Each NAND string includes memory vias 618 and 619, which are filled with material forming memory cells adjacent to the word lines. Region 622 of the stack 610 is shown in more detail in Figure 6D and will be discussed further below. The dielectric layers may have variable thicknesses, allowing some conductive layers to be closer to or further away from adjacent conductive layers. The thickness of the dielectric layer affects the "ON pitch," which is a factor influencing memory density. Specifically, a smaller ON pitch allows more memory cells to be accommodated in a given area, but may compromise reliability.

[0064] Stack 610 includes a substrate 611, an insulating film 612 on the substrate 611, and a portion of a source line SL. NS1 has a source end 613 at the bottom 614 of stack 610 and a drain end 615 at the top 616 of stack. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 may be periodically provided across stack 610 as interconnects extending through stack 610, such as to connect source lines to specific contact lines above stack 610. Contact line connectors 617, 620 may be used during word line formation and then filled with metal. A portion of bit line BL0 is also illustrated. Conductive via 621 connects drain end 615 to BL0.

[0065] Figure 6C illustrates a plot of the memory via diameters in the stack of Figure 6B. The vertical axis is aligned with the stack of Figure 6B and plots the widths (wMH), e.g., diameters, of memory vias 618 and 619. Word line layers WL0 to WL111 in Figure 6A are repeated as examples, at individual heights z0 to z111 in the stack. In this memory device, the memory vias etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory vias can vary along the length of the via. Generally, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, the vias near the selector may narrow slightly at the top, making the diameter slightly wider, and then gradually decrease from the top to the bottom of the memory via.

[0066] Figure 6D shows a close-up view of region 622 of the stack 610 in Figure 6B. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680 and 681 are disposed above dummy memory cells 682 and 683 and data memory cells MC. Atomic layer deposition can be used, for example, to deposit several layers along the sidewall (SW) of the memory via 630 and / or within each word line layer. For example, each pillar (e.g., a pillar formed by material within the memory via 630) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunneling layer 664, a polysilicon or channel 665, and a dielectric core 666. The word line layers may include a barrier oxide / high-k barrier material 660, a metal barrier layer 661, and a conductive metal (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are disposed within the memory via 630. In other methods, some layers may be located within the gate control layer. Similarly, additional pillars are formed within different memory vias. These pillars can form the columnar active area (AA) of the NAND string.

[0067] When a memory cell is programmed, electrons are stored in a portion of a charge trapping layer associated with the memory cell. These electrons are drawn from the channel into the charge trapping layer and then pass through a tunneling layer. The threshold voltage Vt of the memory cell increases proportionally to the amount of stored charge. During a sensing operation, the threshold voltage Vt is detected or measured. During an erase operation, the electrons return to the channel.

[0068] Each of the memory holes 630 may be filled with a plurality of annular layers, which include a barrier oxide layer, a charge trapping layer 663, a tunneling layer 664, and a channel layer. The core region of each of the memory holes 630 is filled with a host material, and the plurality of layers are located between the core region of each of the memory holes 630 and the word line layer. In some cases, the charge trapping layer 663 and the tunneling layer 664 are annular. In other cases, as discussed in further detail below, these layers are semi-circular.

[0069] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by a plurality of word line layers stacked on top of each other and separated by dielectric layers.

[0070] Figure 7A shows a top view of an example word line layer WL0 of the stack 610 of Figure 6B. As described above, a three-dimensional memory device may comprise a stack of alternating conductive and dielectric layers. The conductive layers provide control gates for the SG transistors and memory cells. A layered SG layer is used for the SG transistors, and a layered word line layer is used for the memory cells. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. As a result, vertical NAND strings are formed. Source lines connect to the NAND strings below the stack, while bit lines connect to the NAND strings above the stack.

[0071] In a three-dimensional memory device, a block BLK can be divided into sub-blocks, each containing a NAND string with a common SGD control line. Further, the word line layer within the block can be divided into regions. Each region is located within a separate sub-block and can extend between contact line connectors (e.g., gaps), which are periodically formed in the stack to process the word line layer during the memory device manufacturing process. This processing may include replacing the sacrificial material of the word line layer with metal. Typically, the distance between contact line connectors should be relatively small to address limitations on the distance that etchant can move laterally to remove the sacrificial material and the distance that metal can move to fill the gaps resulting from the removal of the sacrificial material. For example, the distance between contact line connectors may allow for several rows of memory vias between adjacent contact line connectors. The layout of the memory vias and contact line connectors should also take into account the limitation on the number of bit lines that can extend across regions, while each bit line connects to different memory cells. After processing the word line layer, the contact line connectors may be selectively filled with metal to provide interconnects across the stack.

[0072] In this example, there are four columns of memory vias between adjacent contact line connectors. The columns in this document represent a group of memory vias aligned in the x-direction. Furthermore, the columns of memory vias are staggered to increase the density of the memory vias. The word line layer or word line is divided into regions WL0a, WL0b, WL0c, and WL0d, each connected by a free contact line 713. In one method, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact lines 713 are also connected to voltage drivers for the word line layer. Example memory vias 710 and 711 are found along contact line 712 in region WL0a. Example memory vias 714 and 715 are found in region WL0b. Example memory vias 716 and 717 are found in region WL0c. Example memory vias 718 and 719 are found in region WL0d. Memory vias are also shown in Figure 7B. Each memory via may be part of a separate NAND string. For example, memory holes 710, 714, 716, and 718 can be parts of the NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0073] Each circle represents a cross-section of a memory via at a word line layer or SG layer. Example circles shown with dashed lines represent memory cells provided by the material in the memory via and adjacent word line layers. For example, memory cells 720 and 721 are in WL0a, memory cells 724 and 725 are in WL0b, memory cells 726 and 727 are in WL0c, and memory cells 728 and 729 are in WL0d. These memory cells share a common height in the stack.

[0074] Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a to WL0d. Contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, the source line at the bottom of the stack may be connected to a conductive line above the stack, wherein the conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0075] Figure 7B illustrates a top view of the top dielectric layer DL116 of an example stack of Figure 6B. The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a separate voltage driver. This allows simultaneous programming of a set of memory cells in a region of the word line layer, where each memory cell is located in a separate NAND string connected to a separate bit line. Voltages can be set on each bit line during programming, sensing, or erasing operations.

[0076] Region DL116a has instance memory holes 710, 711 along contact line 712 coinciding with bit line BL0. Several bit lines extend above and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a set of memory holes including memory holes 711, 715, 717, 719. Another instance bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, 718. Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 from FIG7A are also shown because they extend perpendicularly through the stack. Bit lines can be numbered in the -x direction across layers DL116 in the order BL0 to BL23.

[0077] Different subsets of bit lines are connected to memory cells in different columns. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to memory cells in the first column of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to memory cells in adjacent columns, which are adjacent to the first column at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to memory cells in the first column of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to memory cells in adjacent columns, which are adjacent to the first column at the left edge.

[0078] Memory cells in a memory block can be programmed to store one or more data bits of multiple data states, each of which is associated with a separate threshold voltage range Vt and a separate bit or series of bits. For example, Figure 8 depicts the threshold voltage Vt distribution of a group of programmed memory cells according to a storage scheme of one bit per memory cell (SLC). In the SLC storage scheme, there are a total of two data states, including an erase state (Er) and a single programmed data state (S1). Figure 9 illustrates the threshold voltage Vt distribution of a three-bit per cell (TLC) storage scheme, which includes eight total data states, namely the erase state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1 to S7) is associated with a separate verification voltage (Vv1 to Vv7), which is used during the verification portion of the programming operation. Similarly, each programmed data state is associated with a unique read voltage, which may be the same as or different from the individual verification voltage. Other storage schemes are also available, such as two-bit per cell (MLC) with four data states, four-bit per cell (QLC) with sixteen data states, or five-bit per cell (PLC) with thirty-two data states. The QLC storage scheme includes an erase state Er and fifteen programmed data states (S1 to S15).

[0079] The programming of memory cells occurs sequentially, word-by-word, from one side of the memory block (source or drain side) toward the opposite side. In other words, the first string of word lines (e.g., four strings) is programmed sequentially one after another, then this operation is repeated for the second word line, and then for the third word line, and so on. Generally, programming memory cells via selected bit lines to retain multiple bits per memory cell (e.g., MLC, TLC, or QLC) begins when the memory cell is in an erased data state and includes multiple programming loops to increase the threshold voltage Vt of those memory cells to an appropriate voltage range associated with their respective expected data states. Each programming loop includes both a programming pulse and a verification operation. Figure 10 depicts waveform 1000 of the voltage applied to the selected word line during an instance programming operation used to program memory cells with a selected word line to a greater number of bits per memory cell (e.g., TLC or QLC). As depicted, each programming loop includes a programming pulse (hereinafter referred to as the VPGM pulse) and one or more verification pulses, depending on which data states are being programmed in a particular programming loop. For simplicity, square waveforms are depicted for each pulse; however, other shapes are possible, such as multi-layered or ramp shapes.

[0080] This example pulse train uses incremental step pulse programming (ISPP), meaning that the VPGM pulse voltage rises or increases in each successive programmed loop. More specifically, the pulse train includes VPGM pulses whose amplitude increases progressively with each successive programmed loop by a programmed voltage step (dVPGM). A new pulse train begins with a VPGM pulse at the starting voltage VPGMU and ends with a final VPGM pulse at a voltage not exceeding the maximum allowable voltage. Example pulse train 1000 includes a series of VPGM pulses 1001 to 1018, which are applied to a control gate via the select word line to program memory cells via the select word line, and the amplitude of these VPGM pulses increases by a programmed voltage step dVPGM between pulses.

[0081] Based on the target data state being verified in each programming loop, one or more verification pulses 1020 to 1036 are provided after each VPGM pulse. The verification voltage may be the voltages Vv1 to Vv7 during TLC programming as shown in Figure 9. Simultaneously with the application of the verification voltage, a sensing operation is performed to determine whether a specific memory cell in the select word line has a threshold voltage Vt higher than the verification voltage Vv associated with its expected data state by sensing the current flowing through the NAND string containing the memory cell. If the memory cell passes verification, the programming of that memory cell is complete, and further programming of that memory cell for all remaining programming loops is prohibited (or locked) by applying a suppression voltage simultaneously with the VPGM pulse to the bit line coupled to the memory cell and skipping the verification for that memory cell. During the bit scan operation, the memory device determines whether the programming of one or more of the data states is complete. Programming continues until all (or a sufficient number) memory cells of the selected word line pass the verification for their expected state (in which case, programming succeeds), or until the predetermined maximum number of programming loops is exceeded (in which case, programming fails).

[0082] Referring now to Figures 11 and 12, during a sensing operation (e.g., programmed verification or read), the sensing node SEN on the drain side of the memory block is charged to a predetermined charging voltage. A reference voltage VCG (e.g., Vv1 to Vv7 in Figure 9 during verification) is applied to the control gate of the selected word line WLn. Simultaneously, by applying a pass voltage VREAD or VREADK to the unselected word lines, all memory cells in the NAND string except those of the selected word line are turned on. A relatively higher pass voltage VREADK is applied to a pair of adjacent word lines WLn-1 and WLn+1 directly adjacent to the selected word line WLn, and a relatively lower pass voltage VREAD is applied to all other unselected word lines in the memory block. The sensing node SEN then discharges through the NAND string for a sensing time T_Sense. Since all memory cells except those via the select word line WLn are turned on by voltages VREAD and VREADK, the discharge current ICELL through the NAND string is largely determined by the threshold voltage Vt of the sensed selected memory cell. More specifically, the discharge current is determined by whether the threshold voltage Vt is greater than or less than the reference voltage VCG applied to the select word line WLn during this procedure. At discharge time T_Sense, the voltage on the sense node SEN is sensed by the sensing circuitry and compared with the sense voltage V_Sense (which is the threshold voltage Vt of the sense transistor). If the threshold voltage Vt of the sensed memory cell is higher than the reference voltage VCG, the selected memory cell will be "off" and conduct a very small / negligible current, resulting in only a small discharge of the SEN node voltage, thus maintaining a higher voltage on the sense node compared to V_Sense. If the sensed threshold voltage Vt of the selected memory cell is lower than the reference voltage VCG, the memory cell is "on" and conducts a larger discharge current, causing the sensing node bias voltage to fall below V_Sense. This procedure determines whether the threshold voltage Vt of the memory cell is higher or lower than the reference voltage VCG. This procedure can be repeated for each programmed data state.

[0083] Figure 13 illustrates an overview of a memory device structure. For example, Figure 13 depicts multiple memory strings (e.g., NAND strings) connected to a common BSL layer or cell source-receiver-container (CELSRC) layer of the memory device. The source nodes of the NAND strings are connected to the CELSRC. As further illustrated in Figure 13, the node connecting the memory vias to the sense amplifiers SA is a bit line BL. During sensing (verification or read), the cell current ICELL flows from the individual sense amplifiers SA to the CELSRC layer. The CELSRC drivers drive the CELSRC layer from opposite sides of the nodes. Therefore, the voltage at individual points around the CELSRC layer may vary as the sensed current ICELL flows into the CELSRC layer through multiple bit lines. More specifically, during sensing, the CELSRC voltage may be at its lowest value adjacent to the connection of the CELSRC drivers, and at its highest value in the central region between the CELSRC drivers.

[0084] The variable voltage across the CELSRC layer, caused by the current in the NAND string, affects the magnitude of the corresponding current ICELL in the NAND string. Without correction, this adjustment to the ICELL can cause sensing problems by making some memory cells appear to have different threshold voltages Vt than they actually do. More specifically, when the CELSRC voltage increases at the location where the NAND string is connected, the gate-to-source level Vgs and drain-to-source level Vds of the memory cells within that NAND string will decrease. The decrease in Vgs and Vds leads to a reduction in the ICELL of the current flowing through the NAND string, causing selected memory cells to appear as if they are not conducting or have a higher threshold voltage Vt than they actually do. This phenomenon is illustrated in Figure 13 and can sometimes cause CELSRC bounce, resulting in a threshold voltage shift (Vt shift). In this figure, the CELSRC gradient is influenced by the IR voltage drop (represented as a resistor in Figure 13) from the center to the edge of the CELSRC layer. Because the Vgs and Vds of NAND strings with cells having higher CELSRC voltages are smaller, CELSRC bounce and gradient can cause sensing errors. Since the voltage of the CELSRC layer varies at different locations, the sensing of memory cells in each NAND string is inconsistent.

[0085] Referring now to Figure 14, a sensing technique sometimes called "negative sensing" can be used to reduce the Vt offset caused by CELSRC bounce. Negative sensing involves applying a positive voltage VCELSRC (e.g., VCELSRC = 1 V) to the CELSRC driver during sensing operation and biasing (increasing) the bit line voltage VBL with the same voltage VCELSRC. The reference voltage VCG and the through voltages VREAD and VREADK are also increased with the same positive voltage VCELSRC. By increasing all these voltages with VCELSRC, the voltage variation at the base of the NAND string throughout the memory block is reduced. However, negative sensing results in high current ICC utilization because all voltages are set at a high level due to the bias. Furthermore, performance is affected because additional time is required to drive these components to a higher voltage level.

[0086] Figure 15 illustrates an alternative sensing technique known as "positive sensing." In positive sensing, a very low voltage (e.g., zero or approximately zero volts, VSS) is applied to the CELSRC layer during sensing, and no additional bias is added to the bit line voltage VBL, the reference voltage VCG (e.g., any of the verification voltages Vv1 to Vv7 shown in Figure 9), or the pass voltages VREAD and VREADK. Therefore, the magnitude of the voltage applied to these components is reduced compared to negative sensing. Consequently, the voltage required to rise for word lines and bit lines is reduced, resulting in lower peak and average current Icc. Additionally, positive sensing eliminates the need for rising and falling CELSRC bias, reducing rise and settling times and improving performance relative to negative sensing while all other variables remain constant. Therefore, positive sensing typically offers higher performance, less current usage, and lower power consumption compared to negative sensing.

[0087] One problem with positive sensing is that, for each data state Sn (e.g., any of S1 to S7), a large CELSRC bounce occurs in the early programming loops. This is because most of the memory cells programmed into that data state Sn are conductive, resulting in current flowing through many NAND strings. This leads to a relatively high CELSRC bounce, which can cause some memory cells programmed into data state Sn to pass verification prematurely, i.e., before their threshold voltage Vt exceeds the verification voltage Vvn. Figure 16 illustrates this phenomenon, where component symbols 1600a and 1600b show the threshold voltage Vt distribution of a plurality of memory cells programmed into data state Sn using positive sensing, and component symbols 1602a and 1602b show the threshold voltage Vt distribution of a plurality of memory cells programmed into the same data state Sn using negative sensing. As shown, because some memory cells erroneously pass verification prematurely, the lower tail of the positive sensing distribution 1602b extends below the verification level Vvn. One way to mitigate this problem is to shift the verification level up during positive sensing to prevent memory cells from passing verification prematurely.

[0088] However, positive sensing can also lead to other problems. During programming verification, the number of conductive NAND strings is less compared to during a typical read operation. This is especially true for higher data states. This is due to the NAND strings associated with data states that are not programmed during programming verification being locked. For example, in TLC programming, regardless of which particular data state Sn is being programmed, only about one-eighth (1 / 8) of the NAND strings may be conductive during any given sensing operation. Conversely, during read operations, the number of locked NAND strings is typically lower for earlier data states (e.g., data states S1, S2, and S3) and higher for later data states (e.g., data states S5, S6, and S6). For example, Figure 17A illustrates the threshold voltage Vt distribution of a plurality of memory cells programmed into TLC during programming verification of data state S6, and Figure 17B illustrates the threshold voltage Vt distribution of a plurality of programmed memory cells during read operations of data state S6. In both of these figures, solid lines represent memory cells coupled to conductive (unlocked) NAND strings, while dashed lines represent memory cells coupled to non-conductive (locked) NAND strings. As shown, substantially more memory cells (and their associated NAND strings) are conductive during reads compared to during program verification. Thus, the CELSRC bounce is similar during program verification and reads of lower data states, but varies more significantly during program verification and reads of higher data states.

[0089] To make CELSRC bounce more consistent during all programmed data state verification and reading, selective unlocked programmed verification technology is employed according to the pattern disclosed herein. This ensures that approximately the same number of NAND strings conduct during both programmed verification and reading, facilitating CELSRC bounce for positive sensing. This has been found to improve reliability and reduce failure bits during reading.

[0090] Figure 18 includes a flowchart 1800 depicting steps of programming a memory cell via a selected word line according to an exemplary embodiment of this disclosure. These steps may be performed by a controller; by a processor, or processing device, or any other circuitry that executes instructions stored in memory; and / or by other circuitry specifically configured / programmed herein to perform the following steps.

[0091] The program begins at step 1802, where the initial data state is programmed. Specifically, data states S1 to Sn-1, where the initial data state Sn is a predetermined data state at which the selective non-locking verification technique begins. During the verification operation of the programmed loop for data states S1 to Sn-1, a positive sensing scheme is used. In an exemplary embodiment, data state Sn is data state S5 of the TLC storage scheme (as shown in FIG9). In some other embodiments, data state Sn in this step may be data state S4, S6, or S7.

[0092] In step 1804, programming for the Sn data state is initiated by applying a VPGM pulse to the select word line. In step 1806, a verification operation is initiated for the data state Sn. In step 1808, memory cells from data state Sn+1 to the highest data state are locked, and memory cells programmed to a data state one level below the selected data state Sn are also locked. During subsequent sensing operations, current will not flow through the NAND string containing the locked memory cells. Instead, current will flow through the NAND string containing memory cells that are not locked during subsequent sensing operations. In the exemplary embodiment of FIG19A, the programmed data state Sn is S6, and data states S7 and S2 are locked. Memory cells for other data states Er, S1, S3, S4, and S5 are not locked.

[0093] In step 1810, a sensing operation is performed on the memory cells programmed into data state Sn to compare the threshold voltage Vt of these programmed memory cells with the verification voltage Vvn associated with the Sn data state. The sensing operation is a positive sensing operation, meaning that the source line is set to approximately zero volts (0 V) during the sensing node discharge. All unlocked NAND strings are conductive during the sensing operation. The number of memory cells that failed verification is then counted and compared with a predetermined threshold to determine whether the programming of the Sn data state is complete.

[0094] In decision step 1812, it is determined whether the verification of the Sn data status has passed. If the answer at decision step 1812 is "no", then in step 1814, the programmed voltage VPGM is increased in increments of step size dVPGM, i.e., VPGM = VPGM + dVPGM. Then another VPGM pulse is applied to the selected word line, and the program returns to step 1806.

[0095] If the answer at decision step 1812 is "yes", the program continues to decision step 1816. In decision step 1816, it is determined whether the data state Sn is the final data state to be programmed, for example, S7 in the case of a TLC. If the answer at decision step 1816 is "no", then in step 1818, the programmed data state Sn is incremented, i.e., Sn = Sn+1. In step 1820, the programmed voltage VPGM is increased in increments of step size dVPGM, i.e., VPGM = VPGM + dVPGM. Then, the VPGM pulse is applied to the select word line. The process then returns to step 1806.

[0096] If the answer at decision step 1816 is "yes", then the programmed operation is completed in step 1822.

[0097] Figure 19A illustrates the threshold voltage Vt distribution of a plurality of memory cells programmed during the programming phase of data state S6, and Figure 19B illustrates the threshold voltage Vt distribution of a plurality of memory cells programmed during the read phase of data state S6. In both figures, solid lines depict memory cells coupled to the NAND string that is on (unlocked), while dashed lines depict memory cells coupled to the NAND string that is locked (non-on) during the sensing phase. As shown, according to the technique disclosed herein, approximately the same number of memory cells conduct during both the programming verification and read phases of data state S6. Specifically, approximately three-quarters (3 / 4) of the NAND string conducts during both operations. Therefore, the CELSRC bounce will be similar during both programming verification and read phases. According to the technique disclosed herein, the same situation will occur for subsequent data states (e.g., data states S5 and S7).

[0098] As shown in Figures 19A and 19B, the technology disclosed herein also allows for the use of substantially the same reference voltage VCG during the subsequent procedural verification and reading of data states.

[0099] This document uses various terms to refer to specific system components. Different companies may use different names to refer to the same or similar components, and this description is not intended to distinguish between components with different names but the same function. Within the scope of the various functional units described in the following disclosure, referred to as "modules," this designation is intended not to unduly limit the scope of potential implementation mechanisms. For example, a "module" may be implemented as hardware circuitry including customized very-large-scale integration (VLSI) circuitry or gate arrays, or as off-the-shelf semiconductors including logic chips, transistors, or other discrete components. In further examples, modules may also be implemented in programmable hardware devices, such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, or the like. Furthermore, modules may also be implemented, at least in part, by software executed by various types of processors. For example, a module may contain executable code that constitutes an entity or logical block of one or more computer instructions that can be translated into objects, programs, or functions. Furthermore, the executable portions of this module are not required to be physically located together, but may contain different instructions stored in different locations. When executed together, these instructions encompass the identified module and achieve the intended purpose of that module. The executable code may contain only a single instruction or a set of multiple instructions, and may be distributed across different code segments, different programs, or several memory devices. In software or partial software module implementations, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based systems, devices, or apparatuses, or any suitable combination thereof. Generally, for the purposes of this disclosure, computer-readable and / or executable storage media may contain any tangible and / or non-transitory media capable of containing and / or storing programs for use by or associated with an instruction execution system, device, processor, or apparatus.

[0100] Similarly, for the purposes of this disclosure, the term "component" may include any tangible, physical, and non-transitory device. For example, a component may take the form of hardware logic circuitry comprising customized VLSI circuitry, gate arrays, or other integrated circuitry, or off-the-shelf semiconductors comprising logic chips, transistors, or other discrete components, or any other suitable mechanical and / or electronic device. Furthermore, components may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc. Additionally, a component may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die planes, and packages, or other discrete electrical devices, electrically communicating with one or more other components via electrical conductors, such as printed circuit boards (PCBs) or the like. Therefore, as described above, a module may be embodied in or implemented as a component in some embodiments, and in some instances, the terms module and component are used interchangeably.

[0101] As used herein, the term "circuit" includes one or more electrical and / or electronic components that form one or more conductive paths that allow current to flow. A circuit can be in the form of a closed-loop configuration or an open-loop configuration. In a closed-loop configuration, the circuit components provide a return path for current. In contrast, in an open-loop configuration, although the circuit components do not include a return path for current, the circuit components can still be considered to form a circuit. For example, an integrated circuit is referred to as a circuit regardless of whether it is grounded (as a return path for current). In some exemplary embodiments, a circuit may include a collection of integrated circuits, a single integrated circuit, or a portion of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In further examples, the circuit may include one or more silicon-based integrated circuit devices, such as wafers, dies, die planes, and packages, or other discrete electrical devices, forming an electrical communication configuration with one or more other components via electrical conductors, such as those on a printed circuit board. The circuit may also be implemented as a composite circuit relative to programmable hardware devices, such as field-programmable gate arrays (FPGAs), programmable array logic, and / or programmable logic devices. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Therefore, the module described above may be embodied or implemented as a circuit in some embodiments.

[0102] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specific stored computer program instructions that control one or more microprocessors in combination with certain non-processor circuitry and other components to implement some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), wherein the functions or some combinations of functions are implemented as custom logic. Combinations of these methods may also be used. Furthermore, the reference to "controller" below shall be defined as including individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and / or processors with control software, or combinations thereof.

[0103] Additionally, the terms “couple,” “coupled,” or “couples” may be used herein to mean a direct or indirect connection. Thus, if a first device is coupled or coupled to a second device, the connection may be a direct connection or an indirect connection via other devices (or components) and connections.

[0104] Regarding the use of terms such as "an embodiment," "one embodiment," "exemplary embodiment," "particular embodiment," or other similar terms as used herein, these terms are intended to indicate that a specific feature, structure, function, operation, or characteristic described in connection with an embodiment is found in at least one embodiment of this disclosure. Therefore, unless expressly stated otherwise, the appearance of phrases such as "in one embodiment," "in an embodiment," "in an exemplary embodiment," etc., may refer to, but not necessarily, the same embodiment, but rather means "one or more but not all embodiments." Furthermore, the terms "comprising," "having," "including," and variations thereof are used in an open-ended manner and, therefore, unless expressly stated otherwise, should be interpreted as "including, but not limited to…." Furthermore, in the absence of further restrictions, adding "comprises … a" before a component does not preclude the existence of additional identical components in the subject program, method, system, article, or device that includes that component.

[0105] Unless otherwise expressly specified, the terms "a," "an," and "the" also mean "one or more." For example, "a processor" programmed to perform various functions means one processor programmed to perform each function, or more than one processor programmed collectively to perform various functions. Furthermore, the phrase "at least one of A and B" may be used herein and / or in the claims below, where A and B are variables indicating specific objects or properties, indicating the selection of A or B, or the selection of both A and B, similar to the phrase "and / or." When this phrase contains more than two variables, it is defined herein as including only one of the variables, any one of the variables, any combination (or subcombination) of any variables, and all variables.

[0106] Furthermore, the terms "about" or "approximately" as used herein apply to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent (e.g., having the same function or result) to the stated value. In some instances, these terms may include numerical values ​​rounded to the nearest significant figure.

[0107] Furthermore, unless otherwise expressly stated, any list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive. Moreover, unless otherwise expressly stated, the term "set" as used herein shall be interpreted as meaning "one or more," and in the case of "set," shall be interpreted as meaning a multiple (or plural) of "one or more," "ones or more," and / or "ones or mores" according to the group theory.

[0108] The foregoing detailed description is for illustrative and descriptive purposes only. It is not intended to be exhaustive or to limit the precise forms disclosed. Many modifications and variations are possible based on the foregoing description. The described embodiments were chosen to best explain the principles of the technology and its practical application, thereby enabling those skilled in the art to best utilize the technology in various embodiments and with various modifications suitable for the intended particular use. The scope of this technology is defined by the appended claims.

[0109] 100: Memory Device 108: Memory chip 110: Control circuit system 112: State Machine 113: Storage Area 114: Chip-based address decoder 116: Power Control Module 118: Line 120: Data Bus 122: Controller 122a:ROM 122b:RAM 122c: Processor 124: Column Decoder 126: Memory Structure 126a: Storage device 128: Read / Write Circuit 132: Line Decoder 140: Host 150: Control Circuit 151: Programmable Circuits 152: Counting Circuit 153: Decision Circuit 160, 161: Steps 200,210: Memory blocks 245: Error Correction Engine 246: Engine Lock 300: Floating gate memory unit 302: Control gate 304: Floating Lock 305: Tunnel Oxidation Layer 306: Passage Area 310: Floating gate memory unit 312: Control gate 314: Floating Lock 315: Tunnel Oxidation Layer 316: Passage Area 320: Floating gate memory unit 321: Floating Lock 322: Control gate 324: Word Line 325: Tunnel Oxidation Layer 326: Passage Area 328: Polycrystalline silicon interlayer dielectric layer 329: Contact Wire Connector 400: Memory Unit 402: Control gate 405: Polycrystalline silicon layer 406: Passage Area 407, 408, 409: Tunnel Oxidation Layer 410: Memory Unit 412: Control gate 415: Polycrystalline silicon layer 416: Passage Area 420: Memory Unit 422: Control gate 424: Word Line 425: Polycrystalline silicon layer 426: Passage Area 428: Charge storage layer 429: Contact Wire Connector 430: NAND string 431: SGS Transistor 433,......,435: Memory units 436: SGD transistor 455: p-type substrate area 456: n-type well 457: P-type well 550a, 551a, 552a, 553a: Sensing circuit 550b, 551b, 552b, 553b: Data latches 560: Sensing Circuit Controller 561: Pre-charge circuit 562: Memory 563: Processor 600: Block 602: Middle Area 603: Upper Area 604: Surrounding Area 605: Voltage Driver 610: Stacking 611: Substrate 612: Insulating film 613: Source Extreme 614: Bottom 615: Drawing Extremes 616: Top 617: Contact Wire Connector 618, 619: Memory Hole 620, 701, 702, 703, 704: Contact line connectors 621: Conductive via 622: Area 630: Memory Hole 660: Blocking oxides / blocking high-k materials 661: Metallic barrier layer 663: Charge trapping layer or film 664: Tunneling Layer 665: Polycrystalline silicon or channel 666: Dielectric core 680, 681: SGD transistors 682, 683: Virtual memory units 690, 691, 692, 693, 694: Control gates 701, 702, 703, 704: Contact line connectors 712, 712a, 713: Contact wire 720, 721, 724, 725, 726, 727, 728, 729: Memory units 1000: Waveform 1001~1018: VPGM pulse 1020~1036: Verification pulse 1600a, 1600b, 1602a, 1602b: Critical Limit Voltage Vt Distribution 1800: Flowchart 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818, 1820, 1822: Steps BL, BL0~BL23: Bit Line BLK, BLK0, BLK1, BLK2, BLK3: Blocks DL116: Top Dielectric Layer DL116a, DL116b, DL116c, DL116d, WL0a, WL0b, WL0c, WL0d: Regions dVPGM: Programmable Voltage Step DWLD0, DWLD1, DWLS0, DWLS1: Virtual word line layer Er: Erasure status Icc: Peak and average current ICELL: Discharge Current NS0_SBa, NS1~NS2, NS1_SBb, NS2_SBc, NS3_SBd, NS4_SBe: NAND string S1~Sn: Data status SA: Sensing Amplifier SB1, SB2, ..., SBp: Sensing blocks sd1, sd2, sd3, sd4, sd5, sd6, sd7: N-type source / diffusion region SEN: Sensing Node SL: Source Line T_Sense: Sensing time VBL: Bit line voltage VCELSRC: Positive Voltage VCG: Reference Voltage Vds: Drain to Source Extreme Position Vgs: Gate-to-source polarity VPGMU: Starting voltage VREAD, VREADK: Through voltage V_Sense: Sensing voltage Vt: Threshold voltage Vv, Vv1~Vv7, Vvn: Verification voltage WL0~WL111: Wordline Layer WLn-1, WLn+1: Adjacent word lines WLn: Selected word line z0~z111: Height

Claims

1. A method of performing a programmed operation in a memory device, comprising the steps of: preparing a memory block including a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings; programming the memory cells of one of the plurality of word lines via a selected word line to a plurality of data states in a plurality of programmed loops, the programmed loops including a programmed pulse and a verification operation; and in at least one of the programmed loops, during the verification operation, not locking a set of the plurality of NAND strings, the set of NAND strings including at least some of the programmed memory cells via the selected word line, such that the NAND strings in the set are conductive during sensing.

2. The method of claim 1, wherein the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of later data states associated with a relatively high threshold voltage range.

3. The method of claim 2, wherein the step of not locking the NAND string of the set so that the NAND string of the set is conductive during sensing occurs during the programming of the plurality of late data states.

4. The method of claim 3, wherein the plurality of programmed data states includes seven programmed data states, and wherein the plurality of subsequent data states includes three of the seven programmed data states.

5. The method of claim 1, wherein the NAND strings in the set include the NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

6. The method of claim 1, further comprising a source line, wherein during sensing, the source line is set to approximately zero volts (0 V).

7. The method of claim 1, further comprising the step of: applying a verification voltage to the selected word line during the verification operation of at least one of the programmed loops.

8. A memory device comprising: a memory block including a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings; and a circuit system configured to program the memory cells of a selected word line among the plurality of word lines into a plurality of data states in a plurality of programmed loops including programmed pulses and verification operations, wherein during at least one of the verification operations, the circuit system is configured to: not lock a set of the plurality of NAND strings, the set of NAND strings including at least some of the programmed memory cells of the selected word line, such that conduction occurs through the NAND strings in the set during sensing.

9. The memory device of claim 8, wherein the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of late data states associated with a relatively high threshold voltage range.

10. The memory device of claim 9, wherein the circuitry is configured to not lock the plurality of NAND strings of the set during programming of the plurality of late data states.

11. The memory device of claim 9, wherein the plurality of programmed data states includes seven programmed data states, and wherein the plurality of later data states includes three of the seven programmed data states.

12. The memory device of claim 8, wherein the NAND strings of the set include the NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

13. The memory device of claim 8 further includes a source line, wherein during sensing, the circuitry sets the source line to approximately zero volts (0 V).

14. The memory device as described in claim 8, wherein, During the verification operation of at least one of these programmed loops, the circuit system applies a verification voltage to the selected word line.

15. A memory device comprising: a memory block including a plurality of memory cells disposed in a plurality of word lines and a plurality of NAND strings; and a programming component for programming the memory cells of a selected word line in the plurality of word lines into a plurality of data states in a plurality of programming loops including programming pulses and verification operations, wherein during at least one of the verification operations, the programming component is configured to: not lock a first set of the plurality of NAND strings, the NAND strings in the first set including at least some of the fully programmed memory cells of the selected word line, and conduct electricity through the NAND strings of the first set and through a second set of NAND strings including the fully programmed memory cells of the selected word line.

16. The memory device of claim 15, wherein the plurality of programmed data states include a plurality of early data states associated with a relatively low threshold voltage range and a plurality of late data states associated with a relatively high threshold voltage range.

17. The memory device of claim 16, wherein the programming component is configured to not lock the plurality of NAND strings of the set during programming the plurality of late data states.

18. The memory device of claim 16, wherein the plurality of programmed data states includes seven programmed data states, and wherein the plurality of later data states includes three of the seven programmed data states.

19. The memory device of claim 15, wherein the first set of NAND strings includes the NAND strings coupled to all but one of the memory cells in the programmed data states that have been programmed.

20. The memory device of claim 15, further comprising a source line, wherein during sensing, the programming component sets the source line to approximately zero volts (0 V).

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