Short channel mosfet devices with low turn-on voltage and their fabrication methods

Abstract

This invention discloses a low-turn-on voltage short-channel MOSFET device and its fabrication method, including: sequentially growing an epitaxial layer and a first oxide layer on a silicon wafer; performing body region implantation and source region implantation on the upper part of the epitaxial layer; etching to form a gate trench; growing a gate oxide layer on the trench wall; forming a gate polysilicon in the gate trench; and completing subsequent fabrication processes. In this invention, by performing body region implantation and source region implantation first, and then etching to form the gate trench, it avoids the situation where over-etching of the polysilicon in the gate trench creates a recessed region, leading to excessively deep source region implantation near the gate trench, resulting in a shorter conductive channel and channel leakage. This makes mass production of low-turn-on voltage short-channel MOSFET devices possible.

Claims

1. A method for fabricating a short-channel MOSFET device with low turn-on voltage, characterized by comprising the following steps: S100, taking a silicon wafer and sequentially growing an epitaxial layer and a first oxide layer on the silicon wafer; S200, performing body region implantation and source region implantation on the upper part of the epitaxial layer; S300, etching to form a gate trench; S400, growing a gate oxide layer on the trench wall of the gate trench; S500, forming a gate polysilicon in the gate trench; S600, completing subsequent fabrication processes; wherein, The minimum design thickness of the gate oxide layer is determined according to the gate withstand voltage requirement of the device, and in step S400, the thickness of the gate oxide layer at the source region corresponding to the gate trench and the thickness of the gate oxide layer at the body region corresponding to the gate trench are both greater than or equal to the minimum design thickness of the gate oxide layer.

2. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 1, wherein, After source region injection, the temperature and time of high-temperature processes in subsequent processes are reduced.

3. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in any one of claims 1-2, wherein, The steps of performing body region injection and source region injection on the upper part of the epitaxial layer include the following sub-steps: S210, performing body region injection on the upper part of the epitaxial layer and starting the sink push; S220, performing source region injection on the upper part of the body region.

4. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 3, wherein, The etching process for forming a gate trench includes the following sub-steps: S310, growing a hard mask as a first mask layer; S320, etching a gate trench region on the first mask layer using photolithography; S330, etching downwards in the gate trench region to form a gate trench using etching; S340, removing the first oxide layer and the first mask layer.

5. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 4, wherein, The step of growing a gate oxide layer on the trench wall of the gate trench includes the following sub-steps: S410, growing an oxide layer on the trench wall of the gate trench to form a sacrificial oxide layer; S420, etching away the sacrificial oxide layer; S430, growing another oxide layer on the trench wall of the gate trench to form a gate oxide layer.

6. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 5, wherein, When forming the sacrificial oxide layer and the gate oxide layer, the temperature for growing the oxide layer is 800℃~900℃, and the time required for growing the oxide layer is shortened by adding a catalyst.

7. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 5, wherein, The step of forming gate polysilicon in the gate trench includes the following sub-steps: S510, depositing polysilicon to fill the gate trench; S520, removing the polysilicon outside the gate trench by dry etching.

8. A method for fabricating a short-channel MOSFET device with low turn-on voltage as described in claim 1, wherein, The subsequent fabrication process includes the following sub-steps: S610, depositing a dielectric layer; S620, etching the contact hole area using photolithography; S630, etching the contact hole using etching; S640, filling the contact hole to form a tungsten plug; S650, depositing a surface metal layer.

9. A short-channel MOSFET device with low turn-on voltage, wherein: It is fabricated using a method for fabricating a short-channel MOSFET device with low turn-on voltage as described in any one of claims 1-8.

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