Semiconductor device

Abstract

This disclosure describes a semiconductor device including a substrate, a drift layer, and a plurality of doped regions. A shielding region is provided to enhance electric field diffusion, thereby improving high-voltage performance. The semiconductor device also includes a doped region connected to a source electrode via a three-dimensional mesh structure to optimize charge balance and reduce field crowding.

Claims

1. A silicon carbide semiconductor device, comprising: A drift layer is disposed on a silicon carbide substrate, the drift layer having a first conductivity type and a first doping concentration; A first doped region having a second conductivity type and formed in the drift layer; a second doped region having the first conductivity type and formed in the first doped region; a third doped region having the first conductivity type and a second doping concentration and formed in the drift layer, the second doping concentration being higher than the first doping concentration; a gate trench extending from an upper surface of the second doped region through the first doped region and into the drift layer, wherein the gate trench is formed such that the drift layer is divided into a plurality of platforms surrounded by the gate trench, each platform including an extension and a plurality of fingers extending from the extension; a plurality of fourth doped regions having the second conductivity type and formed in the drift layer, wherein each fourth doped region is wholly or partially arranged in the platform and connected to the first doped region, and each fourth doped region is deeper than the gate trench; A fifth doped region having the second conductivity type, the fifth doped region being formed in the drift layer and located below or beneath the gate trench, wherein the fifth doped region is connected to the first doped region through the fourth doped region to maintain the same potential; a gate electrode being arranged in the gate trench and dielectrically insulated from the drift layer through a gate insulating layer; and a source electrode being electrically connected to the second doped region and the fourth doped region through a plurality of contact openings arranged on the extensions of the plurality of platforms, and dielectrically insulated from the gate electrode.

2. The silicon carbide semiconductor device as claimed in claim 1, wherein a plurality of the fourth doped regions are all arranged in the extension of the platform, and the fifth doped region is formed below the gate trench, wherein a distance between a bottom of the gate trench and a top of the fifth doped region is greater than 100 nm.

3. The silicon carbide semiconductor device as claimed in claim 2, wherein the fifth doped region is arranged in a rectangular grid pattern below the bottom of the entire gate trench.

4. The silicon carbide semiconductor device as claimed in claim 1, wherein the plurality of platforms include at least two finger-like portions extending from opposite sides of the extension, wherein, All of these finger-like parts extend in a transverse direction.

5. The silicon carbide semiconductor device as claimed in claim 1, wherein a plurality of the platforms include at least four fingers extending from all four sides of the extension.

6. The silicon carbide semiconductor device as claimed in claim 1, wherein the silicon carbide semiconductor device further comprises an edge termination structure, the edge termination structure comprising a plurality of floating guard rings, a single-region or multi-region junction termination extension, or a combination of the floating guard rings and the junction termination extension, wherein, The floating protective ring and the interface terminal extension are formed by the first doped region, the fourth doped region and the fifth doped region.

7. The silicon carbide semiconductor device of claim 1, wherein the depth of the fourth doped region is at least 50% of the thickness of the drift layer, the fourth doped region, the fifth doped region, the drift layer, and the third doped region form a structure having a charge imbalance between -20% and +20%.

8. A silicon carbide semiconductor device, comprising: A drift layer is disposed on a silicon carbide substrate, the drift layer having a first conductivity type and a first doping concentration; A plurality of first doped regions, having a second conductivity type, are formed in the drift layer, wherein each first doped region includes an extension and a plurality of fingers; a plurality of second doped regions, having the first conductivity type, are formed in the first doped regions; a third doped region, having the first conductivity type and a second doping concentration, is formed in the drift layer, wherein the second doping concentration is higher than the first doping concentration, wherein the third doped region is deeper than the first doped region and forms a JFET region with the first doped region; a plurality of fourth doped regions, having the second conductivity type, are formed in the drift layer, wherein each fourth doped region is an extension of the first doped region and is deeper than the first doped region; a fifth doped region, having the second conductivity type, is formed in the drift layer, wherein the fifth doped region is wholly or partially arranged below the JFET region and is connected to the first doped region through the fourth doped region to maintain the same potential; A gate electrode is disposed above the drift layer and is dielectrically insulated from the drift layer through a gate insulating layer; and a source electrode is electrically connected to the second doped region and the fourth doped region through a plurality of contact openings arranged on the extension of the plurality of first doped regions and is dielectrically insulated from the gate electrode.

9. The silicon carbide semiconductor device as claimed in claim 8, wherein a distance between the first doped region and the fifth doped region is greater than 100 nm.

10. The silicon carbide semiconductor device as claimed in claim 8, wherein each of the first doped regions includes at least two fingers extending from opposite sides of the extension.

11. The silicon carbide semiconductor device as claimed in claim 8, wherein the silicon carbide semiconductor device further includes a drain electrode disposed at a bottom of the silicon carbide substrate, wherein, When the thickness of the drift layer is greater than 5 micrometers, the ratio of the capacitance between the gate and the source and the capacitance between the gate and the drain is greater than 200.

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