Semiconductor structures having backside metal die damage rings and methods for manufacturing and testing thereof

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing and testing the semiconductor structure. The semiconductor structure includes: an integrated circuit formed in a semiconductor substrate; a sealing ring located on at least a first side of the semiconductor substrate and surrounding the periphery of the integrated circuit; an input component; an output component; and a backside metal die damage ring (BMDDR) disposed on the first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate. The BMDDR is disposed between the integrated circuit and the sealing ring, at least partially surrounding the periphery of the integrated circuit, and is coupled to the input component and the output component, forming a circuit between the input component and the output component.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] In recent years, the integrated circuit (IC) industry has experienced rapid and sustained growth. Technological advancements in IC materials and design have led to continuous improvements across generations of ICs. Each new generation of circuits is smaller and more complex than its predecessor, resulting in higher functional density (i.e., the number of interconnect devices per wafer area) and smaller geometry (i.e., the smallest components or lines that can be created using manufacturing processes). This scaling down process is beneficial for improving production efficiency and reducing associated costs. However, as feature sizes continue to shrink, manufacturing processes become more challenging, and ensuring the reliability of semiconductor devices becomes increasingly difficult. Therefore, the industry faces the ongoing challenge of developing processes that can manufacture smaller, more reliable ICs. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] As used herein, terms such as “first,” “second,” and “third” describe various components, elements, areas, layers, and / or segments, but these components, elements, areas, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one component, element, area, layer, or segment from another. Unless the context clearly indicates otherwise, the use of terms such as “first,” “second,” and “third” herein does not imply sequence or order.

[0007] For the sake of brevity, known techniques related to the manufacture of conventional semiconductor devices are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functions not described in detail herein. In particular, the various processes in the manufacture of semiconductor devices are well-known, and therefore, for the sake of brevity, many known processes will only be briefly mentioned or omitted entirely without providing well-known process details. Those skilled in the art will readily recognize upon a full reading of this disclosure that the structures disclosed herein can be used with various techniques and incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures include a varying number of elements, and a single element shown in the figures may represent multiple elements.

[0008] Furthermore, for ease of description, spatial relative terms such as "above," "overlapping," "above," "upper," "top," "below," "subordinate to," "lower than," "lower," "bottom," and the like are used herein to describe the relationship between one component or feature and another component(s) as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein will be interpreted accordingly. When a first component is described relative to a second component using spatial relative terms such as those listed above, the first component may be directly above the other component, or there may be an intermediate component or layer. When a component or layer is referred to as "on another component or layer," it may be directly above and in contact with the other component or layer.

[0009] It should be noted that references to "an embodiment," "an exemplary embodiment," "illustrative," and "example" in this specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will be able to influence that feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not).

[0010] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein similar reference numerals are generally used to refer to similar components throughout the document. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other instances, structures and apparatuses are illustrated in block diagram form for ease of description of the claimed subject matter.

[0011] Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some of the features described below may be replaced or eliminated for different embodiments. Although some embodiments are described with operations performed in a particular order, these operations may also be performed in another logical order.

[0012] As used herein, a “layer” is a region, such as a region containing arbitrary boundaries, but not necessarily containing a unique thickness. For example, a layer may be a region containing at least some variations in thickness.

[0013] The manufacture of semiconductor devices typically involves forming a plurality of integrated circuits on a single wafer, followed by a die-cutting (i.e., wafer dicing) process to separate the wafer into individual dies, each of which comprises one or more of the integrated circuits. While this process facilitates the mass production of semiconductor devices, there is a possibility that one or more of the integrated circuits may be damaged during the die-cutting process. In such cases, one or more damaged semiconductor devices may fail to function properly or may have reliability issues.

[0014] Embodiments of semiconductor structures and methods for manufacturing and testing semiconductor structures capable of detecting damage to their integrated circuitry during a die-cutting process are presented herein. In various embodiments, the semiconductor device includes a die having a wafer or substrate in which integrated circuitry is formed. A damage detection component (referred herein to as a backside metal damage detection ring (BMDDR)) defines a continuous circuit that at least partially surrounds the periphery of the integrated circuitry formed in the substrate. A load can be applied to the BMDDR to detect circuit disconnection due to circuit damage, thereby detecting potential damage to the integrated circuitry. In some instances, disconnection can be detected by measuring changes in the resistance (or conductivity) of the circuitry.

[0015] Figures 1 and 2 are cross-sectional and top views, respectively, of an exemplary semiconductor structure 100 at a stage of the manufacturing process according to an embodiment. The semiconductor structure 100 includes a die having a semiconductor substrate 102, which includes a front side 110 and a back side 112.

[0016] The semiconductor structure 100 includes an integrated circuit 114 formed in a semiconductor substrate 102. The integrated circuit 114 may include multiple interconnected electronic components, such as transistors, resistors, and capacitors. The integrated circuit 114 may include or define various types of devices, including, for example, microprocessors, microcontrollers, memory, etc.

[0017] To reduce the possibility of damage to the integrated circuit 114 during the die-cutting process, the semiconductor structure 100 may include a sealing ring 116, which in this example is formed on the front side 110 of the semiconductor substrate 102 and surrounds the periphery of the integrated circuit 114. In this example, the sealing ring 116 defines a square area; however, the sealing ring 116 is not limited to this shape. The sealing ring 116 may serve as a physical barrier layer to facilitate protection of the edges of the integrated circuit 114 during the manufacturing process. Figure 3 is a cross-sectional view illustrating a portion of the exemplary sealing ring 116 as shown in Figure 2. In this example, the sealing ring 116 includes various first semiconductor devices 210 (e.g., transistors, capacitors, diodes, etc.) formed in the semiconductor substrate 102, and a first interconnect structure 208 disposed above the semiconductor substrate 102 and the first semiconductor devices 210.

[0018] The first interconnect structure 208 may include a network of conductive first interconnect metal layer 216 and first interconnect via 214 surrounded by a first interconnect dielectric structure 126. The network of the first interconnect metal layer 216 and the first interconnect via 214 of the first interconnect structure 208 may be electrically coupled to the first semiconductor device 210.

[0019] Integrated circuit 114 and sealing ring 116 are spaced apart from each other on semiconductor structure 100, and BMDDR 120 is disposed in the area between integrated circuit 114 and sealing ring 116. BMDDR 120 may partially or completely surround the periphery of integrated circuit 114. BMDDR 120 is coupled to input component 122 (e.g., input pin) and output component 124 (e.g., output pin). BMDDR 120 defines a continuous circuit between input component 122 and output component 124. A load may be applied between input component 122 and output component 124 to detect a circuit break due to circuit failure of BMDDR 120, thereby detecting potential damage to the edge of integrated circuit 114. In some instances, a break may be detected by measuring a change in the resistance (or conductivity) of the circuit.

[0020] Figure 4 is a cross-sectional view illustrating a portion of the exemplary BMDDR 120 as shown in Figure 2. In this example, BMDDR 120 may include various second semiconductor devices 310 (e.g., transistors, capacitors, diodes, etc.) formed in a semiconductor substrate 102, second interconnect structures 308 disposed on the front side 110 of the semiconductor substrate 102 and on the second semiconductor devices 310, and a third interconnect structure 309 located on the back side 112 of the semiconductor substrate 102. The second interconnect structure 308 and the third interconnect structure 309 may each be electrically connected to the second semiconductor device 310, thereby being electrically connected to each other.

[0021] The second interconnect structure 308 and the third interconnect structure 309 may include a network of conductive second interconnect metal layers 316 and 317, and second interconnect vias 314 and 315, surrounded by the first interconnect dielectric structure 126 and the second interconnect dielectric structure 128. The network of the second interconnect metal layers 316 and 317, and the second interconnect vias 314 and 315 of the second interconnect structure 308 and the third interconnect structure 309 may be electrically coupled to the second semiconductor device 310. In some embodiments, the second interconnect metal layer 316 may be referred to as M1, M2, M3...Mx, and the third interconnect metal layer 317 may be referred to as BM1, BM2, BM3...BMx. In some embodiments, the second interconnect via 314 may be referred to as V1, V2, V3...Vx, and the third interconnect via 315 may be referred to as BV1, BV2, BV3...BVx. In some instances, the first interconnect dielectric structure 126 may include a plurality of first inter-metal dielectric (IMD) layers (not shown separately), which may be referred to as IMD1, IMB2, IMD3...IMDx, and the second interconnect dielectric structure 128 may include a plurality of second inter-metal dielectric (IMD) layers (not shown separately), which may be referred to as BIMD1, BIMD2, BIMD3...BIMDx.

[0022] In some examples, the semiconductor structure 100 may include various layers, such as, but not limited to, a semiconductor substrate 102, an inter-layer dielectric (ILD) layer, etc. In some embodiments, the semiconductor substrate 102 may be one of various types of semiconductor substrates commonly used in semiconductor integrated circuit manufacturing. The semiconductor substrate 102 may belong to any structure containing semiconductor materials, including but not limited to bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. Other semiconductor materials may be used, including group III, group IV, and / or group V semiconductors.

[0023] In some embodiments, the semiconductor substrate 102 may include a first interlayer dielectric layer (ILD) located above the first semiconductor device 210, and contact plugs may be formed in the interlayer dielectric layer to provide electrical connections between other circuits / components. The formation of the contact plugs may include forming openings in the interlayer dielectric layer ILD, filling the openings with a conductive material, and performing planarization such as chemical mechanical polishing (CMP). In some embodiments, the contact plugs may include tungsten (W), but may also include other suitable conductive materials such as silver (Ag), aluminum (Al), copper (Cu), or alloys thereof (AlCu) or the like.

[0024] The first and / or second IMD layers of the first interconnect dielectric structure 126 and the second interconnect dielectric structure 128 may include one or more of the following: low-k dielectric materials, fluorine-doped silica, organosilicon silicates, carbon-doped oxides, porous silica, organic polymer dielectrics (e.g., polyimide, polynorbornene, phenylcyclobutene, and PTFE), silicon-based polymer dielectrics (e.g., hydrogen silsesquioxane, methyl silsesquioxane), and other commonly used materials. The dielectric constant (k value) of the low-k dielectric material may be less than about 3.9, less than about 3.5, or less than about 2.8.

[0025] In some embodiments, the first interconnect metal layer 216, the second interconnect metal layer 316, and / or the third interconnect metal layer 317, as well as the first interconnect via 214, the second interconnect via 314, and / or the third interconnect via 315, may each comprise a single layer or two or more layers. In some embodiments, the first interconnect metal layer 216, the second interconnect metal layer 316, and / or the third interconnect metal layer 317, as well as the first interconnect via 214, the second interconnect via 314, and / or the third interconnect via 315, each comprise a filler material and a bushing located between the filler material and the dielectric material of the corresponding intermetallic dielectric layer. In some embodiments, the bushing may comprise a noble metal or an alloy thereof, such as, but not limited to, rhenium (Re), rhodium (Rh), ruthenium (Ru), or an alloy thereof. In some embodiments, the filler material may comprise copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or an alloy thereof.

[0026] In some instances, BMDDR 120 may be described as a series of electrical interconnect units, each including a portion of a second interconnect structure 308 connecting two entities in the second semiconductor device 310 or a portion of a third interconnect structure 309 connecting two entities in the second semiconductor device 310. For example, Figure 5 shows four first units 510 of the second interconnect structure 308 and three second units 512 of the third interconnect structure 309. In some instances, as shown in Figure 2, BMDDR 120 includes a plurality of first units 510 and a plurality of second units 512, the first units 510 and second units 512 being electrically coupled in series with each other such that the first units 510 and second units 512 alternate linearly along BMDDR 120.

[0027] BMDDR 120 can define electrical paths through semiconductor structures 100 with various patterns. In the example of Figure 5, circuit 514 defined by second interconnect structure 308, third interconnect structure 309, and second semiconductor device 310 defines a serpentine pattern through the front side 110 and back side 112 of semiconductor substrate 102. Figure 6 schematically illustrates the serpentine pattern of Figure 5. However, BMDDR 120 is not limited to this pattern and can define various other patterns.

[0028] Various elements of the semiconductor structure 100, including BMDDR 120, may have various sizes. For example, Figure 7 illustrates the BMDDR 120 of Figure 5 with specific exemplary dimensions, including a first pitch (P1; for example, the dimension between the ends of the first cell 510) of about 600 to about 800 nanometers (nm), a second pitch (P2; for example, the dimension between the ends of the second cell 512) of about 600 to about 800 nm, and a spacing (S1; for example, the dimension between the ends of two adjacent cells) of about 1 to about 10 nm. Although Figure 7 illustrates the BMDDR 120 as having a first pitch (P1), a second pitch (P2), and a spacing (S1) of consistent or uniform size, these dimensions may vary depending on the application.

[0029] In some embodiments, the first semiconductor device 210 and / or the second semiconductor device 310 may be, for example, a metal oxide semiconductor field-effect transistor (MOSFET). For example, Figure 8 is a partial cross-sectional view of one of the second semiconductor devices 310. As shown, the second semiconductor device 310 may include a doped well region 330 located within the semiconductor substrate 102, wherein the doped well region 330 is more heavily doped than the semiconductor substrate 102 and / or has a different doping type. A source / drain structure 332 may reside in the doped well region 330, and a gate electrode 334 located above the gate dielectric layer (not shown) may be disposed on the front side 110 of the semiconductor substrate 102 within the first IMD layer 812. In this disclosure, the source and drain are used interchangeably and their structures are substantially the same.

[0030] Each of the source / drain structures 332 can be electrically contacted with the second interconnect structure 308 via a separate second interconnect via 314 within the first IMD layer 812. Each of the separate second interconnect via 314 can also be coupled to a separate second interconnect metal layer 316 within the second IMD layer 614. Similarly, the source / drain structures 332 can be electrically contacted with the third interconnect structure 309 via separate through substrate vias (TSVs) 320. The through substrate vias 320 extend through the back side 112 of the semiconductor substrate 102 and can also be coupled to a separate third interconnect metal layer 317 within the third IMD layer 616.

[0031] Figures 9 through 11 illustrate various non-limiting alternative examples of semiconductor structures. It should be noted that these examples are for illustrative purposes only, and the semiconductor structures discussed herein may have other configurations, including various combinations of the elements presented in Figures 9 through 11.

[0032] For convenience, consistent reference numerals are used throughout Figures 9 through 11 to identify components that are the same as or functionally related / equivalent to those described in Figures 1 through 8, but with added numerical prefixes (1, 2, or 3, etc.) to distinguish specific instances from other instances in the figures. Given the similarity between the instances, the following discussion of Figures 9 through 11 will focus primarily on the variations of the instances that differ from other instances in some important or significant way. Other variations of instances not discussed in detail in terms of structure, function, materials, etc., may be substantially the same as those described for one or more other instances, including those in Figures 1 through 8.

[0033] Figure 9 is a top view of a portion of an exemplary semiconductor structure 700 at a stage of manufacturing process according to an embodiment. The semiconductor structure 700 includes an integrated circuit 714 formed in a semiconductor substrate 702, a sealing ring 716 surrounding the periphery of the integrated circuit 714, and a BMDDR 720 located between the integrated circuit 714 and the sealing ring 716. In this example, the semiconductor structure 700 includes alternative input and output components for the BMDDR 720. Specifically, the BMDDR 720 is electrically coupled to one or more input pads 722 and one or more output pads 724 of the integrated circuit 714. A load can be applied between any of the input pads 722 and any of the output pads 724 to detect a circuit break in the BMDDR 720. In some embodiments, the semiconductor structure 700 may include more than one of the input pads 722 and more than one of the output pads 724 to provide flexibility in operating the BMDDR 720. Although the BMDDR 720 is presented as continuous and completely surrounding the integrated circuit 714 in this example, the BMDDR 720 may alternatively be discontinuous within one or more disconnections, provided that the circuitry between the input pad 722 and the output pad 724 pair is continuous.

[0034] Figure 10 is a top view of a portion of an exemplary semiconductor structure 800 at a stage of a manufacturing process according to an embodiment. The semiconductor structure 800 includes an integrated circuit 814 formed in a semiconductor substrate 802, a sealing ring 816 surrounding the periphery of the integrated circuit 814, and a BMDDR 820 located between the integrated circuit 814 and the sealing ring 816. In this example, the BMDDR 820 includes three spaced interconnect systems 820A, 820B, and 820C, each of which at least partially surrounds the integrated circuit 814. Notably, the BMDDR 820 may include a variety of numbers of interconnect systems. In this example, all interconnect systems 820A, 820B, and 820C are electrically coupled to an input terminal 822 and an output terminal 824. Alternatively, one or more of the interconnect systems 820A, 820B, and 820C may be electrically coupled to separate input and output components.

[0035] Figure 11 is a top view of a portion of an exemplary semiconductor structure 900 at a stage of a manufacturing process according to an embodiment. The semiconductor structure 900 includes an integrated circuit 914 formed in a semiconductor substrate 902, a sealing ring 916 surrounding the periphery of the integrated circuit 914, and a BMDDR 920 located between the integrated circuit 914 and the sealing ring 916. The BMDDR 920 is coupled to an input terminal 922 and an output terminal 924. In this example, the BMDDR 920 may have a thickness (T) of about 1 to 5 micrometers (μm), a spacing (S2) of about 0.5 to 1.0 μm from the integrated circuit 914, and a spacing (S3) of about 0.5 to 1.0 μm from the sealing ring 916. The periphery of the BMDDR 920 may have a width (W) and a length (L) depending on the size of the integrated circuit 914, as represented by the width (X) and length (Y) of the integrated circuit 914. In some instances, the width (W) of BMDDR 920 can be defined by W=X+(2T+2S2), and the length (L) of BMDDR 920 can be defined by L=Y+(2T+2S2).

[0036] Referring to Figure 12, an exemplary method 1000 for manufacturing and testing a semiconductor structure is provided. At step 1012, method 1000 includes manufacturing a plurality of integrated circuits on a wafer. Various physical and chemical processes can be used to form various elements of the integrated circuits. At least a first of the integrated circuits has BMDDR partially or completely surrounding its periphery. At step 1014, the method includes performing a wafer probing process to test for functional defects in some or all of the integrated circuits. At step 1016, method 1000 includes performing a die-cutting process to separate the wafer into a plurality of individual dies, each of which may include one or more of the integrated circuits. At step 1018, method 1000 includes performing IC packaging. At step 1020, method 1000 includes performing final testing on one or more integrated circuits comprising at least a first semiconductor structure including the first integrated circuit and BMDDR to ensure that desired performance standards are met. During final testing, a load may be applied to the BMDDR of the first semiconductor structure to detect potential damage to the first integrated circuit that may occur during the die-cutting process. At step 1022, method 1000 includes performing reliability testing on one or more integrated circuits, including at least the first semiconductor structure. Various reliability tests may be performed, such as, but not limited to, temperature cycling test (TCT), thermal shock test, high-temperature storage test, temperature, humidity, and bias (THB) test, high-acceleration temperature and humidity stress test, high-temperature operating life (HTOL) test, and / or accelerated life tests (ALT). At step 1024, method 1000 includes mounting the first semiconductor structure in a final product. The first semiconductor structure may be mounted in various final products, such as, but not limited to, computers, laptops, tablets, and smartphones.

[0037] Referring to Figure 13, an exemplary method 1100 for testing a semiconductor structure is proposed. Method 1100 may begin at step 1110. At step 1112, method 1100 includes providing a semiconductor structure having integrated circuitry and a BMDDR partially or completely surrounding the periphery of the integrated circuitry. At step 1114, method 1100 may include applying a load to the BMDDR to detect potential damage to the integrated circuitry. In some instances, the BMDDR defines a circuit, and a break in that circuitry can be detected by measuring changes in the resistance or conductivity of the circuitry. Where appropriate, at step 1116, method 1100 may include detecting the integrated circuitry in response to the detection of a break in the BMDDR. Method 1100 may end at step 1118.

[0038] Referring to Figure 14, an exemplary method 1200 for manufacturing a semiconductor structure is presented. Method 1200 may begin at step 1210. At step 1212, method 1200 may include providing a semiconductor substrate in which integrated circuitry is formed. Various methods for producing semiconductor substrates and integrated circuitry therein are known in the art, and therefore such processes are not discussed in detail herein.

[0039] At step 1214, method 1200 may include forming a semiconductor device in a semiconductor substrate. Various methods for producing semiconductor devices are known in this art, and therefore such processes are not discussed in detail herein.

[0040] At step 1216, method 1200 may include forming a first interconnect structure on a first side of a semiconductor substrate that is overlaid on and electrically coupled to a semiconductor device. Various methods may be used to form the first interconnect structure. For example, Figure 15 illustrates a non-limiting example in which trenches or openings 1464 are formed in a first masking layer 1460 and a second masking layer 1462 and an interlayer dielectric layer 1418 over a semiconductor substrate 1406. In this example, the semiconductor substrate 1406 includes a semiconductor device having a doped well region 1430, a source / drain structure 1432 therein, and a gate electrode 1434 thereon. A portion of the source / drain structure 1432 may be exposed at the bottom of the opening 1464. Where appropriate, a bushing (not shown) may be formed covering the sidewalls of the opening 1464 in the interlayer dielectric layer 1418. The opening 1464 may be filled with a conductive layer (i.e., a filler material). In some embodiments, the conductive layer may comprise a highly conductive metal or alloy. As a non-limiting example, the conductive layer may comprise copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof. A CMP process may be performed to remove a portion of the conductive layer and / or bushing, forming a flush surface over the dielectric structure. Figure 16 illustrates a non-limiting example where opening 1464 has been filled with a conductive material to define interconnect via 1514, and first masking layer 1460 and second masking layer 1462 have been removed. This process may be repeated for each layer of the first interconnect structure. For example, Figure 17 illustrates a non-limiting example in which a second opening 1664 is formed in a third masking layer 1660 and a fourth masking layer 1662 and a first IMD layer 1666 above an interlayer dielectric layer 1418, and Figure 18 illustrates a non-limiting example in which the second opening 1664 is filled with a conductive material to define an interconnect metal layer 1716, and the third masking layer 1660 and the fourth masking layer 1662 have been removed.

[0041] At step 1218, method 1200 may include forming a second interconnect structure on a second side of the semiconductor substrate that lies beneath and is electrically coupled to a semiconductor device, wherein the first interconnect structure, the semiconductor device, and the second interconnect structure define a back-side metal die damage ring (BMDDR) that partially or completely surrounds the integrated circuit. For example, Figure 19 illustrates a non-limiting example in which a trench or opening 1864 is formed through the fifth masking layer 1860 and the sixth masking layer 1862 and the back side of the semiconductor substrate 1406, such that the opening 1864 is open to the back side of the semiconductor substrate 1406. The fifth masking layer 1860 and the sixth masking layer 1862 may be formed on the back side of the semiconductor substrate 1406, for example, by a film deposition process. Various processes may be used to form the opening 1864, such as one or more photolithography and etching processes. In some embodiments, the opening 1864 may be formed to a sufficient depth such that the bottom of the opening 1864 is defined by a portion of the source / drain structure 1432 of the semiconductor device. Depending on the circumstances, an isolation layer can be formed in the opening 1864 using a physical vapor deposition (PVD) process.

[0042] A conductive component 1920 (e.g., a TSV) may be formed in an opening 1864 by depositing a conductive material into the opening 1864, which is exposed on the back side of the semiconductor substrate 1406, extends through the semiconductor substrate 1406, and is electrically coupled to the source / drain structure 1432 of the semiconductor device. The conductive component 1920 may be formed of or include various conductive materials. Non-limiting examples include various metallic materials, such as titanium tungsten nitride alloy, tungsten, cobalt, ruthenium, molybdenum, etc. The fifth mask layer 1860 and the sixth mask layer 1862 and any other excess material (e.g., portions of the first conductive component) may be removed, for example, by a CMP process. Figure 20 illustrates a non-limiting example in which an interconnect metal layer 1916 has been formed into a second IMD layer 1966 by a process substantially similar to that described with reference to Figures 17 and 18.

[0043] At step 1220, method 1200 may include forming an input component electrically coupled to the BMDDR at a first location on the semiconductor substrate, and at step 1222, method 1200 may include forming an output component electrically coupled to the BMDDR at a second location on the semiconductor substrate, wherein the BMDDR forms a continuous circuit between the input component and the output component. Various methods for manufacturing input and output components are known in this art, therefore such processes are not discussed in detail herein.

[0044] Method 1200 may end at step 1224.

[0045] Therefore, this disclosure provides semiconductor structures and methods for manufacturing and testing semiconductor structures that provide detection of damage, for example, that occurs during a die-cutting process. In some embodiments, the semiconductor structure includes a back-side metal grain damage ring defining a circuit surrounding an integrated circuit.

[0046] According to one embodiment, a semiconductor structure is provided, comprising: an integrated circuit formed in a semiconductor substrate; a sealing ring located on at least a first side of the semiconductor substrate and surrounding the periphery of the integrated circuit; an input component; an output component; and a back-side metal die damage ring (BMDDR) disposed on the first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate, the BMDDR being disposed between the integrated circuit and the sealing ring, the BMDDR at least partially surrounding the periphery of the integrated circuit, the BMDDR being coupled to the input component and the output component and forming a circuit between the input component and the output component.

[0047] According to another embodiment, a method is provided, comprising: providing a semiconductor substrate having an integrated circuit and a back-side metal die damage ring (BMDDR) formed therein, the BMDDR being disposed on a first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate, the BMDDR at least partially surrounding the periphery of the integrated circuit; and detecting damage to the BMDDR by applying an electrical load between an input component and an output component to their respective coupled BMDDRs, so as to detect a break in the circuit defined by the BMDDR.

[0048] According to another embodiment, a method is provided, comprising: providing a semiconductor substrate in which an integrated circuit is formed; forming a semiconductor device in the semiconductor substrate; forming a first interconnect structure on a first side of the semiconductor substrate that is overlaid on and electrically coupled to the semiconductor device; forming a second interconnect structure on a second side of the semiconductor substrate that is underlaid on and electrically coupled to the semiconductor device, wherein the first interconnect structure, the semiconductor device, and the second interconnect structure define a back-side metal die damage ring (BMDDR) that partially or completely surrounds the integrated circuit; forming an input component electrically coupled to the BMDDR at a first location on the semiconductor substrate; and forming an output component electrically coupled to the BMDDR at a second location on the semiconductor substrate, wherein the BMDDR forms a continuous circuit between the input component and the output component.

[0049] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other programs and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The nature of this disclosure is best understood in conjunction with the accompanying drawings and the following detailed description. It should be noted that, according to industry standard practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for ease of discussion. Figure 1 is a cross-sectional view of a portion of an exemplary semiconductor structure at a stage in an integrated circuit manufacturing process according to an embodiment. Figure 2 is a top view of a portion of the exemplary semiconductor structure of Figure 1 according to an embodiment. Figure 3 is a cross-sectional view illustrating a portion of an exemplary sealing ring of the semiconductor structure of Figure 1 according to an embodiment. Figure 4 is a cross-sectional view illustrating a portion of an exemplary backside metal damage detection ring (BMDDR) of the semiconductor structure of Figure 1 according to an embodiment. Figure 5 is a cross-sectional view illustrating a portion of an exemplary BMDDR of the semiconductor device of Figure 1 according to an embodiment. Figure 6 schematically illustrates a serpentine pattern of a circuit formed from the BMDDR of Figure 5 according to an embodiment. Figure 7 is a cross-sectional view illustrating exemplary dimensions of the BMDDR of Figure 5 according to an embodiment. Figure 8 is a cross-sectional view illustrating an exemplary semiconductor device of Figures 5 and 7 according to an embodiment. Figure 9 is a cross-sectional view of a portion of another exemplary semiconductor structure at a stage of an integrated circuit manufacturing process according to an embodiment. Figure 10 is a cross-sectional view of a portion of yet another exemplary semiconductor structure at a stage of an integrated circuit manufacturing process according to an embodiment. Figure 11 is a cross-sectional view of a portion of yet another exemplary semiconductor structure at a stage of an integrated circuit manufacturing process according to an embodiment. Figure 12 is a flowchart illustrating an exemplary method for forming and testing a semiconductor structure according to an embodiment. Figure 13 is a flowchart illustrating an exemplary method for testing a semiconductor structure according to an embodiment. Figure 14 is a flowchart illustrating an exemplary method for manufacturing a semiconductor structure according to an embodiment. Figures 15 to 20 illustrate certain non-limiting steps of the method of Figure 14 according to an embodiment. [Biomaterial Storage]

[0051] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor structure comprising: an integrated circuit formed in a semiconductor substrate; a sealing ring located on at least one first side of the semiconductor substrate and surrounding a periphery of the integrated circuit; an input component; an output component; and a backside metal die damage ring. A BMDDR (Boundary Marking Receptacle Memory ...

2. The semiconductor structure as claimed in claim 1, wherein the first units and the second units are coupled along the BMDDR in a serpentine pattern.

3. The semiconductor structure as claimed in claim 1, wherein the input component and the output component are ends of the second interconnect structure coupled to the second side of the semiconductor substrate.

4. The semiconductor structure as claimed in claim 1, wherein the first interconnect structure and the second interconnect structure are each coupled to a plurality of source / drain structures of the semiconductor devices therebetween.

5. The semiconductor structure as claimed in claim 4, wherein the second interconnect structure is coupled to the source / drain structures via a plurality of substrate vias formed in the second side of the semiconductor substrate.

6. The semiconductor structure as claimed in claim 1, wherein the input component and the output component are a plurality of pads coupled to the integrated circuit.

7. A method for testing a semiconductor structure, comprising the following steps: providing a semiconductor substrate having an integrated circuit and a backside metal die damage ring (BMDDR) formed therein, the BMDDR being disposed on a first side of the semiconductor substrate, extending through the semiconductor substrate, and disposed on a second side of the semiconductor substrate, the BMDDR at least partially surrounding the periphery of the integrated circuit, wherein the BMDDR includes a plurality of first units of a first interconnect structure disposed on the first side of the semiconductor substrate and a plurality of second units of a second interconnect structure disposed on the second side of the semiconductor substrate, wherein the first units and the second units are electrically coupled in series with each other, such that the first units and the second units are linearly alternating along the BMDDR and electrically coupled by a plurality of semiconductor devices formed in the semiconductor substrate; and detecting damage to the BMDDR by applying an electrical load between an input component and an output component to the BMDDR to which they are respectively coupled, so as to detect a break in a circuit defined by the BMDDR.

8. The method as described in claim 7, wherein the step of detecting damage to the BMDDR includes the following steps: measuring a change in a resistance or conductivity of the circuit.

9. A method of manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate in which an integrated circuit is formed; forming a plurality of semiconductor devices in the semiconductor substrate; forming a first interconnect structure on a first side of the semiconductor substrate, covering and electrically coupled to the semiconductor devices, wherein the first interconnect structure is formed to include a plurality of first units; forming a second interconnect structure on a second side of the semiconductor substrate, covering and electrically coupled to the semiconductor devices, wherein the first interconnect structure, the semiconductor devices, and the second interconnect structure define a backside metal die damage ring (BMDDR) that partially or completely surrounds the integrated circuit, wherein the second interconnect structure is formed to include a plurality of second units, wherein the first units and the second units are connected in series and electrically coupled to each other, such that the first units and the second units alternate linearly along the BMDDR and are electrically coupled by the semiconductor devices formed in the semiconductor substrate; An input component electrically coupled to the BMDDR at a first location is formed on the semiconductor substrate; and an output component electrically coupled to the BMDDR at a second location is formed on the semiconductor substrate, wherein the BMDDR forms a continuous circuit between the input component and the output component.

10. The method as described in claim 9, wherein the first interconnect structure and the second interconnect structure are each coupled to a plurality of source / drain structures of the semiconductor devices.

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