Integrated circuit device and method of manufacturing

Abstract

This disclosure provides different complementary stacked transistor cell mid-segment connections for power delivery in buried power rail architectures. An integrated circuit device includes a device stack, a top contact structure, a back power rail, and a via interconnect. The device stack includes a bottom semiconductor device and a top semiconductor device stacked on the bottom semiconductor device along a direction. The top contact structure is located above and electrically contacts a source / drain of the top semiconductor device. The via interconnect extends between the top contact structure and the back power rail and is electrically coupled to the top contact structure and the back power rail. The via interconnect tapers gradually along the back power rail toward the top contact structure.

Description

Technical Field

[0001] none Prior Technology

[0002] An integrated circuit (IC) device comprises one or more semiconductor devices represented by an integrated circuit layout (also known as a "layout," "layout," or "integrated circuit layout"). A layout is hierarchical and contains multiple modules that perform high-level functions according to the semiconductor device design specifications. These modules are often composed of combinations of multiple cells, each representing one or more semiconductor structures for performing a specific function. Cells with pre-designed layouts, sometimes called standard cells, are stored in a standard library (hereafter referred to as a "library" or "cell library" for brevity) and are used by various tools, such as Electronic Design Automation (EDA) tools, to generate, optimize, and verify IC designs.

[0003] To reduce the size of integrated circuit devices, sometimes one layer of a semiconductor device is formed or bonded on top of another semiconductor device. For example, in a complementary field effect transistor (CFET) device, a higher or top semiconductor device is stacked on top of a lower or bottom semiconductor device. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The present invention is best understood by reading it in conjunction with the accompanying drawings from the following detailed description. Please note that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration. Figure 1A is a schematic diagram of a stack of semiconductor devices according to some embodiments. Figure 1B is a schematic diagram of an integrated circuit device according to some embodiments, and Figures 1C, 1D, 1E and 1F are schematic cross-sectional views of the integrated circuit device at different stages of the manufacturing process. Figure 2A is a block diagram of an integrated circuit device according to some embodiments. Figure 2B is a schematic diagram of the layout of an integrated circuit device according to some embodiments. Figure 3A is a cross-sectional schematic diagram of one or more circuit regions of one or more integrated circuit devices according to some embodiments, and Figure 3B is a schematic diagram of the layout of the one or more circuit regions of the one or more integrated circuit devices. Figure 4A is a cross-sectional schematic diagram of one or more integrated circuit devices according to some embodiments, and Figure 4B is a schematic diagram of the layout of one or more circuit regions of the one or more integrated circuit devices. Figure 5A is a cross-sectional schematic diagram of one or more integrated circuit devices according to some embodiments, and Figure 5B is a schematic diagram of the layout of one or more circuit regions of the one or more integrated circuit devices. Figures 6A, 6B, and 6C are schematic diagrams showing the layout of different circuit regions of one or more integrated circuit devices according to some embodiments. Figures 7A and 7B are perspective views of different circuit regions of one or more integrated circuit devices according to some embodiments. Figures 8A, 8B, 8C, 8D, and 8E are schematic cross-sectional views of an integrated circuit device at different stages of the manufacturing process according to some embodiments. Figures 9A, 9B, 9C, 9D, and 9E are schematic cross-sectional views of an integrated circuit device at different stages of the manufacturing process according to some embodiments. Figures 10A and 10B are schematic cross-sectional views of an integrated circuit device according to some embodiments at different stages of the manufacturing process. Figures 11A and 11B are schematic diagrams of a portion of the manufacturing process of an integrated circuit device according to some embodiments, and are schematic diagrams of different stages of the manufacturing process of the integrated circuit device. Figures 12A-12D are flowcharts of different methods according to some embodiments. Figure 13 is a block diagram of an electronic design automation system according to some embodiments. Figure 14 is a block diagram of an integrated circuit device manufacturing system and an associated integrated circuit manufacturing process according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific instances of components and configurations will be described below to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the first feature formed above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, one embodiment of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," "top," "bottom," and the like, may be used herein for ease of description to describe the relationship between one or more elements or features as illustrated in the accompanying drawings and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0008] In some embodiments, the integrated circuit device includes a power delivery structure to provide multiple power supply voltages, such as a positive power supply voltage VDD and a reference voltage (e.g., ground voltage) VSS, to various circuits and / or circuit elements within the integrated circuit device. In some configurations, the power delivery structure is located on the front side and the opposite rear side of the integrated circuit, and it includes one or more power tap structures for providing power from the front and rear sides to the other side. The wafer occupied by the power tap structures or power tap units is sometimes referred to as a power tap area.

[0009] In some embodiments, one circuit of the integrated circuit device includes a via interconnect for transmitting power from one side of the integrated circuit device to the other side, for example, from the rear to the front. In at least one embodiment, the via interconnect is embedded in a gate length defining dielectric structure for defining the length of one or more gates in the circuit. In some embodiments, the via interconnect is disposed at the boundary of a first cell corresponding to one of the circuits and is shared with another circuit corresponding to a second cell adjacent to the first cell. In at least one embodiment, the via interconnect is used as a power via to transmit power to a single cell or a single complementary stacked transistor. In some embodiments, the via interconnect is used as a power wall to transmit power to multiple cells or multiple complementary stacked transistors. In one or more embodiments, when the via interconnect is used to transmit power from one side of the integrated circuit device to the other, it may be possible to exclude all power tap structures in the integrated circuit device, or at least reduce the number of power tap structures. Therefore, in one or more embodiments, the circuit tap area of ​​the integrated circuit device can be advantageously reduced, which ensures that the voltage drop in the power transmission structure is within a predetermined or acceptable range.

[0010] In some embodiments, the formation of via interconnects does not increase the number of photomasks required in the intermediate process, such as extreme ultraviolet (EUV) photomasks, or may even reduce the number of EUV photomasks required in the intermediate process compared to other methods. In at least one embodiment, the formation of via interconnects increases the number of EUV photomasks required in the intermediate process by a very small amount compared to other methods, such as a single EUV photomask. One or more additional advantages may be achieved by the different embodiments described below.

[0011] Figure 1A is a schematic diagram of a stack of semiconductor devices, or a device stack 100A, according to some embodiments.

[0012] Device stack 100A includes a stacked structure 10 comprising a bottom semiconductor device 10L and a top semiconductor device 10U. The bottom semiconductor device 10L is located on a substrate. For simplicity, the substrate is not shown in Figure 1A. An exemplary substrate is described in Figures 1B-1F. The top semiconductor device 10U is physically stacked on top of the bottom semiconductor device 10L in the thickness direction of the substrate. This thickness direction is designated as the Z-axis in Figure 1A. In the exemplary configuration of Figure 1A, the top semiconductor device 10U and the bottom semiconductor device 10L are of different conductivity types. Other configurations in which the top semiconductor device 10U and the bottom semiconductor device 10L are of the same conductivity type are also within the scope of this embodiment. Conductivity type is sometimes also referred to as semiconductor type. Examples of conductivity types include N-type and P-type. In one example, the top semiconductor device 10U is an N-type semiconductor device and the bottom semiconductor device 10L is a P-type semiconductor device, and the stacked structure 10 is referred to as an N-on-P structure. In another example, the top semiconductor device 10U is a P-type semiconductor device and the bottom semiconductor device 10L is an N-type semiconductor device, and the stacked structure 10 is referred to as a P-on-N structure. For the sake of brevity, the embodiments described herein include N-on-P structures. One or more features, functions, and / or advantages of embodiments of N-on-P structures are applicable to, and / or can be achieved by, embodiments of P-on-N structures.

[0013] The top semiconductor device 10U includes a gate 80U and a source / drain 62U relative to the gate 80U along the X-axis. The gate 80U extends or elongates along the Y-axis. The X-axis, Y-axis, and Z-axis intersect each other. In some embodiments, the X-axis, Y-axis, and Z-axis are perpendicular to each other. The top semiconductor device 10U further includes a channel region constructed by a nanosheet 26U extending along the X-axis and connecting the source / drain 62U. In the exemplary configuration of Figure 1A, the top semiconductor device 10U includes two nanosheets 26U. Other numbers of nanosheets in each transistor are also within the scope of embodiments disclosed herein. The top semiconductor device 10U includes a gate dielectric layer 78 extending around the nanosheets 26U, and the gate dielectric layer 78 electrically blocks the gate 80U from the nanosheets 26U. In a configuration known as Gate-All-Around (GAA), the gate 80U extends around the gate dielectric layer 78 and the nanosheet 26U. Other gate configurations are also within the scope of embodiments disclosed herein.

[0014] The bottom semiconductor device 10L includes a channel region constructed by a gate 80L, a source / drain 62L, and a nanosheet 26L, and a gate dielectric layer 78 extending around the nanosheet 26L. The gate 80L, source / drain 62L, and nanosheet 26L correspond to the gate 80U, source / drain 62U, and nanosheet 26U, respectively. The gate 80U, source / drain 62U, and nanosheet 26U overlap the gate 80L, source / drain 62L, and nanosheet 26L along the Z-axis. In the exemplary configuration of Figure 1A, the source / drain 62U and 62L are epitaxial structures of different conductivity types. For example, the source / drain 62L is a p-type epitaxial structure and the source / drain 62U is an N-type epitaxial structure.

[0015] The stacked structure 10 further includes an intermediate layer 90 located between gates 80U and 80L. In some embodiments, the intermediate layer 90 is a dielectric layer that electrically isolates gates 80U and 80L, and in a configuration referred to as a barrier gate, gates 80U and 80L are independently controllable. In at least one embodiment, gates 80U and 80L in the barrier gate configuration are still electrically coupled to each other by a conductor, such as a gate local interconnect. In some embodiments, the intermediate layer 90 is a conductive layer electrically coupled to gates 80U and 80L, and in a configuration referred to as a connected gate, gates 80U and 80L form a common gate for one of the top semiconductor device 10U and the bottom semiconductor device 10L. In embodiments of the connected gate configuration, the conductive intermediate layer 90 is formed integrally and / or simultaneously with gates 80U and 80L in the surrounding gate structure.

[0016] As can be seen from Figure 1A, in one or more embodiments, stacking the top semiconductor device 10U on top of the bottom semiconductor device 10L saves 50% of the required wafer area compared to other methods where semiconductor devices are not stacked. In some embodiments, it is possible to fabricate integrated circuit devices comprising multiple stacked devices using a complementary stacked transistor process with only minor or no changes to the fabrication process.

[0017] Figure 1B is a schematic diagram of an integrated circuit device 100 according to some embodiments, and Figures 1C-1F are schematic cross-sectional views of the integrated circuit device 100 in the XZ plane at different stages of the manufacturing process. The integrated circuit device 100 includes a plurality of device stacks corresponding to device stack 100A. For simplicity, corresponding elements in Figures 1A-1F are assigned the same reference numerals. In some embodiments, additional operations are provided before, during, and / or after the manufacturing process shown in Figures 1B-1F, and / or one or more of the aforementioned additional operations are replaced or excluded, and / or the order of these operations may be interchangeable.

[0018] Referring to Figure 1B, the manufacturing process begins with substrate 20. In at least one embodiment, substrate 20 is a semiconductor substrate. In some embodiments, substrate 20 includes at least a single-crystal semiconductor layer on its surface. Exemplary materials for substrate 20 include, but are not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, substrate 20 is a Si substrate. In some embodiments, substrate 20 is an SOI (Silicon-On-Insulator) substrate, which includes an insulating layer disposed between two silicon layers. In at least one embodiment, the insulating layer is an oxide layer.

[0019] A multilayer structure 22 is formed on a substrate 20. In Figure 1B, the multilayer structure 22 is shown after the formation of fins. The multilayer structure 22 includes alternating first semiconductor layers 24A, 24B and second semiconductor layers 26U, 26L. The second semiconductor layers 26U, 26L correspond to the nanosheets described in FIG. 1A and are referred to herein with the same reference numerals as nanosheets for simplicity. The first semiconductor layers 24A, 24B and the second semiconductor layers 26U, 26L contain semiconductor materials with different etching selectivity and / or oxidation rates. For example, the first semiconductor layers 24A, 24B contain silicon germanium, while the second semiconductor layers 26U, 26L contain silicon. In some embodiments, the first and second semiconductor layers 24A, 24B, 26U, 26L are formed by a deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the multilayer structure 22 is carried out through molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) and / or other appropriate epitaxial growth processes.

[0020] After the multilayer structure 22 is formed, fins 28 are formed. Each fin 28 includes a substrate portion 21 of the substrate 20 and a portion 34 of the multilayer structure 22. The portion 34 of the multilayer structure 22 is sometimes referred to as a semiconductor stack 34. In some embodiments, the fins 28 are fabricated using appropriate processes, such as double exposure or multiple exposure processes. For example, in one or more embodiments, a sacrificial layer is formed on the substrate and patterned using a lithography process. A spacer layer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer layer can be used to pattern the fins 28 by etching the multilayer structure 22 and the substrate 20. Exemplary etching processes include, but are not limited to, dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Two fins 28 are shown in Figure 1B; however, the number of fins is not limited to two. The fins 28 extend or lengthen along the X-axis.

[0021] Shallow trench isolation (STI) 32 of insulating material is formed in trenches (not numbered) above substrate 20 and between fins 28. For example, insulating material is deposited on substrate 20 and fins 28. Exemplary insulating materials for shallow trench isolation 32 include, but are not limited to, silicon oxide, fluorine-doped silicate glass (FSG), silicon nitride, silicon oxynitride (SiON), silicon oxycarbonate (SiOCN), silicon carbide (SiCN), low-k dielectric materials, or similar materials. The deposition of the insulating material includes suitable methods such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD). Subsequently, a planarization process, such as Chemical Mechanical Polishing (CMP) and / or etching back, is performed to expose the top of the fins 28 from the insulating material. A portion of the insulating material between adjacent fins 28 is removed. The remaining portion of the insulating material forms shallow trench isolation 32. The partial removal of the insulating material includes dry etching, wet etching, or similar methods.

[0022] Sacrificial gate dielectric layer 36, sacrificial gate electrode layer 38, and photomask structure 40 are deposited on shallow trench isolation 32 and fin 28. The sacrificial gate dielectric layer 36 comprises one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer 36 is deposited using CVD, sub-atmospheric CVD (SACVD), FCVD, atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes. In at least one embodiment, the sacrificial gate electrode layer 38 comprises polycrystalline silicon. In some embodiments, the photomask structure 40 comprises a multilayer structure. In some embodiments, the sacrificial gate electrode layer 38 and the photomask structure 40 are formed through one or more processes, such as layer deposition, such as CVD (including LPCVD and PECVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques. Structure 100B is available.

[0023] Referring to Figure 1C, the sacrificial gate stack 42 is formed through one or more patterning and / or etching processes performed on the deposited sacrificial gate dielectric layer 36, sacrificial gate electrode layer 38, and photomask structure 40 of structure 100B. Exemplary patterning processes include lithography. Exemplary etching processes include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. Each sacrificial gate stack 42 includes a portion of each of the sacrificial gate dielectric layer 36, sacrificial gate electrode layer 38, and photomask structure 40. The sacrificial gate stack 42 extends or elongates along the Y-axis. Three sacrificial gate stacks 42 are illustrated in Figure 1C; however, the number of sacrificial gate stacks 42 is not limited to three.

[0024] Spacer layer 44 is formed on the sidewall of sacrificial gate stack 42. For example, spacer layer 44 is formed by first depositing a conformal layer and then etching back to form spacer layer 44. Spacer layer 44 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide, silicon oxide, silicon oxide, and / or combinations thereof. In some embodiments, spacer layer 44 comprises multiple layers.

[0025] Exposed portions of the semiconductor layer stack 34 of the fins 28 not covered by the sacrificial gate stack 42 and spacer layer 44 are selectively removed, for example, by one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof, to form trench 46. In Figure 1C, the lowermost layer of the second semiconductor layer 26U and the uppermost layer of the second semiconductor layer 26L are designated as the intermediate second semiconductor layer 26M, with the intermediate first semiconductor layer 24B sandwiched between them. The intermediate second semiconductor layer 26M and the intermediate first semiconductor layer 24B are not used to form the channel regions of the top semiconductor device 10U and the bottom semiconductor device 10L. The edge portions of the first semiconductor layers 24A, 24B and the second semiconductor layers 26U, 26L, 26M are exposed in the trench 46. The trench 46 also exposes a portion of the substrate portion 21. Thus, structure 100C is obtained.

[0026] Referring to Figure 1D, the exposed edge portion of the first semiconductor layer 24A is removed. In some embodiments, this removal includes a selective wet etching process. The selective wet etching process further completely (or substantially completely) removes the first semiconductor layer 24B located in the middle of the semiconductor layer stack 34. For example, in an embodiment where the first semiconductor layers 24A, 24B contain silicon and germanium and the second semiconductor layers 26U, 26L, 26M contain silicon, the selective wet etching is used to etch the first semiconductor layer 24B at the highest etch rate, etch the first semiconductor layer 24A at the second highest etch rate, and etch the second semiconductor layers 26U, 26L, 26M at the slowest etch rate. As a result, the exposed edge portion of the first semiconductor layer 24A and all (or substantially all) of the first semiconductor layer 24B are removed, while the second semiconductor layers 26U, 26L, 26M remain substantially unchanged.

[0027] Dielectric material is deposited on and within the space created after the removal of the first semiconductor layer 24B and the edge portion of the partial removal of the first semiconductor layer 24A. The dielectric material filling the space created by the partial removal of the edge portion of the first semiconductor layer 24A constitutes the internal spacer layer 54. The dielectric material filling the space created by removing the first semiconductor layer 24B constitutes the internal isolation structure 56. Examples of dielectric materials forming the internal spacer layer 54 and the internal isolation structure 56 include, but are not limited to, low-k dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon carbide, or silicon carbide, or high-k dielectric materials, such as hafnium dioxide (HfO2), zirconium oxide (ZrOx), zirconium alumina (ZrAlOx), hafnium alumina (HfAlOx), hafnium silicon oxide (HfSiOx), aluminum oxide (AlOx), or other suitable dielectric materials. In some embodiments, the internal spacer layer 54 and the internal isolation structure 56 comprise different dielectric materials. In one exemplary process, the internal spacer layer 54 and the internal isolation structure 56 are formed by depositing a conformal layer of dielectric material using a conformal deposition process (such as ALD), followed by anisotropic etching to remove the conformal layer portion other than the internal spacer layer 54 and the internal isolation structure 56.

[0028] A source / drain 62L is formed and contacts the exposed portion of the substrate portion 21 and the exposed edge portion of the second semiconductor layer 26L. In the example configuration of Figure 1D, the source / drain 62L includes an epitaxial structure and is sometimes referred to as the source / drain epitaxial structure 62L. In some embodiments, the source / drain epitaxial structure 62L includes one or more layers of silicon, silicon-germanium, or germanium to form a P-type bottom semiconductor device. Exemplary epitaxial growth processes for growing the source / drain epitaxial structure 62L include, but are not limited to, CVD, ALD, and MBE. In some embodiments, the source / drain epitaxial structure 62L is grown to a height exceeding that of the uppermost second semiconductor layer 26L, and then the top portion of the source / drain epitaxial structure 62L is partially removed, for example, by dry etching or wet etching, so that the remaining upper surface of the source / drain epitaxial structure 62L is at the level of the uppermost first semiconductor layer 24A immediately below the lower intermediate second semiconductor layer 26M, as shown in Figure 1D.

[0029] A substrate 6 is formed at least on the upper surface of the source / drain epitaxial structure 62L and the exposed sides of the intermediate second semiconductor layer 26M and the internal isolation structure 56. In some embodiments, the substrate 63 comprises silicon. In an exemplary process, the substrate 63 is a conformal layer formed by a conformal process (such as an ALD process).

[0030] Dielectric material 68 is formed on the substrate 63 and above the source / drain epitaxial structure 62L. In some embodiments, dielectric material 68 comprises the same material as shallow trench isolation 32 and / or is formed using the same method as shallow trench isolation 32. The substrate 63 and dielectric material 68 are removed outside the trench 46 and partially removed inside the trench 46, for example, by dry etching or wet etching. Thus, the upper surfaces of the substrate 63 and dielectric material 68 are located at the level of the lowermost first semiconductor layer 24A immediately above the higher intermediate second semiconductor layer 26M, as shown in Figure 1D. The substrate 63 and dielectric material 68 form an isolation structure between the source / drain 62L and source / drain 62U to be formed subsequently.

[0031] A source / drain 62U is formed and contacts the upper surface of the substrate 63 and the dielectric material 68, as well as the exposed edge portion of the second semiconductor layer 26U. In the exemplary configuration of Figure 1D, the source / drain 62U includes an epitaxial structure and is sometimes referred to as a source / drain epitaxial structure 62U. The source / drain epitaxial structure 62U has a different conductivity type than the source / drain epitaxial structure 62L. In some embodiments, the source / drain epitaxial structure 62U is manufactured using the same or similar process as the source / drain epitaxial structure 62L. In at least one embodiment, the source / drain epitaxial structure 62U has the same configuration as the source / drain epitaxial structure 62L, such as the same size, shape, and height. In one example, the source / drain epitaxial structure 62U includes one or more layers of silicon, silicon phosphide (SiP), silicon carbide (SiC), and silicon phosphide carbide (SiCP) to form an N-type top semiconductor device. In some embodiments, the source / drain epitaxial structure 62U is grown to a height exceeding the sacrificial gate dielectric layer 36, and then the top portion of the source / drain epitaxial structure 62U is partially removed, for example by dry etching or wet etching, so that the remaining upper surface of the source / drain epitaxial structure 62U is at the level of the sacrificial gate dielectric layer 36, as shown in Figure 1D. This is one example, and the height of the source / drain epitaxial structure 62U is controllable, depending on application and / or process requirements.

[0032] A contact etch stop layer (CESL) 70 is formed on the source / drain epitaxial structure 62U. Exemplary materials for the contact etch stop layer 70 include, but are not limited to, silicon nitride, silicon carbide, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, and combinations thereof. The contact etch stop layer 70 is formed using CVD, PECVD, ALD, or any suitable deposition technique.

[0033] An interlayer dielectric (ILD) layer 72 is formed on the contact etch stop layer 70. Exemplary materials for the interlayer dielectric layer 72 include, but are not limited to, tetraethylorthosilicate (TES) oxide, undoped silicate glass, or doped silica oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 72 is deposited using a PECVD process or other suitable deposition techniques. This yields a structure 100D.

[0034] Referring to Figure 1E, a planarization process, such as a CMP process, is performed to remove the photomask structure 40 and expose the sacrificial gate electrode layer 38. This planarization process also removes a portion of the interlayer dielectric layer 72 and the contact etch stop layer 70.

[0035] The exposed sacrificial gate electrode layer 38 and sacrificial gate dielectric layer 36 will be removed, for example, through one or more suitable processes, such as dry etching, wet etching, or a combination thereof.

[0036] Next, the first semiconductor layer 24A is removed, for example by any suitable process, such as dry etching, wet etching, or a combination thereof. The removal of the first semiconductor layer 24A exposes the inner spacer layer 54 and the second semiconductor layers 26U, 26L, forming spaces between and around the exposed portions of the second semiconductor layers 26U, 26L not covered by the inner spacer layer 54. The exposed portions of the second semiconductor layers 26U, 26L constitute nanosheets 26U, 26L as shown in FIG. 1A. The intermediate second semiconductor layer 26M and the inner isolation structure 56 are covered by the substrate 63 and the dielectric material 68, and are substantially unaffected by the removal of the first semiconductor layer 24A.

[0037] A gate dielectric layer 78 is formed on and around nanosheets 26U and 26L. In some embodiments, the gate dielectric layer 78 comprises the same material as the sacrificial gate dielectric layer 36. In some embodiments, the gate dielectric layer 78 comprises a high-k dielectric material. In some embodiments, the gate dielectric layer 78 is formed by a conformal process (e.g., an ALD process).

[0038] Gate electrode material is formed on and around the gate dielectric layer 78 and nanosheets 26U and 26L. The gate material surrounding each nanosheet 26U constitutes gate 80U. The gate material surrounding each nanosheet 26L constitutes gate 80L. In some embodiments, the gate electrode material comprises multiple gate electrode layers. Exemplary gate electrode materials include, but are not limited to, polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, titanium nitride (TiN), tungsten nitride (WN), tungsten carbide (WCN), titanium aluminum nitride (TiAl), titanium tantalum nitride (TiTaN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum carbide (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode material comprises a P-type gate electrode layer, such as titanium nitride, tantalum nitride, titanium tantalum nitride, titanium aluminum nitride, tungsten carbide, tungsten, nickel, cobalt, or other suitable materials, for constituting a P-type bottom semiconductor device. In at least one embodiment, the gate electrode material comprises an N-type gate layer, such as titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum silicon carbide (TiSiAlC), titanium carbide (TiC), tantalum aluminum silicon carbide (TaSiAlC), or other suitable materials, for constituting an N-type top semiconductor device. Exemplary processes for depositing the gate electrode material include, but are not limited to, PVD, CVD, ALD, electroplating, or other suitable methods.

[0039] In some embodiments, each gate 80U and gate 80L includes a corresponding GAA structure, and the gates 80U and 80L are physically and electrically separated from each other by an intermediate second semiconductor layer 26M and an internal isolation structure 56. In some embodiments, the combination of the intermediate second semiconductor layer 26M and the internal isolation structure 56 corresponds to the intermediate layer 90 being the dielectric material in the isolated gate configuration. In at least one embodiment, the gates 80U and 80L in the isolated gate configuration are still electrically coupled to each other through a conductor (e.g., an MGLI interconnect). In some embodiments, the gates 80U and 80L are part of a unified GAA structure that extends around each nanosheet 26U, 26L and forms a common gate for the top semiconductor device and the bottom semiconductor device. The formation of the gates 80U and 80L completes the formation of the top semiconductor device 10U and the bottom semiconductor device 10L. An interlayer dielectric layer 92, similar to the interlayer dielectric layer 72, is deposited on the gate 80U, and a planarization process (e.g., CMP) is performed. This allows us to obtain structure 100E.

[0040] Referring to Figure 1F, an opening is formed in the interlayer dielectric layer 72 to expose the source / drain epitaxial structure 62U. A silicate layer 94 is formed over the exposed source / drain epitaxial structure 62U, and then source / drain contacts 96U are formed in each opening and on the silicate layer 94. Source / drain contacts (or source / drain contact structures) are sometimes referred to as metal-to-device (MD) contacts. Source / drain contacts of a top semiconductor device are sometimes referred to as MD contacts or top contact structures. Source / drain contacts of a bottom semiconductor device are sometimes referred to as BMD contacts or bottom contact structures. For simplicity, MD contacts or contact structures here refer to upper MD contacts or lower BMD contacts unless otherwise stated. Exemplary materials for source / drain contacts 96U include, but are not limited to, ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride. The source / drain contacts 96U are formed using any suitable process, such as PVD, ECP, or CVD.

[0041] Dielectric layers 104 and 106 are deposited on the MD contact 96U and the interlayer dielectric layer 92. Multiple vias 108 and 110 are formed by etching openings in the dielectric layers 104 and 106 and the interlayer dielectric layer 92, and then filling the openings with a conductive material (e.g., metal). Vias above and electrically in contact with the MD contact are sometimes referred to as via-to-device (VD) vias. Vias electrically in contact with the gate are sometimes referred to as via-to-gate (VG) vias. In the exemplary configuration shown in Figure 1F, via 108 is a VG via located above the gate 80U, while via 110 is a VD via correspondingly located above the MD contact 96U. The VG and VD vias of the bottom semiconductor devices are sometimes referred to as BVG and BVD vias, respectively. The resulting structure 112 includes various semiconductor devices formed on the front (or top) side of the substrate 20, and corresponding MD contacts, VG, and VD vias.

[0042] A redistribution structure 114 is formed on the VD and VG vias 110 and 108 of structure 112. The redistribution structure 114 includes multiple metal layers 118A-118C and via layers 117A and 117B sequentially and alternately formed on the VD and VG vias 110 and 108. The redistribution structure 114 further includes multiple interlayer dielectric (ILD) layers 116, in which the metal layers and via layers are embedded. The metal layers and via layers of the redistribution structure 114 are used to electrically couple multiple semiconductor devices, or circuits of the IC device 100, to each other, and / or to external circuits. In the redistribution structure 114, the lowest metal layer 118A, which is immediately above and electrically in contact with the vias 110 and 108 of VD and VG, is the M0 (metal zero) layer. The next metal layer 118B immediately above the M0 layer is the M1 layer, and the next metal layer 118C immediately above the M1 layer is the M2 layer, and so on. The conductive pattern in the M0 layer is called the M0 conductive pattern, the conductive pattern in the M1 layer is called the M1 conductive pattern, and so on. The via layer Vn is disposed between the Mn layer and the Mn+1 layer and electrically coupled to the Mn layer and the Mn+1 layer, where n is an integer of 0 or above. For example, the via layer 117A is the via zero (V0) layer, which is the lowest via layer arranged between the M0 layer 118A and the M1 layer 118B and electrically coupled to the M0 layer 118A and the M1 layer 118B. The next via layer 117B is the V1 layer, which is a via layer arranged between the M1 layer 118B and the M2 layer 118C, and electrically coupled to the M1 layer 118B and the M2 layer 118C. The vias in the V0 layer are called V0 vias, the vias in the V1 layer are called V1 vias, and so on. For simplicity, the metal layers and via layers in the redistribution structure 114 are not fully shown in Figure 1F. The redistribution structure 114 and its interconnects are formed on the front side of the substrate 20, and are sometimes referred to as the front redistribution structure and the front interconnect. Thus, structure 100F is obtained, as shown in Figure 1F.

[0043] In some embodiments, the fabrication of the IC device 100 further includes forming various features and / or structures on the back side of the substrate 20 (e.g., the lower side in Figure 1F). In an exemplary fabrication process, structure 100F is flipped and temporarily bonded to a carrier (not shown). Wafer thinning is performed from the back side (now facing upwards) to remove a portion of the substrate 20. For example, as shown in Figure 1F, the substrate portion 130 of the substrate 20 is retained due to the wafer thinning on the back side. In some embodiments, the wafer thinning process includes a grinding operation, a polishing operation (e.g., chemical mechanical polishing (CMP)), or a similar operation. In at least one embodiment, the substrate 20 is completely removed, and a new substrate (not shown), such as an insulating substrate, is formed on the bottom semiconductor device 10L. Subsequently, a plurality of BMD contacts, BVG vias, and BVD vias are formed in a manner similar to that described correspondingly for the formation of MD contacts, VG vias, and VD vias. The back-side redistribution structure is formed in a manner similar to redistribution structure 114. The back-side redistribution structure comprises multiple back-side metal layers and multiple back-side via layers arranged alternately along the thickness direction (i.e., along the Z-axis). The back-side redistribution structure further includes multiple interlayer dielectric (ILD) layers, in which the back-side metal layers and back-side via layers are embedded. The back-side metal layer immediately adjacent to the bottom semiconductor device 10L is the back-side M0 (BM0) layer, the next back-side metal layer is the back-side M1 (BM1) layer, and so on. A back-side via layer BVn is disposed between the BMn layer and the BMn+1 layer, and electrically couples the BMn layer and the BMn+1 layer, where n is an integer of 0 or higher. For example, via layer BV0 is a back-side via layer disposed between the BM0 layer and the BM1 layer, electrically coupling the BM0 layer and the BM1 layer. Other back-side via layers are BV1, BV2, and so on. The conductive pattern in the BM0 layer is called the BM0 conductive pattern, the conductive pattern in the BM1 layer is called the BM1 conductive pattern, and so on. The vias in the BV0 layer are called BV0 vias, the vias in the BV1 layer are called BV1 vias, and so on. While the manufacturing process described in one or more embodiments includes the formation of nanosheet devices, other types of devices, such as nanowires, FinFETs, planar or similar elements, are also within the scope of various embodiments. The process and / or operation sequence described is exemplary. Other process and / or operation sequences are also within the scope of various embodiments.

[0044] In some embodiments, the formation of the top and bottom semiconductor devices, including gates, channel regions, and source / drain regions, is referred to as front-end-of-line (FEOL) fabrication, while the formation of the front and back redistribution structures is referred to as back-end-of-line (BEOL) fabrication, to provide routing for the semiconductor devices. Various features between FEOL and BEOL fabrication are referred to as middle-of-line (MOL) fabrication. Examples of MOL features include, but are not limited to, MD contacts, BMD contacts, via interconnects (e.g., power vias and / or power walls as described herein), dielectric structures corresponding to cut-metal-gate (CMG) regions, various vias coupled to the gate, MD contacts, BMD contacts and / or via interconnects, or similar features.

[0045] Figure 2A is a block diagram of an IC device 200A according to some embodiments.

[0046] In Figure 2A, IC device 200A includes macro 202. In some embodiments, macro 202 includes one or more of memory, electrical grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 202 is understood in the context of an architecture level analogous to modular programming, where a subroutine / program is called by a main program (or other subroutine) to perform a specified operational function. Under this premise, IC device 200A uses macro 202 to perform one or more given functions. Therefore, in terms of the aforementioned architecture level, IC device 200A is similar to a main program, and macro 202 is similar to a subroutine / program. In some embodiments, macro 202 is a soft macro. In some embodiments, macro 202 is a hard macro. In some embodiments, macro 202 is a soft macro described in bits of Register Transport Layer (RTL) code. In some embodiments, macro 202 has not yet been synthesized, placed, and routed; therefore, the soft macro can be synthesized, placed, and routed for various process nodes. In some embodiments, macro 202 is a hard macro described digitally in a binary file format (e.g., Graphical Database System II (GDSII) streaming format), wherein the binary file format represents the planar geometry, text labels, other information, etc., of one or more layout diagrams of macro 202 in a hierarchical manner. In some embodiments, macro 202 has been synthesized, placed, and routed, making the hard macro specific to a particular process node.

[0047] Macro 202 includes a region 204 containing a device stack with a top semiconductor device that receives power from a back-side power rail via MOL features. Embodiments of the device stack and top semiconductor device have been described in FIG. 1A. Embodiments of the back-side power rail are described herein, for example, in FIG. 2B. In some embodiments, in FEOL fabrication, region 204 includes a substrate having circuitry formed thereon. Furthermore, above and / or below the substrate (e.g., on the front and / or back side of the substrate), region 204 includes multiple metal layers stacked above and / or below an insulating layer in BEOL fabrication. BEOL fabrication provides a power network and / or routing for the circuitry of IC device 200A (including macro 202 and region 204). Region 204 further includes one or more MOL features electrically coupling the back-side power rail in the power network to the top semiconductor device, as described herein.

[0048] Figure 2B is a schematic diagram of layout 200B and an IC device according to some embodiments. In some embodiments, layout 200B corresponds to IC device 200A. For simplicity, several features of layout 200B are omitted in Figure 2B. In at least one embodiment, layout 200B is stored on a non-transitory computer-readable recording medium.

[0049] Layout 200B includes a power delivery structure and one or more functional circuits coupled to and powered by the power delivery structure. In the exemplary configuration shown in Figure 2B, the power delivery structure includes a power delivery network 210, and the one or more functional circuits are schematically represented as multiple units C1-C4.

[0050] The power delivery network 210 includes a plurality of power rails 220-224 extending along a first axis (i.e., the X-axis) and spaced apart from each other by a center-to-center cell height along a second axis (Y-axis) transverse to the first axis. In at least one embodiment, the Y-axis is perpendicular to the X-axis. In some embodiments, the power delivery network 210 is disposed on the back side of an IC device as a back-side power delivery network, the IC device further comprising a front side opposite the back side in the thickness direction of the IC device. The power rails 220-224 of the power delivery network 210 are used to provide a first power supply voltage and a second power supply voltage different from the first power supply voltage. For example, the first power supply voltage is one of VSS and VDD, and the second power supply voltage is the other of VSS and VDD. The power rail used to provide VSS is sometimes referred to herein as the VSS power rail, and the power rail used to provide VDD is sometimes referred to herein as the VDD power rail. The VDD power rail and the VSS power rail are arranged alternately along the Y-axis. In the exemplary configuration of Figure 2B, power rails 220, 222, and 224 are VSS power rails, which are alternately arranged with VDD power rails including power rails 221 and 223. In some embodiments, power supply voltages (e.g., VSS and VDD) are provided to power rails 220-224 via one or more backside metal layers and via layers described herein.

[0051] In some embodiments, the power delivery structure further includes a front-side power delivery network (not shown) located on the side in front of the IC device. In at least one embodiment, the front-side power delivery network includes one or more power rails extending along the X-axis and arranged in a front-side metal layer as described herein. The power delivery structure further includes power tap structures or circuitry (not shown) for delivering VDD and / or VSS from the power delivery network 210 to the front-side power delivery network. In some embodiments, the power tap structures are uniformly or substantially uniformly distributed over the area of ​​layout 200B.

[0052] Units C1-C4 correspond to one or more functional circuits of the IC device. Functional circuits are used to perform one or more functions of the IC device. In some embodiments, functional circuits include one or more active elements, passive elements, logic circuits, or similar elements. Examples of logic circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, clock, memory, or similar elements. Exemplary memory cells include, but are not limited to, Static Random Access Memory (SRAM), Dynamic RAM (DRAM), Resistive RAM (RRAM), Magnetoresistive RAM (MRAM), Read-Only Memory (ROM), or similar elements. Examples of active devices or active elements include, but are not limited to, transistors, diodes, or similar elements. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, or similar elements. In some embodiments, functional circuits comprise a device stack of semiconductor devices or CFET devices as described herein.

[0053] The functional circuitry is electrically coupled to and powered by power rails 220-224 and / or one or more power rails of the front-end power delivery network. In some embodiments, the front-end power delivery network and associated power tap structures are omitted, and the functional circuitry of the IC device is coupled only to the power delivery network 210 on the back side of the IC device and receives power (e.g., VDD and VSS) from it.

[0054] In some embodiments, to generate layout 200B, multiple cells, such as cells C1-C4, are placed on power transmission network 210 during a layout operation performed by an EDA tool or an Automatic Layout and Routing (APR) system. In Figure 2B, cells C1-C4 are schematically represented by their corresponding boundaries. One or more cells are placed in the layout operation along their boundaries, which are adjacent to the boundaries of one or more other cells. For example, on the X-axis, cell C1 is placed adjacent to cell C2 along a common edge 234. On the Y-axis, cell C1 is placed adjacent to cell C3 along a common edge 232. Cells are not always placed adjacently (or may be placed adjacently). For example, cell C4 is placed spaced apart from cell C2 along the X-axis. The described layout operation is an example. Other layout operations are also within the scope of the various embodiments.

[0055] Cells are placed on one or more power rails 220-224 to receive VDD and / or VSS from the underlying power rails. In some embodiments, a cell is placed above and coincides with the center lines of two power rails with corresponding boundaries. The cell height along the Y-axis corresponds to the center-to-center distance between the two power rails. For example, in Figure 2B, the boundary of cell C1 has edges 231, 232 that coincide with the center lines of power rails 222, 223. Therefore, the cell height of cell C1 is 1CH (single cell height), which is the center-to-center distance of power rails 222, 223. The functional circuitry in cell C1 is used to receive VSS from power rail 222 and VDD from power rail 223. In another example, the boundary of cell C4 has edges 241, 242 that coincide with the center lines of power rails 220, 222, so the cell height of cell C4 is 2CH (double cell height), which is the center-to-center distance of power rails 220, 222. Unit C4 is further located above power rail 221. The functional circuitry in unit C4 is used to receive VSS from power rails 220 and 222, and VDD from power rail 221. The aforementioned unit with a single unit height or double a unit height is an example. Other units with greater unit heights, such as 3CH, 4CH, or similar units, are also within the scope of the various embodiments.

[0056] Figure 3A is a schematic cross-sectional view of a circuit region of one of the IC devices 300A according to some embodiments. In some embodiments, IC device 300A corresponds to one or more of IC devices 100, 200A and layout 200B. In at least one embodiment, Figure 3A corresponds to the cross-sectional view in Figure 2B taken along the Y-axis across a cell (e.g., cell C1).

[0057] As shown in Figure 3A, IC device 300A includes a substrate 303 having a front side 304 and a back side 305 opposite to the front side 304 in the thickness direction (i.e., the Z-axis) of the substrate 303. In some embodiments, the substrate 303 comprises a semiconductor material, such as silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials. In some embodiments, the substrate 303 comprises a dielectric material, such as silicon nitride, silicon oxide, ceramic, glass, or other suitable materials. In some embodiments, the substrate 303 comprises a multilayer structure. In some embodiments, the substrate 303 is omitted or comprises an insulating layer replacing the initial semiconductor block used in the manufacturing process. In at least one embodiment, the substrate 303 corresponds to one or more substrates as shown in Figures 1A-1F.

[0058] IC device 300A further includes device stack 308, which includes a bottom semiconductor device MP and a top semiconductor device MN stacked on top of the bottom semiconductor device MP along the thickness direction (i.e., the Z-axis). In some embodiments, device stack 308 corresponds to device stack 100A and / or is manufactured by one or more processes or operations described in Figures 1B-1F. Device stack 308 is disposed on the front side 304 of substrate 303.

[0059] In the exemplary configuration shown in Figure 3A, the top semiconductor device MN is an N-type semiconductor device, and the bottom semiconductor device MP is a P-type semiconductor device, together configuring device stack 308 as a CFET device. Each of the top and bottom semiconductor devices includes a channel disposed in a corresponding active region. For example, channel 321 of the top semiconductor device MN contains semiconductor material, such as Si, in the corresponding top active region (unnumbered), and is configured as at least one N-type nanosheet. In some embodiments, channel 321 contains a plurality of N-type nanosheets spaced apart from each other and stacked in the thickness direction (two nanosheets are shown in the exemplary configuration of Figure 3A). Similarly, channel 331 of the bottom semiconductor device MP contains semiconductor material, such as Si, in the corresponding bottom active region (unnumbered) below the top active region, and is configured as at least one P-type nanosheet. In some embodiments, channel 331 contains a plurality of P-type nanosheets spaced apart from each other and stacked in the thickness direction (two nanosheets are shown in the exemplary configuration of Figure 3A). The channel materials and nanosheets described are merely examples. Other channel materials and / or channel types, such as nanowires, FinFETs, planar or similar structures, are also within the scope of the various embodiments.

[0060] Each of the top semiconductor device and the bottom semiconductor device further includes a gate. For example, the top semiconductor device MN includes a gate 325, which is a surrounding gate extending around channel 321, while the bottom semiconductor device MP includes a gate 335, which is a surrounding gate extending around channel 331. In the exemplary configuration of Figure 3A, gates 325 and 335 are electrically isolated from each other through dielectric layer 345 in the isolated gate configuration described herein. In at least one embodiment, gates 325 and 335 are electrically coupled to each other via a conductor, such as gate local interconnect (MGLI) (not shown). In some embodiments, gates 325 and 335 are metallic gates. Other gate materials, such as polysilicon, are also within the scope of the various embodiments. In some embodiments, the gate material of gate 325 and / or gate 335 replaces sacrificial material, such as silicon germanium, in the corresponding active region during manufacturing. Gates 325 and 335 and dielectric layer 345 (or MGLI) together constitute the gate structure of device stack 308. It should be noted that the cross-sectional view in Figure 3A is a combination of two cross-sectional views, namely, one cross-sectional view is along section line A-A' in Figure 3B and includes gates 325 and 335 and dielectric layer 345, and the other view is along section line B-B' in Figure 3B and includes the remaining features other than gates 325, 335 and dielectric layer 345.

[0061] Each top or bottom semiconductor device further includes a gate dielectric layer (not shown) located between the corresponding gate and channel. For example, the gate dielectric layer is located between each gate 325 and the corresponding channel 321 and extends around the channel 321. Example materials for the gate dielectric layer include high-k dielectric materials or similar materials.

[0062] Each top semiconductor device further includes a source / drain (sometimes referred to as a top source / drain) in a corresponding top active region, and each bottom semiconductor device further includes a source / drain (sometimes referred to as a bottom source / drain) in a corresponding bottom active region. For example, the top semiconductor device MN includes a source / drain 322, while the bottom semiconductor device MP includes a source / drain 332. Other sources / drains of the top semiconductor device MN and the bottom semiconductor device MP are not visible / not shown in Figure 3A. In some embodiments, the sources / drains of the semiconductor devices are coupled to corresponding channels and arranged in the same active region as the channels. For example, the source / drain 322 of the top semiconductor device MN and other sources / drains (not shown) are coupled by channel 321 and are all in the top active region containing channel 321. In another example, the source / drain 332 of the bottom semiconductor device MP and other sources / drains (not shown) are coupled by channel 331 and are all located in the bottom active region containing channel 331.

[0063] In the exemplary configuration shown in Figure 3A, the IC device 300A further includes a source / drain local interconnect (MDLI) 342 disposed between and electrically coupled to the source / drain electrodes 322 and 332. In some embodiments, the source / drain local interconnect 342 is omitted, i.e., replaced by a dielectric material to electrically isolate the source / drain electrodes 322 and 332. In at least one embodiment, source / drain local interconnects other than the source / drain local interconnect 342 are provided between and electrically coupled to the source / drain electrodes 322 and 332. An exemplary material for the source / drain local interconnects includes a metal.

[0064] IC device 300A further includes MD contacts for a top semiconductor device MN and BMD contacts for a bottom semiconductor device MP. For example, MD contact 324 (i.e., the top contact structure) is located above and electrically contacts the source / drain 322 of the top semiconductor device MN, while BMD contact 334 (i.e., the bottom contact structure) is located below and electrically contacts the source / drain 332 of the bottom semiconductor device MP. MD contacts similar to MD contact 324 (not shown) are located above and electrically contact other sources / drains of the top semiconductor device MN. BMD contacts similar to BMD contact 334 (not shown) are located below and electrically contact other sources / drains of the bottom semiconductor device MP.

[0065] IC device 300A further includes a dielectric structure 350 that contacts gates 325, 335 along surface 352. In some embodiments, dielectric structure 350 corresponds to a diced metal gate (CMG) mask, or a diced polysilicon (CPO) mask, or a similar diced gate mask used to define or set the length of one or more gates. For simplicity, CMG, CPO, and diced gate are used interchangeably here to specify such gate lengths defining the mask. IC device 300A includes another dielectric structure similar to dielectric structure 350 (not shown for simplicity), but located on the opposite side of gates 325, 335 along the Y-axis and contacting gates 325, 335 along surface 351 opposite to surface 352. The length of gates 325, 335 is defined or set by the distance along the Y-axis between dielectric structure 350 and the other dielectric structure. In the exemplary configuration of Figure 3A, dielectric structure 350 and another dielectric structure have corresponding center lines 311, 312. In some embodiments, as shown in Figure 2B, center lines 311, 312 correspond to the center lines of the respective power rails and / or the edges of a cell boundary.

[0066] IC device 300A includes a via interconnect 360 embedded in and surrounded by a dielectric structure 350. Along the thickness direction, i.e., the Z-axis, the dielectric structure 350 and the via interconnect 360 have a height H1 greater than the height H of the gate structure of the device stack 308. In at least one embodiment, the top surface (unnumbered) of the dielectric structure 350, the top surface 361 of the via interconnect 360, and the top surface (unnumbered) of the gate 325 (which is also the top surface of the gate structure of the device stack 308) are flush with each other. In at least one embodiment, the bottom surface (unnumbered) of the dielectric structure 350 and the bottom surface 362 of the via interconnect 360 are flush with each other and lower than the bottom surface (unnumbered) of the gate 335 (which is also the bottom surface of the gate structure of the device stack 308). The dielectric structure 350 and the via interconnect 360 are at the same height as the gates 325 and 335. In at least one embodiment, the dielectric structure 350 and the via interconnect 360 are at the same height as the gate structure of the device stack 308. The dielectric structure 350 electrically isolates the via interconnect 360 from the gates 325 and 335. In some embodiments, the via interconnect 360 is formed using the same CMG photomask used to form the dielectric structure 350, and is therefore referred to as a self-aligned via interconnect 360. Exemplary processes according to some embodiments are described in Figure 11A. In at least one embodiment, the via interconnect 360 may also be formed using a separate photomask other than the CMG photomask used to form the dielectric structure 350. Figure 11B illustrates exemplary processes according to some embodiments.

[0067] The via interconnect 360 extends between and electrically couples the MD contact 324 and the back power rail 391, as will be described in further detail here. For simplicity, the back power rail 391 is sometimes referred to as the power rail 391. The top of the via interconnect 360 is electrically coupled to the MD contact 324. In the exemplary configuration shown in Figure 3A, the MD contact 324 extends along the Y-axis to the top of the via interconnect 360 such that the top surface 361 of the via interconnect 360 lies along the Z-axis between the top surface 326 and the bottom surface 327 of the MD contact 324. Other configurations are also within the scope of the various embodiments. For example, in one or more embodiments, the top surface 326 of the MD contact 324 is flush with or below the top surface 361 of the via interconnect 360. The bottom portion of the via interconnect 360 is electrically coupled to the power rail 391. In some embodiments, the through-hole interconnect 360 is in direct contact with the power rail 391. For example, the bottom surface 362 of the through-hole interconnect 360 is located above and in direct contact with the top surface of the power rail 391. Other configurations are also within the scope of the various embodiments.

[0068] In the exemplary configuration shown in Figure 3A, the via interconnect 360 tapers along its thickness direction from the back-side power rail 391 toward the MD contact 324. In other words, along the Y-axis, the width of the upper surface 361 is smaller than the width of the lower surface 362. In some embodiments, the upwardly taper shape of the via interconnect 360 is achieved by etching an opening of the via interconnect 360 from the back side of the IC device 300A, as shown in Figure 8C. In some embodiments, the via interconnect 360 and / or dielectric structure 350 have a centerline that coincides with or is aligned with the centerline 311. In some embodiments, this configuration indicates that the via interconnect 360 is shared between a cell (or device stack) located to the right of the centerline 311 in Figure 3A and another cell (or device stack) located to the left of the centerline 311. In the exemplary configuration in Figure 3A, the MD contact 324 extends along the Y-axis toward the centerline 311, but does not reach the centerline 311. This configuration indicates that, in a plan view along the thickness direction (i.e., the Z-axis), the MD contact 324 overlaps with less than half of the through-hole interconnect 360. Other configurations and / or manufacturing methods of the through-hole interconnect 360 are also within the scope of the various embodiments.

[0069] In some embodiments, IC device 300A further includes at least one of a VG via (not shown) above and electrically contacting gate 325, or a BVG via (not shown) below and electrically contacting gate 335. In at least one embodiment, IC device 300A further includes at least one VD via (not shown) located above and electrically contacting another source / drain via of the top semiconductor device MN, or at least one BVD via located below and electrically contacting at least one BMD contact of the bottom semiconductor device MP. In the exemplary configuration of Figure 3A, IC device 300A includes a BVD via 374 below and electrically contacting the BMD contact 334. Specifically, the BVD via 374 extends from the back side 305 through the substrate 303 to the front side 304, where the BVD via 374 contacts the BMD contact 334.

[0070] IC device 300A further includes a front-side redistribution structure 380 and a back-side redistribution structure 390. The redistribution structure 380 is located on the front side, above the VD and VG vias, and includes multiple metal layers and via layers arranged sequentially and alternately above the VD and VG vias, as shown in Figure 1F herein. The back-side redistribution structure 390 is located on the back side and similarly includes multiple metal layers and via layers arranged sequentially and alternately below the BVD and BVG vias. Figure 3A illustrates a metal layer of the front-side redistribution structure 380, namely the M0 layer, and a metal layer of the back-side redistribution structure 390, namely the BMO layer. For simplicity, other layers and / or features of the front-side redistribution structure 380 and the back-side redistribution structure 390 are omitted. Among the metal layers of the front-side redistribution structure 380, the M0 layer is the metal layer closest to the device stack 308. In the metal layers of the backside redistribution structure 390, the BMO layer is the metal layer closest to the device stack 308.

[0071] In the exemplary configuration shown in Figure 3A, the M0 layer includes metal patterns 381-384 on the device stack 308, corresponding to M0 conductors M0_1-M0_4. In some instances, one or more metal patterns 381-384 are omitted. Conductors M0_1-M0_4 extend along the X-axis (Figure 2B) and are arranged side-by-side along the Y-axis. Specifically, conductor M0_1 is adjacent to conductor M0_2, conductor M0_2 ​​is adjacent to conductor M0_3, and conductor M0_3 is adjacent to conductor M0_4. When there are no other M0 conductors between two M0 conductors, these two M0 conductors are considered directly adjacent (or adjacent). M0 metal patterns on adjacent M0 conductors are considered adjacent. For example, metal pattern 381 is adjacent to metal pattern 382 along the Y-axis. Along the Y-axis, the width of metal pattern 381 on conductor M0_1 is greater than the width of each metal pattern 382-384 on conductors M0_2-M0_4.

[0072] Metal pattern 381 extends across centerline 311 and is shared with another device stack (not shown) to the left of device stack 308 in Figure 3A. In some embodiments, metal pattern 381 has a centerline that coincides with or is aligned with centerline 311. In some embodiments, metal pattern 381 includes a power rail similar to one or more power rails described in Figure 2B, but belonging to the front-end power delivery network. For example, metal pattern 381 is configured as a VSS power rail in one or more embodiments to provide VSS to one or more N-type top semiconductor devices in one or more device stacks of IC device 300A. In at least one embodiment, since the power supplied to the N-type top semiconductor device (e.g., top semiconductor device MN) is delivered from the back side (e.g., through via interconnect 360 as described herein), metal pattern 381 is configured for other purposes, such as for signaling. For example, in one or more embodiments, a dual-cell height (2CH) cell comprises two single-cell height (1CH) structures that are symmetrically positioned across centerline 311, one of which is the 1CH structure between centerlines 311 and 312 in FIG. 3A. In such a 2CH cell, the metal pattern 381 is shared by the two 1CH structures and constitutes the internal signal pattern of the 2CH cell.

[0073] Metal patterns 382-384 on conductors M0_2-M0_4 are arranged between center lines 311 and 312. In some embodiments, metal patterns 382-384 are used to transmit signals between device stack 308 in IC device 300A and other device stacks or CFET devices. Metal patterns 382-384 and conductors M0_2-M0_4 are sometimes referred to as M0 signal patterns and M0 signal conductors, respectively. For example, at least one of the metal patterns 382-384 is electrically coupled to the gate 325 or source / drain of the top semiconductor device MN through a corresponding VG or VD via. In some embodiments, at least one of the metal patterns 382-384 is electrically coupled to the gate 335 or the source / drain of the bottom semiconductor device MP through a via or local interconnect (not shown) extending between the M0 layer and the gate 335 or the source / drain of the bottom semiconductor device MP. The number of three MO signal conductors (i.e., more than 1 CH) described between center lines 311 and 312 is merely an example. The number of other MO signal conductors exceeding 1 CH is also within the range of various embodiments. In at least one embodiment, the MO layer has no power rails directly located on the device stack 308, that is, all metal patterns 381-384 are MO signal patterns.

[0074] In the exemplary configuration shown in Figure 3A, the BM0 layer includes metal patterns 391-393 below the device stack 308 and on the back side 305 of the substrate 303, correspondingly located on BM0 conductors BM0_1-BM0_3. Conductors BM0_1-BM0_3 extend along the X-axis and are arranged side-by-side along the Y-axis. Specifically, conductor BM0_1 is adjacent to conductor BM0_2, and conductor BM0_2 is adjacent to conductor BM0_3. When there are no other BM0 conductors between two BM0 conductors, these two BM0 conductors are considered directly adjacent (or adjacent). BM0 metal patterns on adjacent BM0 conductors are considered adjacent. For example, metal pattern 391 is adjacent to metal pattern 392 along the Y-axis. Along the Y-axis, the width of metal patterns 391 and 393 on conductors BM0_1 and BM0_3 is greater than the width of metal pattern 392 on conductor BM0_2.

[0075] Metal pattern 391 extends across centerline 311 and is shared with another device stack (not shown) to the left of device stack 308 in Figure 3A. In some embodiments, metal pattern 391 has a centerline that coincides with or is aligned with centerline 311, and / or coincides with or is aligned with the centerline of at least one of dielectric structure 350 or via interconnect 360. Metal pattern 393 extends across centerline 312 and is shared with another device stack (not shown) to the right of device stack 308 in Figure 3A. In some instances, metal pattern 393 has a centerline that coincides with or is aligned with centerline 312. Metal patterns 391 and 393 serve as back-side power rails for the back-side power transmission network described in Figure 2B. In the exemplary configuration of Figure 3A, metal pattern 391 is a VSS power rail used to provide VSS to the top semiconductor device MN and corresponds to one or more VSS power rails 220, 222, 224, while metal pattern 393 is a VDD power rail used to provide VDD to the bottom semiconductor device MP and corresponds to one or more VDD power rails 221, 223 in Figure 2B. BM0 conductors BM0_1 and BM0_3 are sometimes referred to as BM0 power conductors.

[0076] Metal patterns 392 on conductor BMO_2 are arranged between center lines 311 and 312. In some embodiments, metal patterns 392 are used to transmit signals between device stack 308 in IC device 300A and other device stacks or CFET devices. Metal patterns 392 and conductor BMO_2 are generally referred to as BMO signal patterns and BMO signal conductors, respectively. For example, metal patterns 392 are electrically coupled to the gate 335 or source / drain of the bottom semiconductor device MP through corresponding BVG or BVD vias. In some embodiments, metal patterns 392 are electrically coupled to the gate 325 or the source / drain of the top semiconductor device MN through vias or partial interconnects (not shown) extending between the BMO layer and the gate 325 or the source / drain of the top semiconductor device MN. The described number of BMO signal conductors between center lines 311 and 312 (i.e., more than 1 CH) is only an example. The number of other BMO signal conductors exceeding 1 CH is also within the range of various embodiments. In some embodiments, the metal pattern 392 and / or the wire BMO_2 are omitted.

[0077] In the exemplary configuration of Figure 3A, the metal pattern 393, referred to herein as power rail 393, is in electrical contact with the BVD via 374. Therefore, VDD on the power rail 393 is supplied to the source / drain 332 of the bottom semiconductor device MP through the BVD via 374 and the BMD contact 334. In some embodiments, the BVD path 374 is omitted, for example, when the bottom semiconductor device MP is not directly powered by VDD.

[0078] Metal pattern 391, referred to herein as power rail 391, is electrically contacted with via interconnect 360, which in turn is electrically contacted with MD contact 324. Therefore, the VSS on power rail 391 is provided to the source / drain 322 of the top semiconductor device MN through the electrical connection including via interconnect 360 and MD contact 324. The top semiconductor device MN receives power (i.e., VSS) from the back-side power delivery network rather than the front-side power delivery network. The entire electrical connection from power rail 391 to source / drain 322, i.e., via interconnect 360 and MD contact 324, is located below layer M0, that is, below the metal layer of the front redistribution structure 380. In the exemplary configuration in FIG3A, in a plan view along the Z-axis, power rail 391 completely overlaps with at least one of via interconnect 360 or metal pattern 381.

[0079] As described herein, since the top semiconductor device MN receives power (e.g., VSS) from the back-side power delivery network through via interconnect 360, it is no longer necessary to supply power (e.g., VSS) to the top semiconductor device MN from the front-side power delivery network, i.e., from one or more metal layers of the front-side redistribution structure 380. In some embodiments, the IC device 300A may be configured without a front-side power delivery network. In at least one embodiment, the MO layer in the IC device 300A is configured without power rails directly above the via interconnect 360, i.e., the metal pattern 381 is not a power rail. Since a front-side power delivery network for powering the top semiconductor device is not required in one or more embodiments, a power tap structure for transmitting power from the back-side power delivery network to the front-side power delivery network is also not required. In at least one embodiment, the IC device 300A does not have a power tap structure. Therefore, in one or more embodiments, IC design and / or manufacturing can be simplified, freeing up front-side metal layers for purposes other than power delivery, while saving wafer area that would otherwise be configured as a power tap area.

[0080] In some embodiments, one or more circuit regions of the IC device 300A still require a front-end power delivery network for design and / or operational reasons. In these embodiments, the IC device 300A includes one or more power tap structures. However, compared to other methods where the top semiconductor device of a CFET device is powered by a front-end power delivery network, the number of required power tap structures and / or power tap regions is still reduced. Additionally or alternatively, in one or more embodiments, it is possible to ensure that the voltage drop (or IR drop) in the power delivery structure of the IC device 300A is within a predetermined or acceptable range. One or more further advantages are possible in the various embodiments, as described herein.

[0081] In at least one embodiment, forming via interconnects (e.g., via interconnect 360) does not increase the number of photomasks required for the MOL process compared to other methods. For example, other methods form vertical local interconnect (VLI) structures for electrical connections from the back to the front of the IC device. In one example, such a vertical local interconnect structure is an intra-cell structure, e.g., confined within the boundary of a cell and / or not configured to be shared with another cell. In some cases, forming a VLI structure requires at least one photomask, i.e., a VLI photomask and / or a cut-VLI (CVLI) photomask. In at least one embodiment, the formation of the VLI structure in other methods is omitted, thereby saving at least one photomask. In one or more embodiments, via interconnects are formed, such as via interconnect 360, instead of VLI structures. As described herein, when the via interconnect is a power via according to some embodiments, an additional photomask is required, therefore the number of photomasks used in the MOL process is the same as other methods. However, when the via interconnect is a power wall according to some embodiments, no additional photomask is required, thereby reducing the number of photomasks used for the MOL process by one compared to other methods.

[0082] In some embodiments, one or more photomasks used in the MOL process are EUV photomasks. In at least one embodiment, the EUV photomask is a reflective photomask, which is more expensive and / or more complex to manufacture than a transmissive photomask. Therefore, the through-hole interconnects formed according to some embodiments reduce or at least do not increase the number of EUV photomasks required for the MOL process, offering various advantages in terms of manufacturing cost, time, materials, complexity, or similar aspects.

[0083] In some embodiments, the formation of the via interconnect 360 includes etching an opening for the via interconnect 360 from the back side of the IC device 300A toward the MD contact 324. The formation of such an opening sometimes involves the risk of MD misalignment, i.e., the etched opening misses or does not adequately expose the MD contact 324. In at least one embodiment, the risk of MD misalignment can be significantly reduced or eliminated by reducing the aspect ratio of the opening (or the via interconnect 360). In some embodiments, the aspect ratio can be reduced by increasing the cross-sectional area of ​​the opening or reducing the height (or depth) of the opening. In the exemplary configuration of Figure 3A, the former is employed, i.e., the aspect ratio is reduced by increasing the cross-sectional area of ​​the opening. In at least one embodiment, the cross-sectional area of ​​the opening (or via interconnect 360) can be wider than, for example, when the opening is confined within a cell or locally formed for a single device stack, by arranging the opening (or via interconnect 360) on the boundary of a cell or in the space between two adjacent device stacks. Therefore, in one or more embodiments, the risk of MD misalignment can be significantly reduced or eliminated.

[0084] The described configuration for powering an N-type top semiconductor device in a device stack is merely an example. Other configurations are also within the scope of the various embodiments. For example, in some embodiments where device stack 308 includes a P-type top semiconductor device on top of an N-type bottom semiconductor device, power rails 391, 393 are respectively configured as VDD power rail and VSS power rail, and VDD is provided from power rail 391 to the P-type top semiconductor device via an electrical connection including a via interconnect 360. One or more advantages described herein regarding a device stack or CFET device including an N-type top semiconductor device on top of a P-type bottom semiconductor device can also be implemented in a device stack or CFET device including a P-type top semiconductor device on top of an N-type bottom semiconductor device.

[0085] Figure 3B is a schematic diagram of a circuit region layout 300B of an IC device according to some embodiments. In some embodiments, layout 300B corresponds to one or more circuit regions of IC devices 100, 200A, and 300A, and / or a region or a unit of layout 200B. In at least one embodiment, layout 300B is stored on a non-transitory computer-readable recording medium. Corresponding elements in Figures 3A and 3B are designated with the same reference numerals.

[0086] In Figure 3B, the circuit region represented by layout 300B is a cell containing a device stack or CFET device having an NMOS transistor N1 and a PMOS transistor P1. In some embodiments, transistor N1 is coupled to transistor P1 to configure an inverter, and the cell represented by layout 300B is an inverter cell. In the exemplary configuration in Figure 3B, transistor N1 is a top semiconductor device located on transistor P1, while transistor P1 is a bottom semiconductor device.

[0087] Layout 300B includes an upper layer 301 and a lower layer 302. Layout 300B further includes a boundary 310 (i.e., a cell boundary). In some embodiments, boundary 310 corresponds to the boundary of one or more cells C1-C4 as described in Figure 2B. Boundary 310 includes edges 311, 312, 313, and 314. Edges 311 and 312 extend along the X-axis, while edges 313 and 314 extend along the Y-axis. In some embodiments, the X-axis is an example of one of a first direction and a second direction, while the Y-axis is an example of the other of the first and second directions. Edges 311, 312, 313, and 314 are joined together to form a closed boundary 310. In the placement and routing operation described herein (also known as "Automatic Placement and Routing (APR)"), cells in the IC layout are placed adjacent to each other at their respective boundaries. The rectangular shape of boundary 310 is merely an example. Other boundary shapes for various cells are also within the scope of the various embodiments. The cell represented by layout 300B has a cell height of 1 CH.

[0088] Upper layer 301 includes a top semiconductor device, such as transistor N1, corresponding to a CFET device. Upper layer 301 includes an NMOS active region OD_1 and a functional gate region N1, schematically shown along its centerline and, for simplicity, referred to by the same reference numerals as the corresponding transistor N1. Upper layer 301 further includes MD contacts MD_0, MD_1, CMG regions CMG_1, CMG_2 of the CMG photomask, and via interconnects PV. In some embodiments, layout 300B further includes one or more M0 metal patterns (not shown) along one or more tracks M0_1-M0_4. Edges 311, 312 of boundary 310 correspondingly coincide with the centerlines of regions CMG_1, CMG_2. In some embodiments, layout 300B further includes dummy gate regions (not shown) correspondingly located on edges 313, 314 of boundary 310.

[0089] The lower layer 302 includes the bottom semiconductor device of the corresponding CFET device, such as transistor P1. Boundary 310, regions CMG_1, CMG_2, and via interconnect PV are shared by the upper layer 301 and the lower layer 302. The lower layer 302 further includes a PMOS active region OD_2 and a functional gate region P1, schematically indicated by their centerline and the same reference numerals as the corresponding transistor P1 for simplicity. Gate region N1 is aligned with gate region P1 and shares the same centerline. The lower layer 302 further includes BMD contacts BMD_0, BMD_1, BVD via BVDR, and VSS and VDD power rails (not shown) correspondingly located on conductors BMO_1 and BMO_3. In some embodiments, layout 300B further includes one or more BMO metal patterns (not shown) along conductor BMO_2.

[0090] The configuration of layout 300B described is merely an example. In some embodiments, the layout of the IC device includes multiple gate regions extending along an active region extending along the X-axis and across an active region along a Y-axis. Each active region and each gate region is configured with a corresponding CFET device, resulting in multiple CFET devices or a device stack. The active region includes a top active region (e.g., active region OD_1) for a top semiconductor device of the CFET device, and a bottom active region (e.g., active region OD_2) for a bottom semiconductor device of the CFET device. As shown in Figure 3B, the gate regions are arranged along the X-axis at a regular spacing designated as CPP (contact polycrystalline pitch). CPP is the center-to-center distance along the X-axis between two directly adjacent gate regions. Two gate regions are considered directly adjacent (or adjacent) when there are no other gate regions between them. CFET devices corresponding to adjacent gate regions are considered adjacent CFET devices. Some gate regions in the layout are functional gate regions that, together with the active regions, configure semiconductor devices or transistors to couple into a circuit to perform a predetermined operation or function. Examples of functional gate regions include the gate regions N1 and P1 described herein. Some other gate regions in the layout are non-functional gate regions, or dummy gate regions. Dummy gate regions are not configured to form transistors together with active regions, and / or one or more transistors formed by dummy gate regions together with active regions are not electrically coupled to other circuitry. In at least one embodiment, the non-functional gate or dummy gate corresponding to the dummy gate region comprises dielectric material in the manufactured IC device. Examples of dummy gate regions are gate regions arranged along edges 313 and 314 of boundary 310.

[0091] The length of each gate region is defined or configured by a pair of CMG regions of the CMG mask. For example, the length of each gate region N1, P1 along the Y-axis is defined by and lies between regions CMG_1 and CMG_2, which correspond to dielectric structure 350 as shown in Figure 3A and another dielectric structure. Dielectric structure 350 and similar dielectric structures described in Figure 3A are sometimes referred to as gate length-defined dielectric structures, in which one or more via interconnects similar to via interconnects 360 are embedded.

[0092] In some embodiments, each of regions CMG_1, CMG_2, and their corresponding dielectric structures has a fixed width along the Y-axis over the entire length of the CMG region or dielectric structure along the X-axis. Regions CMG_1 and CMG_2 have corresponding centerlines 311 and 312 spaced 1 cm apart along the Y-axis. In some embodiments, gate regions in a layout have different lengths. For example, in regions where no CMG regions are shown (not illustrated), one or more gate regions extend beyond their corresponding centerlines (e.g., 311 or 312).

[0093] In one layout, source / drain contacts (e.g., MD and BMD contacts) and gate regions are arranged alternately along the X-axis. Examples of MD and BMD contacts include contacts MD_0, MD_1, BMD_0, and BMD_1. Each MD contact overlaps a corresponding BMD contact. For example, contact MD_0 overlaps contact BMD_0, and contact MD_1 overlaps contact BMD_1. If there are no other MD contacts (or BMD contacts) between two MD contacts (or BMD contacts) along the X-axis, they are considered directly adjacent (or immediately adjacent). The spacing between directly adjacent MD contacts (or BMD contacts), i.e., the center-to-center distance along the X-axis, is the same as the spacing CPP between directly adjacent gate regions. Similar to the gate regions, MD and BMD contacts extend along the Y-axis.

[0094] In at least one embodiment where transistor N1 and transistor P1 are coupled to form an inverter, the gate regions N1 and P1 are electrically coupled to each other, for example, through an MGLI interconnect (not shown). To configure the inverter, layout 300B further includes an MDLI interconnect (not shown) that overlaps and electrically couples the source / drain regions in the active region OD_1 below contact MD_1 with the source / drain regions in the active region OD_2 above contact BMD_1.

[0095] In at least one embodiment, as described herein, the cross-sectional view in Figure 3A is a combination of two cross-sectional views: one view along section line A-A' of the center line of gate region G1, and another view along section line B-B' of the center lines of contact points MD_0 and BMD_0 in Figure 3B. For example, the source / drain in the active region OD_1 below contact point MD_0 corresponds to source / drain 322, while the source / drain in the active region OD_2 above contact point BMD_0 corresponds to source / drain 332. Gate region N1 corresponds to gate 325, and gate region P1 corresponds to gate 335. Contact MD_0 corresponds to MD contact 324, and contact BMD_0 corresponds to BMD contact 334. Region CMG_1 corresponds to dielectric structure 350, and via interconnect PV corresponds to via interconnect 360. Via BVDR corresponds to BVD via 374.

[0096] In Figure 3B, the VDD power rail on conductor BM0_3 extends along the X-axis and overlaps with via BVDR and contact point BMD_0, while contact point BMD_0 overlaps with the source / drain of transistor P1 in active region OD_2. Therefore, the VDD power rail on conductor BM0_3 is electrically coupled to the source / drain of transistor P1 through via BVDR and contact point BMD_0. The VSS power rail on conductor BM0_1 extends along the X-axis and overlaps with via interconnect PV and contact point MD_0, while contact point MD_0 overlaps with the source / drain of transistor N1 in active region OD_1. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 through via PV and contact point MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PV in the manner described herein. In some embodiments, the VSS power rail on conductor BM0_1 overlaps the entire via interconnect PV. According to some embodiments, one or more advantages described herein can be achieved by layout 300B and / or IC devices manufactured with respect to layout 300B.

[0097] Figure 4A is a schematic cross-sectional view of the circuit region of IC device 400A according to some embodiments. In some embodiments, IC device 400A corresponds to one or more of IC devices 100, 200A, 300A and layouts 200B, 300B. The cross-sectional view in Figure 4A is similar to the cross-sectional view in Figure 3A, therefore corresponding elements in Figures 3A and 4A are assigned the same reference numerals. The difference between IC device 400A and IC device 300A lies in the configuration of the via interconnects and how the via interconnects are electrically coupled to the back-side power rails.

[0098] IC device 400A includes a dielectric structure 450 corresponding to dielectric structure 350 and in contact with gates 325, 335 along surface 352. In some embodiments, dielectric structure 450 corresponds to a CMG region of a CMG mask used to define or configure the length of gates 325, 335. Similar to IC device 300A, IC device 400A includes another dielectric structure similar to dielectric structure 450 (not shown for simplicity), but located on the opposite side of gates 325, 335 along the Y-axis and in contact with gates 325, 335 along surface 351 opposite to surface 352. The length of gates 325, 335 is defined or configured by the distance along the Y-axis between dielectric structure 450 and the other dielectric structure. In the exemplary configuration in Figure 4A, dielectric structure 450 and the other dielectric structure have corresponding centerlines 311, 312.

[0099] IC device 400A further includes a via interconnect 460 corresponding to via interconnect 360. The via interconnect 460 is embedded in and surrounded by a dielectric structure 450. The dielectric structure 450 electrically isolates the via interconnect 460 from gates 325 and 335. In at least one embodiment, the top surface (unnumbered) of the dielectric structure 450, the top surface 461 of the via interconnect 460, and the top surface (unnumbered) of the gate 325 (which is also the top surface of the gate structure of the device stack 308) are flush with each other. In at least one embodiment, the bottom surface (unnumbered) of the dielectric structure 450 and the bottom surface 462 of the via interconnect 460 are flush with each other, and also flush with the bottom surface (unnumbered) of the gate 335 (which is also the bottom surface of the gate structure of the device stack 308).

[0100] Compared to dielectric structure 350 and via interconnect 360, dielectric structure 450 and via interconnect 460 have a lower height. In the exemplary configuration of Figure 4A, along the thickness direction, i.e., the Z-axis, dielectric structure 450 and via interconnect 460 have the same height H as the gate structure of device stack 308, which is less than the height H1 of dielectric structure 350 and via interconnect 360. In at least one embodiment, the entire gate 325 and / or the entire gate 335 are at the same height as dielectric structure 450 and / or via interconnect 460.

[0101] Furthermore, compared to the via interconnect 360 which tapers along the Z-axis from the back power rail 391 toward the MD contact 324, the via interconnect 460 tapers along the Z-axis in the opposite direction from the MD contact 324 toward the back power rail 391. In other words, along the Y-axis, the width of the upper surface 461 of the via interconnect 460 is greater than the width of the lower surface 462 of the via interconnect 460. In some embodiments, as shown in Figure 9B, the downward taper shape of the via interconnect 460 is obtained by etching an opening of the via interconnect 460 from the front side of the IC device 400A. In some embodiments, the via interconnect 460 and / or dielectric structure 450 have a centerline that coincides with or is aligned with the centerline 311. In some embodiments, this configuration indicates that the via interconnect 460 is shared between a cell (or device stack) located to the right of the centerline 311 in Figure 4A and another cell (or device stack) located to the left of the centerline 311. In the exemplary configuration shown in Figure 4A, the MD contact 324 extends along the Y-axis toward the centerline 311, but does not reach the centerline 311. This configuration indicates that, in a plan view along the thickness direction, i.e., the Z-axis, the MD contact 324 overlaps with less than half of the via interconnect 460. Other configurations and / or manufacturing methods of the via interconnect 460 are also within the scope of the various embodiments.

[0102] IC device 400A further includes a conductor 436, which shares the same height as the BMD contact 334 along the Z-axis and is spaced from the BMD contact 334 by a distance d0 along the Y-axis. In some embodiments, when at least a portion of a first element and at least a portion of a second element are on a plane perpendicular to the Z-axis, the first element shares the same height as the second element. In at least one embodiment, the entire conductor 436 shares the same height as the BMD contact 334. In some embodiments, the conductor 436 comprises the same material as the BMD contact 334. In some embodiments, the conductor 436 and the BMD contact 334 are formed simultaneously using the same material, in the same process, and using the same photomask (e.g., a BMD photomask using an EUV photomask in one or more embodiments). In other words, the conductor 436, like the BMD contact 334, is a bottom contact structure, except that the conductor 436 does not overlap and contacts the source / drain or active region. Furthermore, along the Z-axis, the height h1 of the BMD contact 334 is greater than the height h2 of the conductor 436. In other words, conductor 436 is thinner than BMD contact 334. In some embodiments, the bottom surface (not numbered) of conductor 436 is flush with the bottom surface (not numbered) of BMD contact 334. In at least one embodiment, the distance d0 between BMD contact 334 and conductor 436 along the Y-axis is equal to or greater than a predetermined distance to ensure that IC device 400A can be manufactured.

[0103] The top of the via interconnect 460 is electrically coupled to the MD contact 324. In the exemplary configuration shown in Figure 4A, the MD contact 324 extends along the Y-axis into the top of the via interconnect 460, such that the top surface 461 of the via interconnect 460 is positioned along the Z-axis between the top surface 326 and the bottom surface 327 of the MD contact 324. Other configurations are also within the scope of the various embodiments. The bottom portion of the via interconnect 460 is electrically coupled to the conductor 436. In the exemplary configuration shown in Figure 4A, the bottom surface 462 of the via interconnect 460 is above and in contact with the top surface of the conductor 436. Other configurations are also within the scope of the various embodiments.

[0104] IC device 400A further includes a via 476 below and electrically in contact with conductor 436. Specifically, via 476 extends from rear side 305 through substrate 303 to front side 304, and contacts conductor 436 on front side 304. In some embodiments, via 476 comprises the same material as BVD via 374. In some embodiments, via 476 and BVD via 374 are formed simultaneously in the same process using the same photomask (e.g., BVD photomask) and the same material. In other words, via 476 is a BVD via similar to BVD via 374, except that via 476 contacts conductor 436 rather than BMD contacts on the source / drain or active region. In some embodiments, the height h3 of the BVD through hole 476 is the same as the height h3 of the BVD through hole 374, and / or the maximum dimension d3 of the BVD through hole 476 in the XY plane is the same as the maximum dimension d3 of the BVD through hole 374 in the XY plane.

[0105] Power rail 391 is electrically contacted with BVD via 476 and electrically coupled to via interconnect 460 through BVD via 476 and conductor 436. Therefore, the VSS on power rail 391 is provided to the source / drain 322 of the top semiconductor device MN through an electrical connection including BVD via 476, conductor 436, via interconnect 460, and MD contact 324. The top semiconductor device MN receives power (i.e., VSS) from the back-side power delivery network rather than the front-side power delivery network. The entire electrical connection from power rail 391 to source / drain 322, i.e., BVD via 476, conductor 436, via interconnect 460, and MD contact 324, is below layer M0, i.e., below the metal layer of the front redistribution structure 380. In the exemplary configuration shown in Figure 4A, the power rail 391 overlaps along the Z-axis with an integral portion of at least one of the following: BVD via 476, conductor 436, via interconnect 460, or metal pattern 381.

[0106] In at least one embodiment, the formation of via interconnects (e.g., via interconnect 460) and corresponding features (e.g., conductor 436 and BVD via 476) does not increase the number of photomasks required for the MOL process compared to other methods. One reason is that conductor 436 can be fabricated using the same photomask as the BMD contact, while BVD via 476 can be fabricated using the same photomask as other BVD vias. Furthermore, in at least one embodiment, the formation of the VLI structure in other methods is omitted, thus saving at least one photomask. In one or more embodiments, via interconnects, such as via interconnect 460, are formed instead of VLI structures. As described herein, when the via interconnect is a power via, the number of photomasks used in the MOL process is the same as other methods, while when the via interconnect is a power wall, the number of photomasks used in the MOL process is reduced by one compared to other methods. According to some embodiments, one or more advantages described herein can be achieved by IC device 400A.

[0107] Figure 4B is a schematic diagram of a layout 400B of a circuit region of an IC device according to some embodiments. In some embodiments, layout 400B corresponds to a circuit region of one or more IC devices 100, 200A, 300A, 400A and / or a region or unit of layout 200B, 300B. In at least one embodiment, layout 400B is stored on a non-transitory computer-readable recording medium. The layout in Figure 4B is similar to the layout in Figure 3B, and corresponding elements in Figures 3B and 4B are designated with the same reference numerals. Layout 400B differs from layout 300B at a lower layer by additionally including features for electrically coupling a back-side power rail to a via interconnect.

[0108] Layout 400B includes an upper layer 301 and a lower layer 402 as in layout 300B. Compared to the lower layer 302 of layout 300B, the lower layer 402 further includes a contact portion BMD_PV and a via BVD_PV. In some embodiments, the contact portion BMD_PV belongs to the same photomask as other BMD contacts (e.g., contacts BMD_0, BMD_1), and / or the via BVD_PV belongs to the same photomask as other BVD vias (e.g., via BVDR). As can be seen from Figure 4B, the spacing between the contact portion BMD_0 and the contact portion BMD_PV along the Y-axis corresponds to the spacing d0. In some embodiments, in the layout of Figure 4B, the via BVDR has the same dimensions as the via BVD_PV. In at least one embodiment, region CMG_1 corresponds to dielectric structure 450, via interconnect PV corresponds to via interconnect 460, via BVD_PV corresponds to BVD via 476, and contact BMD_PV corresponds to conductor 436.

[0109] The VSS power rail on conductor BM0_1 extends along the X-axis and overlaps with via BVD_PV, contact BMD_PV, via interconnect PV, and contact MD_0. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 through via BVD_PV, contact BMD_PV, via interconnect PV, and contact MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PV in a manner as described herein. In some embodiments, the VSS power rail on conductor BM0_1 overlaps entirely with at least one of via BVD_PV, contact BMD_PV, or via interconnect PV. According to some embodiments, one or more advantages described herein can be achieved by IC devices manufactured with layout 400B and / or corresponding to layout 400B.

[0110] Figure 5A is a cross-sectional view of the circuit region of an IC device 500A according to some embodiments. In some embodiments, IC device 500A corresponds to one or more of IC devices 100, 200A, 300A, 400A and layouts 200B, 300B, 400B. The cross-sectional view in Figure 5A is similar to that in Figure 4A, and corresponding elements in Figures 4A and 5A are designated with the same reference numerals. The difference between IC device 500A and IC device 400A lies in how the via interconnects are electrically coupled to the back-side power rail.

[0111] Compared to IC device 400A, IC device 500A includes a back-side via 576, instead of the conductor 436 and BVD via 476 of IC device 400A. The back-side via 576 extends from the back side 305 through the substrate 303 to the front side 304 and contacts the via interconnect 460 in the front side 304. The back-side via 576 has a top surface electrically contacting the bottom surface 462 of the via interconnect 460, and a bottom surface electrically contacting the power rail 391. In some embodiments, at least one of the electrical contact between the back-side via 576 and the via interconnect 460 or the electrical contact between the back-side via 576 and the power rail 391 is an oriented contact. The back-side via 576 has an upper portion that shares the same height along the Z-axis as the lower portion of the BMD contact 334, and a lower portion that shares the same height as the BVD via 374. In at least one embodiment, the BVD through-hole 374 is at the same height as the back-side through-hole 576. The height h4 of the back-side through-hole 576 is greater than the height h3 of the BVD through-hole 374. In at least one embodiment, the maximum dimension d4 of the back-side through-hole 576 in the XY plane is greater than the maximum dimension d3 of the BVD through-hole 374 in the XY plane. In some embodiments, the back-side through-hole 576 comprises the same material as the BVD through-hole 374 and / or other BVD through-holes.

[0112] Power rail 391 is electrically contacted with back-side via 576 and electrically coupled to via interconnect 460 through back-side via 576. Therefore, the VSS on power rail 391 is provided to the source / drain 322 of the top semiconductor device MN through an electrical connection including back-side via 576, via interconnect 460, and MD contact 324. The top semiconductor device MN receives power (i.e., VSS) from the back-side power delivery network, not the front-side power delivery network. The entire electrical connection from power rail 391 to source / drain 322, i.e., back-side via 576, via interconnect 460, and MD contact 324, is located below layer M0, i.e., below the metal layer of the front redistribution structure 380. In the exemplary configuration of Figure 4A, power rail 391 overlaps the entirety of at least one of back-side via 576, via interconnect 460, or metal pattern 381 along the Z-axis.

[0113] In at least one embodiment, the back-side via 576 is formed in a separate process using a different photomask than that used to form the BVD via (e.g., BVD via 374). One reason for this is that the size and / or height of the back-side via 576 differs from that of the BVD via. In at least one embodiment, the formation of the VLI structure in other methods is omitted, thereby saving at least one photomask. In one or more embodiments, a via interconnect, such as via interconnect 460, is formed instead of a VLI structure. When the via interconnect is a power via according to some embodiments, the formation of the via interconnect (e.g., via interconnect 460) and the corresponding feature (e.g., back-side via 576) will increase the number of photomasks required for a MOL process, i.e., a separate photomask for fabricating the back-side via 576 or similar vias. When the via interconnect is a power wall according to some embodiments, the number of photomasks used in the MOL process is the same as in other methods, despite the separate photomask for fabricating the back-side via 576 or similar vias. According to some embodiments, one or more advantages described herein can be achieved by IC device 500A.

[0114] Figure 5B is a schematic diagram of a layout 500B of a circuit region of an IC device according to some embodiments. In some embodiments, layout 500B corresponds to a circuit region of one or more IC devices 100, 200A, 300A, 400A, 500A and / or a region or unit of layouts 200B, 300B, 400B. In at least one embodiment, layout 500B is stored on a non-transitory computer-readable recording medium. The layout in Figure 5B is similar to the layouts in Figures 3B and 4B, and corresponding elements in Figures 3B, 4B, and 5B are designated with the same reference numerals. Layout 500B differs from layouts 300B and 400B in that its underlying layer includes different features for electrically coupling a back-side power rail to a via interconnect.

[0115] Layout 500B includes the same upper layer 301 and lower layer 502 as layout 300B. Compared to the lower layer 302 of layout 300B, the lower layer 502 additionally includes a back-side via BVc_PV. In some embodiments, the via BVc_PV is part of or manufactured by a separate photomask different from the photomask used to form the BVD via (e.g., via BVDR). In some embodiments, the separate photomask used to form the via BVc_PV is an EUV photomask. In the exemplary configuration of Figure 5B, the size of the via BVc_PV is larger than the size of the via BVDR. For example, the width of the via BVc_PV along the X-axis is greater than the width of the via BVDR, and the height of the via BVc_PV along the Y-axis is also greater than the height of the via BVDR. In at least one embodiment, region CMG_1 corresponds to dielectric structure 450, via interconnect PV corresponds to via interconnect 460, and via BVc_PV corresponds to back-side via 576.

[0116] The VSS power rail on conductor BM0_1 extends along the X-axis and overlaps with conductor BVc_PV, via interconnect PV, and contact MD_0. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 through via BVc_PV, via interconnect PV, and contact MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PV in a manner as described herein. In some embodiments, the VSS power rail on conductor BM0_1 completely overlaps with at least one of via BVc_PV or via interconnect PV. According to some embodiments, one or more advantages described herein may be achieved by IC devices manufactured with layout 500B and / or corresponding to layout 500B.

[0117] The via interconnects (PVs) described in Figures 3B, 4B, and 5B are merely one example of power vias. Figure 7A depicts another example of a power via. In some embodiments, the power path is used for power delivery in a single cell or a single CFET device, as described in Figures 3B, 4B, and 5B. In at least one embodiment, the power via is formed using a photomask different from or independent of the CMG photomask used to form the power via embedded in the dielectric structure.

[0118] Another configuration of via interconnects includes power walls. Figures 6A, 6B, 6C, and 7B illustrate various examples of power walls. In some embodiments, power walls are used for power delivery across several cells or several CFET devices. In at least one embodiment, the power walls are formed using the same CMG photomask used to form the power walls embedded in the dielectric structure.

[0119] Figure 6A is a schematic diagram of a layout 600A of a circuit region of an IC device according to some embodiments. In some embodiments, layout 600A corresponds to one or more circuit regions of IC devices 100, 200A, 300A, 400A, 500A and / or regions or units of layouts 200B, 300B, 400B, 500B. In at least one embodiment, layout 600A is stored on a non-transitory computer-readable recording medium. The layout in Figure 6A is similar to the layouts in Figures 3B, 4B, 5B, and the corresponding elements in Figures 3B, 4B, 5B, and 6A are designated with the same reference numerals. Layout 600A differs from layout 300B in the configuration of via interconnects, i.e., layout 600A includes power walls instead of power vias as in layout 300B.

[0120] Layout 600A includes an upper layer 601 and a lower layer 602. Upper layer 601 is identical to upper layer 301 of layout 300B, except that upper layer 601 includes via interconnects PW for power walls, instead of via interconnects PV for power vias in layout 300B. Similarly, lower layer 602 is identical to lower layer 302 of layout 300B, except that via interconnects PW replace via interconnects PV in layout 300B. The cross-sectional view in Figure 3A corresponds to a combination of two cross-sectional views in Figure 6A: a view along section line A-A' of the center line of the gate region G1 in Figure 6A, and another view along section line B-B' of the center line of the contact portions MD_0 and BMD_0 in Figure 6A. A VSS power rail (not shown) on conductor BM0_1 extends along the X-axis and overlaps with the via interconnect PW and contact MD_0, while contact MD_0 overlaps with the source / drain of transistor N1 in active region OD_1. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 through via PW and contact MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PV in a manner as described herein. In some embodiments, the VSS power rail on conductor BM0_1 overlaps entirely with the via interconnect PW.

[0121] In Figure 3B, the via interconnect PV is used for a single cell within boundary 310 or for a power via of a single CFET device containing transistors N1 and P1. The via interconnect PV has a finite dimension along the X-axis, which is independent of the dimension of the corresponding region CMG_1 along the X-axis. For example, the via interconnect PV does not overlap contacts MD_1 and BMD_1 along the Y-axis. The finite or independent dimension of the via interconnect PV along the X-axis is the reason why, in one or more instances, the via interconnect PV belongs to a photomask independent of the CMG photomask containing region CMG_1. The via interconnect PV belonging to such an independent photomask is sometimes referred to as a non-self-aligned feature. In some embodiments, the independent photomask used to form the via interconnect PV is an EUV photomask.

[0122] In Figure 6A, the via interconnect PW is a power wall for several cells or several CFET devices. The via interconnect PW is longer than the via interconnect PV and overlaps with the contacts MD_1 and BMD_1 along the Y-axis. Although Figure 6A shows the via interconnect PW extending to edges 313 and 314, the via interconnect PW actually extends along the X-axis beyond at least one of edges 313 and 314 to provide power transmission to one or more cells and / or CFET devices outside the boundary 310. In some embodiments, the dimension of the via interconnect PW along the X-axis corresponds to the dimension of the region CMG_1 along the X-axis. In some embodiments, the via interconnect (e.g., via interconnect 360) corresponding to the via interconnect PW is fabricated from the same CMG mask containing the region CMG_1. Therefore, the via interconnect PW is sometimes referred to as a self-aligning feature.

[0123] Compared to via interconnects (PV), via interconnects (PW) have a longer physical length, resulting in more parasitic capacitance. However, in one or more embodiments, the formation of via interconnects (PW) does not require a separate photomask (e.g., an EUV photomask) from the CMG photomask. Therefore, manufacturing costs, time, and / or materials are reduced compared to embodiments using via interconnects (PV) for power transmission. In some embodiments, a trade-off is made between reducing parasitic capacitance (using via interconnects (PV)) and reducing manufacturing costs, time, and / or materials (using via interconnects (PW)) during the IC device design and / or manufacturing stages. According to some embodiments, one or more of the advantages described herein can be achieved through layout 600A and / or IC devices manufactured corresponding to layout 600A.

[0124] Figure 6B is a schematic diagram of a layout 600B of a circuit region of an IC device according to some embodiments. In some embodiments, layout 600B corresponds to one or more circuit regions of IC devices 100, 200A, 300A, 400A, 500A and / or regions or units of layouts 200B, 300B, 400B, 500B, 600A. In at least one embodiment, layout 600B is stored on a non-transitory computer-readable recording medium. The layout in Figure 6B is similar to the layouts in Figures 3B, 4B, 5B, 6A, and corresponding elements in Figures 3B, 4B, 5B, 6A, 6B are designated with the same reference numerals. Layout 600B differs from layout 400B in the configuration of via interconnects, i.e., layout 600B includes power walls instead of power vias as in layout 400B.

[0125] Layout 600B comprises an upper layer 601 and a lower layer 622. The lower layer 622 is identical to the lower layer 402 of layout 400B, except that the via interconnect PW replaces the via interconnect PV of layout 400B. The cross-sectional view in Figure 4A corresponds to a combination of two cross-sectional views in Figure 6B, namely, one view along the cross-sectional line A-A' of the center line of the gate region G1 in Figure 6B, and another view along the cross-sectional plane B-B' of the center line of the contact portions MD_0 and BMD_0 in Figure 6B.

[0126] A VSS power rail (not shown) on conductor BM0_1 extends along the X-axis and overlaps with via BVD_PV, contact BMD_PV, via interconnect PW, and contact MD_0. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 via via BVD_PV, contact BMD_PV, via interconnect PW, and contact MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PW in a manner as described herein. In some embodiments, the VSS power rail on conductor BM0_1 completely overlaps with at least one of via BVD_PV, contact BMD_PV, or via interconnect PW. According to some embodiments, one or more advantages described herein can be achieved by layout 600B and / or IC devices manufactured corresponding to layout 600B.

[0127] Figure 6C is a schematic diagram of a layout 600C of a circuit region of an IC device according to some embodiments. In some embodiments, layout 600C corresponds to one or more circuit regions of IC devices 100, 200A, 300A, 400A, 500A and / or regions or units of layouts 200B, 300B, 400B, 500B, 600A, 600B. In at least one embodiment, layout 600C is stored on a non-transitory computer-readable recording medium. The layout in Figure 6C is similar to the layouts in Figures 3B, 4B, 5B, 6A, 6B, and corresponding elements in Figures 3B, 4B, 5B, 6A, 6B, 6C are designated with the same reference numerals. Layout 600C differs from layout 500B in the configuration of via interconnects, i.e., layout 600C includes power walls instead of power vias as in layout 500B.

[0128] Layout 600C includes an upper layer 601 and a lower layer 642. The lower layer 642 is the same as the lower layer 502 of layout 500B, except that the via interconnect PW replaces the via interconnect PV of layout 500B. The cross-sectional view in Figure 5A corresponds to a combination of two cross-sectional views in Figure 6C, namely, one view along the cross-sectional line A-A' of the center line of the gate region G1 in Figure 6C, and another view along the cross-sectional line B-B' of the center line of the contact portions MD_0 and BMD_0 in Figure 6C.

[0129] A VSS power rail (not shown) on conductor BM0_1 extends along the X-axis and overlaps with via BVc_PV, via interconnect PW, and contact MD_0. Therefore, the VSS power rail on conductor BM0_1 is electrically coupled to the source / drain of transistor N1 through via BVc_PV, via interconnect PW, and contact MD_0. Thus, power is supplied from the back-side power delivery network to the top semiconductor device N1 via via interconnect PW in a manner as described herein. In some embodiments, the VSS power rail on conductor BM0_1 completely overlaps with at least one of via BVc_PV or via interconnect PW. According to some embodiments, one or more advantages described herein can be achieved by layout 600C and / or IC devices manufactured corresponding to layout 600C.

[0130] Figure 7A is a perspective view of the circuit region of an IC device 700A according to some embodiments. In some embodiments, IC device 700A corresponds to one or more of IC devices 100, 200A, 300A and / or layouts 200B, 300B. Corresponding elements in Figures 3A, 3B, and 7A are designated with the same reference numerals. In some embodiments, the perspective view in Figure 7A corresponds to the cross-sectional view in Figure 3A and the layout in Figure 3B, and shows power vias in the form of via interconnects 360°.

[0131] Figure 7A illustrates other source / drain electrodes of the top semiconductor device MN and the bottom semiconductor device MP, which are not visible in Figure 3A. Specifically, the top semiconductor device MN includes a source / drain 712, which, together with source / drain 322 (below the MD contact 324 in Figure 7A) and channel 321 (not shown in Figure 7A), belongs to the top active region OD_1. The bottom semiconductor device MP includes a source / drain 713, which, together with source / drain 332 (not shown in Figure 7A) and channel 331 (not shown in Figure 7A), belongs to the bottom active region OD_2. Power rail 391 is electrically contacted with via interconnect 360, which in turn is electrically contacted with MD contact 324. Figure 7A includes arrows 702, 704, and 706, which schematically illustrate the connection of VSS from power rail 391 via via interconnect 360 and MD contact 324 to source / drain 322 (not shown in Figure 7A).

[0132] In some embodiments, IC device 700A includes a conductor and a BVD via (not shown) between power rail 391 and via interconnect 360, configured similarly to the configuration described in Figure 7B and corresponding to the cross-sectional view in Figure 4A. In some embodiments, IC device 700A includes a back-side via (not shown) between power rail 391 and via interconnect 360, configured corresponding to the cross-sectional view in Figure 5A. According to some embodiments, one or more advantages described herein may be achieved through IC device 700A.

[0133] Figure 7B is a perspective view of the circuit region of an IC device 700B according to some embodiments. In some embodiments, IC device 700B corresponds to one or more of IC devices 100, 200A, 400A and / or layouts 200B, 600B. In some embodiments, the perspective view in Figure 7B corresponds to the cross-sectional view in Figure 4A and the layout in Figure 6B, and shows a power wall in the form of a through-hole interconnect 760.

[0134] IC device 700B includes a plurality of CFET devices 720, 721 arranged along the X-axis. In some embodiments, each of the CFET devices 720, 721 corresponds to device stack 100A. The CFET devices 720, 721 include corresponding gates 730, 731 extending along the Y-axis and spanning an active region including a top active region OD_1 and a bottom active region OD_2. The CFET devices 720, 721 and their corresponding gates 730, 731 are adjacent to each other along the X-axis. The active regions on opposite sides of the gate regions form the source / drain of the corresponding CFET device. IC device 700B includes an MD contact 742 located on and electrically contacting the top source / drain of CFET device 720 to the left of gate 730 (in Figure 7B), and an MD contact 744 located on and electrically contacting the top source / drain of CFET device 721 to the right of gate 731 (in Figure 7B). IC device 700B further includes a bottom source / drain 724 of CFET device 721 located below top source / drain 722, and a top source / drain 726 serving as a common top source / drain for CFET devices 720 and 721. IC device 700B further includes conductors 781, 785, BVD vias 771, 775, and a back power rail 791 for providing a power supply voltage (e.g., VSS) to the top semiconductor devices of CFET devices 720 and 721. For the sake of simplicity, several other features of IC device 700B are not shown.

[0135] The via interconnect 760 is a power wall extending along the X-axis and is used to provide power to CFET devices 720, 721. The via interconnect 760 is embedded in a gate length-defined dielectric structure (not shown) corresponding to the CMG region and is electrically isolated from gates 730, 731 through the gate length-defined dielectric structure. In some embodiments, via interconnect 760 corresponds to via interconnect 460. In some embodiments, conductors 781, 785 correspond to conductor 436 and / or are made using the same photomask as the BMD contact (not shown) of IC device 700B. In at least one embodiment, conductors 781, 785 are thinner than the BMD contact of IC device 700B. In some embodiments, BVD vias 771, 775 correspond to BVD via 476 and / or are made using the same photomask as the BVD via of IC device 700B.

[0136] MD contact 742 is electrically coupled to power rail 791 via via interconnect 760, conductor 781, and BVD via 771. MD contact 744 is electrically coupled to power rail 791 via via interconnect 760, conductor 785, and BVD via 775. In other words, via interconnect 760 is used to transmit VSS power from power rail 791 to the top semiconductor device of CFET devices 720 and 721, similar to the description of via interconnect 460 in Figure 4A.

[0137] In at least one embodiment, conductor 781 and BVD via 771 are omitted, or conductor 785 and BVD via 775 are omitted. In some embodiments, conductors 781, 785 and BVD vias 771, 775 are all omitted, and via interconnect 760 is electrically contacted with power rail 791 in a configuration similar to that shown in Figure 7A, corresponding to the cross-sectional view in Figure 3A and the layout in Figure 6A. In some embodiments, conductors 781, 785 and BVD vias 771, 775 are replaced by a back-side via (not shown) between power rail 791 and via interconnect 760, the configuration corresponding to the cross-sectional view in Figure 5A and the layout in Figure 6C. According to some embodiments, one or more advantages described herein may be achieved by IC device 700B.

[0138] Figures 8A, 8B, 8C, 8D, and 8E are schematic cross-sectional views of an IC device 800 at various stages of the manufacturing process according to some embodiments. In some embodiments, the IC device 800 corresponds to one or more of IC devices 100, 200A, 300A, and / or layouts 200B, 300B. Corresponding elements in Figures 3A-3B and 8A-8E are designated with the same reference numerals. The upper and lower sides in Figures 8A-8E correspond to the front and back sides of the IC device 800.

[0139] In Figure 8A, a device stack 810 is formed, as described in Figures 1B-1E, for example. The device stack 810 includes a gate structure 801 and source / drain electrodes 322, 332. In some embodiments, the gate structure 801 includes gates 325, 335 as described in Figure 3A. A dielectric structure 350 is formed from a CMG mask and corresponds to a CMG region of the CMG mask. In some embodiments, the CMG mask is not an EUV mask. The dielectric structure 350 contacts the gate structure 801 and defines the length of the gate structure 801 along the Y-axis. In the exemplary configuration in Figure 8A, along the Z-axis, the top surface 802 of the gate structure 801 is flush with the top surface 804 of the dielectric structure 350, while the bottom surface 803 of the gate structure 801 is above the bottom surface 805 of the dielectric structure 350. In some embodiments, the dielectric structure 350 is formed by etching an opening from the front side into a semiconductor structure containing the device stack 810, and then filling the opening with a dielectric material. This yields structure 800A.

[0140] In Figure 8B, MD contacts are formed on the top source / drain electrode of structure 800A. For example, MD contact 324 is formed on the source / drain electrode 322 and a portion of the dielectric structure 350. In some embodiments, the photomask used to form the MD contacts is an EUV photomask. This results in structure 800B.

[0141] In Figure 8C, an opening 809 is formed through the dielectric structure 350 to expose a portion of the MD contact 324. The opening 809 is etched from the back side toward the front side and has an upwardly tapering shape, as shown in Figure 8C and described in Figure 3A. In at least one embodiment, structure 800B is inverted, and the opening 809 is etched from above (i.e., from the back side now in the upper position). This inversion direction remains unchanged during the operations described in Figures 8D and 8E. This results in structure 800C.

[0142] In Figure 8D, conductive material is filled into opening 809 to obtain via interconnect 360 that is electrically in contact with MD contact 324. In at least one embodiment, opening 809 is formed by a separate photomask different from the CMG photomask used to form dielectric structure 350, and via interconnect 360 is a power via, as depicted in Figure 7A, for example. In at least one embodiment, opening 809 is formed by the CMG photomask used to form dielectric structure 350, and via interconnect 360 is a power wall, as depicted in Figure 7B, for example. Thus, structure 800D is obtained.

[0143] In Figure 8E, the BMD contact 334 is formed on the source / drain 332. In some embodiments, the photomask used to form the BMD contact is an EUV photomask. Next, a BVD via 374 is formed on the BMD contact 334. Then, a BMO layer is deposited on the BVD via 374 and patterned to form a power rail 391 electrically contacting the bottom surface 362 of the via interconnect 360, and another power rail 393 electrically contacting the BVD via 374. Thus, a structure 800E corresponding to the IC device 300A described in Figure 3A can be obtained. In at least one embodiment, one or more advantages described herein can be achieved by an IC device 800 manufactured as described in Figures 8A-8E.

[0144] Figures 9A, 9B, 9C, 9D, and 9E are schematic cross-sectional views of the IC device 900 at various stages of the manufacturing process according to some embodiments. In some embodiments, the IC device 900 corresponds to one or more of IC devices 100, 200A, 400A, and / or layouts 200B, 400B. Corresponding elements in Figures 3A-3B, 4A-4B, 8A-8E, and 9A-9E are designated with the same reference numerals. The upper and lower sides in Figures 9A-9E correspond to the front and back sides of the IC device 900.

[0145] In Figure 9A, the device stack 810 is formed as described in Figures 1B-1E. A dielectric structure 450 is formed from a CMG photomask and corresponds to a CMG region of the CMG photomask. The dielectric structure 450 contacts a gate structure 801 and defines the length of the gate structure 801 along the Y-axis. In the exemplary configuration of Figure 9A, along the Z-axis, the top surface 802 of the gate structure 801 is flush with the top surface 904 of the dielectric structure 450, and the bottom surface 803 of the gate structure 801 is flush with the bottom surface 905 of the dielectric structure 450. In some embodiments, the dielectric structure 450 is formed by etching an opening from the front side into the semiconductor structure containing the device stack 810 and then filling the opening with a dielectric material. This yields structure 900A.

[0146] In Figure 9B, an opening 909 is formed through the dielectric structure 450. The opening 909 is etched from the front side towards the back side and has a downwardly tapering shape, as shown in Figure 9B and described in Figure 4A. This yields structure 900B.

[0147] In Figure 9C, conductive material is filled into opening 909 to obtain via interconnect 460. In at least one embodiment, opening 909 is formed by a separate photomask from the CMG photomask used to form dielectric structure 450, and via interconnect 460 is a power via, as depicted in Figure 7A. In at least one embodiment, opening 909 is formed by the CMG photomask used to form dielectric structure 450, and via interconnect 460 is a power wall, as depicted in Figure 7B. Thus, structure 900C is obtained.

[0148] In Figure 9D, MD contacts are formed on the top source / drain of structure 900C. For example, MD contacts 324 are formed on the source / drain 322 and on portions of each dielectric structure 450 and via interconnect 460, making MD contacts 324 electrically contact the via interconnect 460. The resulting structure is inverted and this inverted orientation is maintained in the remaining operations described in Figures 9D and 9E. BMD contacts 334 are formed on the source / drain 332, while a conductor 436 is formed and electrically contacted on the bottom surface 462 of the via interconnect 460 using the same photomask. In some embodiments, the photomask used to form the BMD contacts and the conductor (e.g., conductor 436) is an EUV photomask. This yields structure 900D.

[0149] In Figure 9E, a BVD via 374 is formed on the BMD contact 334, and simultaneously, a BVD via 476 is formed on the conductor 436 using the same photomask and electrically contacts the conductor 436. Next, a BMO layer is deposited on the BVD vias 374 and 476 and patterned to form a power rail 391 electrically contacting the BVD via 476, and another power rail 393 electrically contacting the BVD via 374. Thus, a structure 900E corresponding to the IC device 400A described in Figure 4A is obtained. In at least one embodiment, one or more advantages described herein can be achieved by the IC device 900 manufactured as described in Figures 9A-9E.

[0150] Figures 10A and 10B are schematic cross-sectional views of the IC device 1000 at various stages of the manufacturing process according to some embodiments. In some embodiments, the IC device 1000 corresponds to one or more of IC devices 100, 200A, 500A and / or layouts 200B, 500B. Corresponding elements in Figures 3A-3B, 4A-4B, 5A-5B, 8A-8E, 9A-9E, and 10A-10B are designated with the same reference numerals. The upper and lower sides in Figures 10A and 10B correspond to the front and back sides of the IC device 1000, respectively. Operations described in detail in Figures 10A and 10B are performed in the inverted direction as described herein.

[0151] In Figure 10A, a structure similar to structure 900D can be obtained through the operations described in Figures 9A to 9D. In Figure 10A, except that conductor 436 is not formed on via interconnect 460, a structure similar to structure 900D can be obtained through the operations described in Figures 9A to 9D. Thus, structure 1000A can be obtained.

[0152] In Figure 10B, a BVD via 374 is formed on the BMD contact 334, and a back-side via 576 is formed on the bottom surface 462 of the via interconnect 460 and is electrically in contact with the bottom surface 462 of the via interconnect 460. The BVD via 374 and other BVD vias are formed by a different photomask than the one used to form the back-side via 576. In some embodiments, the photomask used to form the back-side via (e.g., back-side via 576) is an EUV photomask. In some embodiments, the BVD via is formed before the back-side via 576. In at least one embodiment, the back-side via 576 is formed before the BVD via. Subsequently, a BMO layer is deposited on the BVD via 374 and the back-side via 576, and patterned to form a power rail 391 electrically in contact with the back-side via 576, and another power rail 393 electrically in contact with the BVD via 374. Therefore, a structure 1000B corresponding to the IC device 500A described in Figure 5A can be obtained. In at least one embodiment, one or more advantages described herein can be achieved by an IC device 1000 manufactured as described in Figures 10A and 10B.

[0153] Figure 11A includes a schematic diagram of a portion of an IC manufacturing process 1100A according to some embodiments, and schematic diagrams of IC devices at various stages of the manufacturing process. In some embodiments, process 1100A is performed to manufacture one or more IC devices 100, 200A, 300A, 400A, 500A, 700A, 700B, 800, 900, 1000 and / or according to one or more layouts 200B, 300B, 400B, 500B, 600A, 600B, 600C. Process 1100A includes operations 1102, 1104, 1106, and 1108.

[0154] In operation 1102, a semiconductor structure 1120 is formed. In at least one embodiment, one or more operations as described in Figures 1B-1F are performed to obtain the semiconductor structure 1120. The semiconductor structure 1120 includes a plurality of extending, consecutive gate structures 1130, 1140, 1150, 1160, and 1170 extending across first and second active regions 1121 and 1122. As described herein, each active region 1121 and 1122 includes a bottom active region and a top active region stacked on the bottom active region. Each of the gate structures 1130, 1140, 1150, 1160, and 1170 includes a first all-around gate extending around one or more channels in the top active region and a second all-around gate extending around one or more channels in the bottom active region, as described herein.

[0155] In operation 1104, CMG openings 1181, 1182, and 1183 are formed in semiconductor structure 1120 using a CMG photomask, for example, through etching. This operation is sometimes referred to as CMG patterning. As described herein, each of the CMG openings 1181, 1182, and 1183 corresponds to a CMG region. Each CMG opening 1181, 1182, and 1183 extends through the entire thickness or height of gate structures 1130, 1140, 1150, 1160, and 1170 to cut each gate structure 1130, 1140, 1150, 1160, and 1170 into unconnected portions. For example, gate structures 1130, 1140, 1150, 1160, and 1170 are cut into corresponding gate structures 1131 and 1132, 1141 and 1142, 1151 and 1152, 1161 and 1162, and 1171 and 1172. For simplicity, gate structures 1132, 1142, 1152, 1162, and 1172, active region 1122, and the structure corresponding to CMG opening 1183 are not shown in subsequent operations.

[0156] In operation 1106, conformal deposition of dielectric material is performed to deposit dielectric material on the sidewalls of the CMG openings that will subsequently form via interconnects. In an exemplary process, a conformal deposition process, such as ALD, is performed to deposit a conformal layer 1185 of dielectric material on the sidewalls of CMG opening 1182, followed by anisotropic etching to remove the conformal layer portion except for the portion on the sidewalls of CMG opening 1182. Therefore, the central region 1186 of CMG opening 1182 remains unfilled. In other CMG openings that do not subsequently form via interconnects, dielectric material is filled to form the corresponding dielectric structure. For example, CMG opening 1181 is filled with dielectric material to obtain dielectric structure 1184.

[0157] In operation 1108, conductive material is deposited in the unfilled intermediate region 1186 of the CMG opening 1182 to obtain via interconnect 1187. In some embodiments, via interconnect 1187 corresponds to one or more via interconnects as described herein, and as described herein, a layer 1185 of dielectric material corresponds to one or more dielectric structures surrounding such via interconnects. In at least one embodiment, via interconnect 1187 corresponds to a power wall as described herein. In some embodiments, the formation of via interconnect 1187 is adapted to fabricate one or more via interconnects 360, 460 in one or more of the processes described in Figures 8A-8A, 9A-9E, 10A-10E.

[0158] In the exemplary process 1100A described herein, forming the via interconnect 1187 does not require an additional photomask. Specifically, the via interconnect 1187 is self-aligned and formed by a CMG photomask. In at least one embodiment, this is an advantage because the manufacturing process is not significantly complicated by the formation of the via interconnect. In at least one embodiment, one or more of the advantages described herein may be achieved by one or more IC devices manufactured according to process 1100A.

[0159] Figure 11B includes a schematic diagram of a portion of an IC process 1100B according to some embodiments, and schematic diagrams of IC devices at various stages of the manufacturing process. In some embodiments, process 1100B is performed to manufacture one or more IC devices 100, 200A, 300A, 400A, 500A, 700A, 700B, 800, 900, 1000 and / or in one or more layouts 200B, 300B, 400B, 500B, 600A, 600B, 600C. Elements in Figure 11B having corresponding elements in Figure 11A are designated with the same reference numerals as in Figure 11A.

[0160] Process 1100B includes operations 1102 and 1104 as described in Figure 11A, as well as operations 1110, 1112, and 1114. For simplicity, several features of operations 1102 and 1104 are not shown in Figure 11B, and the details of operation 1104 are not repeated.

[0161] In operation 1110, dielectric material is deposited in all CMG openings to form the corresponding dielectric structures. For example, dielectric material is filled into CMG openings 1181 and 1182 to obtain the corresponding dielectric structures 1184 and 1195.

[0162] In operation 1112, a via patterning process is performed to form via openings in the dielectric structure to which via interconnects will subsequently be formed. For example, an etching process is performed using an additional photomask to form via openings 1196 in the dielectric structure 1195. In some embodiments, the additional photomask or similar mask used to form via openings 1196 is an EUV photomask.

[0163] In operation 1114, conductive material is deposited in via 1196 to obtain via interconnect 1197. In some embodiments, via interconnect 1197 corresponds to one or more via interconnects described herein, and dielectric structure 1195 corresponds to one or more dielectric structures described herein surrounding such via interconnects. In at least one embodiment, via interconnect 1197 corresponds to power vias described herein. In some embodiments, the formation of via interconnect 1197 is adapted to fabricate one or more via interconnects 360, 460 in one or more of the processes described in Figures 8A-8E, 9A-9E, 10A-10B. In at least one embodiment, one or more advantages described herein may be achieved by one or more IC devices fabricated according to process 1100B.

[0164] Figure 12A is a flowchart of a method 1200A for generating a layout and manufacturing an IC device using the layout, according to some embodiments. Method 1200A is achievable, for example, using an EDA system and / or an integrated circuit (IC) manufacturing system as described herein, according to some examples. Examples of layouts for method 1200A include the layouts disclosed herein or similar layouts. Examples of IC devices manufactured according to method 1200A include one or more IC devices disclosed herein.

[0165] In operation 1202, a layout is generated that includes at least one via interconnect embedded in the dielectric structure corresponding to the cut gate region of the cut gate photomask described herein.

[0166] In operation 1204, depending on the layout, one of the following is performed: (A) one or more lithography exposures are performed, (B) one or more semiconductor photomasks are fabricated, or (C) one or more elements in one layer of an IC device are fabricated. Examples of operation 1204 are described in Figures 12B-12D.

[0167] Figure 12B is a flowchart of a method 1200B for manufacturing an IC device according to some embodiments. The flowchart of Figure 12B illustrates additional operations according to one or more embodiments, showing examples of procedures that can implement one or more of the operations 1204 of Figure 12A. Method 1200B includes operations 1220, 1222, 1224, and 1226.

[0168] In operation 1220, a dielectric structure is formed to contact the gate structure of the device stack of an integrated circuit (IC) device under manufacturing. For example, as shown in Figure 8A, a dielectric structure 350 is formed to contact the gate structure 801 of the device stack 810 of the IC device under manufacturing.

[0169] In operation 1222, an opening is etched from the back side of the IC device to expose a portion of a top contact structure that is electrically in contact with the source / drain of the top semiconductor device of the device stack. For example, as shown in Figure 8C, an opening 809 is etched from the back side of the IC device to expose a portion of a top contact structure 324 that is electrically in contact with the source / drain 322 of the top semiconductor device of the device stack 810.

[0170] In operation 1224, the opening is filled with a conductive material to obtain a via interconnect that is electrically in contact with the top contact structure. For example, as shown in Figure 8D, the opening is filled with a conductive material to obtain a via interconnect 360 that is electrically in contact with the top contact structure 324.

[0171] In operation 1226, a back-side metal layer is deposited and patterned to obtain a back-side power rail that covers and is electrically contacted with the via interconnect. For example, as shown in Figure 8E, a BMO layer is deposited and patterned to obtain a back-side power rail 391 that covers and is electrically contacted with the via interconnect 360. In at least one embodiment, one or more of the advantages described herein can be achieved by an IC device manufactured according to method 1200B.

[0172] Figure 12C is a flowchart of a method 1200C for manufacturing an IC device according to some embodiments. The flowchart of Figure 12C illustrates additional operations according to one or more embodiments, showing examples of procedures that can implement one or more of the operations 1204 of Figure 12A. Method 1200C includes operations 1240, 1242, 1244, and 1246.

[0173] In operation 1240, via interconnects are formed in a dielectric structure that contacts the gate structure of the device stack. For example, as shown in Figures 9A-9C, via interconnects are formed in a dielectric structure 450 that contacts the gate structure 801 of the device stack 810.

[0174] In operation 1242, a top contact structure is formed on the top surface of the source / drain of the top semiconductor device and the via interconnect of the device stack, and is in electrical contact with the top surface of the source / drain of the top semiconductor device and the via interconnect of the device stack. For example, as shown in Figure 9D, a top contact structure 324 is formed on the top surface of the source / drain 322 of the top semiconductor device and the via interconnect 460 of the device stack 810, and is in electrical contact with the top surface of the source / drain 322 of the top semiconductor device and the via interconnect 460 of the device stack 810.

[0175] In operation 1244, the bottom contact structure and the conductor are formed simultaneously. The bottom contact structure is formed on and electrically contacts the source / drain of the bottom semiconductor device of the device stack. The conductor forms an electrical contact with the bottom surface of the via interconnect 460. For example, as shown in Figure 9E, the bottom contact structure 334 and the conductor 436 are formed simultaneously, for example, using the same photomask to form the BMD contact portion. The bottom contact structure 334 is formed on and electrically contacts the source / drain 332 of the bottom semiconductor device of the device stack 810. The conductor 436 forms an electrical contact with the bottom surface 462 of the via interconnect 460.

[0176] In operation 1246, a back-side metal layer is deposited and patterned to obtain a back-side power rail electrically coupled to a conductor. For example, as shown in Figure 9E, a BMO layer is deposited and patterned to obtain a back-side power rail 391, which is electrically coupled to a conductor 436 through a BVD via 476. In at least one embodiment, one or more of the advantages described herein can be achieved by an IC device manufactured according to method 1200C.

[0177] Figure 12D is a flowchart of a method 1200D for manufacturing an IC device according to some embodiments. The flowchart of Figure 12D illustrates additional operations according to one or more embodiments, showing examples of procedures that can implement one or more of the operations 1204 of Figure 12A. Method 1200D includes operations 1240, 1242, 1264, and 1266.

[0178] Operations 1240 and 1242 are as described in Figure 12C.

[0179] In operation 1264, a back-side via is formed on and electrically contacts the bottom surface of the via interconnect. For example, as shown in Figure 10A, a back-side via 576 is formed on the bottom surface 462 of the via interconnect 460 and electrically contacts it.

[0180] In operation 1266, a back-side metal layer is deposited and patterned to obtain a back-side power rail that covers and is electrically contacted with the back-side via. For example, as shown in Figure 10B, a BMO layer is deposited and patterned to obtain a back-side power rail 391 that is located above and electrically contacted with the back-side via 576. In at least one embodiment, one or more of the advantages described herein can be achieved by an IC device manufactured according to method 1200D.

[0181] The described method includes several exemplary operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, replaced, ordered, and / or eliminated according to the spirit and scope of the examples disclosed herein. Embodiments combining different features and / or different embodiments are all within the scope of this disclosure, and such implementations will be apparent to those skilled in the art upon reading this disclosure.

[0182] In some embodiments, all or part of at least one of the methods discussed above is performed by at least one EDA system. In some embodiments, the EDA system can be used as part of the design room of the IC manufacturing system discussed below.

[0183] Figure 13 is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0184] In some embodiments, EDA system 1300 includes an APR system. According to one or more embodiments, the design layout method for representing wiring arrangements described herein can be implemented, for example, using EDA system 1300 in some embodiments.

[0185] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable recording medium 1304. Among other things, the recording medium 1304 is encoded (i.e., stored computer program code 1306) with computer program code 1306 (i.e., a set of executable instructions). The hardware processor 1302 executes the instructions 1306 to represent (at least part of) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0186] Processor 1302 is electrically coupled to computer-readable recording medium 1304 via bus 1308. Processor 1302 is also electrically coupled to I / O interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314, so processor 1302 and computer-readable recording medium 1304 can be connected to external components via network 1314. Processor 1302 is used to execute computer program code 1306 encoded in computer-readable recording medium 1304 to enable system 1300 to perform part or all of the processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0187] In one or more embodiments, the computer-readable recording medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable recording medium 1304 includes semiconductor or solid-state memory, magnetic tape, removable disk drive, random access memory (RAM), read-only memory (ROM), hard disk drive, and / or optical disc. In one or more embodiments using optical discs, the computer-readable recording medium 1304 includes compressed disk-read-only memory (CD-ROM), compressed disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0188] In one or more embodiments, the computer-readable recording medium 1304 stores computer program code 1306, which is used to enable the EDA system 1300 (wherein this implementation represents (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, the computer-readable recording medium 1304 also stores information that facilitates the performance of some or all of the said processes and / or methods. In one or more embodiments, the computer-readable recording medium 1304 stores a unit library 1307 including the standard units disclosed herein.

[0189] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is connected to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for communicating information and commands to processor 1302.

[0190] EDA system 1300 also includes a network interface 1312 coupled to processor 1302. Network interface 1312 allows system 1300 to communicate with network 1314, where one or more other computer systems are connected. Network interface 1312 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EDA systems 1300.

[0191] EDA system 1300 is used to receive information through I / O interface 1310. The information received through I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1302. The information is transmitted to processor 1302 via bus 1308. EDA system 1300 is also used to receive UI-related information through I / O interface 1310. This information is stored in computer-readable recording medium 1304 as user interface (UI) 1342.

[0192] In some embodiments, some or all of the processes and / or methods are implemented as standalone software applications for processor execution. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as add-ons to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by the EDA system 1300. In some embodiments, the layout including standard cells is generated using VIRTUOSO® of CADENCE DESIGN SYSTEMS, Inc. or other suitable layout generation tools.

[0193] In some implementations, these programs are implemented as functions of programs stored in non-transitory computer-readable recording media. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), and semiconductor memories (e.g., ROM, RAM, memory cards, etc.).

[0194] Figure 14 is a block diagram of an integrated circuit (IC) manufacturing system 1400 and an associated IC manufacturing process according to some embodiments. In some embodiments, depending on the layout, the manufacturing system 1400 is used to manufacture (A) one or more semiconductor photomasks or (B) at least one element in one layer of a semiconductor integrated circuit.

[0195] In Figure 14, the IC manufacturing system 1400 includes entities such as a design plant 1420, a photomask plant 1430, and an IC manufacturer / fab ("fab") 1450, which interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 1460. The entities in the IC manufacturing system 1400 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design plant 1420, photomask plant 1430, and IC fabrication plant 1450 are owned by a single large company. In some embodiments, two or more of the design plant 1420, photomask plant 1430, and IC fabrication plant 1450 coexist in a shared facility and use shared resources.

[0196] Design facility (or design team) 1420 generates IC design layout 1422. IC design layout 1422 contains various geometric patterns designed for IC device 1460. These geometric patterns correspond to patterns of metal layers, oxide layers, or semiconductor layers that constitute various elements of the IC device 1460 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1422 includes various IC features such as active regions, gates, sources and drains, metal lines or vias for interlayer interconnects, and openings for bonding pads, which are formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers on the semiconductor substrate. Design facility 1420 performs suitable design procedures to form IC design layout 1422. Design procedures include one or more of logic design, physical design, or placement and routing operations. IC design layout 1422 is presented as one or more data files containing geometric pattern information. For example, IC design layout 1422 may be represented in GDSII file format or DFII file format.

[0197] Photomask fabrication 1430 includes data preparation 1432 and photomask fabrication 1444. Photomask fabrication 1430 uses an IC design layout 1422 to fabricate one or more photomasks 1445 for fabricating layers of an IC device 1460 according to the IC design layout 1422. Photomask fabrication 1430 performs photomask data preparation 1432, in which the IC design layout 1422 is translated into a Representative Data File ("RDF"). Photomask data preparation 1432 provides the RDF to photomask fabrication 1444. Photomask fabrication 1444 includes a photomask writer. The photomask writer converts the RDF into an image on a substrate, such as photomask 1445 or semiconductor wafer 1453. The design layout 1422 is processed by photomask data preparation 1432 to conform to the specific characteristics of the photomask writer and / or the requirements of the IC fabrication plant 1450. In Figure 14, photomask data preparation 1432 and photomask fabrication 1444 are shown as separate components. In some embodiments, photomask data preparation 1432 and photomask manufacturing 1444 can be collectively referred to as photomask data preparation.

[0198] In some embodiments, mask preparation 1432 includes Optical Proximity Correction (OPC), which uses lithography techniques to compensate for image errors, such as those that may arise from diffraction, interference, or other process effects. OPC can adjust the IC design layout 1422. In some embodiments, mask preparation 1432 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0199] In some embodiments, the mask data preparation 1432 includes a Mask Rule Checker (MRC), which checks the IC design layout 1422 processed in the OPC against a set of mask building rules. These mask building rules include certain geometric and / or connectivity constraints to ensure sufficient margins, take into account the variability of semiconductor processes, etc. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, and can undo some modifications performed by the OPC to comply with the mask building rules.

[0200] In some embodiments, mask data preparation 1432 includes Lithography Process Checking (LPC), a simulation of the process performed by IC manufacturer 1450 to manufacture IC device 1460. LPC simulates this process based on IC design layout 1422 to create a simulated manufactured device, such as IC device 1460. Processing parameters in the LPC simulation may include parameters related to various stages of the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and similar factors or combinations thereof. In some embodiments, after creating the simulated manufactured device through LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC will be repeated to further refine the IC design layout 1422.

[0201] It should be understood that, for clarity, the description of the photomask data preparation 1432 above has been simplified. In some embodiments, data preparation 1432 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1422 according to manufacturing rules. Furthermore, the procedures applied to the IC design layout 1422 during data preparation 1432 can be executed in various different sequences.

[0202] Following photomask data preparation 1432 and during photomask fabrication 1444, photomask 1445 or a set of photomasks 1445 are fabricated based on a modified IC design layout 1422. In some embodiments, photomask fabrication 1444 includes performing one or more lithography exposures based on the IC design layout 1422. In some embodiments, an electron beam or multiple electron beam mechanism is used to form a pattern on photomask 1445 based on the modified IC design layout 1422. Photomask 1445 can be formed using various techniques. In some embodiments, photomask 1445 can be formed using a binary technique. In some embodiments, the photomask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensing material layer (e.g., photoresist) coated on a wafer, will be blocked by the opaque areas and penetrate the transparent areas. In one example, a binary photomask version of photomask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque areas of the binary photomask. In another example, photomask 1445 is formed using a phase-shift mask technique. In the phase-shift mask (PSM) version of photomask 1445, various features in the pattern formed on the phase-shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In several examples, the phase-shift mask can be an attenuating PSM or an alternating PSM. The photomask produced by photomask fabrication 1444 can be used in a variety of processes. For example, such photomasks are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or for other suitable processes.

[0203] IC manufacturing plant 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC manufacturing plant 1450 is a semiconductor wafer foundry. For example, there may be one manufacturing facility for front-end manufacturing (FEOL) of multiple IC products, a second manufacturing facility for back-end manufacturing (BEOL) of IC product interconnects and packaging, and a third manufacturing facility for other foundry services.

[0204] IC manufacturing plant 1450 includes manufacturing tools 1452 for performing various manufacturing operations on semiconductor wafer 1453, enabling IC device 1460 to be manufactured according to a photomask, such as photomask 1445. In various embodiments, manufacturing tools 1452 include one or more of a wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable processes discussed herein.

[0205] IC manufacturing plant 1450 uses a photomask 1445 manufactured by photomask plant 1430 to manufacture IC device 1460. Therefore, IC manufacturing plant 1450 uses IC design layout 1422 at least indirectly to manufacture IC device 1460. In some embodiments, IC manufacturing plant 1450 uses photomask 1445 to manufacture semiconductor wafer 1453 to form IC device 1460. In some embodiments, IC manufacturing includes performing one or more lithography exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1453 further includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0206] In some embodiments, the integrated circuit (IC) device includes a device stack, a top contact structure, a back power rail, and via interconnects. The device stack includes a bottom semiconductor device and a top semiconductor device stacked on the bottom semiconductor device along a certain direction. The top contact structure is located above the source / drain of the top semiconductor device and electrically contacts the source / drain. The via interconnects extend between the top contact structure and the back power rail and electrically couple the top contact structure and the back power rail. The via interconnects taper gradually from the back power rail toward the top contact structure along this direction.

[0207] In some embodiments, the integrated circuit (IC) device includes a device stack, a top contact structure, a bottom contact structure, conductors, via interconnects, and a back-side power rail. The device stack includes a bottom semiconductor device and a top semiconductor device stacked on top of the bottom semiconductor device in one direction. The top contact structure is located above and electrically contacts the source / drain of the top semiconductor device. The bottom contact structure is located below and electrically contacts the source / drain of the bottom semiconductor device. The conductor is spaced apart from and at the same height as the bottom contact structure, and is thinner than the bottom contact structure. The via interconnect extends between the top contact structure and the conductor, and electrically couples the top contact structure and the conductor. The back-side power rail is located below the conductor and electrically couples the conductor.

[0208] In some embodiments, a method includes forming via interconnects in a dielectric structure that contacts a gate structure of a device stack. The method further includes forming a top contact structure on the top surface of the source / drain of a top semiconductor device and the via interconnect of the device stack, and electrically contacting the top contact structure with the source / drain of the top semiconductor device and the top surface of the via interconnect. The method further includes forming a back-side via on the bottom surface of the via interconnect, and electrically contacting the bottom surface of the via interconnect. The method further includes depositing and patterning a back-side metal layer to obtain a back-side power rail on the back-side via and electrically contacting the back-side via.

[0209] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0210] 100A: Device Stack 10: Stacked structure 10L: Bottom Semiconductor Device 10U: Top Semiconductor Device 80U, 80L: Gate 62U, 62L: Source / Drain 26U, 26L: Nanoparticles 90: Intermediate layer 100: Integrated circuit device 100B: Structure 20:Substrate 21: Substrate section 22: Multi-layer structure 24A, 24B: First semiconductor layer 26U, 26L: Second semiconductor layer 28: Fins 32: Shallow trench isolation 34: Semiconductor layer stacking 36: Sacrificial gate dielectric layer 38: Sacrificial gate electrode layer 40: Photomask Structure 100C: Structure 26M: Second semiconductor layer 42: Sacrificial gate stack 44: Spare layer 46: Trench 100D: Structure 54: Internal spacer layer 56: Internal isolation structure 63: Lining 68: Dielectric materials 70: Contact Etching Stop Layer 72, 92: Interlayer dielectric layer 78: Gate dielectric layer 110F: Structure 94: Silicon layer 96U: Source / Drain Contact 104, 106: Dielectric layers 108, 110: Through holes 112: Structure 114: Redistribution Structure 116: Interlayer dielectric layer 117A, 117B: Through-hole layer 118A, 118B, 118C: Metal layers 130: Substrate portion 200A: IC device 202: Mega Series 204: Area 200B: Layout 210: Power transmission network 220, 221, 222, 223, 224: Power rails 231, 232: Edges 234: Shared Edge 241, 242: Edges C1, C2, C3, C4: Units 300A: IC device 380: Front Redistribution Structure 390: Dorsal redistribution structure 303:Substrate 304: Front 305: Dorsal side 334: BMD Contact Section 332: Source / Drain 331: Channel 335: Gate 345: Dielectric layer 342: Source / Drain Local Interconnect 322: Source / Drain 321: Channel 327: Bottom surface 325: Gate 351: Surface 324:MD contact part 326: Top surface 350: Dielectric structure 352: Surface 360: Through-hole interconnect 361: Top Surface 362: Bottom Surface 311: Centerline 312: Centerline 381, 382, ​​383, 384: Metallic Patterns 391, 392, 393: BM0 conductor M0: Metal layer M0_1, M0_2, M0_3, M0_4: M0 conductor BMO: Metal layer BM0_1, BM0_2, BM0_3: BM0 wires H, H1: Height 374: BVD through hole 308: Device Stacking MN: Top Semiconductor Device MP: Bottom Semiconductor Device 300B: Layout 301: Upper Level 302: Lower level 310: Boundary 313, 314: Edges MD_0, MD_1: MD contact parts CMG_1, CMG_2: CMG regions N1: NMOS transistor OD_1: Top Active Region PV: Through-hole interconnect BMD_0, BMD_1: BMD contact parts BVDR: Through Hole OD_2: Bottom Active Region P1: PMOS transistor 400A: IC device 436: Conductor 462: Bottom surface 450: Dielectric structure 461: Top surface 476: Through hole h1, h2, h3: Height d0: Spacing d3: Dimensions 400B: Layout 402: Lower Level BMD_PV: Contact area BVD_PV: Through hole 500A: IC device 576: Backside through hole h4: height d4: Dimensions 500B: Layout 502: Lower layer BVc_PV: Backside through hole 600A: Layout 601: Upper Level 602: Lower layer PW: Through-hole interconnect 600B: Layout 622: Lower level 600C: Layout 642: Lower layer 700A: IC device 702, 704, 706: Arrows 712, 713: Source / Drain 700B: IC device 720, 721: CFET device 730, 731: Gate 742, 744: MD contact section 722: Top Source / Drain 724: Bottom Source / Drain 726: Top Source / Drain 760: Through-hole interconnect 771, 775: BVD through holes 781, 785: Conductors 791: Power Rail 800: IC device 800A: Structure 801: Gate structure 802: Top surface 803: Bottom Surface 804: Top Surface 805: Bottom surface 810: Device stacking 800B, 800C: Structure 809: Opening 800D, 800E: Structure 900: IC device 900A: Structure 904: Top Surface 905: Bottom Surface 900B: Structure 909: Opening 900C, 900D, 900E: Structure 1000: IC device 1000A, 1000B: Structure 1100A: IC manufacturing process 1102, 1104, 1106, 1108: Operation 1120: Semiconductor Structure 1121: First Active Region 1122: Second Active Region 1130, 1140, 1150, 1160, 1170: Gate structure 1131, 1141, 1151, 1161, 1171: Gate structure 1181, 1182, 1183: CMG opening 1132, 1142, 1152, 1162, 1172: Gate structure 1184: Dielectric Structure 1185: Conformal Layer 1186: Middle area 1187: Through-hole interconnect 1100B: IC manufacturing process 1110, 1112, 1114: Operations 1195: Dielectric Structure 1196: Through-hole opening 1197: Through-hole interconnect 1200A: Method 1202, 1204: Operation 1200B: Method 1220, 1222, 1224, 1226: Operations 1200C: Method 1240, 1242, 1244, 1246: Operations 1200D: Method 1264, 1266: Operations 1300: Electronic Design Automation System 1302: Hardware Processor 1304: Non-transitory computer-readable recording media 1306: Computer program code 1307: Standard Unit Library 1308: Busbar 1310:I / O interface 1312: Network Interface 1314: Internet 1342: User Interface 1400: Integrated Circuit Manufacturing System 1420: Design Factory 1422: IC Design Layout 1430: Photomask Factory 1432: Data Preparation 1444: Photomask Manufacturing 1445: Light Mask 1450: IC manufacturing plant 1452: Manufacturing Tools 1453: Wafer 1460: IC device

[0211] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An integrated circuit device comprising: a device stack including: a bottom semiconductor device; and a top semiconductor device stacked on the bottom semiconductor device along a direction; a top contact structure located above and electrically contacting a source / drain of the top semiconductor device; a back power rail; and a via interconnect extending between the top contact structure and the back power rail and electrically coupling the top contact structure and the back power rail; wherein the via interconnect gradually tapers from the back power rail toward the top contact structure along the direction.

2. The integrated circuit device as claimed in claim 1, further comprising: an additional top contact structure located above and electrically contacting an additional source / drain of the top semiconductor device; wherein, The back power rail and the through-hole interconnect extend along a first direction, the top contact structure and the additional top contact structure extend along a second direction that crosses the first direction, and the additional top contact structure overlaps with the through-hole interconnect along the second direction.

3. The integrated circuit device as claimed in claim 1, further comprising: an additional device stack including: an additional bottom semiconductor device; and an additional top semiconductor device stacked on the additional bottom semiconductor device along the direction; and an additional top contact structure located above and electrically contacting a source / drain of the additional top semiconductor device; wherein, The via interconnect extends between the additional top contact structure and the back power rail and is electrically coupled to the additional top contact structure and the back power rail.

4. The integrated circuit device as claimed in claim 1, further comprising: a plurality of metal layers located on the stack of the device; wherein, The metal layer closest to the device stack is not in contact with a power rail located directly on the device stack.

5. An integrated circuit device comprising: a device stack including: a bottom semiconductor device; and a top semiconductor device stacked on the bottom semiconductor device in one direction; a top contact structure located above and electrically contacting the source / drain of the top semiconductor device; a bottom contact structure located below and electrically contacting the source / drain of the bottom semiconductor device; a conductor spaced apart from and at the same height as the bottom semiconductor device, and thinner than the bottom contact structure; a via interconnect extending between the top contact structure and the conductor and electrically coupling the top contact structure and the conductor; and a back-side power rail located below and electrically coupled to the conductor.

6. The integrated circuit device as claimed in claim 5, further comprising: an additional top contact structure located above and electrically contacting an additional source / drain of the top semiconductor device; wherein, The back power rail and the through-hole interconnect extend along a first direction, the top contact structure and the additional top contact structure extend along a second direction that crosses the first direction, and the additional top contact structure overlaps with the through-hole interconnect along the second direction.

7. The integrated circuit arrangement as claimed in claim 5, further comprising: an additional device stack including: an additional bottom semiconductor device; and an additional top semiconductor device stacked on the additional bottom semiconductor device along the direction; an additional top contact structure located above and electrically contacting a source / drain of the additional top semiconductor device; and an additional conductor spaced from and at the same height as the bottom contact structure, and thinner than the bottom contact structure; wherein, The via interconnect extends between and electrically couples the additional top contact structure and the additional conductor, and the back-side power rail is located below and electrically coupled to the additional conductor.

8. A method of manufacturing an integrated circuit device, comprising: forming a via interconnect in a dielectric structure, the dielectric structure contacting a gate structure of a device stack; forming a top contact structure on a source / drain of a top semiconductor device of the device stack and a top surface of the via interconnect, and electrically contacting the source / drain of the top semiconductor device and the top surface of the via interconnect; forming a back-side via on a bottom surface of the via interconnect, and electrically contacting the bottom surface of the via interconnect; and depositing and patterning a back-side metal layer to obtain a back-side power rail on the back-side via and electrically contacting a back-side power rail of the back-side via.

9. The manufacturing method as claimed in claim 8, wherein the step of forming the via interconnect comprises: etching an opening in a semiconductor structure, wherein the semiconductor structure includes a plurality of gate structures, the gate structures including gate structures of the device stack, the gate structures being arranged side by side along a first axis and extending along a second axis transverse to the first axis, and the opening extending along the first axis and cutting through the gate structures; depositing a dielectric material in the opening to obtain the dielectric structure; etching a via opening in the dielectric structure; and filling the via opening with a conductive material to obtain the via interconnect.

10. The manufacturing method of claim 8, wherein the step of forming the via interconnect comprises: etching an opening on a semiconductor structure, wherein the semiconductor structure includes a plurality of gate structures, the gate structures including gate structures of a device stack, the gate structures being arranged side-by-side along a first axis and extending along a second axis transverse to the first axis, and the opening extending along the first axis and cutting through the gate structures; depositing a conformal layer of dielectric material on the sidewall of the opening, leaving a middle region of the opening unfilled; and filling the middle region of the opening with a conductive material to obtain the via interconnect extending along the first axis, the via interconnect being electrically isolated from the cut-out ends of the gate structures through the dielectric material on the sidewall of the opening.

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