Wiring board and method for manufacturing wiring board

Abstract

The present invention aims to provide a wiring substrate and a method for manufacturing the wiring substrate, which enables the reliable mounting of micro-wiring components 50 within a cavity 35 and close to its sidewall. The present invention is a wiring substrate 20, which carries at least one semiconductor element 40. The wiring substrate has a core layer 60, on which wiring layers (21, 22) are disposed. The core layer has at least one through electrode 30 extending from the first surface to the second surface. Furthermore, on the surface of the core layer carrying the semiconductor element, at least one bottomed cavity 35 is formed. The inclination angle of the sidewall of the cavity, relative to the depth D1 of the cavity, is in the range of 25 degrees to 60 degrees from the bottom of the cavity to 40% of its height of the sidewall; the inclination angle θ2 of the sidewall at 40% or more of its height from the bottom of the cavity is in the range of 1.5 degrees to 5.0 degrees.

Description

Technical Field

[0001] Wiring board and method for manufacturing wiring board Prior Technology

[0002] In recent years, thanks to innovations in semiconductor technology, semiconductor packaging technology, manufacturing engineering technology, and software technology, the performance of electronic products has been rapidly advancing. Semiconductor technology achieves linewidths of less than micrometers, and with the realization of tens of millions of highly concentrated cells on a single chip, it enables diverse advancements such as high-speed operation and thermal management. However, in response to the increasing sophistication of these semiconductor components, there are times when packaging technology is not yet fully developed, and the performance of the final semiconductor product is sometimes limited by packaging technology and its electrical interconnection technology.

[0003] Ceramic or resin is commonly used as a packaging substrate material. While ceramic substrates offer high resistance and excellent insulation against direct current, their high permittivity leads to greater energy loss in alternating current fields, making them unsuitable for mounting high-performance, high-frequency semiconductor devices. Resin substrates, while capable of mounting high-frequency semiconductor devices, have limited wiring spacing, and warping due to thermal runaway makes it difficult to install high-performance semiconductor devices.

[0004] On the other hand, in recent years, the technology of applying silicon or glass to high-end packaging substrates has attracted much attention. Through-holes are formed in silicon or glass substrates, and conductive materials are attached to these through-holes to form an intermediate substrate for use between semiconductor devices and motherboards. In this way, it can become an intermediate substrate with shorter wiring length and excellent electrical characteristics between semiconductor devices and motherboards.

[0005] For example, Patent Document 1 discloses, with the aim of providing a packaging substrate having a cavity structure that can be applied to high-speed circuits and a semiconductor device containing therein, the following: "The semiconductor device 100 includes a semiconductor element section 30 containing semiconductor elements 32, 34, and 36, and a packaging substrate 20 electrically connected to the semiconductor element section. By using a glass substrate as a core in the packaging substrate 20, the semiconductor elements and the motherboard are connected more closely, transmitting electronic signals over the shortest distance. This significantly improves electrical characteristics such as signal transmission speed, and simplifies the insulating film processing steps by substantially preventing the generation of parasitic elements." [Previous Technical Documents] [Patent Literature]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2023-52130 Summary of the Invention

[0007] [The technical problem that the invention aims to solve] In Patent Document 1, in order to fix a component (cavity element) within a cavity, an arc-shaped support protrudes into the cavity space, connecting one end of the cavity portion to the other end. Furthermore, this support fixes the position of the cavity element. However, since glass substrate is a brittle material, using a support with an arc shape connecting one end to the other carries the risk of cracks or chipped corners during component fixing. Furthermore, if an arc shape connecting one end to the other is used, it becomes difficult to shorten the distance between the cavity and the through electrode of the component.

[0008] Furthermore, in the process of mounting components inside the cavity, a DAF (Die Attach Film) material formed on the mounting component by applying temperature and load is used to assemble the component. The thickness of the DAF material is generally in the range of 15~20μm. However, through the heat and load during component mounting, it has been confirmed that the DAF material has climbed to the sides and onto the surface of the mounting component. In addition, since the coefficient of linear expansion (CET) and elastic modulus of the DAF material are different from those of the insulating resin used in the wiring board, the stress applied to the mounting component during the wiring board formation is different. The following reliability issues as packaging substrates have been identified: damage to the mounting component and delamination at the interface with the mounting component. Furthermore, after the components are embedded inside the cavity, the surface of the wiring board is filled with insulating resin. However, if the insulating resin contains solid substances such as fillers, and the gap between the inner wall of the cavity and the mounted components differs greatly in the vertical direction, some fillers may become trapped between the inner wall and the mounted components, preventing the insulating resin from fully penetrating into the cavity.

[0009] Therefore, the object of the present invention is to provide a wiring board and a method for manufacturing the wiring board, which can reliably install micro wiring components in a cavity and close to its sidewall. [Technical means]

[0010] To address the aforementioned issues, one representative example of the present invention is a multilayer wiring substrate, which is equipped with at least one semiconductor element; The aforementioned wiring board has a core layer; Wiring layers are disposed on the first and second surfaces of the aforementioned core layer; The aforementioned core layer has at least one through electrode extending from the aforementioned first surface to the aforementioned second surface. Furthermore, on the surface of the aforementioned core layer where the semiconductor element is mounted, at least one bottomed cavity is formed; The aforementioned cavity houses a micro-wiring component; The inclination angle of the aforementioned cavity sidewall is: Relative to the cavity depth D1, the inclination angle θ1 from the bottom of the cavity to the sidewall at 40% of its height ranges from 25 degrees to 60 degrees; The inclination angle θ2 of the sidewall, which is more than 40% of the height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees.

[0011] Furthermore, one representative method for manufacturing a wiring board according to the present invention comprises: The process involves irradiating the predetermined portion for forming the through electrode and the predetermined portion for forming the cavity in the core layer of the wiring substrate with laser, followed by etching, to form a cavity with a roughness of Sa of 500 nm or more at the bottom of the through hole and the cavity; and The steps of configuring micro-wiring components within the aforementioned cavity. [Effects of the Invention]

[0012] According to the present invention, a wiring substrate and a method for manufacturing the wiring substrate are provided, which can reliably install micro wiring components in a cavity and close to its sidewall, and the gap between the inner wall of the cavity and the micro wiring components is not significantly different in the vertical direction. Other issues, structures, and effects not described above will be revealed through the following description of the embodiments of the invention. Simple Explanation of the Diagram

[0013] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor packaging substrate. [Figure 2A] Figure 2A is a plan view of a semiconductor packaging substrate on which a wiring substrate is mounted. [Figure 2B] Figure 2B is a plan view of a semiconductor packaging substrate on which multiple wiring substrates are mounted. [Figure 3] Figure 3 is a cross-sectional view of an example of a semiconductor packaging substrate. [Figure 4] Figure 4 is a cross-sectional view showing the structure of the core layer. [Figure 5A] Figure 5A is a diagram illustrating the shape of the bottom of the cavity. [Figure 5B] Figure 5B is a diagram illustrating the shape of the bottom of the cavity. [Figure 6] Figure 6 is a diagram illustrating the shape of the sidewall of the cavity. [Figure 7] Figure 7 is a diagram illustrating the inclination angle of the sidewall of the cavity. [Figure 8] Figure 8 is a diagram illustrating the positional relationship between the cavity and the through hole. [Figure 9] Figure 9 is a cross-sectional view illustrating the through-electrode and wiring formed in the core layer. [Figure 10] Figure 10 is a cross-sectional view of the semiconductor packaging substrate according to the second embodiment. [Figure 11] Figure 11 is a cross-sectional view illustrating the third embodiment of the cavity of mixed complex type. [Figure 12] Figure 12 is a diagram showing the steps of dissolving the core layer. [Figure 13] Figure 13 is a diagram showing the steps of laser processing in the core layer to become the starting point of through holes and cavities. [Figure 14] Figure 14 is a diagram illustrating the overlap of modified parts after laser modification and etching. [Figure 15] Figure 15 is a diagram illustrating the steps of forming through holes and cavities in the core material by etching. [Figure 16] Figure 16 is a diagram illustrating the shape of the through-hole formed in the core layer. [Figure 17] Figure 17 is a diagram illustrating the steps of forming a conductor layer through a through-hole formed in the core layer. [Figure 18] Figure 18 is a diagram illustrating the steps of mounting a fine wiring component in the cavity. [Figure 19] Figure 19 illustrates the steps of forming an insulating resin layer on the front and back surfaces of the micro-wiring components and core material. [Figure 20] Figure 20 is a diagram illustrating the wiring steps of the insulating resin layer formed on the front and back sides of the core material. [Figure 21] Figure 21 is a diagram illustrating the steps of forming the wiring layer and the terminals for connection. [Figure 22] Figure 22 is a diagram illustrating the connection steps between semiconductor devices and wiring boards. [Figure 23] Figure 23 is a diagram illustrating the filling steps of the bottom filler at the connection between the semiconductor element and the wiring substrate. [Figure 24] Figure 24 is a diagram illustrating the formation of the protective resin for semiconductor devices. [Figure 25] Figure 25 is a diagram illustrating the laser processing steps of the second embodiment. [Figure 26] Figure 26 is a diagram illustrating the etching steps of the second embodiment. [Figure 27] Figure 27 is a diagram illustrating the laser processing steps that form the starting point of the through hole in the cavity portion in a modified example of the semiconductor packaging substrate according to an embodiment of the present invention. [Figure 28] Figure 28 is a diagram illustrating the etching steps for forming through holes in the cavity portion in a modified example of the semiconductor packaging substrate according to an embodiment of the present invention. Implementation

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Furthermore, the embodiments and examples shown below are only examples of embodiments of the present invention, and the present invention is not limited to the explanations of these embodiments and examples. Furthermore, in the drawings referenced in the embodiments of the present invention, there are instances where identical or similar symbols are added to the same parts (only symbols such as A, B, etc. are added after the numbers), and repeated explanations are omitted. In addition, the descriptions of dimensions and proportions in the drawings differ from the actual proportions due to convenience of explanation or labeling, or are omitted from some components.

[0015] The positions, sizes, shapes, and extents of the constituent elements shown in the drawings may not actually represent these dimensions for ease of understanding. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and extents disclosed in the drawings.

[0016] Furthermore, in this invention, "surface" refers not only to the surface of the plate-shaped component, but also sometimes to the interface of a layer that is slightly parallel to the surface of the plate-shaped component. Additionally, "top" and "bottom" refer to the surface shown above or below in a drawing illustrating the layers contained in the plate-shaped component or plate-shaped material. Also, "top" and "bottom" are sometimes referred to as "first surface" and "second surface," respectively.

[0017] Furthermore, "side surface" refers to the face or thickness of a layer contained in a plate-like component or material. Additionally, sometimes a portion of a face and the side surface are collectively referred to as the "end." Furthermore, regarding through holes set in an object, "the side of the through hole" refers to the interface on the object that forms the through hole. Furthermore, "above" refers to the direction perpendicular to the top when a plate-like component or layer is placed horizontally. Further, regarding "above" and its opposite "below," these are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction"; regarding the horizontal direction, they are sometimes referred to as the "X-axis direction" and the "Y-axis direction."

[0018] Furthermore, the distance along the Z-axis is called "height," and the distance on the XY plane defined by the X and Y axes is called "width." Additionally, the term "thickness" is used to refer to the height of a layered object. Furthermore, "through electrode" refers to a conductive path provided for electrically connecting the first and second surfaces of a glass substrate when the glass substrate is used as part of a multilayer wiring substrate. It does not necessarily have to be a single conductive material that completely penetrates the glass substrate. As long as the conductive path from the first surface connects to the conductive path from the second surface, it is considered a through electrode. Further, the form of a through electrode can include any of the following: a filling structure where the through hole is filled with conductive material, or a conformal structure where only the sidewalls of the through hole are covered with conductive material.

[0019] Furthermore, "planar shape" and "top view" refer to the shape when a surface or layer is visually confirmed from above. Further, "sectional shape" and "sectional view" refer to the shape when a plate-like component or layer is cut in a specific direction and visually confirmed from a horizontal direction. Furthermore, "central part" refers to the central part of a part other than the periphery of a surface or layer. And "central direction" refers to the direction from the periphery of a surface or layer toward the center in the planar shape of the surface or layer.

[0020] Furthermore, when a numerical range is expressed as "3~10 ppm / ℃", it indicates a range of 3 ppm / ℃ to 10 ppm / ℃. The same applies to other numerical ranges.

[0021] Furthermore, for the average surface of a surface, the roughness Sa refers to the absolute value of the height difference between points, defined by the following mathematical formula. [Number 1] Also, A: ranges from 120 μm² to 650 μm².

[0022] Furthermore, the PV value refers to the height difference between the highest point (peak) and the lowest point (valley) on the surface. The depth of the depression is further defined by the following mathematical formula. [Number 2]

[0023] <First Implementation Method> (Semiconductor packaging substrate) First, referring to FIG1, the structure of the semiconductor packaging substrate in the first embodiment will be described. FIG1 is a cross-sectional view of the semiconductor packaging substrate placed on the motherboard 1. The semiconductor packaging substrate 100 of the embodiment of the present invention is composed of an FC-BGA substrate 10, a wiring substrate 20, and a semiconductor element 40. The wiring substrate 20 is used to connect the FC-BGA substrate and the semiconductor element 40, and a micro-wiring component 50 is mounted on the wiring substrate 20. As shown in FIG1, the semiconductor packaging substrate 100 is placed on the motherboard 1 and transmits electrical signals from the outside of the motherboard 1 to the semiconductor element 40. In addition, the micro-wiring component 50 mounted on the wiring substrate 20 can electrically connect a plurality of semiconductor elements mounted on the wiring substrate 20 to each other. As the semiconductor element 40, the CPU can be equipped with high bandwidth memory (HBM) or the like.

[0024] (Planar shape of semiconductor packaging substrate) Next, referring to Figures 2A and 2B, the planar shape of the semiconductor packaging substrate 100 on which the semiconductor element 40 and the wiring substrate 20 are mounted, viewed from above, will be described. Figure 2A is a plan view of the semiconductor packaging substrate 100 on which one wiring substrate is mounted, and Figure 2B is a plan view of the semiconductor packaging substrate 100 on which a plurality of wiring substrates are mounted. As shown in Figures 2A and 2B, at least one semiconductor element in the semiconductor packaging substrate 100 is mounted on the wiring substrate 20, and the semiconductor elements are electrically connected to each other via the wiring substrate 20. In addition, the semiconductor element 40 is connected to the motherboard 1 via the FC-BGA substrate 10 and is capable of transmitting and receiving electronic signals to the outside.

[0025] (Cross-section of a semiconductor packaging substrate) Next, referring to FIG3, the cross-sectional structure of the semiconductor packaging substrate 100 will be described. FIG3 is a cross-sectional view of the semiconductor packaging substrate. In FIG3, the wiring substrate 20 is configured as follows: a first wiring layer 21 is formed on a first surface above the core layer 60, and a second wiring layer 22 is formed on a second surface of the core layer 60. Furthermore, a semiconductor element 40 is mounted above the first wiring layer 21 via an underfill 86. In addition, a cavity 35 is formed in the core layer 60, and a micro-wiring component 50 is placed inside the cavity 35 via a DAF (die bonding film) 51. Furthermore, a through electrode 30 is formed, extending from the first surface of the core layer to the aforementioned second surface. The through electrode 30 is used to connect the first and second surfaces of the core layer 60 electrically, and the micro-wiring component 50 is used to electrically connect the wiring component of the semiconductor element 40 and is embedded in the cavity 35.

[0026] In this way, a plurality of semiconductor elements 40 can be electrically connected via the micro-wiring component 50 of the wiring substrate 20 and the first wiring layer 21 of the core layer 60. The micro-wiring component 50 is matched with the concave-convex shape of the bottom of the cavity 35 (described later) and fixed by the insulating resin 85 of the first wiring layer 21 of the core layer 60.

[0027] (Cross-section of the core layer) Next, referring to Figure 4, the structure of the core layer 60 will be explained. Figure 4 is a cross-sectional view of the portion of the core layer that forms the cavities 35 and through holes 70. In the core layer 60, a plurality of cavities 35 and through holes 70 are formed by laser irradiation and etching, which will be described later. The core layer 60 is a composite material comprising at least one of the following: quartz, alkali-free glass, alkali-containing glass, Al₂O₃, SiO₂, CaO, MgO, SrO, BaO, and ZrO₃. As a key physical property of the core layer 60, its composition ratio can be appropriately set if the linear expansion coefficient is in the range of 3~10 ppm / ℃ and the elastic modulus is above 40 GPa, ideally around 60 GPa. The thickness T1 of the core layer 60 is in the range of 100~1,800 μm, ideally in the range of 200~1,000 μm. However, the thickness T1 of the core layer 60 is not limited to the above range, and its thickness T1 can be appropriately set.

[0028] The depth D1 of the cavity 35 with a bottom structure formed in the core layer 60 is greater than or equal to the thickness T2 of the micro-wiring component 50, and at least the relationship between D1 and T2 is D1 > T2 + 5 μm. Furthermore, the relationship with the thickness T1 of the core layer 60 is T1 > D1. As long as the depth D1 of the cavity 35 is greater than or equal to D1 > T2 + 5 μm, it is acceptable to set the depth D1 of the cavity 35 appropriately.

[0029] The relationship between the width W1 and length W2 of the cavity 35 with a bottom structure formed in the core layer 60 and the w1 and w2 of the micro-wiring component 50 is w1+20μm>W1>w1+3μm, w2+20μm>W2>w2+3μm. As long as the above conditions are met, it is acceptable to set the width W1 and length W2 of the cavity 35 appropriately. If W1>w1+20μm and W2>w2+20μm, sometimes when the first wiring layer 21 is formed on the core layer 60, depressions may occur in the insulating resin 85, the reliability of wiring formation may be reduced, and the yield of the wiring substrate 20 may be significantly reduced.

[0030] (The concave and convex shape at the bottom of the cavity) Next, the irregularities formed at the bottom of cavity 35 will be explained with reference to Figures 5A and 5B. Figure 5A is a diagram illustrating the irregularities at the bottom of the cavity. As shown in Figures 5A and 5B, minute irregularities are formed at the bottom of the cavity 35 with a bottomed structure formed in the core layer 60, with an ideal roughness Sa: 500~1500 nm. The minute irregularities have a periodic structure, with the period set in the range of 5.0~25 μm. The aforementioned minute irregularities improve the adhesion to the DAF (die bonding film) used when mounting the micro-wiring component 50. When Sa: is below 500 nm, it is difficult to obtain the anchoring effect required to improve adhesion. Furthermore, if Sa is above 1500 nm, the unevenness at the bottom will increase, affecting the parallelism when mounting the micro-wiring component 50. Therefore, its roughness is Sa: 500~1000 nm, ideally within the range of 500~800 nm. As long as it maintains adhesion and the mounting ability of the micro-wiring component 50, a suitable roughness setting is acceptable. The same applies to the period of the micro-unevenness; a range of 5.0~25 μm is suitable.

[0031] Furthermore, as shown in Figure 5B, the concave-convex shape of the bottom of the cavity can also be represented by a period of 5.0~25μm and a pointed shape with a height of 0.25~10μm. The bottom of the cavity can meet the above-mentioned conditions such as Sa and the shape of the pointed tip.

[0032] (The sidewall of the cavity) Next, the irregularities of the sidewalls formed in the cavity 35 will be explained with reference to FIG6. FIG6(a) is a diagram illustrating the shape of the sidewalls of the cavity. As shown in FIG6(a), the sidewalls of the cavity 35 with a bottom structure formed in the core layer 60 have ridges in the longitudinal and transverse directions. The PV value of the ridges is 1.2 μm or more and 3.6 μm or less, and the depth of the recess is in the range of 0.5 μm or more and 4.1 μm or less. These plurality of longitudinal and transverse ridges form a plurality of slightly rectangular recesses that can be observed under an optical microscope at a magnification of 50x or higher. The intervals between the longitudinal ridges are 5 μm or more and 20 μm or less, and the intervals between the transverse ridges are 2 μm or more and 25 μm or less. In addition, Figure 6(b) is an optical microscope photograph of the upper part of the side wall of cavity 35 as viewed from above. The ridges of the sidewalls of the cavity 35 with the bottom structure and the plurality of slightly rectangular recesses have the effect of fixing the micro wiring component 50 and improving the adhesion of the insulating resin 85 used in the first wiring layer 21 formed on the core layer 60 to the core layer 60.

[0033] Generally, chemical bonding treatment is used to ensure adhesion between the core layer 60 and the insulating resin 85. However, it has been confirmed that due to the stress caused by the difference in the coefficients of linear expansion of the materials used, delamination occurs at the interface. By forming unevenness within the aforementioned range on the sidewalls of the cavity 35 with a bottom structure, an anchoring effect can be generated to ensure adhesion between the core layer 60 and the insulating resin 85, thereby ensuring the reliability of the wiring board. Figure 6(b) is an optical microscope photograph of the side wall of cavity 35 viewed from above the z-axis, which can visually confirm the formation of small bumps and depressions.

[0034] (Angle of the cavity sidewall) Next, referring to Figure 7, the inclination angle of the cavity sidewall will be explained. Figure 7 is a cross-sectional view illustrating the inclination angle of the cavity sidewall. In the wiring substrate 20 of this invention, as shown in FIG7, the inclination angle of the sidewall of the cavity 35 with a bottom structure formed on the core substrate 60 is relative to the depth D1 of the cavity. The inclination angle of the sidewall from the bottom of the cavity to 40% of its height is in the range of 25 degrees to 60 degrees, and the inclination angle of the sidewall above 40% of its height from the bottom of the cavity can be set in the range of 1.5 degrees to 5.0 degrees. Regarding the inclination angle of the sidewall of the cavity 35, as shown in FIG7, the depth D1 of the cavity can be derived from the relationship between the opening difference S1 between the upper part and the bottom of the cavity. By changing the inclination angle of the sidewall of the cavity 35 at the position of 40% of the height of the depth D1, the climb of the DAF when the micro wiring component 50 is mounted can be suppressed. By setting the tilt angle θ1 at a position 40% of the height of the cavity depth D1 to a range of 25 degrees or more and 60 degrees or less, the climb of the DAF when carrying the micro wiring component 50 can be suppressed. Furthermore, by setting the tilt angle of the position at 40% or more of the cavity depth D1 to a range of 1.5 degrees to 20 degrees, as shown in Figure 8, the distance between the cavity 35 and the through electrode 30 formed on the core substrate 60 can be set to 40 μm or more and 150 μm or less. When the tilt angle at 40% or more of the cavity depth D1 is set to 20° or more, the distance between the cavity 35 and the through electrode 30 becomes 150 μm or more. This increases the wiring length on the wiring substrate 20 and the overall wiring length of the semiconductor element 40, FC-BGA substrate 10, motherboard 1, and semiconductor packaging substrate 100, resulting in decreased transmission characteristics. Therefore, the tilt angle of the cavity sidewall is relative to the cavity depth D1. The tilt angle of the sidewall from the bottom of the cavity to 40% of its height is in the range of 25 degrees to 60 degrees, and the tilt angle of the sidewall above 40% of its height from the bottom of the cavity is in the range of 1.5 degrees to 5.0 degrees. As long as it is within the above range and the relationship θ1>θ2 can be maintained, the tilt angle of the cavity 35 sidewall can be set appropriately.

[0035] Furthermore, the method for measuring the depth D1 of the cavity 35 with a bottom structure and the tilt angle of the cavity sidewall is to cut (cut) the substrate 10A of the mother material by scribing and exposing the cross-section (cut surface) of the through hole 70, and then analyze the SEM image observed by SEM (Scanning Electron Microscope) using image analysis software. Regarding the method for measuring the tilt angle of the sidewall of the cavity 35, the distance to the bottom surface of the cavity 35 is set as D1, the distance to the first surface of the core material is divided into 10 equal parts, and the upright part of the cavity sidewall is used as a reference point to measure the tilt angle θ at various positions from 10% to 100%.

[0036] Next, referring to Figure 8, the through-hole 70 around the cavity 35 will be explained. Figure 8 is a diagram illustrating the positional relationship between the cavity 35 and the through-hole 70, and is also a plan view of the core layer from above. As shown in Figure 8, if the inclination angle of the sidewall of the cavity 35 becomes too large, a useless area will be generated on the core layer, and the distance from the micro-wiring component 50 to the through electrode 30 formed in the through-hole 70 will become longer.

[0037] (Organic resin layer) Next, referring to FIG9, the through electrode and wiring formed on the surface of the core layer will be described. FIG9 is a cross-sectional view illustrating the through electrode 30, the first wiring layer 21, and the second wiring layer 22 formed on the core layer material. As shown in FIG9, in the embodiment, the wiring substrate 20 has an organic resin layer 80 with a thickness of 100 nm or more and 10,000 nm or less formed at the interfaces of the core substrate 60 and the first wiring layer 21, the second wiring layer 22, and the through electrode 30, respectively. The organic resin layer 80 is formed to cover the microcracks that occur in the core layer 60, and has the effect of preventing the core layer 60 from breaking and the progression of microcracks. Furthermore, it ensures the adhesion between the core layer 60 and the conductor layer. The organic resin layer 80 is formed by spin coating or impregnation, for example, a resin selected from at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin. When the thickness of the organic resin layer 80 is less than 100 nm, its effect on covering microcracks in the core layer 60 and thus inhibiting their progression is relatively small. Furthermore, if the thickness is greater than 10,000 nm, the stress generated by the increased thickness becomes a problem. Therefore, the ideal thickness of the organic resin layer 80 is between 100 nm and 10,000 nm, and more ideally between 200 nm and 800 nm. The thickness of the organic resin layer 80 can be appropriately set as long as it falls within the above range.

[0038] Furthermore, the conductor layers used in the core layer 60, the first wiring layer 21, the second wiring layer 22, and the through electrode 30 can be, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc., but ideally Cu. The thickness of the wiring can be appropriately set to the desired thickness. Regarding the seed layer used to form the conductor layer, any material that can be formed in the organic resin layer 80 can be selected, for example, from Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, etc. However, Cu is ideal, and its formation method can be any appropriate process such as sputtering, electroless plating, CVD treatment, etc.

[0039] The insulating resin 85 formed on the first wiring layer 21 and the second wiring layer 22 formed on the front and back sides of the core layer 60 is, for example, a material in which silicon dioxide, titanium dioxide, aluminum oxide, magnesium oxide or zinc oxide, etc., are added as fillers to at least one resin selected from epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin and polyamide resin. The material has an elastic modulus in the range of 6 to 15 GPa and a coefficient of linear expansion in the range of 11 to 30 ppm / Deg. C. Ideally, it is a thermosetting resin. Methods for forming the insulating resin layer include spin coating, vacuum pressure bonding, hot pressing, compression molding, and transfer molding. As long as the micro-wiring component 50 can be embedded in the cavity 35 of the core layer 60 with a bottom structure, the forming method can be appropriately set. Ideally, a vacuum pressure bonding method is preferred, and ideally, a processing method that simultaneously applies heat and pressure under vacuum is selected. The processing method is not limited to one; multiple combinations of methods other than those mentioned above are acceptable.

[0040] Furthermore, as shown in Figure 3, the semiconductor element connection terminal that electrically connects the semiconductor element 40 to the wiring substrate 20 is a pillar structure, with structures such as SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, and OPS. The pillar diameter ranges from 10μm to 30μm, and the period is 20 to 50μm. The aforementioned pillar diameter and spacing are appropriately set to match the structure of the semiconductor element 40 and the connection terminal.

[0041] Furthermore, the core layer 60 used in the wiring substrate 20 is made of glass, and the SiO₂ content of the glass is in the range of 55% by mass or more and 85.0% by mass or less. When the glass composition has a SiO₂ content of less than 55% by mass, it is difficult to form the aforementioned cavity structure. Furthermore, when the SiO₂ content is 85.0% by mass or more, the difference in the coefficients of linear expansion between the core layer 60 and the first wiring layer 21 and the second wiring layer 22 increases, generating stress that causes warping of the wiring substrate 20, or delamination at the interfaces between the first wiring layer 21, the second wiring layer 22 and the core layer 60, and at the interfaces between the core layer 60 and the micro-wiring component 50. Therefore, the SiO₂ content of the core layer 60 is ideally in the range of 55% by mass or more and 85% by mass or less, and more ideally in the range of 75% by mass or more and 85% by mass or less. As long as it is within the above range, the SiO₂ content of the core layer 60 can be appropriately set.

[0042] <Second Implementation Method> Next, referring to FIG11, the second embodiment will be described. The second embodiment differs from the first embodiment in that a through electrode point is also formed in the region below where the cavity 35 is formed. In the following description, the same symbols are used for the same or equivalent components as those in the first embodiment described above, and their descriptions are simplified or omitted. In the wiring substrate of the second embodiment shown in FIG10, the diameters of the through electrode 30 formed in the core layer 60 and the cavity through electrode 31 formed below the cavity with a bottom structure are different. When the processing diameter of the through electrode 30 extending from the first surface to the second surface of the core layer 60 is Φ1 and the processing diameter of the cavity through electrode 31 formed in the cavity with a bottom structure is Φ2, then Φ1>Φ2. By having the diameter of the through electrode Φ1>Φ2, when the micro wiring component 50 arranged in the cavity 35 is electrically connected to the outside, the miniaturization of the connection terminal can be achieved. With the above, in addition to the micro wiring component 50, functional components such as semiconductor elements and capacitors can be mounted in the cavity with a bottom structure, thus enhancing the function of the wiring substrate 20, that is, enabling the multifunctional semiconductor packaging substrate 100.

[0043] <Third Implementation Method> Next, referring to FIG12, the third embodiment will be described. FIG12 is a cross-sectional view of a wiring board having cavities of various depths and through electrodes on the same substrate. The cavities and through electrodes described in the first and second embodiments are formed on the same substrate, with the longitudinal and transverse dimensions and depth of the cavities and the shape of the through electrodes being variable. The wiring substrate shown in Figure 3 has cavities with depths of 70 μm and 200 μm formed simultaneously on a glass panel with a panel size of 510 mm × 515 mm and a thickness of 0.44 mm. Figure 12(a) shows the structure in the second embodiment in which a through electrode is formed at the bottom of the cavity, and the cavity is formed to a depth of 200 μm. Furthermore, Figure 12(b) shows the cavity structure described in the first embodiment, wherein the cavity is formed with a depth of 200 μm. Furthermore, Figure 12(c) shows the cavity structure described in the first embodiment, wherein the cavity is formed with a depth of 70 μm. The depth of these cavities is achieved by locally altering the intensity of laser modification and controlling the etching conditions, allowing for the fabrication of various sizes and shapes even at depths other than those shown in Figure 12.

[0044] The through-hole shown in Figure 12(d) is an X-shaped through-hole with an opening diameter of 60 μm, which can be formed by etching from both sides of the glass substrate. The characteristic of this type of through-hole is that the opening diameter is minimized near the center of the thickness of the glass panel. Furthermore, the through electrode in Figure 12(e) and the bottom hole in Figure 12(f) are referred to as V-shaped, and the cross-section of the through hole presents a V-shape. This shape can be created by shielding one side of the glass panel and etching only from the other side. Also, when etching one side of the glass panel, it is ideal to divide the glass panel into approximately 100mm × 100mm sections before processing.

[0045] <Manufacturing Method of Wiring Board in Embodiments of the Invention> The manufacturing method of the wiring board 20 in the embodiments of the present invention will be described below using Figures 12 to 22.

[0046] (Core layer fabrication) Figure 12 illustrates the steps of etching the substrate 61, which serves as the base material for the core layer. When the core material is glass, hydrogen fluoride-based or alkaline etching is performed to adjust the glass thickness. Furthermore, the thickness T1A of the substrate 61, which forms the basis of the core layer 60, can be appropriately set according to the application after considering the thickness reduction through the etching steps used to form through-holes. For example, T1A is in the range of 200 to 1,900 μm, and the thickness reduction T1 of the substrate formed through the through-holes can be set to the range of 100 to 1,800 μm.

[0047] (The structure of a through hole and a bottomed cavity) Figure 13 shows the steps of forming the laser-modified section, which serves as the starting point for the through-hole and cavity, in the core layer 60. Figure 14 shows the structure of the laser-modified section, which serves as the starting point for the cavity 35 with a bottom structure. Figure 15 shows the steps of forming the through-hole and cavity by etching away the through-hole 70 and the cavity 35 with a bottom structure. Figure 16 illustrates the cross-sectional shape of the through-hole 70 formed by etching and the tilt angle of the conductive path.

[0048] (Laser modification) To form the through-hole 70 and the bottomed cavity 35, the substrate 61 shown in FIG12, as shown in FIG13, is laser-processed to form a laser-modified portion 75, which serves as the starting point (pre-formation portion for the through electrode and the pre-formation portion for the cavity) of the through-hole 70 and the cavity 35, followed by an etching expansion process. Regarding the laser processing, for example, when using a femtosecond laser or a picosecond laser, the ideal oscillation wavelength is any one of 1064nm, 532nm, or 355nm. Alternatively, the through-hole 70 and the bottomed cavity 35 can also be formed by CO₂ laser processing or electrical discharge machining. The bottomed cavity 35 differs from the through-hole 70 in that the height of the laser-modified portion 75 is adjusted and processed. In order to add an angle to the wall of cavity 35 in two stages, this can be achieved by using a method such as laser irradiation near the periphery of cavity 35 to achieve a shallower treatment compared to the center. Regarding the laser-processed core layer 60, it is immersed in hydrogen fluoride or a highly concentrated alkaline etching solution (such as an aqueous solution of sodium hydroxide or potassium hydroxide). The core layer 60 is then etched along the starting point of the through-hole 11, forming the through-hole 11 and the cavity 35 with a bottom structure. Furthermore, generally, etching in the XY plane is performed isotropically, and the etching speed varies according to the thickness direction (Z-axis direction) of the base substrate 61. Therefore, the cylindrical space formed in the core layer 60 after etching becomes the through-hole 70.

[0049] In the formation of the bottomed cavity 35 described above, when the laser-modified portion, which serves as the starting point of the cavity, is formed by laser processing, as shown in Figure 14, the laser-modified portion 75 is formed by overlapping etched through-holes 70. A higher overlap rate indicates a higher proportion of overlap between the through-hole 11 and adjacent through-holes. Figure 14(a) shows the case where there are two laser-modified portions, and Figure 14(b) shows the case where a plurality of laser-modified portions are formed to create a bottomed cavity. When forming the bottomed cavity 35, the laser-modified portion 75 is ideally processed with a period of 5 μm to 25 μm, and more ideally, it is in the range of 5 μm to 10 μm. By processing with the above-mentioned period, the bottom of the bottomed cavity is in the range of Sa: 500~3000 nm, and the micro-unevennesses are periodically arranged with a spacing of 5~25 μm. On the sidewall of cavity 35, ridges are formed in the longitudinal and transverse directions. The PV value of the ridges is 1.8 μm or more and 3.6 μm or less, and the depth of the recess is 0.5 μm or more and 4.1 μm or less. The interval between the longitudinal ridges is 5 μm or more and 15.5 μm or less, and the interval between the transverse ridges is 2 μm or more and 25 μm or less. The inclination angle of the sidewall of cavity 35 can be formed in the following manner: relative to the depth D1 of the cavity depth, the inclination angle of the sidewall from the bottom of the cavity to 40% of the height is in the range of 25 degrees to 60 degrees, and the inclination angle of the sidewall from the bottom of the cavity to 40% or more of the height is in the range of 1.5 degrees to 5.0 degrees.

[0050] (Cross-sectional shape of the through hole) Figure 16 is a magnified cross-sectional view of the through-hole 70 formed in the core layer 60. Figure 16(a) is a cross-sectional view of the through-hole 70, and Figure 16(b) is a diagram showing the tilt angle of the through-hole 70. The method for measuring the tilt angle will be described later. The cross-section of the through-hole 70 shown in Figure 16 is obtained by scribing (cutting) along the thickness direction of the base substrate 10A to expose the cross-section (cut surface) of the through-hole 70, and is obtained by analyzing the SEM image observed by SEM (Scanning Electron Microscope) using image analysis software. As shown in Figure 16, it is an hourglass shape, and the angle of the side of the through-hole 70 is a shape that is reversed vertically based on the position of 50% of the central part. The shape of the through-hole 70 is not limited to the above shape, as long as it penetrates the first surface 60a and the second surface 60b of the core layer 60, the shape can be appropriately set. The shape of the through hole 70 is an example of a through hole that can be obtained by laser processing and etching, but the present invention is not limited to the shape described above.

[0051] The through-hole 70 shown in Figure 16(a) has an almost vertically symmetrical structure at the 50% mark. Regarding the method for measuring the inclination angle of the side of the through-hole 70, for the interval from 5% to 50% of the distance from the first surface 60a, as shown in Figure 16(b), a center line TC perpendicular to the first surface 60a is drawn at the center of the opening on the first surface 60a side of the core layer 60. Next, as indicated by arrow A1, the center line TC is moved parallel to both sides of the through-hole 11 and contacts the point where the diameter of the through-hole 11 reaches its minimum value; this contact point is taken as the reference point RP. Furthermore, from the reference point RP, tangents ss are drawn on the side at positions corresponding to the 5% to 50% marks, and the inclination angle θ of the tangent ss is measured. This inclination angle θ is taken as the inclination angle at the position of the cross-section from 5% to 50%. The inclination angle θ is positive in the direction in which the diameter of the through-hole 11 expands upwards. Furthermore, regarding the interval from 50% to 95% of the distance from the first surface 10a, the centerline TC is moved in parallel to the reference point RP, and tangents ss are drawn on the side at each position corresponding to the scale from 50% to 95%. The inclination angle θ of the tangent ss is measured, and this inclination angle θ is used as the inclination angle at each position of the cross-section from 50% to 95%. The inclination angle θ is negative with the direction of the through hole 11 expanding downwards. As shown in Figure 16(b), the tilt angle θ changes from positive to negative with the 50% position as the boundary, and the absolute value of the tilt angle θ is approximately between 14 and 15 degrees.

[0052] (Formation of a through electrode) Next, using Figure 17, the steps of forming a conductive layer in the through-hole 70 formed in the core layer 60 to form the through electrode 30 will be explained. To form the through electrode 30, an organic resin layer 80 is formed on the surface of the core layer 60. The organic resin layer 80 is, for example, a mixture of at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, formed by spin coating or impregnation. When the thickness of the organic resin layer 80 is less than 100 nm, its effect on tracking microcracks generated in the core layer 60 is relatively small, making it difficult to suppress the progression of microcracks. Furthermore, when the thickness is 10,000 nm or more, the stress generated by the increased thickness increases. Therefore, a range of 100 nm or more and 10,000 nm is ideal, and more ideally, a range of 200 nm or more and 800 nm or less is preferable. The thickness of the organic resin layer 80 can be appropriately set as long as it is within the above range.

[0053] For the core layer 60, a seed layer is formed after the organic resin layer 80 is formed. Examples of metal seed layers include Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but ideally Cu. Examples of formation methods include electroless plating, with a solution composition including copper salts such as copper sulfate and copper chloride, and Rochelle salt, EDTA (ethylenediaminetetraacetic acid), and formalin to retain copper ions. The solution composition can be adjusted appropriately according to the chemical resistance of the insulating resin used. The thickness of the metal seed layer formed by the electroless plating process, within the secondary through-hole 12, is ideally at least 0.3 μm. If the thickness is less than 0.3 μm, the coverage of the metal seed layer formed by electroless plating is insufficient, and the conductive layer formed by electroplating will be discontinuous. When the thickness of the metal seed layer formed by electroless plating is 0.3 μm or more, the thickness of the metal seed layer can be appropriately set. As a method for forming the seed layer other than electroless plating, sputtering is an example. Examples of seed layers formed by sputtering include Ti, Cu, and at least one metal layer made of these materials. Regarding the method for forming the seed layer, it is acceptable to choose a suitable method from the methods mentioned above.

[0054] (The formation of wiring) The core layer 60, to which the aforementioned seed layer is formed, is formed by photolithography to create a photoresist pattern, followed by electroplating to form the through electrode 30, the first wiring layer 21, and the second wiring layer 22. In the photolithography process, the photoresist pattern is formed, for example, by laminating a dry film photoresist, exposing it to create the pattern, and then developing it. Generally, the material used in the wiring formation step of an FC-BGA is used for the photolithography process to form the photoresist pattern. The photoresist pattern is stripped after electroplating, and excess seed layer is removed by etching. When forming the photoresist pattern via photolithography, the bottom of the cavity 35 formed by the substrate structure is protected with the photoresist pattern as needed. In the electrolytic plating process of the through-hole 70, the through electrode 30 can be formed with metals such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt, but ideally Cu. The solution composition is mainly composed of copper sulfate pentahydrate, sulfuric acid, and chloride ions. To ensure the uniformity of the plated film, a plating solution containing at least one additive is used to form the through electrode 30, the first wiring 21a1, and the second wiring 22b1. Ideally, the thickness of the through electrode 30, the first wiring 21a1, and the second wiring 22b1 should be at least 2 μm.

[0055] (Installation of micro-wiring components) Next, referring to Figure 18, the mounting of a micro-wiring component 50 within the cavity 35 formed by the bottomed structure of the core layer 60 will be described. The micro-wiring component 50 is mounted in the cavity formed by the bottomed structure using DAF (die bonding film) material via face-up mounting. The thickness of the DAF material used is at least 5 μm and less than 30 μm. If the thickness of the DAF material is less than 5 μm, it is difficult to follow the unevenness of the bottom of the cavity 35 formed by the bottomed structure. Furthermore, if the thickness of the DAF material is greater than 30 μm, the DAF material may rise to the sides and top of the micro-wiring component 50 due to heat and pressure during mounting. Therefore, it is acceptable to set the thickness of the DAF material within a suitable range of 5 μm to 30 μm. Furthermore, in mounting the micro-wiring component 50, the wiring pattern formed on the core layer 60 can be used as an alignment mark to ensure correct mounting. The shape of the alignment mark for the wiring pattern can be arbitrarily set. When mounting the micro-wiring component 50, the platform temperature can be set to 80°C or higher, and the load can be set to 10N or higher. Ideally, an installation machine with a mounting accuracy of (average +4σ) ±5μm or lower should be used.

[0056] (Formation of the insulating resin layer) Next, referring to Figure 19, the formation of the insulating resin layer will be explained. After the micro-wiring component 50 is mounted in the cavity 35 formed by the bottom structure of the core layer 60, as shown in FIG19, an insulating resin 85 is formed on the front and back surfaces of the core layer 60. The insulating resin 85 is, for example, a material in which at least one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin is added as a filler such as silicon dioxide, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide. The insulating resin 85 is a material with an elastic modulus in the range of 6 to 15 GPa and a coefficient of linear expansion in the range of 11 to 30 ppm / Deg.C, and ideally it is a thermosetting resin.

[0057] Regarding methods for forming the insulating resin layer, examples include spin coating, vacuum pressure bonding, hot pressing, compression molding, and transfer molding. As long as the micro-wiring component 50 can be embedded in the cavity 35 of the bottomed structure of the core layer 60, the forming method can be appropriately chosen. Furthermore, vacuum pressure bonding is ideal, and ideally, a processing method that simultaneously applies heat and pressure under vacuum should be selected. The processing method is not limited to one; multiple combinations of methods other than those mentioned above are also acceptable. Insulating resin 85 is formed on the front and back surfaces of the core layer 60, thereby sealing the micro-wiring component 50 in the cavity 35 formed by the bottom structure.

[0058] (Formation of the conduction pathway) Next, referring to Figure 20, the formation of the conduction path will be explained. Insulating resin 85 is formed on both the front and back surfaces of the core layer 60, thereby forming conductive pathways in the insulating resin 85 for electrical connection with the micro-wiring components 50 sealed within the cavity 35 formed by the bottom structure. The conductive pathways can be formed, for example, using UV laser or CO₂ laser processing. Alternatively, if a photosensitive insulating resin material is used for the insulating resin 85, optical pathways can be formed by photolithography. Any means and methods can be appropriately selected as long as it is a pathway for electrical connection with the micro-wiring component 50. In the pathway formed by insulating resin 85, after forming a seed layer and creating a pattern through photolithography, wiring is formed. The seed layer is formed, for example, by electroless plating or sputtering, using materials such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt. Similarly, the wiring layer is formed using materials such as Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, and Pt. Ideally, the metal material for both the seed layer and the wiring layer is Cu, and it must be formed from at least one metal containing Cu.

[0059] (Formation of wiring layers and connection terminals) Next, referring to Figure 21, the formation of the wiring layer and connection terminals will be explained. After forming insulating resin 85 and wiring containing pathways on the front and back surfaces of the core layer 60, a plurality of wirings are formed as shown in FIG21, forming a first wiring layer 21 and a second wiring layer 22. The first wiring layer 21 and the second wiring layer 21 are formed at least one layer, forming the necessary number of layers. Furthermore, in the first wiring layer 21, semiconductor element connection terminals 23 for electrical connection with the semiconductor element 40 are formed. The semiconductor element connection terminals 23 have a pillar structure, and their structure is SnAg / Ni, SnAgCu / Ni, SnCu / Ni, SnAg / Cu / Ni, Au / Pd / Ni, Au / Ni, IT, OPS, etc. The pillar system has a diameter in the range of Φ10μm to 30μm, and a period of 20 to 50μm. The above-mentioned pillar diameter and spacing can be appropriately designed to match the structure of the semiconductor element 40 and the connection terminals.

[0060] (Electrical connection with semiconductor devices) Next, referring to Figure 22, the formation of the wiring layer will be explained. After forming the first wiring layer 21 and the second wiring layer 22 on the front and back sides of the core layer 60, electrical bonding with the semiconductor element 40 is performed as shown in FIG22. Examples of bonding with the wiring substrate 20 of the semiconductor element 40 include: reflow soldering (using heat treatment to bond the solder after mounting the semiconductor element), and thermal compression bonding (TCB) (applying heat and load to bond the solder with the wiring substrate 20). Regarding the bonding method between the semiconductor element 40 and the wiring substrate 20, the appropriate method can be selected based on the diameter of the connection terminals and the distance between the connection terminals. However, when the distance between the connection terminals is 30 μm or less, thermal compression bonding (TCB) can reduce connection defects between the semiconductor element 40 and the wiring substrate 20.

[0061] (Bottom filler) Next, referring to Figure 23, the filling of the bottom filler will be explained. After the semiconductor element 40 is connected to the wiring substrate 20, as shown in FIG23, an underfill 86 is applied to protect the connection between the semiconductor element 40 and the wiring substrate 20. The underfill 86 is, for example, made by adding silica, titanium dioxide, aluminum oxide, magnesium oxide, or zinc oxide as fillers to at least one resin selected from epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and polyamide resin, thereby filling the junction between the semiconductor element 40 and the wiring substrate 20 through capillary action. The underfill 86 can be applied using capillary action or by first placing the substrate on the substrate and then filling it during thermal compression bonding (TCB). In the case of first mounting the substrate using thermal compression bonding (TCB), non-conductive paste (NCP) or non-conductive film (NCF) is used. Both NCP and NCF mentioned above are intended to protect the junction between the semiconductor element 40 and the wiring substrate 20, and the composition of the resin materials used is also the same. As for the underfiller 86, the material and method used can be appropriately set according to the bonding method between the semiconductor element 40 and the wiring substrate 20.

[0062] (Resin mold) Next, as shown in Figure 23, the periphery of the semiconductor element 40 is protected with molding resin 87. The molding resin can be, for example, an epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, or polyamide resin, to which fillers such as silicon dioxide, titanium dioxide, aluminum oxide, magnesium oxide, or zinc oxide are added, and formed by compression molding, transfer molding, or other processes. After forming the molding resin 87, a grinding process is performed to achieve a low backing of the wiring substrate 20, and the substrate can be ground to the required thickness. The grinding amount can be appropriately set according to the thickness of the wiring substrate 20.

[0063] (Manufacturing method 1 of the second embodiment) Next, referring to Figures 25 and 26, a manufacturing method 1 according to the second embodiment of the present invention will be described. Figures 25 and 26 are diagrams illustrating the steps of forming a cavity through hole 71 in a cavity 35 formed by a bottomed structure. Figure 25 illustrates the steps for forming the laser-modified portion 75, which serves as the starting point of the through-hole 70 and cavity 35 in the core layer 60. When forming the modified portion 75 using a femtosecond or picosecond laser, the formation of the laser-modified portion 75, which serves as the starting point of the through-hole 70 and cavity 35, is performed simultaneously by controlling the Z-axis of the laser and the depth of the laser-modified portion 75. In the second embodiment, in order to add an angle to the wall of the cavity 35 in two stages, the laser irradiation at the periphery of the cavity 35 is treated more superficially than at the center. Subsequently, as shown in Figure 26, through-holes 71 are formed in the cavity 35 formed by the core layer 60 and the bottom structure through etching. The through-holes 71 formed in the cavity 35 formed by the core layer 60 and the bottom structure have different opening diameters due to the different contact times of the laser modified part 75 with the etching solution, with the through-hole 70 being larger than the cavity through-hole 71.

[0064] (Manufacturing method 2 of the second embodiment) Next, referring to Figures 27 and 28, the manufacturing method 2 of the second embodiment will be described. Figure 27 illustrates the steps of forming a laser-modified portion 75 in the cavity 35 with a bottom structure by laser processing and etching of the core layer 60 to form a through hole 70. Figure 28 illustrates the steps of etching the laser-modified portion 75 formed in the cavity 35 with the bottom structure of Figure 27 to form a cavity through hole 71.

[0065] <Functions and Effects> The manufacturing methods 1 and 2 of the second embodiment described above are steps for forming a cavity through hole 71 in the cavity 35 formed by the bottom structure, and the steps before and after are the same as those in the manufacturing method of the first embodiment.

[0066] The following describes the detailed contents of the embodiments and comparative examples in the implementation plan using examples and comparative examples. Furthermore, the embodiments shown below are examples of embodiments of the present invention, and the present invention is not limited to the explanation of these embodiments.

[0067] <Examples and Comparative Examples of Embodiments of the Invention> Regarding the embodiments and comparative examples, a cavity 35 with a bottom structure was formed on the core material of the wiring board 20, various steps were performed, and temperature cycling tests were conducted. Table 1 shows the manufacturing conditions and the shape of the cavity 35 with the bottom structure for the embodiments and comparative examples. In embodiments 1 to 5, the processing spacing of the laser-modified part was varied, thereby changing the roughness, PV, and edge spacing of the bottom and sides of the cavity 35 with the bottom structure formed by etching. In comparative example 1, the laser processing spacing was set to a larger value than that in embodiments 1 to 5, and the cavity with the bottom structure was formed by etching. In addition, comparative example 2 shows that a photoresist pattern was formed on the core material by photolithography, and then the cavity 35 with the bottom structure was formed by etching. Furthermore, the Sa, PV, and bump period of the bottom of the cavity were measured in the range of 174 × 174 μm using a white interferometer (Zygo NeX View NX2). As shown in Table 1, it can be seen that if the laser processing spacing increases, the Sa, PV, unevenness period, PV on the side surface, and edge spacing of the cavity 35 also increase accordingly. The mounting performance of the micro-wiring component 50 is relative to the thickness of the DAF material used in the component being 15 μm. In Comparative Example 1, because the average PV at the bottom of the cavity is above 15,000 nm, the mounting performance is considered to be reduced. Furthermore, in the reliability evaluation of the temperature cycling test, because the average PV at the bottom is above 15,000 nm, maintaining the DAF bonding becomes difficult, resulting in reduced reliability. In Comparative Example 2, where the core material is photolithographically patterned and then etched, the bottom and side surfaces are smooth, but the distance to the adjacent through-hole is set to be wider. Furthermore, the reliability evaluation of the temperature cycling test confirms component peeling, indicating poor performance. [Table 1]

[0068] Next, Table 2 shows the results of changing the tilt angle of the sidewall of cavity 35 by changing the etching rate of the etching solution. The results of performing each installation step and evaluating the transmission characteristics of the micro-wiring component 50 mounted on cavity 35 are shown in Table 2. Examples 6-11 involved processing by varying the etching rate, the tilt angle of the sidewall of cavity 35, and the distance between cavity 35 and through electrode 30. Comparative Example 3 shows a case where the tilt angle of the cavity sidewall was set to a higher θ₁≒θ₂ under the same processing conditions as in Example 6, and Comparative Example 4 shows a case where processing was performed in the same manner as in Comparative Example 2. Furthermore, regarding the transmission characteristics shown in Table 2, the micro-wiring components and the through electrode 30 form and connect the micro-wiring with a line width and space of 5 / 5 μm using a semi-additive process (SAP). As shown in Table 2, in Examples 6 to 11, the mounting compatibility of the micro-wiring component 50 is good. However, in Comparative Example 3, the DAF climb was confirmed in the cavity tilt angle system θ₁≒θ₂, indicating that the mounting compatibility of the component with the micro-wiring layer is poor. In the measurement of transmission characteristics, the S-parameter (S21), which represents the frequency dependence of the propagation wave corresponding to the input wave, is used. S21 is expressed as the logarithm of the power ratio (transmitted wave power / input wave power), and the smaller the absolute value, the smaller the transmission loss. A network analyzer was used to measure the S-parameter (S21). Furthermore, in the evaluation of transmission characteristics, S21 values ​​below -3.0 dB were considered unsuitable. As shown in Table 2, in Examples 6-11, the distance between the through electrode 30 adjacent to the cavity 35 can be set in the range of 20 to 150 μm, and the transmission characteristic S21 is below -3.0 dB. In Comparative Example 1, the cavity 35 and the through electrode 30 are difficult to be adjacent, and the transmission characteristic S21 is above -3.0 dB. [Table 2]

[0069] Next, the adhesion at the interface between the core material and the through electrode and metal wiring layer was evaluated based on the presence or absence of an organic resin layer, as shown in Table 3. In Examples 12-15, the thickness of the organic resin layer was varied to form a seed layer using electroless plating and sputtering, followed by electroplating, and the adhesion was evaluated by a peel test. Comparative Example 5 indicates that the evaluation was performed without the formation of an organic resin layer. Furthermore, a peel strength of 0.3 kN / m or higher was considered acceptable. As shown in Table 3, in each embodiment where an organic resin layer was formed, it was confirmed that high peel strength was obtained in both electroless plating and sputtering of the seed layer. Furthermore, the results of the comparative examples confirmed that the peel strength was below 0.3 kN / m when no organic resin layer was present. [Table 3]

[0070] Table 4 shows the results of component loading yield, substrate warpage, and reliability evaluation of temperature cycling tests in Examples 16, 6, and 7 of the present invention. In the evaluations shown in Table 4, a 100×100mm substrate was fabricated and evaluated using the structure shown in FIG. 2(a). In Comparative Example 6, similar to Comparative Example 1 shown in Table 2, a photoresist pattern was formed in the core material by photolithography, and a cavity 35 with a bottom structure was formed. In Comparative Example 7, it was fabricated and evaluated according to the same specifications as in Prior Art Document 1: Japanese Patent No. 6665375. <Temperature Cycling Test> The test conditions were varied from -55°C to RT (Room Temperature) to 125°C as one cycle, and each temperature was maintained for 30 minutes, up to 1000 cycles. Observation method: Resistance value measurement (judgment standard: resistance value change rate is less than 10% relative to the initial state) Observation of substrate expansion (evaluating the expanded area in the cross-section using an ultrasonic flaw detection device when expansion occurs) As shown in Table 4, by using glass in the core material, substrate warping can be suppressed compared to Comparative Example 7. In the reliability evaluation through temperature cycling test, compared to Comparative Example 6 which performed poorly at 700 cycles, Example 16 of the present invention has been confirmed to have no problems up to 1000 cycles of temperature cycling test. [Table 4]

[0071] <Functions and Effects> By adjusting the roughness of the bottom and side surfaces of the cavity 35 formed by the bottom structure in the core layer 60, the adhesion to the components mounted in the cavity 35 can be improved. Furthermore, by adjusting the tilt angle of the side surfaces, transmission characteristics through proximity to the through electrode 30 can be ensured. Further, by forming an organic resin layer at the interface between the core layer 60, the through electrode 30, and the metal wiring, adhesion can be achieved. Therefore, according to the embodiment of the present invention, the semiconductor packaging substrate 100 using the wiring substrate 20 can also possess high reliability. By means of the embodiments of the present invention, and the manufacturing method and examples of the embodiments of the present invention, warping can be suppressed, and a wiring board with high reliability and a method for manufacturing the wiring board can be provided.

[0072] The above describes the embodiments of the present invention. However, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit and scope of the present invention. Furthermore, the present invention includes the following aspects.

[0073] <Other Implementation Methods> The present invention also includes the following states. (State 1) A wiring substrate, which is equipped with at least one or more semiconductor devices, is characterized by: The aforementioned wiring board has a core layer; Wiring layers are disposed on the first and second surfaces of the aforementioned core layer; The aforementioned core layer system has at least one through electrode extending from the aforementioned first surface to the aforementioned second surface; On the surface of the aforementioned core layer where the semiconductor device is mounted, at least one bottomed cavity is formed; The aforementioned cavity is equipped with micro-wiring components; The inclination angle of the sidewalls of the aforementioned cavity is; The inclination angle θ1 from the bottom of the cavity to the sidewall at 40% of its height, relative to the depth D1 of the cavity, ranges from 25 degrees to 60 degrees. The inclination angle θ2 of the sidewall, which is more than 40% of the height from the bottom of the cavity, is in the range of 1.5 degrees to 5.0 degrees.

[0074] (State 2) As described in sample 1, the bottom of the aforementioned cavity is periodically formed with roughness Sa: 500~1,500nm at intervals between 5.0~15.5μm.

[0075] (State 3) As described in sample 1 or 2, the bottom of the aforementioned cavity is formed with irregularities consisting of pointed tips with a height of 0.25 to 10.0 µm at a period of 5.0 to 25 µm in the horizontal direction.

[0076] (State 4) The wiring substrate described in any one of the embodiments 1 to 3, wherein the sidewall of the aforementioned cavity is formed with ridges in the longitudinal and transverse directions, the PV value of the ridges is 1.2µm or more and 3.6µm or less, and the depth of the recess is 0.5µm or more and 4.1µm or less.

[0077] (Style 5) The wiring substrate as described in any one of samples 1 to 4, wherein the sidewall of the aforementioned cavity is formed with a plurality of slightly rectangular recesses composed of a plurality of longitudinal ridges and transverse ridges; The spacing between longitudinal edges is 5µm or more and 15.5µm or less, and the spacing between transverse edges is 2.0µm or more and 25µm or less.

[0078] (Style 6) The wiring substrate as described in any one of 1 to 5, wherein the distance between the aforementioned cavity and the nearest through electrode is 20µm or more and 150µm or less.

[0079] (Style 7) The wiring substrate described in any one of the embodiments 1 to 6, wherein the interface between the core layer and the wiring layer and the interface between the core layer and the through electrode are formed with an organic resin layer of at least 100 nm and less than 5,000 nm.

[0080] (Style 8) The wiring substrate described in any one of Specimens 1 to 7, wherein the material of the aforementioned core layer is glass with a SiO₂ content of 55% by mass or more and 85.0% by mass or less.

[0081] (Style 9) The wiring substrate described in any one of 1 to 8, wherein the aforementioned core layer is formed with cavities of different depths.

[0082] (Style 10) A method for manufacturing a multilayer wiring substrate, wherein the wiring substrate is mounted with at least one semiconductor device, and the wiring substrate has a first surface and a second surface, and has at least one through electrode extending from the first surface to the second surface. On the first surface, which serves as the mounting surface for the semiconductor device, the core material of the wiring substrate has at least one bottomed cavity structure, and the core material of the wiring substrate is embedded with components forming a fine wiring layer; The aforementioned manufacturing method has the following characteristics: The process involves forming a predetermined portion of a through-hole and a predetermined portion of a bottomed cavity in the core material of the wiring board, irradiating the area near the outer periphery of the cavity with a laser at a shallower depth than the center portion, and etching the laser-irradiated portion to form a through-hole and a bottomed cavity. The steps include: forming a seed layer in a core material with a through-hole and a bottomed cavity; forming a photoresist pattern; and forming a wiring layer by electroplating. The step of placing a component with a fine wiring layer into a bottomed cavity; The step of forming an insulating resin layer on the first and second surfaces of a component and a core material having a fine wiring layer disposed in a cavity with a bottom; The steps of forming at least two wiring layers on the first and second surfaces; and the step of monolithizing the wiring substrate.

[0083] (Style 11) In the method for manufacturing a wiring substrate as described in Sample 10, in the step of irradiating the core material of the aforementioned wiring substrate with a laser to form a predetermined portion of a through electrode and a predetermined portion of a bottomed cavity, By subjecting the core material to laser irradiation in the vertical direction at the predetermined portion of the through electrode formation, the core material undergoes comprehensive modification along its thickness direction. A predetermined section is formed in a bottomed cavity, and the core material is subjected to laser irradiation in the vertical direction, which partially modifies the thickness direction of the core material. (Style 12) The method for manufacturing a wiring substrate as described in Sample 10 or Sample 11, wherein a component having a fine wiring layer formed is disposed in the aforementioned bottomed cavity, The aforementioned component is made of DAF material and mounted in the aforementioned bottomed cavity. (Style 13) The method for manufacturing a wiring substrate as described in any one of Specimens 10 to 12, wherein the thickness of the aforementioned DAF material is in the range of 5 μm or more and 30 μm or less.

[0084] 1: Motherboard 10:FC-BGA 20: Wiring board 21: First wiring layer 22: Second wiring layer 23: Terminals for connecting semiconductor components 30: Through electrode 31: Cavity through electrode 35: Cavity 40: Semiconductor components 50: Micro-wiring components 51:DAF 60: Core layer 60a: First page 60b: Second page 61: Base material substrate 70: Through hole 71: Through hole in the cavity 75: Laser Modification Department 80: Organic resin layer (primer layer) 85: Insulating resin 86: Bottom filler 87: Mold Resin 100: Semiconductor packaging substrate T1: Thickness of the core substrate T2: Thickness of components with micro-wiring layers D1: Cavity depth W1: Cavity width W2: Cavity length w1: The width of the micro-wiring layer; w2: The length of the component with the micro-wiring layer. S1: The difference in opening between the upper and lower parts of the cavity, θ: Cavity angle CB: Bottom of cavity TC: Centerline of TGV SS: TGV Tangent

Claims

1. A wiring substrate, which is equipped with at least one semiconductor element, characterized in that: the wiring substrate has a core layer; wiring layers are disposed on a first surface and a second surface of the core layer; the core layer has at least one through electrode extending from the first surface to the second surface; at least one bottomed cavity is formed on the surface of the core layer where the semiconductor element is mounted; the cavity is equipped with a micro-wiring component; the tilt angle of the sidewall of the cavity is: relative to the depth D1 of the cavity, the tilt angle θ1 from the bottom of the cavity to 40% of the height of the sidewall is in the range of 25 degrees to 60 degrees; the tilt angle θ2 of the sidewall at 40% or more of the height from the bottom of the cavity is in the range of 1.5 degrees to 5.0 degrees.

2. The wiring board as described in claim 1, wherein, The bottom of the cavity is periodically formed with irregular bumps and depressions with a roughness of Sa: 500 to 1,500 nm at intervals of 5.0 to 15.5 µm.

3. The wiring board as described in claim 1, wherein, The bottom of the cavity is formed with irregularities in the horizontal direction at a period of 5.0 to 25 µm, consisting of pointed tips with a height of 0.25 to 10.0 µm.

4. The wiring board as described in any one of claims 1 to 3, wherein, The sidewalls of the cavity are formed with ridges in the longitudinal and transverse directions. The PV value of the ridges is above 1.2µm and below 3.6µm, and the depth of the recess is above 0.5µm and below 4.1µm.

5. The wiring board as described in any one of claims 1 to 3, wherein, The sidewall of the cavity is formed with a plurality of slightly rectangular recesses consisting of a plurality of longitudinal ridges and transverse ridges; the interval between the longitudinal ridges is 5µm or more and 15.5µm or less, and the interval between the transverse ridges is 2µm or more and 25µm or less.

6. The wiring board as described in any one of claims 1 to 3, wherein, The distance between the cavity and the nearest through electrode is greater than 20µm and less than 150µm.

7. The wiring board as described in any one of claims 1 to 3, wherein, The interface between the core layer and the wiring layer, and the interface between the core layer and the through electrode, are formed with an organic resin layer of at least 100 nm and less than 5,000 nm.

8. The wiring board as described in any one of claims 1 to 3, wherein, The core layer is made of glass with a SiO2 content of 55% to 85% by mass.

9. The wiring board as described in any one of claims 1 to 3, wherein, The core layer system forms cavities of varying depths.

10. A method for manufacturing a wiring substrate, the wiring substrate mounting at least one semiconductor element; and the wiring substrate having a first surface and a second surface, and having at least one through electrode extending from the first surface to the second surface; on the first surface, which serves as the mounting surface of the semiconductor element, the core material of the wiring substrate having at least one bottomed cavity structure; the core material of the wiring substrate having a component with a fine wiring layer embedded therein; and the manufacturing method comprising: forming predetermined portions of the through electrodes and the bottomed cavity in the core material of the wiring substrate; irradiating the periphery of the cavity with a laser at a shallower depth than the center portion; and etching the laser-irradiated portion to form through holes and bottomed cavities; forming a seed layer in the core material having through holes and bottomed cavities; forming a photoresist pattern and forming a wiring layer by electrolytic plating; and disposing the component with the fine wiring layer in the bottomed cavity. The steps include: forming an insulating resin layer on the first and second surfaces of a component and a core material having a fine wiring layer disposed in a cavity with a bottom; forming at least two wiring layers on the first and second surfaces; and monolithically forming the wiring substrate.

11. A method for manufacturing a wiring board as described in claim 10, wherein, In the steps of irradiating the core material of the wiring board with lasers to form a predetermined portion of the through electrode and a predetermined portion of the bottomed cavity, the core material is irradiated with lasers in the vertical direction to comprehensively modify the thickness direction of the core material in the predetermined portion of the through electrode; the core material is irradiated with lasers in the vertical direction to partially modify the thickness direction of the core material in the predetermined portion of the bottomed cavity.

12. A method for manufacturing a wiring board as described in claim 10 or 11, wherein, In the step of placing the component with the micro-wire layer formed thereon into the bottomed cavity, the component is made of DAF material and mounted in the bottomed cavity.

13. A method for manufacturing a wiring board as described in claim 12, wherein, The thickness of this DAF material is in the range of 5µm or more and 30µm or less.

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