Thin film transistor, method for manufacturing the same and display apparatus comprising the same

Abstract

One embodiment of this disclosure provides a thin-film transistor comprising a seed layer, an active layer overlapping the seed layer and including a channel portion, and a gate electrode overlapping at least a portion of the active layer. The channel portion is in contact with the seed layer and has a crystalline structure. The seed layer has an amorphous structure and overlaps with the gate electrode. The seed layer is disposed in a region of the gate electrode, and in a planar view, the active layer and the gate electrode overlap in this region. Furthermore, another embodiment of this disclosure provides a method for manufacturing such a thin-film transistor and a display device comprising such a thin-film transistor.

Description

[Technical Field]

[0001] This disclosure relates to a thin-film transistor having a seed layer, a method for manufacturing such a thin-film transistor, and a display device comprising such a thin-film transistor. [Previous Technology]

[0002] Transistors are widely used as switching or driving devices in the field of electronic devices. In particular, thin-film transistors, because they can be manufactured on glass or plastic substrates, are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting devices.

[0003] Based on the material constituting the active layer, thin film transistors can be divided into: amorphous silicon thin film transistors with amorphous silicon as the active layer, polycrystalline silicon thin film transistors with polycrystalline silicon as the active layer, and oxide semiconductor thin film transistors with oxide semiconductor as the active layer.

[0004] Because amorphous silicon can be deposited to form an active layer in a short time, amorphous silicon thin film transistors (a-Si TFTs) have the advantages of short process time and low production cost. However, amorphous silicon thin film transistors also have disadvantages such as low mobility, poor current driving capability, and critical voltage variation, which limits their application in active matrix organic light emitting diodes (AMOLEDs).

[0005] Polycrystalline silicon thin film transistors (poly-Si TFTs) are manufactured by crystallizing amorphous silicon after deposition. Polycrystalline silicon thin film transistors have advantages such as high electron mobility, good stability, thin thickness, high resolution, and high power efficiency. Examples of such polycrystalline silicon thin film transistors include low-temperature poly-silicon (LTPS) thin film transistors or polycrystalline silicon thin film transistors. Because the manufacturing process of polycrystalline silicon thin film transistors requires an amorphous silicon crystallization process, the increased number of processes leads to higher manufacturing costs, and crystallization must be carried out at high temperatures.

[0006] Oxide semiconductor thin-film transistors possess high mobility and high resistance characteristics that vary with oxygen content, offering the advantage of easily obtaining the desired properties. Furthermore, since the oxide constituting the active layer can be formed at relatively low temperatures during the manufacturing process of oxide semiconductor thin-film transistors, the manufacturing cost is lower. Because oxide semiconductors are transparent due to their oxide composition, they also have advantages in realizing transparent displays.

[0007] However, the performance of oxide semiconductor thin-film transistors may be degraded by hydrogen, and the on-state voltage may become unstable. In particular, when oxide semiconductor thin-film transistors are used in environments containing large amounts of hydrogen or in high-temperature environments, the performance degradation or instability caused by hydrogen may be exacerbated.

[0008] Therefore, in order to prevent the oxide thin film transistor from deteriorating and to improve its stability, it is necessary to protect the oxide semiconductor thin film transistor from the influence of hydrogen. [Summary of the Invention]

[0009] One embodiment of this disclosure aims to provide a thin-film transistor comprising a seed layer and an active layer in contact with the seed layer.

[0010] One embodiment of this disclosure aims to provide a thin-film transistor that has excellent hydrogen resistance due to having a channel portion crystallized by a seed layer.

[0011] One embodiment of this disclosure provides a thin-film transistor, wherein the active layer can be formed of an oxide semiconductor layer with conductive properties, and the channel portion can be crystallized through a seed crystal layer to have semiconductor properties.

[0012] One embodiment of this disclosure provides a thin-film transistor, wherein the channel portion may have a crystalline structure and the connection portion may have an amorphous structure.

[0013] One embodiment of this disclosure provides a method for manufacturing a thin-film transistor, which is made using an oxide semiconductor material with conductive properties, thus eliminating the need for a conductor-forming process.

[0014] Another embodiment of this disclosure provides a method for manufacturing a thin-film transistor using an oxide semiconductor material with conductive properties and a seed layer.

[0015] Another embodiment of this disclosure provides a display device with excellent reliability, which includes the aforementioned thin-film transistor.

[0016] In one embodiment, the thin-film transistor includes: a seed layer having an amorphous structure; an active layer overlapping the seed layer and including a channel portion, the channel portion being in contact with the seed layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the seed layer and the active layer in a planar view of the thin-film transistor.

[0017] In one embodiment, the method of manufacturing a thin-film transistor includes: forming a seed layer on a substrate; forming an active layer overlapping the seed layer, such that a portion of the active layer is in contact with the seed layer while another portion of the active layer is not in contact with the seed layer; crystallizing the portion of the active layer in contact with the seed layer by heat treatment; and forming a gate electrode on the active layer.

[0018] In one embodiment, the thin-film transistor includes: a seed layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer including a channel portion covering the upper surface and side surface of the seed layer, a first connection portion located on a first side of the channel portion, and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the seed layer and the channel portion, such that the channel portion is located between the seed layer and the gate electrode, wherein the first carrier concentration of the first oxide semiconductor material in the seed layer is less than the second carrier concentration of the second oxide semiconductor material in the active layer, and the first oxygen concentration of the first oxide semiconductor material is greater than the second oxygen concentration of the second oxide semiconductor material.

Implementation Method

[0020] The advantages, features, and implementation methods of this disclosure will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various other forms. These embodiments are provided to complete the disclosure and to facilitate understanding of the invention by those skilled in the art.

[0021] For the purpose of illustrating the embodiments of this disclosure, the shapes, sizes, proportions, angles, quantities, etc., disclosed in the drawings are all exemplary, and this disclosure is not limited to the content shown in the drawings. Identical elements throughout the specification may be represented by the same numbers. Furthermore, if it is believed that a detailed description of related known technologies may unnecessarily obscure the essence of this disclosure, such detailed description will be omitted.

[0022] In this specification, when terms such as "including," "having," and "comprising" are used, other parts may be added unless the expression "only" is used. When an element is described as singular, the plural form is included unless explicitly stated otherwise.

[0023] When explaining components, even if not explicitly stated separately, it is interpreted as including the error range.

[0024] When the positional relationship is described as, for example, when the positional relationship between two parts is described as "above", "above", "below", "adjacent", etc., unless the word "direct" is used, there may be one or more other parts between the two parts.

[0025] Spatial relative terms such as "below," "under," "lower," "above," and "higher" are used to simplify the description of the relationship between one element or component and another element or component in a diagram. These spatial relative terms should be understood to include, in addition to the orientation shown in the diagram, the different orientations of the element during use or operation. For example, if an element in the diagram is flipped, an element described as "below" or "under" may end up "above" another element. Therefore, the exemplary term "below" can include both vertical and horizontal directions. Similarly, the exemplary terms "above" or "above" can include both vertical and horizontal directions.

[0026] When describing time-related terms, such as “after,” “next,” “adjacent,” “before,” etc., discontinuous situations may also be included unless “immediately” or “directly” is used.

[0027] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component described below can also be the second component within the technical concept disclosed herein.

[0028] The term "at least one" should be understood to include all combinations that can be presented in one or more related items. For example, "at least one of the first, second and third items" means not only each of the first, second or third items, but also all combinations of two or more of the first, second and third items.

[0029] The individual features of the embodiments disclosed herein may be combined in part or in whole, or technically linked and driven in various ways. Each embodiment may be implemented independently or jointly in accordance with the relevant relationship.

[0030] The thin-film transistor and the display device including the thin-film transistor of the present disclosure embodiment will be described in detail below with reference to the figures. When identifying the reference symbols of the elements in the figures, the same elements in different figures are represented by the same symbols as much as possible.

[0031] In the embodiments disclosed herein, the source electrode and the drain electrode are different but interchangeable. For example, the source electrode in one embodiment may become the drain electrode in another embodiment, and the drain electrode in one embodiment may become the source electrode in another embodiment.

[0032] In the embodiments disclosed herein, for ease of explanation, a source region and a source electrode are distinguished, and a drain region and a drain electrode are distinguished, but the embodiments disclosed herein are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. Furthermore, the source region may be a drain electrode, and the drain region may be a source electrode.

[0033] Figure 1 is a plan view of a thin-film transistor 100 according to an embodiment of the present disclosure, Figure 2 is a cross-sectional view along line I-I' of Figure 1, and Figure 3 is a cross-sectional view along line II-II' of Figure 1.

[0034] This disclosure discloses a thin-film transistor 100 comprising a seed layer 120, an active layer 130 overlapping the seed layer 120, and a gate electrode 150 overlapping at least a portion of the active layer 130. The active layer 130 includes a channel portion 130n. Furthermore, the active layer 130 may include a first connection portion 130a connected to a first side of the channel portion 130n and a second connection portion 130b connected to a second side of the channel portion 130n. The channel portion 130n overlaps with the seed layer 120 and the gate electrode 150.

[0035] Referring to Figures 2 and 3, the thin-film transistor 100 may be disposed on the substrate 110. Any object that can support the thin-film transistor 100 may be referred to as the substrate 110 and is not limited to the embodiments disclosed herein.

[0036] The substrate 110 may be made of glass or plastic. The substrate 110 may be made of a transparent plastic with flexible properties. Among various plastics, for example, when polyimide is used as the substrate 110, considering that a high-temperature deposition process is required on the substrate 110, a heat-resistant polyimide with high temperature resistance may be used.

[0037] A light-shielding layer 111 may be provided on the substrate 110. The light-shielding layer 111 overlaps with the channel portion 130n. The light-shielding layer 111 blocks external incident light, thereby protecting the channel portion 130n.

[0038] The light-shielding layer 111 may be made of a light-shielding material. The light-shielding layer 111 may contain at least one of aluminum-based metals such as aluminum (Al), aluminum alloys, molybdenum-based metals such as molybdenum (Mo), molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to one embodiment of this disclosure, the light-shielding layer 111 may be conductive.

[0039] The light-shielding layer 111 may be electrically connected to the source electrode 161 or the drain electrode 162. The light-shielding layer 111 may also be connected to the gate electrode 150. In other embodiments, this light-shielding layer 111 may be omitted.

[0040] A buffer layer 115 is provided on the light-shielding layer 111. The buffer layer 115 may be made of an insulating material. For example, the buffer layer 115 may contain at least one of insulating materials such as silicon oxide, silicon nitride, and metal oxides. The buffer layer 115 may have a single-film structure or a multi-film structure.

[0041] The buffer layer 115 can protect the active layer 130 by blocking air and moisture. In addition, the buffer layer 115 can make the surface of the upper part of the substrate 110 on which the light-shielding layer 111 is provided uniform.

[0042] The seed layer 120 may be disposed on the substrate 110. Referring to FIG2, the seed layer 120 may be disposed on the buffer layer 115.

[0043] The seed layer 120 may have the function of selectively crystallizing a portion of the active layer 130 that is in contact with the seed layer 120. The seed layer 120 may serve as a seed for crystal growth. Selected portions of the active layer 130 may be crystallized by the seed layer 120. Therefore, a portion of the active layer 130 may have crystalline properties.

[0044] According to one embodiment of the present disclosure, the seed layer 120 may comprise an oxide semiconductor material.

[0045] For example, the seed layer 120 may include at least one of indium zinc oxide (InZnO) based oxide semiconductor material, indium gallium zinc oxide (InGaZnO) based oxide semiconductor material, indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, gallium zinc oxide (GaZnO) based oxide semiconductor material and gallium oxide (GaO) based oxide semiconductor material.

[0046] The seed layer 120 selectively crystallizes the active layer 130 without affecting the electrical properties of the active layer 130.

[0047] According to one embodiment of this disclosure, although the basic composition of the seed layer 120 is an oxide semiconductor material, it contains a large amount of oxygen. As a result, the seed layer 120 can have the characteristics of an insulating layer in terms of electrical properties.

[0048] Specifically, the seed layer 120 may be formed of an oxide semiconductor material with low carrier concentration and high oxygen concentration. In one embodiment of this disclosure, the seed layer 120 may have high resistivity. The high-resistivity seed layer 120 exhibits electrical properties similar to an insulator and does not participate in carrier movement of the active layer 130. In one embodiment of this disclosure, the seed layer 120 does not affect carrier movement of the active layer 130. According to one embodiment of this disclosure, the carrier concentration of the seed layer 120 is lower than that of the channel portion 130n, the first connection portion 130a, and the second connection portion 130b.

[0049] According to one embodiment of this disclosure, the carrier concentration of the seed layer 120 may be 1.0 × 10¹⁶ ea / cm³ or lower. When the carrier concentration of the seed layer 120 is 1.0 × 10¹⁶ ea / cm³ or lower, the seed layer 120 may have electrical characteristics similar to those of an insulating layer.

[0050] According to one embodiment of this disclosure, the carrier concentration of the seed layer 120 is 1.0 × 10¹⁶ ea / cm³ or lower, which is a relatively low carrier concentration and therefore has insulating properties. Thus, the seed layer 120 does not affect the conduction current characteristics of the thin-film transistor 100.

[0051] According to one embodiment of the present disclosure, the thickness of the seed layer 120 may be from 1 nanometer (nm) to 10 nm. In order not to affect the electrical characteristics of the active layer 130, the thickness of the seed layer 120 may be 10 nm or thinner.

[0052] Even if the seed layer 120 has a low carrier concentration, when the thickness of the seed layer 120 is large, there is still a possibility that charge can flow through the seed layer 120. For example, when the thickness of the seed layer 120 increases, electron-hole pairs can be formed in the seed layer 120, causing the seed layer 120 to exhibit semiconductor characteristics. When the seed layer 120 has semiconductor characteristics, it becomes difficult to control the electrical characteristics of the thin-film transistor 100.

[0053] Since the thickness of the seed layer 120 may cause changes in the carrier movement of the thin film transistor 100 when the thickness exceeds 10 nm, according to one embodiment of the present disclosure, the thickness of the seed layer 120 is designed to be 10 nm or less.

[0054] On the other hand, when the thickness of the seed layer 120 is less than 1 nm, the seed layer 120 may be too thin to serve as a seed for crystal growth. Furthermore, when the thickness of the seed layer 120 is designed to be less than 1 nm, it may be easily damaged due to its thinness, and the mechanical stability of the seed layer 120 may be deteriorated. Therefore, according to one embodiment of this disclosure, the thickness of the seed layer 120 may be designed to be 1 nm or greater.

[0055] The seed layer 120 has an amorphous structure. According to one embodiment of the present disclosure, the seed layer 120 is an amorphous layer.

[0056] According to one embodiment of this disclosure, in a cross-section of a layer, when the total area of ​​crystals with a grain size of 1 nm or larger accounts for 10% or less of the total cross-sectional area, this layer is referred to as an amorphous layer. Specifically, in a transmission electron microscope (TEM) image of the cross-section of the layer under test, when the total area of ​​crystals with a grain size of 1 nm or larger accounts for 10% or less of the total cross-sectional area, this layer is referred to as an amorphous layer.

[0057] According to one embodiment of the present disclosure, the seed layer 120 is an amorphous layer, wherein the total area of ​​crystals with a grain size of 1 nm or larger is 10% or less based on the total cross-sectional area of ​​the seed layer 120.

[0058] On the other hand, if the total area of ​​crystals with a grain size of 1 nm or larger accounts for 50% or more of the total cross-sectional area, this layer is called a crystalline layer. Specifically, in the transmission electron microscope image of the cross-section of the layer under test, if the total area of ​​crystals with a grain size of 1 nm or larger accounts for 50% or more of the total cross-sectional area, this layer is called a crystalline layer.

[0059] Referring to Figures 2 and 3, the active layer 130 is disposed on the seed crystal layer 120.

[0060] According to one embodiment of the present disclosure, the active layer 130 may be formed of a semiconductor material. The active layer 130 may comprise an oxide semiconductor material. For example, the active layer 130 may comprise an oxide semiconductor layer.

[0061] Figures 1 to 3 illustrate an example of a thin-film transistor 100 in which the active layer 130 is an oxide semiconductor layer.

[0062] According to one embodiment of this disclosure, the active layer 130 may be formed of an oxide semiconductor material with high mobility, similar to that of a conductor. For example, the active layer 130 may be formed of an amorphous oxide semiconductor material with a carrier concentration of 1.0 × 10¹⁹ ea / cm³ or higher. On the other hand, the seed layer 120 may be formed of an amorphous oxide semiconductor material with a carrier concentration lower than that of the active layer 130.

[0063] The active layer 130 may include at least one of, for example, an indium gallium zinc oxide (InGaZnO) based oxide semiconductor material, an indium gallium oxide (InGaO) based oxide semiconductor material, an indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, a gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, a gallium zinc oxide (GaZnO) based oxide semiconductor material, a gallium oxide (GaO) based oxide semiconductor material, a tin oxide (SnO) based oxide semiconductor material, an indium tin oxide (InSnO) based oxide semiconductor material, an indium tin zinc oxide (InSnZnO) based oxide semiconductor material, an indium zinc oxide (InZnO) based oxide semiconductor material, a zinc oxide (ZnO) based oxide semiconductor material, an indium oxide (InO) based oxide semiconductor material, a zinc oxide (ZnO) based oxide semiconductor material, and an iron indium zinc oxide (FeInZnO) based oxide semiconductor material. However, this embodiment is not limited to this, and other known oxide semiconductor materials with high mobility can also be applied to the active layer 130 of this embodiment.

[0064] According to one embodiment of this disclosure, an indium-based oxide semiconductor material having an atomic percentage (at%) of 50 or more of indium (In) based on the total number of metal atoms can be used as the oxide semiconductor material forming the active layer 130. The active layer 130 may comprise at least one of, for example, an indium zinc oxide (InZnO)-based oxide semiconductor material, an indium gallium oxide (InGaO)-based oxide semiconductor material, an indium gallium zinc oxide (InGaZnO)-based oxide semiconductor material, an indium tin oxide (InSnO)-based oxide semiconductor material, and an indium gallium zinc tin oxide (InGaZnSnO)-based oxide semiconductor material, having an indium (In) content of 50 or more of the total number of metal atoms.

[0065] Specifically, the active layer 130 may include: an indium zinc oxide (InZnO) based oxide semiconductor material in which the atomic percentage of indium (In) is 50 or more of the total content of indium (In) and zinc (Zn); an indium gallium oxide (InGaO) based oxide semiconductor material in which the atomic percentage of indium (In) is 70 or more of the total content of indium (In) and gallium (Ga); an indium gallium zinc oxide (InGaZnO) based oxide semiconductor material in which the atomic percentage of indium (In), gallium (Ga) and zinc (Zn) is 50 or more of the total content of indium (In), gallium (Ga) and zinc (Zn); an indium tin oxide (InSnO) based oxide semiconductor material in which the atomic percentage of indium (In) and tin (Sn) is 80 or more of the total content of indium (In) and tin (Sn); and an indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material in which the atomic percentage of a mixture of indium (In) and tin (Sn) is 50 or more of the total content of indium (In), gallium (Ga), zinc (Zn) and tin (Sn).

[0066] According to one embodiment of the present disclosure, the active layer 130 may have a low oxygen concentration.

[0067] When the active layer 130 contains a high concentration of indium (In) and a low concentration of oxygen, the active layer 130 can have high mobility and excellent conductivity.

[0068] According to one embodiment of this disclosure, the active layer 130 may further comprise at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr). These elements may be dispersed in an oxide semiconductor material.

[0069] According to one embodiment of this disclosure, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y) or zirconium (Zr) may be referred to as crystallization control elements.

[0070] The crystallization control element is an element that has a strong affinity for oxygen and can delay the crystallization of the active layer 130. The active layer 130 can be formed by deposition and patterning. The crystallization control element prevents the active layer 130 from crystallizing during the deposition process, thereby avoiding the deterioration of the patterning characteristics of the active layer 130.

[0071] On the other hand, the crystallization control element does not completely prevent the crystallization of the active layer 130. Therefore, when heat treatment is performed while the active layer 130 is in contact with the seed crystal layer 120, the portion of the active layer 130 in contact with the seed crystal layer 120 can be crystallized.

[0072] According to one embodiment of this disclosure, the crystallization control element has an atomic percentage (at%) of 0.1 to 6% of the total number of atoms (excluding oxygen atoms) in the active layer 130. When the crystallization control element content is less than 0.1% of the total number of atoms (excluding oxygen atoms) in the active layer 130, the crystallization prevention effect during deposition may be insufficient. Therefore, the patterning process after the deposition of the oxide semiconductor material forming the active layer 130 may be difficult.

[0073] On the other hand, if the content of the crystallization control element accounts for more than 6% of the total number of atoms in the active layer 130 excluding oxygen atoms, then due to the excess of the crystallization control element, for example, a selected part of the active layer 130 (the part in contact with the seed crystal layer 120) may not be able to crystallize or the crystallization rate may be reduced.

[0074] According to one embodiment of the present disclosure, the active layer 130 and the seed layer 120 may contain one or more of the same metal elements. When the active layer 130 and the seed layer 120 contain the same elements, the bonding strength between them can be improved.

[0075] According to one embodiment of the present disclosure, the active layer 130 includes a channel portion 130n. The channel portion 130n is in direct contact with the seed layer 120. Furthermore, the channel portion 130n overlaps with the seed layer 120 and the gate electrode 150, such that the channel portion 130n is located between the seed layer 120 and the gate electrode 150.

[0076] According to one embodiment of the present disclosure, the channel portion 130n has a crystalline structure.

[0077] According to one embodiment of the present disclosure, after the active layer 130 is formed with an amorphous oxide semiconductor material, the region where the active layer 130 overlaps with the seed layer 120 can be crystallized to form a channel portion 130n. The channel portion 130n may refer to a portion 130c of the active layer 130 crystallized through the seed layer 120.

[0078] According to one embodiment of this disclosure, the transformation from an amorphous structure to a crystalline structure is called "crystallization". Furthermore, the crystallization of a specific portion of the active layer 130 is called "selective crystallization".

[0079] According to one embodiment of the present disclosure, the channel portion 130n may be referred to as the portion 130c of the active layer 130 that has been selectively crystallized by the seed crystal layer 120.

[0080] For example, when oxygen contained in the seed layer 120 diffuses to the active layer 130 in contact with the seed layer 120, selective crystallization of the active layer 130 may occur. The seed layer 120 serves as the seed crystal for crystallization. Using the seed layer 120 as the seed crystal, crystallization can begin from the portion of the active layer 130 in contact with the seed layer 120.

[0081] During the selective crystallization of the active layer 130 in contact with the seed layer 120 to form the channel portion 130n, oxygen (O) migration may occur. Oxygen (O) can migrate from the seed layer 120 to the channel portion 130n. Therefore, the oxygen concentration of the channel portion 130n may be higher than that of the first connecting portion 130a and the second connecting portion 130b. However, the oxygen concentration of the channel portion 130n will not be equal to or higher than that of the seed layer 120.

[0082] According to one embodiment of this disclosure, the oxygen concentration of the channel portion 130n is lower than the oxygen concentration of the seed layer 120. The oxygen concentration can be expressed or calculated as an atomic percentage (at%).

[0083] According to one embodiment of the present disclosure, the active layer 130 includes a first connection portion 130a and a second connection portion 130b. The first connection portion 130a is connected to one side of the channel portion 130n, and the second connection portion 130b is connected to the other side of the channel portion 130n.

[0084] The portion of the active layer 130 that contacts the seed layer 120 and its surrounding area can be crystallized to form a channel portion 130n, while the portion that does not contact the seed layer 120 becomes the first connecting portion 130a and the second connecting portion 130b. Therefore, since the channel portion 130n covers the seed layer 120, the seed layer 120 does not contact the first connecting portion 130a or the second connecting portion 130b.

[0085] The region of the active layer 130 that is not in contact with the seed layer 120 can remain in an amorphous state and maintain a high carrier concentration. The amorphous portion 130m of the active layer 130 can become the first connecting portion 130a and the second connecting portion 130b. The oxygen concentration of the channel portion 130n can be higher than that of the first connecting portion 130a and the second connecting portion 130b.

[0086] The first connecting portion 130a and the second connecting portion 130b are uncrystallized portions. According to one embodiment of this disclosure, the first connecting portion 130a and the second connecting portion 130b may have excellent electrical conductivity similar to that of a metal.

[0087] The carrier concentration of channel portion 130n is lower than that of the first connection portion 130a and the second connection portion 130b. In addition, the mobility of channel portion 130n is lower than that of the first connection portion 130a and the second connection portion 130b.

[0088] Referring to Figure 2, the channel portion 130n can be formed on the upper surface and side surface of the seed layer 120. Therefore, the channel portion 130n is in contact with the upper surface and side surface of the seed layer 120. Specifically, a portion of the active layer 130 in contact with the upper surface and side surface of the seed layer 120 can be crystallized into the channel portion 130n. Therefore, the length L2 of the channel portion 130n can be greater than the length L1 of the seed layer 120. Here, the length is measured along the line connecting the first connecting portion 130a and the second connecting portion 130b. Referring to Figure 1, the length is the distance measured along the direction dr1 connecting the first connecting portion 130a and the second connecting portion 130b.

[0089] However, since the seed layer 120 is extremely thin, the portion of the active layer 130 that contacts the side surface of the seed layer 120 is extremely small. Therefore, the portion of the active layer 130 that contacts the side surface of the seed layer 120 and crystallizes can be ignored. In this case, the length of the channel portion 130n can be the same as that of the seed layer 120, or the length of the channel portion 130n can be substantially the same as that of the seed layer 120 (L1=L2).

[0090] According to one embodiment of this disclosure, in the cross-section of the channel portion 130n, the total area of ​​crystals with a grain size of 1 nm or larger accounts for 50% or more of the total cross-sectional area. Specifically, based on a transmission electron microscope image of the channel portion 130n cross-section, the total area of ​​crystals with a grain size of 1 nm or larger accounts for 50% or more of the total cross-sectional area.

[0091] According to one embodiment of the present disclosure, the channel portion 130n may include at least one crystal structure selected from, for example, cubic crystal structure, ferromanganese structure, cubic ferromanganese structure, spinel structure, hexagonal structure and wurtzite structure.

[0092] According to one embodiment of the present disclosure, the channel portion 130n may have crystal planes. The crystal planes of the channel portion 130n may include at least one of, for example, a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (001) crystal plane. The crystal planes of the channel portion 130n may be identified or measured by X-ray diffraction analysis (XRD).

[0093] The channel portion 130n with a crystalline structure can exhibit excellent physical and chemical stability. As a result, during the manufacturing or use of the thin-film transistor 100, damage to the channel portion 130n or deformation of its physical properties can be suppressed or prevented. Furthermore, because the channel portion 130n can have a crystalline structure with excellent hydrogen resistance, the channel portion 130n can exhibit excellent stability. According to one embodiment of this disclosure, because the channel portion 130n has excellent stability, the thin-film transistor 100 can exhibit excellent operational stability.

[0094] The first connecting portion 130a and the second connecting portion 130b, which are uncrystallized and exist in an amorphous state, can possess excellent electrical conductivity. According to one embodiment of this disclosure, the carrier concentration of each of the first connecting portion 130a and the second connecting portion 130b can be 1.0 × 10¹⁹ ea / cm³ or higher. Specifically, the carrier concentration of each of the first connecting portion 130a and the second connecting portion 130b can be 1.0 × 10²¹ ea / cm³ or higher.

[0095] Furthermore, the sheet resistance of each of the first connection portion 130a and the second connection portion 130b may be 10³ Ω / sq or lower. Specifically, the sheet resistance of each of the first connection portion 130a and the second connection portion 130b may be 10² Ω / sq or lower.

[0096] The first connection portion 130a and the second connection portion 130b, which have high carrier concentration and low surface resistance, can have electrical properties similar to those of a conductor without the need for a separate conductor-forming process.

[0097] According to one embodiment of this disclosure, the first connection portion 130a and the second connection portion 130b can be formed without performing a conductor-forming process on the active layer 130. Therefore, it is possible to prevent the conductive region from extending into the channel portion 130n during the conductor-forming process.

[0098] Referring to Figures 2 and 3, a gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 may contain at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure. The gate insulating layer 140 protects the channel portion 130n.

[0099] Referring to FIG2, the gate insulating layer 140 may be formed on the entire upper surface of the substrate 110. For example, the gate insulating layer 140 may cover the entire channel portion 130n, the first connection portion 130a and the second connection portion 130b except for the contact area.

[0100] However, one embodiment of this disclosure is not limited thereto, and the gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned into a shape corresponding to the gate electrode 150.

[0101] The gate electrode 150 is disposed on the gate insulating layer 140.

[0102] The gate electrode 150 may comprise at least one of aluminum-based metals such as aluminum (Al), aluminum alloys, silver-based metals such as silver (Ag), silver alloys, copper-based metals such as copper (Cu), copper alloys, molybdenum-based metals such as molybdenum (Mo), molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may also have a multilayer structure comprising at least two conductive layers with different physical properties.

[0103] The gate electrode 150 overlaps with the channel portion 130n of the active layer 130. In addition, the seed layer 120 overlaps with the gate electrode 150.

[0104] Referring to Figures 1 and 2, in a planar view, the seed layer 120 can be disposed in the region where the active layer 130 overlaps with the gate electrode 150, and in the region defined by the gate electrode 150. Specifically, in a planar view, the seed layer 120 can be disposed in the region where the active layer 130 overlaps with the gate electrode 150, and in the region defined by the gate electrode 150.

[0105] According to one embodiment of the present disclosure, the active layer 130 is disposed between the seed layer 120 and the gate electrode 150. In addition, the channel portion 130n is disposed between the seed layer 120 and the gate electrode 150.

[0106] When a voltage is applied to the gate electrode 150, the channel portion 130n of the active layer 130 has semiconductor characteristics and can be conductive. In order to drive the thin film transistor 100, the channel portion 130n is placed in the region where the electric field generated by the gate electrode 150 is applied.

[0107] Referring to FIG1, in a planar view, the seed layer 120 is disposed within the area defined by the gate electrode 150. Therefore, the channel portion 130n (i.e., the crystalline portion 130c of the active layer 130) can be disposed within the area of ​​the gate electrode 150.

[0108] If the seed layer 120 extends beyond the region defined by the gate electrode 150, the crystalline portion 130c of the active layer 130 may be formed outside the region defined by the gate electrode 150. In this case, even if a voltage is applied to the gate electrode 150, the crystalline portion 130c located outside the region defined by the gate electrode 150 may not have sufficient mobility. Therefore, the thin-film transistor 100 may not be able to be driven normally.

[0109] Therefore, as shown in Figure 2, in the region overlapping with the active layer 130, the length L1 of the seed layer 120 can be designed to be less than the length L3 of the gate electrode 150.

[0110] Furthermore, referring to FIG1, in the region overlapping with the gate electrode 150, the width w1 of the seed layer 120 can be designed to be greater than the width w2 of the active layer 130. Here, this width is measured along the direction (dr2) perpendicular to the straight line connecting the first connection portion 130a and the second connection portion 130b.

[0111] If a portion of the active layer 130 does not overlap with the seed layer 120 in the width direction dr2, a short circuit may occur.

[0112] Specifically, the portion of the active layer 130 that does not overlap with the seed layer 120 will not crystallize and will have a high carrier concentration and low resistance. When a portion of the active layer 130 does not overlap with the seed layer 120 in the width direction dr2 and extends from the first connection portion 130a to the second connection portion 130b to form a connection region along the direction dr1, current flows through this connection region. Therefore, an electrical short circuit or leakage current will occur between the first connection portion 130a and the second connection portion 130b, causing the thin-film transistor 100 to fail to perform the switching function.

[0113] According to one embodiment of the present disclosure, based on a planar view, the active layer 130 may be disposed in the region defined by the seed layer 120 in the region overlapping with the seed layer 120.

[0114] Referring to Figure 2, an interlayer insulating film 170 is disposed on the gate insulating layer 140 and the gate electrode 150. The interlayer insulating film 170 is an insulating layer made of insulating material. The interlayer insulating film 170 can be made of organic material, inorganic material, or a laminate of organic material layer and inorganic material layer. A source electrode 161 and a drain electrode 162 are disposed on the interlayer insulating film 170.

[0115] Each of the source electrode 161 and the drain electrode 162 may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrode 161 and the drain electrode 162 may each be composed of a single metal layer or a metal alloy layer, or may be composed of a multilayer structure with two or more layers.

[0116] According to one embodiment of the present disclosure, the source electrode 161 may be connected to the first connection portion 130a. The source electrode 161 may be electrically connected to the first connection portion 130a of the active layer 130 through a contact hole.

[0117] The drain electrode 162 may be disposed at a distance from the source electrode 161 and connected to the second connection portion 130b. The drain electrode 162 may be electrically connected to the second connection portion 130b of the active layer 130 through a contact hole.

[0118] According to one embodiment of the present disclosure, the first connection portion 130a of the active layer 130 may be a source region, and the second connection portion 130b may be a drain region. According to one embodiment of the present disclosure, the first connection portion 130a may serve as a source electrode, and the second connection portion 130b may serve as a drain electrode. The first connection portion 130a and the second connection portion 130b are interchangeable.

[0119] Figure 4 is a cross-sectional schematic diagram of a thin-film transistor 200 according to another embodiment of the present disclosure.

[0120] According to one embodiment of the present disclosure, the gate insulating layer 140 may be patterned. Referring to FIG4, the gate insulating layer 140 may be patterned into a shape corresponding to the gate electrode 150.

[0121] Figure 5 is a cross-sectional schematic diagram of a thin-film transistor 300 according to another embodiment of the present disclosure.

[0122] Referring to FIG5, the source electrode 161, the drain electrode 162, and the gate electrode 150 can be disposed on the same layer. Specifically, the source electrode 161 and the drain electrode 162 can be disposed on the gate insulating layer 140. In this case, the source electrode 161 and the drain electrode 162 can be formed with the same material through the same process as the gate electrode 150.

[0123] Referring to FIG5, after a contact hole is formed in the gate insulating layer 140, a gate electrode 150, a source electrode 161 and a drain electrode 162 are formed, such that each of the source electrode 161 and the drain electrode 162 contacts the active layer 130.

[0124] Each of the gate electrode 150, source electrode 161, and drain electrode 162 may include a first layer m1 and a second layer m2 disposed on the first layer m1. The first layer m1 and the second layer m2 are made of different materials. According to one embodiment of the present disclosure, the first layer m1 may include at least one of molybdenum (Mo), titanium (Ti), chromium (Cr), nickel (Ni), and neodymium (Nd). The second layer m2 may include at least one of copper (Cu), aluminum (Al), and gold (Au).

[0125] Figure 6 is a cross-sectional schematic diagram of a thin-film transistor 400 according to another embodiment of the present disclosure.

[0126] Referring to FIG6, the source electrode 161 may be connected to the light-shielding layer 111. Specifically, the source electrode 161 may contact the light-shielding layer 111 through a contact hole formed through the gate insulating layer 140 and the buffer layer 115.

[0127] FIG7 is a plan view of a thin film transistor 500 according to another embodiment of the present disclosure, and FIG8 is a cross-sectional view along line III-III' of FIG7 according to an embodiment.

[0128] Referring to Figures 7 and 8, the gate electrode 150 can be connected to the light-shielding layer 111. Specifically, the gate electrode 150 can contact the light-shielding layer 111 through a contact hole that penetrates the gate insulating layer 140 and the buffer layer 115.

[0129] When the gate electrode 150 is connected to the light-shielding layer 111, the light-shielding layer 111 can serve as the lower gate electrode. Accordingly, the thin-film transistor 500 can have the effect of a dual-gate structure. The thin-film transistor 500 in Figures 7 and 8 can be referred to as a dual-gate structure thin-film transistor.

[0130] FIG9 is a plan view of a thin film transistor 600 according to another embodiment of the present disclosure, and FIG10 is a cross-sectional view along line IV-IV' of FIG9 according to an embodiment.

[0131] According to another embodiment of the present disclosure, the seed layer 120 may include a first pattern 121 and a second pattern 122 spaced apart from each other. Accordingly, the seed layer 120 has a plurality of mutually spaced patterns.

[0132] The first pattern 121 and the second pattern 122 of the seed layer 120 overlap with the gate electrode 150. In addition, the first pattern 121 and the second pattern 122 are in contact with the active layer 130 respectively.

[0133] The portion of the active layer 130 that overlaps with the first pattern 121 and the second pattern 122 can be crystallized to form a channel portion 130n. The portion of the active layer 130 that overlaps with the first pattern 121 can become a first channel 130n1, and the portion of the active layer 130 that overlaps with the second pattern 122 can become a second channel 130n2.

[0134] Referring to Figures 9 and 10, the channel portion 130n may include a first channel 130n1 that contacts the first pattern 121 and a second channel 130n2 that contacts the second pattern 122.

[0135] Referring to Figures 9 and 10, the seed layer 120 may further include a third pattern 123. The portion of the active layer 130 that overlaps with the third pattern 123 may become a third channel 130n3. At this time, the channel portion 130n may include a first channel 130n1, a second channel 130n2, and a third channel 130n3.

[0136] Referring to Figure 10, the amorphous portion 130m may exist between the first pattern 121 and the second pattern 122 and between the second pattern 122 and the third pattern 123.

[0137] FIG11 is a plan view of a thin film transistor 700 according to another embodiment of the present disclosure, and FIG12 is a cross-sectional view along line V-V' of FIG11 according to an embodiment.

[0138] As shown in Figures 11 and 12, the seed layer 120 may have one or more through holes 120r. The through holes 120r may overlap with the gate electrode 150.

[0139] The portion of the active layer 130 disposed within the through-hole 120r may not be crystallized. Specifically, the amorphous portion 130m of the active layer 130 may be disposed within the through-hole 120r of the seed layer 120. Except for the through-hole 120r, the active layer 130 disposed on the seed layer 120 may be crystallized. The crystalline portion 130c of the active layer 130 may be disposed on the seed layer 120 other than the through-hole 120r.

[0140] The channel portion 130n can be divided by the through hole 120r. Through the through hole 120r, a plurality of separate channels can be connected in series or in parallel.

[0141] Figure 13 is a cross-sectional schematic diagram of a thin-film transistor 800 according to another embodiment of the present disclosure.

[0142] In the thin film transistor 800 in Figure 13, the active layer 130 has a multilayer structure.

[0143] As shown in FIG13, the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 disposed on the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may contain the same semiconductor material or different semiconductor materials.

[0144] Each of the portion of the first oxide semiconductor layer 131 that overlaps with the seed crystal layer 120 and the portion of the second oxide semiconductor layer 132 that overlaps with the seed crystal layer 120 is crystallized to form a channel portion 130n.

[0145] The first oxide semiconductor layer 131 supports the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 can be referred to as a support layer. The main channel portion can be formed in the second oxide semiconductor layer 132. However, the embodiments disclosed herein are not limited thereto, and the main channel portion can also be formed in the first oxide semiconductor layer 131.

[0146] Referring to FIG13, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be disposed between the seed layer 120 and the gate electrode 150.

[0147] FIG14 is a plan view of a thin film transistor 900 according to another embodiment of the present disclosure, FIG15 is a cross-sectional view along line VI-VI' of FIG14 according to an embodiment, and FIG16 is a cross-sectional view along line VII-VII' of FIG14 according to an embodiment.

[0148] According to another embodiment of the present disclosure, the active layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 disposed on the first oxide semiconductor layer 131. In addition, a seed layer 120 may be disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132.

[0149] The portion of the first oxide semiconductor layer 131 that overlaps with and contacts the seed crystal layer 120 can be crystallized to form a first channel portion 131n. The portion of the second oxide semiconductor layer 132 that overlaps with and contacts the seed crystal layer 120 can be crystallized to form a second channel portion 132n. Accordingly, channel portions can be formed on the lower and upper sides of the seed crystal layer 120.

[0150] Referring to Figures 14 and 16, in the region overlapping with the gate electrode 150, the width w1 of the seed layer 120 can be designed to be greater than the width wa1 of the first oxide semiconductor layer 131 and the width wa2 of the second oxide semiconductor layer 132.

[0151] As shown in Figure 16, the seed layer 120 can cover the side surface of the first oxide semiconductor layer 131 in the width direction.

[0152] FIG17 is a plan view of a thin film transistor 1000 according to another embodiment of the present disclosure, and FIG18 is a cross-sectional view along line VIII-VIII' of FIG17 according to an embodiment.

[0153] As shown in Figures 17 and 18, the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, and the seed layer 120 can be disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132.

[0154] The seed crystal layer 120 may have multiple patterns, including a first pattern 121, a second pattern 122 and a third pattern 123 that are spaced apart from each other.

[0155] The first pattern 121, the second pattern 122 and the third pattern 123 overlap with the gate electrode 150. In addition, the first pattern 121, the second pattern 122 and the third pattern 123 are in contact with the active layer 130.

[0156] The portion of the active layer 130 that overlaps with the first pattern 121, the second pattern 122 and the third pattern 123 can be crystallized to form a channel portion 130n.

[0157] Each of a portion of the first oxide semiconductor layer 131 and a portion of the second oxide semiconductor layer 132 that overlaps with the first pattern 121 may be crystallized to form a first channel 130n1.

[0158] Each of a portion of the first oxide semiconductor layer 131 and a portion of the second oxide semiconductor layer 132 that overlaps with the second pattern 122 may be crystallized to form a second channel 130n2.

[0159] A portion of the first oxide semiconductor layer 131 and a portion of the second oxide semiconductor layer 132 that overlap with the third pattern 123 may be crystallized to form a third channel 130n3.

[0160] As shown in Figures 17 and 18, the channel portion 130n may include a first channel 130n1, a second channel 130n2 and a third channel 130n3.

[0161] As shown in Figures 17 and 18, the amorphous portion 130m of the active layer 130 may be located between the first pattern 121 and the second pattern 122 and between the second pattern 122 and the third pattern 123.

[0162] Figure 19 is a plan view of a thin-film transistor 1100 according to another embodiment of the present disclosure.

[0163] According to another embodiment of this disclosure, the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, and a seed layer 120 may be disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. The seed layer 120 may have one or more vias 120r. The vias 120r may overlap with the gate electrode 150.

[0164] Referring to Figure 19, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be in contact with each other within the through hole 120r.

[0165] FIG20 is a cross-sectional schematic diagram of a thin-film transistor 1200 according to another embodiment of the present disclosure.

[0166] Referring to FIG20, a thin-film transistor 1200 according to another embodiment of the present disclosure includes a gate electrode 150 disposed on a substrate 110, a gate insulating layer 140 disposed on the gate electrode 150, an active layer 130 disposed on the gate insulating layer 140, and a seed layer 120 disposed on the active layer 130. Furthermore, the thin-film transistor 1200 according to another embodiment of the present disclosure may include a source electrode 161 and a drain electrode 162 disposed on the gate insulating layer 140. The source electrode 161 and the drain electrode 162 are spaced apart from each other and are in contact with the active layer 130 respectively.

[0167] Referring to FIG20, the active layer 130 may be disposed between the gate electrode 150 and the seed layer 120. The entire area of ​​the active layer 130 may overlap with the seed layer 120 in a planar view, and the entire active layer 130 may be crystallized.

[0168] Each of the source electrode 161 and the drain electrode 162 may be in contact with the seed layer 120.

[0169] As shown in FIG20, a thin-film transistor in which the gate electrode 150 is disposed below the active layer 130 is called a bottom-gate structure thin-film transistor. On the other hand, as shown in FIG1 to FIG19, a thin-film transistor in which the gate electrode 150 is disposed above the active layer 130 is called a top-gate structure thin-film transistor.

[0170] Figure 21 is a cross-sectional schematic diagram of a thin-film transistor 1300 according to another embodiment of the present disclosure.

[0171] Referring to FIG21, the active layer 130 includes a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 located on the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may contain the same or different semiconductor materials.

[0172] The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are crystallized through the seed crystal layer 120 and serve as channel portions.

[0173] Referring to FIG21, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be disposed between the seed layer 120 and the gate electrode 150. However, the embodiments disclosed herein are not limited thereto, and the seed layer 120 may be disposed between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. In addition, the seed layer 120 may be divided into multiple patterns, and the seed layer 120 may have one or more through holes.

[0174] The following describes a method for manufacturing a thin-film transistor 100 according to an embodiment of the present disclosure.

[0175] A method for manufacturing a thin-film transistor 100 according to an embodiment of the present disclosure includes: forming a seed layer 120 on a substrate 100; forming an active layer 130 overlapping the seed layer 120; crystallizing a portion of the active layer overlapping the seed layer 120 by heat treatment of the active layer 130; and forming a gate electrode 150 on the active layer 130.

[0176] Figures 22A to 22E are schematic cross-sectional views illustrating a method for manufacturing a thin-film transistor 100 according to an embodiment of the present disclosure.

[0177] As shown in FIG22A, a light-shielding layer 111 is formed on a substrate 110, a buffer layer 115 is formed on the light-shielding layer 111, and a seed crystal layer 120 is formed on the buffer layer 115.

[0178] The thickness of the seed crystal layer 120 can be from 1 nm to 10 nm.

[0179] As shown in Figure 22B, the active layer 130 may be formed on the seed layer 120. The active layer 130 may overlap with the seed layer 120. A portion of the active layer 130 may be in contact with the seed layer 120.

[0180] The active layer 130 may be made of an amorphous oxide semiconductor material. Such an amorphous oxide semiconductor material may have a high carrier concentration and conductivity similar to that of a metal or conductor.

[0181] Next, the active layer 130 is heat-treated. When the active layer 130 is heat-treated, the portion of the active layer 130 that overlaps with the seed layer 120 is crystallized.

[0182] The heat treatment temperature can be from 300°C to 500°C. The heat treatment temperature can vary depending on the thickness of the seed layer 120.

[0183] For example, when the thickness of the seed layer 120 is 1 nm to 4 nm, the heat treatment can be performed at 300°C to 400°C. When the thickness of the seed layer 120 is 4 nm to 6 nm, the heat treatment can be performed at 350°C to 450°C. When the thickness of the seed layer 120 is 6 nm to 10 nm, the heat treatment can be performed at 400°C to 500°C.

[0184] According to one embodiment of the present disclosure, when the thickness of the seed crystal layer 120 is "x" nm and the heat treatment temperature is "y" °C, the heat treatment can be carried out under the condition of satisfying the following Equation 1.

[0185] "Equation 1"

[0186] Y = 22.2x + 277.8

[0187] As shown in Figure 22C, an active layer 130 comprising a crystalline portion 130c and an amorphous portion 130m is formed after heat treatment. Specifically, in the step of forming the active layer 130 before heat treatment, the active layer 130 has an amorphous structure. The portion of the active layer 130 overlapping with the seed crystal layer 120 is transformed into a crystalline structure after heat treatment.

[0188] The crystalline portion 130c of the active layer 130 becomes the channel portion 130n. The amorphous portion 130m of the active layer 130 becomes the first connecting portion 130a and the second connecting portion 130b.

[0189] As shown in FIG22D, a gate insulating layer 140 is formed on the active layer 130, and a gate electrode 150 is formed on the gate insulating layer 140. The gate electrode 150 at least partially overlaps with the active layer 130. Specifically, the gate electrode 150 is formed to overlap with the channel portion 130n.

[0190] As shown in FIG22E, an interlayer insulating film 170 is formed on the gate electrode 150, and a source electrode 161 and a drain electrode 162 are formed on the interlayer insulating film 170. According to another embodiment of the present disclosure, when the gate electrode 150 is formed, the source electrode 161 and the drain electrode 162 may be formed together with the gate electrode 150.

[0191] The following will describe in detail a display device comprising at least one of the aforementioned thin-film transistors.

[0192] FIG23 is a schematic diagram of a display device 1400 according to another embodiment of the present disclosure.

[0193] A display device 1400 according to another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330 and a control unit 340.

[0194] A gate line GL and a data line DL are provided on the display panel 310, and a pixel P is arranged in the intersection area of ​​the gate line GL and the data line DL. An image is displayed by driving the pixel P.

[0195] The control unit 340 (e.g., circuit) controls the gate driver 320 and the data driver 330.

[0196] The control unit 340 uses signals provided by an external system to output a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. In addition, the control unit 340 samples and rearranges the image data input from the external system, and provides the rearranged image data RGB to the data driver 330.

[0197] The gate control signal GCS may include the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. In addition, the gate control signal GCS may include control signals for controlling the shift register.

[0198] The data control signal DCS may include the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, the polarity control signal POL, etc.

[0199] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 can convert the image data RGB input from the control unit 340 into analog data voltage and provide this data voltage to the data line DL.

[0200] The gate driver 320 sequentially provides the gate pulse GP to the gate line GL during one frame period. Here, one frame refers to the period during which an image is output through the display panel. In addition, during the remaining period of one frame period when the gate pulse GP is not supplied, the gate driver 320 supplies the gate turn-off signal Goff, which can turn off the switching element, to the gate line GL. Hereinafter, the gate pulse GP and the gate turn-off signal Goff are collectively referred to as the scan signal SS.

[0201] According to one embodiment of the present disclosure, the gate driver 320 may be mounted on the substrate 110. As previously described, this structure in which the gate driver 320 is directly mounted on the substrate 110 is called a Gate In Panel (GIP) structure.

[0202] Figure 24 is a circuit diagram of a single pixel P in Figure 23, Figure 25 is a plan view of pixel P according to an embodiment, and Figure 26 is a cross-sectional view along line IX-IX' of Figure 25 according to an embodiment.

[0203] The circuit diagram in Figure 24 is an equivalent circuit diagram of the pixel P of the display device 1400, which includes an organic light-emitting diode (OLED) as a display element 710.

[0204] Pixel P includes display element 710 and pixel driver PDC that drives display element 710.

[0205] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided through the gate line GL.

[0206] The data line DL provides the data voltage Vdata to the pixel driver PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0207] The driving power line PL provides the driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is used to drive the pixels of the organic light-emitting diode (OLED) that serves as the display element 710.

[0208] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied via the data line DL is provided to the gate electrode of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata charges the first capacitor C1 formed between the gate electrode and the source electrode of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0209] The current supplied to the organic light-emitting diode OLED, which serves as the display element 710, is controlled by the second thin-film transistor TR2 according to the data voltage Vdata, and thus the grayscale of the light output from the display element 710 can be controlled.

[0210] As shown in Figures 25 and 26, the first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0211] The substrate 110 may be made of glass or plastic. As the substrate 110, a flexible plastic, such as polyimide (PI), may be used.

[0212] A light-shielding layer 111 is disposed on the substrate 110. The light-shielding layer 111 may have light-shielding properties. The light-shielding layer 111 may block external incident light to protect the active layer A2.

[0213] A buffer layer 115 is disposed on the light-shielding layer 111. The buffer layer 115 is made of insulating material and protects the active layers A1 and A2 from external moisture or oxygen. A portion of the light-shielding layer 111 may serve as a capacitor electrode.

[0214] The seed layer 120 is disposed on the buffer layer 115. The seed layer 120 can be disposed in the region corresponding to the channel portion of the first thin-film transistor TR1 and the region corresponding to the channel portion of the second thin-film transistor TR2.

[0215] The active layer A1 of the first thin-film transistor TR1 and the active layer A2 of the second thin-film transistor TR2 are disposed on the seed layer 120.

[0216] For example, active layers A1 and A2 may comprise an oxide semiconductor material. Active layers A1 and A2 may be formed from oxide semiconductor layers made of oxide semiconductor material. Active layers A1 and A2 may comprise crystalline portions and amorphous portions. The channel portions of active layers A1 and A2 have a crystalline structure. The portions of active layers A1 and A2 that overlap with the seed crystal layer 120 may be crystallized and have a crystalline structure.

[0217] A gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 has insulating properties, separating the active layers A1 and A2 from the gate electrodes G1 and G2. The gate insulating layer 140 can cover the entire upper surface of the active layers A1 and A2.

[0218] The gate electrode G1 of the first thin-film transistor TR1 and the gate electrode G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0219] The gate electrode G1 of the first thin-film transistor TR1 overlaps at least partially with the active layer A1 of the first thin-film transistor TR1. The gate electrode G2 of the second thin-film transistor TR2 overlaps at least partially with the active layer A2 of the second thin-film transistor TR2.

[0220] Referring to Figures 25 and 26, the first capacitor electrode CE1 may be disposed on the same layer as the gate electrodes G1 and G2. According to one embodiment of this disclosure, the gate electrode G2 of the second thin-film transistor TR2 may extend on the gate insulating layer 140 to become the first capacitor electrode CE1.

[0221] An interlayer insulating film 170 is disposed on the gate electrodes G1, G2 and the first capacitor electrode CE1.

[0222] Source electrodes S1, S2 and drain electrodes D1, D2 are disposed on the interlayer insulating film 170. The source electrodes S1, S2 and drain electrodes D1, D2 are distinguished only for ease of explanation and are interchangeable.

[0223] Furthermore, the data line DL and the drive power line PL are disposed on the interlayer insulating film 170. The source electrode S1 of the first thin-film transistor TR1 can be integrally formed with the data line DL. The drain electrode D2 of the second thin-film transistor TR2 can be integrally formed with the drive power line PL.

[0224] According to one embodiment of the present disclosure, the source electrode S1 and drain electrode D1 of the first thin-film transistor TR1 are spaced apart from each other and are respectively connected to the active layer A1 of the first thin-film transistor TR1. The source electrode S2 and drain electrode D2 of the second thin-film transistor TR2 are spaced apart from each other and are respectively connected to the active layer A2 of the second thin-film transistor TR2.

[0225] Specifically, the source electrode S1 of the first thin-film transistor TR1 is connected to the active layer A1 of the first thin-film transistor TR1 through the first contact hole H1.

[0226] The drain electrode D1 of the first thin-film transistor TR1 contacts the drain connection portion of the active layer A1 through the second contact hole H2, and is connected to the first capacitor electrode CE1 through the third contact hole H3.

[0227] The source electrode S2 of the second thin-film transistor TR2 extends above the interlayer insulating film 170, and a portion of the second thin-film transistor TR2 serves as the second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 overlap to form the first capacitor C1.

[0228] The source electrode S2 of the second thin-film transistor TR2 contacts the light-shielding layer 111 through the fourth contact hole H4 and the active layer A2 through the fifth contact hole H5.

[0229] The drain electrode D2 of the second thin-film transistor TR2 contacts the active layer A2 through the sixth contact hole H6.

[0230] The first thin-film transistor TR1 is a switching transistor that controls the data voltage Vdata applied to the pixel driver PDC. The second thin-film transistor TR2 is a driving transistor that controls the driving voltage Vdd applied to the display element 710.

[0231] A planarization layer 180 is disposed on the source electrodes S1, S2, drain electrodes D1, D2, second capacitor electrode CE2, data line DL, and drive power line PL. The planarization layer 180 planarizes the upper part of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0232] The first electrode 711 of the display element 710 is disposed on the planarization layer 180. The first electrode 711 of the display element 710 contacts the second capacitor electrode CE2 through the seventh contact hole H7 formed in the planarization layer 180. Accordingly, the first electrode 711 can be connected to the second source electrode S2 of the second thin-film transistor TR2.

[0233] A dam layer 750 is arranged at the edge of the first electrode 711. The dam layer 750 defines the light-emitting area of ​​the display element 710.

[0234] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Therefore, the display element 710 is completed. The display element 710 shown in FIG26 is an organic light-emitting diode (OLED). Therefore, the display device 100 of this disclosed embodiment is an organic light-emitting display device.

[0235] The pixel driver PDC of another embodiment disclosed herein can be formed in various structures other than those described above. The pixel driver PDC may include, for example, three or more thin-film transistors and two or more capacitors.

[0236] The foregoing disclosure is not limited to the foregoing embodiments and drawings. Those skilled in the art to which this disclosure pertains may make various substitutions, modifications and changes without departing from the technical details of this disclosure.

[0237] A thin-film transistor according to one embodiment of the present disclosure includes a seed layer and an active layer in contact with the seed layer, and the portion of the active layer in contact with the seed layer may have a crystalline structure. The crystalline portion of the active layer may be a channel portion. According to one embodiment of the present disclosure, the channel portion may have a crystalline structure, thus exhibiting excellent hydrogen resistance and excellent stability. Therefore, the thin-film transistor according to one embodiment of the present disclosure may have excellent electrical stability.

[0238] According to one embodiment of this disclosure, the portion of the active layer that contacts the seed layer may have a crystalline structure and become a channel portion, while the portion that does not contact the seed layer may have electrical properties similar to those of a metal. Therefore, according to one embodiment of this disclosure, a connection portion serving as a wiring portion can be formed without a conductor-forming process.

[0239] According to one embodiment of this disclosure, since the active layer simultaneously has crystalline and amorphous portions, the thin-film transistor can exhibit excellent reliability and electrical characteristics. Display devices incorporating such thin-film transistors according to embodiments of this disclosure can exhibit excellent display performance and excellent reliability.

[0240] According to one embodiment of the present disclosure, an active layer may be included, and the portion of the active layer that contacts the seed crystal layer may have a crystalline structure.

[0241] In one embodiment, the thin-film transistor includes: a seed layer having an amorphous structure; an active layer overlapping the seed layer and including a channel portion, the channel portion being in contact with the seed layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the seed layer and the active layer in a planar view of the thin-film transistor.

[0242] In one embodiment, the channel portion is located between the seed layer and the gate electrode.

[0243] In one embodiment, the active layer includes a first connection portion connected to a first side of the channel portion and a second connection portion connected to a second side of the channel portion opposite to the first side, wherein each of the first connection portion and the second connection portion has an amorphous structure that is different from the crystalline structure of the channel portion.

[0244] In one embodiment, along the first direction, the length of the seed layer is less than the length of the gate electrode.

[0245] In one embodiment, the width of the seed layer is greater than the width of the active layer along a second direction different from the first direction.

[0246] In one embodiment, the carrier concentration of the seed crystal layer is less than the carrier concentration of the channel portion, the carrier concentration of the first connection portion, and the carrier concentration of the second connection portion.

[0247] In one embodiment, the carrier concentration of the seed layer is 1.0 × 10¹⁶ ea / cm³ or lower.

[0248] In one embodiment, the thickness of the seed layer ranges from 1 nm to 10 nm.

[0249] In one embodiment, the amorphous structure of the seed crystal layer has crystals with a grain size of 1 nm or more, wherein the total area of ​​the crystals with a grain size of 1 nm or more accounts for 10% or less of the total cross-sectional area of ​​the seed crystal layer.

[0250] In one embodiment, the seed layer comprises at least one of indium zinc oxide (InZnO) based oxide semiconductor material, indium gallium zinc oxide IGZO (InGaZnO) based oxide semiconductor material, indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, gallium zinc oxide (GaZnO) based oxide semiconductor material, and gallium oxide (GaO) based oxide semiconductor material.

[0251] In one embodiment, the active layer comprises at least one of indium gallium zinc oxide (InGaZnO) based oxide semiconductor material, indium gallium oxide (InGaO) based oxide semiconductor material, indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, gallium zinc oxide (GaZnO) based oxide semiconductor material, gallium oxide (GaO) based oxide semiconductor material, tin oxide (SnO) based oxide semiconductor material, indium tin oxide (InSnO) based oxide semiconductor material, indium tin zinc oxide (InSnZnO) based oxide semiconductor material, indium zinc oxide (InZnO) based oxide semiconductor material, zinc oxide (ZnO) based oxide semiconductor material, indium oxide (InO) based oxide semiconductor material, zinc oxide (ZnO) based, and iron indium zinc oxide (FeInZnO) based oxide semiconductor material.

[0252] In one embodiment, the active layer further comprises at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y) and zirconium (Zr).

[0253] In one embodiment, the seed layer and the active layer contain at least one of the same metal elements.

[0254] In one embodiment, in the channel portion, the total area of ​​crystals with a grain size of 1 nm or above accounts for 50% or more of the total cross-sectional area of ​​the channel portion.

[0255] In one embodiment, the crystal structure of the channel portion includes at least one of the following: (400) crystal plane, (222) crystal plane, (220) crystal plane, (311) crystal plane or (001) crystal plane.

[0256] In one embodiment, the seed layer includes a first pattern and a second pattern that are spaced apart from each other and overlap with the gate electrode, and the active layer is located between the first pattern and the second pattern, such that the active layer contacts the first pattern and the second pattern.

[0257] In one embodiment, the channel portion includes a first channel that contacts a first pattern and a second channel that contacts a second pattern.

[0258] In one embodiment, the seed layer has at least one through hole, the at least one through hole overlaps with the gate electrode, and a portion of the active layer is disposed in the at least one through hole.

[0259] In one embodiment, the active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer disposed on the first oxide semiconductor layer, wherein the seed layer is located between the first oxide semiconductor layer and the second oxide semiconductor layer.

[0260] In one embodiment, the method of manufacturing a thin-film transistor includes: forming a seed layer on a substrate; forming an active layer overlapping the seed layer, such that a portion of the active layer is in contact with the seed layer while another portion is not in contact with the seed layer; crystallizing the portion of the active layer in contact with the seed layer by heat treatment; and forming a gate electrode on the active layer.

[0261] In one embodiment, during the step of forming the active layer, the active layer has an amorphous structure, and the portion of the active layer that is in contact with the seed crystal layer is heat-treated to transform it into a crystalline structure.

[0262] In one embodiment, the thickness of the seed layer is 1 nm to 10 nm, and the heat treatment temperature range is 300°C to 500°C.

[0263] In one embodiment, the formation of the seed crystal layer includes forming the thickness of the seed crystal layer according to Equation 1: "Equation 1" Y = 22.2x + 277.8, where "x" is in nm and the heat treatment temperature "Y" is in °C.

[0264] In one embodiment, the thin-film transistor includes: a seed layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer including a channel portion covering an upper surface and a plurality of side surfaces of the seed layer, a first connection portion located on a first side of the channel portion and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the seed layer and the channel portion, such that the channel portion is located between the seed layer and the gate electrode, wherein the first carrier concentration of the first oxide semiconductor material in the seed layer is less than the second carrier concentration of the second oxide semiconductor material in the active layer, and the first oxygen concentration of the first oxide semiconductor material is greater than the second oxygen concentration of the second oxide semiconductor material.

[0265] In one embodiment, the channel portion directly contacts the upper surface of the seed crystal layer and a plurality of side surfaces.

[0266] In one embodiment, the channel portion has a crystalline structure, while the first connecting portion, the second connecting portion, and the seed crystal layer have an amorphous structure.

[0267] In one embodiment, the seed layer includes a first pattern and a second pattern that are spaced apart from each other and overlap with the gate electrode, and the active layer is located between the first pattern and the second pattern such that the active layer contacts the first pattern and the second pattern.

[0268] In one embodiment, the channel portion includes: a first channel in contact with a first pattern; and a second channel in contact with a second pattern.

[0269] In one embodiment, the seed layer has at least one via overlapping with the gate electrode, and a portion of the active layer is disposed in the at least one via.

[0270] In one embodiment, the active layer comprises a plurality of semiconductor layers, and a seed layer is located between the semiconductor layers.

[0271] In addition to the aforementioned effects, other features and advantages of this disclosure will be described below, or may be clearly understood by those skilled in the art to which this disclosure pertains based on such descriptions and explanations. [Simplified Explanation of the Diagram]

[0019] The foregoing and other objects, features and advantages of this disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a plan view of a thin-film transistor according to one embodiment of this disclosure; Figure 2 is a cross-sectional view along line I-I' of Figure 1; Figure 3 is a cross-sectional view along line II-II' of Figure 1; Figure 4 is a cross-sectional view of a thin-film transistor according to another embodiment of this disclosure; Figure 5 is a cross-sectional view of a thin-film transistor according to another embodiment of this disclosure; Figure 6 is a cross-sectional view of a thin-film transistor according to another embodiment of this disclosure; Figure 7 is a plan view of a thin-film transistor according to another embodiment of this disclosure; Figure 8 is a cross-sectional view along line III-III' of Figure 7 according to one embodiment of this disclosure; Figure 9 is a plan view of a thin-film transistor according to another embodiment of this disclosure; Figure 10 is a cross-sectional view along line IV-IV' of Figure 9 according to one embodiment of this disclosure; Figure 11 is a plan view of a thin-film transistor according to another embodiment of this disclosure; Figure 12 is a cross-sectional view along line V-V' of Figure 11 according to one embodiment of this disclosure; Figure 13 is a cross-sectional schematic diagram of a thin-film transistor according to another embodiment of the present disclosure; Figure 14 is a plan view of a thin-film transistor according to another embodiment of the present disclosure; Figure 15 is a cross-sectional schematic diagram along line VI-VI' of Figure 14 according to an embodiment of the present disclosure; Figure 16 is a cross-sectional schematic diagram along line VII-VII' of Figure 14 according to an embodiment of the present disclosure; Figure 17 is a plan view of a thin-film transistor according to another embodiment of the present disclosure; Figure 18 is a cross-sectional schematic diagram along line VIII-VIII' of Figure 17 according to an embodiment of the present disclosure; Figure 19 is a plan view of a thin-film transistor according to another embodiment of the present disclosure; Figure 20 is a cross-sectional schematic diagram of a thin-film transistor according to another embodiment of the present disclosure; Figure 21 is a cross-sectional schematic diagram of a thin-film transistor according to another embodiment of the present disclosure; Figures 22A to 22E are cross-sectional schematic diagrams illustrating a method for manufacturing a thin-film transistor according to an embodiment of the present disclosure; Figure 23 is a schematic diagram of a display device according to another embodiment of the present disclosure; Figure 24 is a circuit diagram of a single pixel in Figure 23 according to an embodiment of the present disclosure; Figure 25 is a plan view of the pixels of Figure 24 according to an embodiment of the present disclosure; and Figure 26 is a cross-sectional view along line IX-IX' of Figure 25 according to an embodiment of the present disclosure.

Claims

1. A thin-film transistor, comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the length of the crystalline layer along a first direction is less than the length of the gate electrode along the first direction.

2. The thin-film transistor as claimed in claim 1, wherein the channel portion is located between the crystalline layer and the gate electrode.

3. The thin-film transistor as claimed in claim 1, wherein the active layer comprises: a first connection portion connected to a first side of the channel portion; and a second connection portion connected to a second side of the channel portion opposite to the first side of the channel portion, wherein each of the first connection portion and the second connection portion has an amorphous structure different from the crystalline structure of the channel portion.

4. The thin-film transistor as claimed in claim 1, wherein the width of the crystalline layer along a second direction different from the first direction is greater than the width of the active layer along the second direction.

5. The thin-film transistor as claimed in claim 3, wherein the carrier concentration of the crystalline layer is less than the carrier concentration of the channel portion, the carrier concentration of the first connection portion, and the carrier concentration of the second connection portion.

6. The thin-film transistor as claimed in claim 5, wherein the carrier concentration of the crystalline layer is 1.0 × 10¹⁶ ea / cm³ or lower.

7. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the thickness of the crystalline layer is in the range of 1 nanometer to 10 nanometers.

8. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the amorphous structure of the crystalline layer has a plurality of crystals with a grain size of 1 nanometer or larger, wherein the total area of ​​the crystals with a grain size of 1 nanometer or larger is 10% or less of the total cross-sectional area of ​​the crystalline layer.

9. A thin-film transistor, comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the crystalline layer comprises at least one of indium zinc oxide (InZnO) based oxide semiconductor material, indium gallium zinc oxide (InGaZnO) based oxide semiconductor material, indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, gallium zinc oxide (GaZnO) based oxide semiconductor material, and gallium oxide (GaO) based oxide semiconductor material.

10. The thin-film transistor as claimed in claim 9, wherein the active layer comprises at least one of indium gallium zinc oxide (InGaZnO) based oxide semiconductor material, indium gallium oxide (InGaO) based oxide semiconductor material, indium gallium zinc tin oxide (InGaZnSnO) based oxide semiconductor material, gallium zinc tin oxide (GaZnSnO) based oxide semiconductor material, gallium zinc oxide (GaZnO) based oxide semiconductor material, gallium oxide (GaO) based oxide semiconductor material, tin oxide (SnO) based oxide semiconductor material, indium tin oxide (InSnO) based oxide semiconductor material, indium tin zinc oxide (InSnZnO) based oxide semiconductor material, indium zinc oxide (InZnO) based oxide semiconductor material, zinc oxide (ZnO) based oxide semiconductor material, indium oxide (InO) based oxide semiconductor material, zinc oxide (ZnO) based oxide semiconductor material, and iron indium zinc oxide (FeInZnO) based oxide semiconductor material.

11. The thin-film transistor as claimed in claim 10, wherein the active layer further comprises at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr).

12. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the crystalline layer and the active layer comprise at least one of the same metallic elements.

13. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein in the channel portion, the total area of ​​a plurality of crystals with a grain size of 1 nanometer or larger accounts for 50% or more of the total cross-sectional area of ​​the channel portion.

14. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the crystalline structure of the channel portion includes at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (001) crystal plane.

15. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the crystalline layer includes a first pattern and a second pattern spaced apart from each other and overlapping the gate electrode, and the active layer is located between the first pattern and the second pattern, such that the active layer is in contact with the first pattern and the second pattern.

16. The thin-film transistor as claimed in claim 15, wherein the channel portion comprises: a first channel contacting the first pattern; and a second channel contacting the second pattern.

17. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the crystalline layer has at least one via, the at least one via overlapping the gate electrode, and a portion of the active layer is disposed in the at least one via.

18. A thin-film transistor comprising: a crystalline layer having an amorphous structure; an active layer overlapping the crystalline layer and including a channel portion, the channel portion being in contact with the crystalline layer and having a crystalline structure; and a gate electrode overlapping at least a portion of the crystalline layer and the active layer in a planar view of the thin-film transistor; wherein the active layer comprises: a first oxide semiconductor layer; and a second oxide semiconductor layer located on the first oxide semiconductor layer, wherein the crystalline layer is located between the first oxide semiconductor layer and the second oxide semiconductor layer.

19. A display device comprising: a thin-film transistor as described in any one of claims 1 to 18.

20. A method for manufacturing a thin-film transistor, comprising: forming a crystalline layer on a substrate; forming an active layer overlapping the crystalline layer, such that a portion of the active layer contacts the crystalline layer and another portion of the active layer does not contact the crystalline layer; crystallizing the portion of the active layer in contact with the crystalline layer by performing a heat treatment on the active layer; and forming a gate electrode on the active layer.

21. The manufacturing method as claimed in claim 20, wherein in the formation of the active layer, the active layer has an amorphous structure, and the portion of the active layer in contact with the crystalline layer is transformed into a crystalline structure through the heat treatment.

22. The manufacturing method as described in claim 20, wherein the thickness of the crystalline layer is 1 nanometer to 10 nanometers, and wherein the temperature range of the heat treatment is 300°C to 500°C.

23. The manufacturing method as claimed in claim 20, wherein the formation of the crystal layer comprises forming a thickness of the crystal layer according to Equation 1: "Equation 1" Y = 22.2x + 277.8 where "x" is in nanometers and the temperature of the heat treatment is "Y" in °C.

24. A thin-film transistor, comprising: a crystalline layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer including a channel portion covering an upper surface and a plurality of side surfaces of the crystalline layer, a first connection portion located on a first side of the channel portion, and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the crystalline layer and the channel portion, such that the channel portion is located between the crystalline layer and the gate electrode, wherein a first carrier concentration of the first oxide semiconductor material in the crystalline layer is less than a second carrier concentration of the second oxide semiconductor material in the active layer, and a first oxygen concentration of the first oxide semiconductor material is greater than a second oxygen concentration of the second oxide semiconductor material; and wherein the channel portion directly contacts the upper surface and the side surfaces of the crystalline layer.

25. The thin-film transistor as claimed in claim 24, wherein the channel portion has a crystalline structure, and the first connection portion, the second connection portion, and the crystalline layer have an amorphous structure.

26. A thin-film transistor, comprising: a crystalline layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer including a channel portion covering an upper surface and a plurality of side surfaces of the crystalline layer, a first connection portion located on a first side of the channel portion, and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the crystalline layer and the channel portion, such that the channel portion is located between the crystalline layer and the gate electrode, wherein a first carrier concentration of the first oxide semiconductor material in the crystalline layer is less than a second carrier concentration of the second oxide semiconductor material in the active layer, and a first oxygen concentration of the first oxide semiconductor material is greater than a second oxygen concentration of the second oxide semiconductor material; wherein the crystalline layer includes a first pattern and a second pattern spaced apart from each other and overlapping the gate electrode, and the active layer is located between the first pattern and the second pattern, such that the active layer is in contact with the first pattern and the second pattern.

27. The thin-film transistor as claimed in claim 26, wherein the channel portion comprises: a first channel contacting the first pattern; and a second channel contacting the second pattern.

28. A thin-film transistor, comprising: a crystalline layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer including a channel portion covering an upper surface and a plurality of side surfaces of the crystalline layer, a first connection portion located on a first side of the channel portion, and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the crystalline layer and the channel portion, such that the channel portion is located between the crystalline layer and the gate electrode, wherein a first carrier concentration of the first oxide semiconductor material in the crystalline layer is less than a second carrier concentration of the second oxide semiconductor material in the active layer, and a first oxygen concentration of the first oxide semiconductor material is greater than a second oxygen concentration of the second oxide semiconductor material; wherein the crystalline layer has at least one via, the at least one via overlapping the gate electrode, and a portion of the active layer is disposed in the at least one via.

29. A thin-film transistor, comprising: a crystalline layer comprising a first oxide semiconductor material; an active layer comprising a second oxide semiconductor material, the active layer comprising a channel portion covering an upper surface and a plurality of side surfaces of the crystalline layer, a first connection portion located on a first side of the channel portion, and a second connection portion located on a second side of the channel portion opposite to the first side; and a gate electrode overlapping the crystalline layer and the channel portion, such that the channel portion is located between the crystalline layer and the gate electrode, wherein a first carrier concentration of the first oxide semiconductor material in the crystalline layer is less than a second carrier concentration of the second oxide semiconductor material in the active layer, and a first oxygen concentration of the first oxide semiconductor material is greater than a second oxygen concentration of the second oxide semiconductor material; wherein the active layer comprises a plurality of semiconductor layers, and the crystalline layer is located between the semiconductor layers.

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