Static random-access memory layout structure

Abstract

This invention discloses an SRAM layout structure comprising a substrate, multiple diffusion regions extending along a first direction, and gate structures extending along a second direction and traversing the diffusion regions to form multiple transistors. The structure features T-shaped first and second gate structures that span the first and second diffusion regions, respectively, forming a first access transistor (PG1) and a third access transistor (RPG). These T-shaped gates partially overlap with a first bulk contact doped region located between the first and second diffusion regions. The first bulk contact doped region is adjacent to the channel regions of the first and third access transistors. The first bulk contact doped region can be electrically connected to ground potential via a metal contact, providing a charge release path to improve the floating body effect.

Claims

1. A static random access memory (SRAM) layout structure, comprising: a substrate; a plurality of diffusion regions disposed on the substrate, the plurality of diffusion regions including at least a first diffusion region, a second diffusion region, a third diffusion region, a fourth diffusion region, and a fifth diffusion region; and a plurality of gate structures disposed on the substrate, each gate structure extending along a second direction and traversing the plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, a first access transistor, a second access transistor, and a third access transistor; wherein, When viewed from above, the complex gate structure includes a T-shaped first gate structure and a T-shaped second gate structure, with the T-shaped first gate structure spanning the first diffusion region and the T-shaped second gate structure spanning the second diffusion region, forming the first access transistor and the third access transistor, respectively. The first diffusion region is adjacent to and parallel to the second diffusion region, and the T-shaped first gate structure and the T-shaped second gate structure overlap with a first bulk contact doped region located between the first diffusion region and the second diffusion region.

2. The SRAM layout structure as described in claim 1, wherein the T-shaped first gate structure is mirror-symmetrical with respect to the first body contact doped region and the T-shaped second gate structure.

3. The SRAM layout structure as described in claim 2, wherein the width of the T-shaped first gate structure and the T-shaped second gate structure along the first direction is greater than or equal to the width of the first body contact doped region.

4. The SRAM layout structure as described in claim 1, wherein the first body contact doped region is adjacent to the first channel region of the first access transistor and the second channel region of the third access transistor.

5. The SRAM layout structure as described in claim 4, wherein the first channel region of the first access transistor and the second channel region of the third access transistor are P channels, and wherein the first body contact doped region is a P+ doped region.

6. The SRAM layout structure as described in claim 4, wherein the complex gate structure further includes a third gate structure that spans the first diffusion region and extends laterally to the second diffusion region, thereby forming the first pull-down transistor and the third pull-down transistor, wherein the first pull-down transistor is connected in series with the first access transistor, and the third pull-down transistor is connected in series with the third access transistor.

7. The SRAM layout structure as described in claim 6, wherein the third gate structure partially overlaps with the second bulk contact doped region located between the first diffusion region and the second diffusion region.

8. The SRAM layout structure as described in claim 6, wherein the third gate structure further includes a first protrusion extending toward the T-shaped first gate structure and a second protrusion extending toward the T-shaped second gate structure.

9. The SRAM layout structure as described in claim 7, wherein the second body contact doped region is adjacent to the first diffusion region and the second diffusion region.

10. The SRAM layout structure as described in claim 7, wherein the second body contact doped region is adjacent to the third channel region of the first pull-down transistor (PD1) and the fourth channel region of the third pull-down transistor.

11. The SRAM layout structure as described in claim 10, wherein the third gate structure extends into and across the third diffusion region adjacent to the first diffusion region, thereby forming the first pull-up transistor.

12. The SRAM layout structure as described in claim 11, wherein the third gate structure partially overlaps with a third body contact doped region located between the first diffusion region and the third diffusion region.

13. The SRAM layout structure as described in claim 12, wherein the third body contact doped region is adjacent to the third diffusion region and the fifth channel region of the first pull-up transistor.

14. The SRAM layout structure as described in claim 13, wherein the third gate structure further includes a third protrusion extending toward the second pull-up transistor.

15. The SRAM layout structure as described in claim 1, wherein the substrate is a silicon-coated insulating substrate.

16. The SRAM layout structure as described in claim 1, wherein the first pull-up transistor and the second pull-up transistor are PMOS transistors.

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