Electronic system with serial peripheral interface and error detection method thereof

Abstract

An electronic system with a serial peripheral interface and its error detection method are disclosed. The host and device sides transmit a chip select signal bidirectionally via a chip select pin. When an error is detected, the device side switches the chip select signal to a first logic level. The host side responds by transmitting an error acknowledgment clock signal to the device side via a clock pin when the chip select signal is detected to be switched to the first logic level during the detection period. During the next data transmission, the host side receives error report data via a device-to-host transmission pin.

Claims

1. An electronic system having a serial peripheral interface, comprising: One host side; The host terminal unidirectionally outputs a clock signal and a data output signal to the device terminal via a clock pin and a host-to-device transmission pin, respectively, and unidirectionally receives a data input signal from the device terminal via a device-to-host transmission pin. The host terminal and the device terminal bidirectionally transmit a chip select signal via a chip select pin. Each of the host terminal and the device terminal includes: a bidirectional chip select control circuit that controls the logic level of the chip select signal. The bidirectional chip select control circuit includes: a transistor coupled between the chip select pin and ground, whose conduction state is changed by a drive signal; and a pull-up resistor coupled between a pull-up voltage and the chip select pin. When the device detects an error, it switches the chip select signal to a first logic level. The host detects the logic level of the chip select signal during a detection period and responds by sending an error acknowledgment clock signal to the device via the clock pin during the detection period. In the next data transmission period, the host receives an error report via the device-to-host transmission pin.

2. The electronic system with a serial peripheral interface as claimed in claim 1, wherein the host terminal alternately enters a data transmission period and the detection period before the device terminal detects an error, the host terminal converts the chip select signal to the first logic level during the data transmission period, and outputs the clock signal and the data output signal to the device terminal from the clock pin and the host-to-device transmission pin, respectively, and the host terminal does not transmit the clock signal during the detection period, and converts the chip select signal to a second logic level.

3. The electronic system with a serial peripheral interface as described in claim 1, wherein the device switches the chip select signal to the first logic level before the host enters the next data transmission period or at the end of the current transmission after detecting an error.

4. The electronic system having a serial peripheral interface as described in claim 1, wherein the first logic level is a low logic level.

5. An electronic system having a serial peripheral interface as described in claim 1, wherein the host does not transmit data during the transmission of the error acknowledgment clock signal.

6. An electronic system having a serial peripheral interface as described in claim 1, wherein the error reporting data indicates the cause of the error.

7. An error detection method suitable for detecting the cause of errors in an electronic system having a serial peripheral interface, the electronic system including a host terminal and a device terminal, wherein the host terminal unidirectionally outputs a clock signal and a data output signal to the device terminal via a clock pin and a host-to-device transmission pin, respectively, and unidirectionally receives a data input signal from the device terminal via a device-to-host transmission pin, the host terminal and the device terminal bidirectionally transmit a chip select signal via a chip select pin, wherein the host terminal and the device terminal each include a bidirectional chip select control circuit for controlling the logic level of the chip select signal, the bidirectional chip select control circuit including: A transistor is coupled between the chip's select pin and a ground, and its conduction state is changed by a drive signal. And a pull-up resistor coupled between a pull-up voltage and the chip select pin, the error detection method includes: controlling the host to detect whether the chip select signal is switched to a first logic level during a detection period; In response to the detection that the chip select signal has switched to the first logic level during the detection period, the host terminal is controlled to send an error acknowledgment clock signal to the device terminal through the clock pin; and the host terminal is controlled to receive an error report data through the device to host transmission pin during the next data transmission period.

8. The error detection method as described in claim 7, wherein the host terminal alternately enters a data transmission period and the detection period before the device terminal detects an error, the host terminal converts the chip select signal to the first logic level during the data transmission period, and outputs the clock signal and the data output signal to the device terminal from the clock pin and the host-to-device transmission pin, respectively, and the host terminal does not transmit the clock signal during the detection period, and converts the chip select signal to a second logic level.

9. The error detection method as described in claim 7, wherein after detecting an error, the device switches the chip select signal to the first logic level before the host enters the next data transmission period.

10. The error detection method as described in claim 7, wherein the first logic level is a low logic level.

11. The error detection method as described in claim 7, wherein the host does not transmit data during the transmission of the error acknowledgment clock signal.

12. The error detection method as described in claim 7, wherein the error report data indicates the cause of the error.

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